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/********************************************************************** Standard register and bit definitions for the Texas Instruments* MSP430 microcontroller.** This file supports assembler and C development for* MSP430x43x devices.** Texas Instruments, Version 2.6** Rev. 1.1, Enclose all #define statements with parentheses* Rev. 1.2, Defined vectors for USART (in addition to UART)* Rev. 1.3, Added USART special function labels (UxME, UxIE, UxIFG)* Rev. 1.4, Removed incorrect label 'BTRESET'* Added missing labels for FLL* Rev. 2.1, Fixed definition of FLL_DIV0 and FLL_DIV1* Alignment of defintions in Users Guide and of version numbers* Rev. 2.11,Removed definition of LCDLOWR (not available at 4xx devices)* Rev. 2.2, Fixed type in ADC12 bit definitions (replaced ADC10 with ADC12)* Rev. 2.3, Removed unused def of TASSEL2 / TBSSEL2* Rev. 2.4, Added VLD bits in SVS module* Rev. 2.5, Removed definitions for BTRESET* Rev. 2.6, added definitions for Interrupt Vectors xxIV*********************************************************************/#ifndef __msp430x43x#define __msp430x43x#ifdef __cplusplusextern "C" {#endif/*----------------------------------------------------------------------------*//* PERIPHERAL FILE MAP *//*----------------------------------------------------------------------------*//* External references resolved by a device-specific linker command file */#define SFR_8BIT(address) extern volatile unsigned char address#define SFR_16BIT(address) extern volatile unsigned int address/************************************************************* STANDARD BITS************************************************************/#define BIT0 (0x0001)#define BIT1 (0x0002)#define BIT2 (0x0004)#define BIT3 (0x0008)#define BIT4 (0x0010)#define BIT5 (0x0020)#define BIT6 (0x0040)#define BIT7 (0x0080)#define BIT8 (0x0100)#define BIT9 (0x0200)#define BITA (0x0400)#define BITB (0x0800)#define BITC (0x1000)#define BITD (0x2000)#define BITE (0x4000)#define BITF (0x8000)/************************************************************* STATUS REGISTER BITS************************************************************/#define C (0x0001)#define Z (0x0002)#define N (0x0004)#define V (0x0100)#define GIE (0x0008)#define CPUOFF (0x0010)#define OSCOFF (0x0020)#define SCG0 (0x0040)#define SCG1 (0x0080)/* Low Power Modes coded with Bits 4-7 in SR */#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define LPM0 (CPUOFF)#define LPM1 (SCG0+CPUOFF)#define LPM2 (SCG1+CPUOFF)#define LPM3 (SCG1+SCG0+CPUOFF)#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)/* End #defines for assembler */#else /* Begin #defines for C */#define LPM0_bits (CPUOFF)#define LPM1_bits (SCG0+CPUOFF)#define LPM2_bits (SCG1+CPUOFF)#define LPM3_bits (SCG1+SCG0+CPUOFF)#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)#include "in430.h"#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */#endif /* End #defines for C *//************************************************************* PERIPHERAL FILE MAP************************************************************//************************************************************* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS************************************************************/SFR_8BIT(IE1); /* Interrupt Enable 1 */#define U0IE IE1 /* UART0 Interrupt Enable Register */#define WDTIE (0x01)#define OFIE (0x02)#define NMIIE (0x10)#define ACCVIE (0x20)#define URXIE0 (0x40)#define UTXIE0 (0x80)SFR_8BIT(IFG1); /* Interrupt Flag 1 */#define U0IFG IFG1 /* UART0 Interrupt Flag Register */#define WDTIFG (0x01)#define OFIFG (0x02)#define NMIIFG (0x10)#define URXIFG0 (0x40)#define UTXIFG0 (0x80)SFR_8BIT(ME1); /* Module Enable 1 */#define U0ME ME1 /* UART0 Module Enable Register */#define URXE0 (0x40)#define UTXE0 (0x80)#define USPIE0 (0x40)SFR_8BIT(IE2); /* Interrupt Enable 2 */#define BTIE (0x80)SFR_8BIT(IFG2); /* Interrupt Flag 2 */#define BTIFG (0x80)/************************************************************* WATCHDOG TIMER************************************************************/#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */SFR_16BIT(WDTCTL); /* Watchdog Timer Control *//* The bit names have been prefixed with "WDT" */#define WDTIS0 (0x0001)#define WDTIS1 (0x0002)#define WDTSSEL (0x0004)#define WDTCNTCL (0x0008)#define WDTTMSEL (0x0010)#define WDTNMI (0x0020)#define WDTNMIES (0x0040)#define WDTHOLD (0x0080)#define WDTPW (0x5A00)/* WDT-interval times [1ms] coded with Bits 0-2 *//* WDT is clocked by fSMCLK (assumed 1MHz) */#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " *//* WDT is clocked by fACLK (assumed 32KHz) */#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " *//* Watchdog mode -> reset after expired time *//* WDT is clocked by fSMCLK (assumed 1MHz) */#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " *//* WDT is clocked by fACLK (assumed 32KHz) */#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " *//* INTERRUPT CONTROL *//* These two bits are defined in the Special Function Registers *//* #define WDTIE 0x01 *//* #define WDTIFG 0x01 *//************************************************************* DIGITAL I/O Port1/2************************************************************/#define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */#define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */SFR_8BIT(P1IN); /* Port 1 Input */SFR_8BIT(P1OUT); /* Port 1 Output */SFR_8BIT(P1DIR); /* Port 1 Direction */SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */SFR_8BIT(P1SEL); /* Port 1 Selection */SFR_8BIT(P2IN); /* Port 2 Input */SFR_8BIT(P2OUT); /* Port 2 Output */SFR_8BIT(P2DIR); /* Port 2 Direction */SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */SFR_8BIT(P2SEL); /* Port 2 Selection *//************************************************************* DIGITAL I/O Port3/4************************************************************/#define __MSP430_HAS_PORT3__ /* Definition to show that Module is available */#define __MSP430_HAS_PORT4__ /* Definition to show that Module is available */SFR_8BIT(P3IN); /* Port 3 Input */SFR_8BIT(P3OUT); /* Port 3 Output */SFR_8BIT(P3DIR); /* Port 3 Direction */SFR_8BIT(P3SEL); /* Port 3 Selection */SFR_8BIT(P4IN); /* Port 4 Input */SFR_8BIT(P4OUT); /* Port 4 Output */SFR_8BIT(P4DIR); /* Port 4 Direction */SFR_8BIT(P4SEL); /* Port 4 Selection *//************************************************************* DIGITAL I/O Port5/6************************************************************/#define __MSP430_HAS_PORT5__ /* Definition to show that Module is available */#define __MSP430_HAS_PORT6__ /* Definition to show that Module is available */SFR_8BIT(P5IN); /* Port 5 Input */SFR_8BIT(P5OUT); /* Port 5 Output */SFR_8BIT(P5DIR); /* Port 5 Direction */SFR_8BIT(P5SEL); /* Port 5 Selection */SFR_8BIT(P6IN); /* Port 6 Input */SFR_8BIT(P6OUT); /* Port 6 Output */SFR_8BIT(P6DIR); /* Port 6 Direction */SFR_8BIT(P6SEL); /* Port 6 Selection *//************************************************************* BASIC TIMER************************************************************/#define __MSP430_HAS_BT__ /* Definition to show that Module is available */SFR_8BIT(BTCTL); /* Basic Timer Control *//* The bit names have been prefixed with "BT" */#define BTIP0 (0x01)#define BTIP1 (0x02)#define BTIP2 (0x04)#define BTFRFQ0 (0x08)#define BTFRFQ1 (0x10)#define BTDIV (0x20) /* fCLK2 = ACLK:256 */#define BTHOLD (0x40) /* BT1 is held if this bit is set */#define BTSSEL (0x80) /* fBT = fMCLK (main clock) */SFR_8BIT(BTCNT1); /* Basic Timer Count 1 */SFR_8BIT(BTCNT2); /* Basic Timer Count 2 *//* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */#define BT_fCLK2_ACLK (0x00)#define BT_fCLK2_ACLK_DIV256 (BTDIV)#define BT_fCLK2_MCLK (BTSSEL)/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */#define BT_fCLK2_DIV2 (0x00) /* fINT = fCLK2:2 (default) */#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT = fCLK2:16 */#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT = fCLK2:64 */#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT = fCLK2:128 */#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 *//* Frequency of LCD coded with Bits 3-4 */#define BT_fLCD_DIV32 (0x00) /* fLCD = fACLK:32 (default) */#define BT_fLCD_DIV64 (BTFRFQ0) /* fLCD = fACLK:64 */#define BT_fLCD_DIV128 (BTFRFQ1) /* fLCD = fACLK:128 */#define BT_fLCD_DIV256 (BTFRFQ1+BTFRFQ0) /* fLCD = fACLK:256 *//* LCD frequency values with fBT=fACLK */#define BT_fLCD_1K (0x00) /* fACLK:32 (default) */#define BT_fLCD_512 (BTFRFQ0) /* fACLK:64 */#define BT_fLCD_256 (BTFRFQ1) /* fACLK:128 */#define BT_fLCD_128 (BTFRFQ1+BTFRFQ0) /* fACLK:256 *//* LCD frequency values with fBT=fMCLK */#define BT_fLCD_31K (BTSSEL) /* fMCLK:32 */#define BT_fLCD_15_5K (BTSSEL+BTFRFQ0) /* fMCLK:64 */#define BT_fLCD_7_8K (BTSSEL+BTFRFQ1+BTFRFQ0) /* fMCLK:256 *//* with assumed vlues of fACLK=32KHz, fMCLK=1MHz *//* fBT=fACLK is thought for longer interval times */#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms " */#define BT_ADLY_1 (BTIP2) /* 1ms " */#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms " */#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms " */#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms " */#define BT_ADLY_16 (BTDIV) /* 16ms " */#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms " */#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms " */#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms " */#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms " */#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms " */#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms " */#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms " *//* fCLK2=fMCLK (1MHz) is thought for short interval times *//* the timing for short intervals is more precise than ACLK *//* NOTE *//* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz *//* Too low interval time results in interrupts too frequent for the processor to handle! */#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms " *** too short for */#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms " *** interrupt */#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms " *** handling */#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms " */#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms " */#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms " */#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms " *//* Reset/Hold coded with Bits 6-7 in BT(1)CTL *//* this is for BT *///#define BTRESET_CNT1 (BTRESET) /* BTCNT1 is reset while BTRESET is set *///#define BTRESET_CNT1_2 (BTRESET+BTDIV) /* BTCNT1 .AND. BTCNT2 are reset while ~ is set *//* this is for BT1 */#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set *//* INTERRUPT CONTROL BITS *//* #define BTIE 0x80 *//* #define BTIFG 0x80 *//************************************************************* SYSTEM CLOCK, FLL+************************************************************/#define __MSP430_HAS_FLLPLUS__ /* Definition to show that Module is available */SFR_8BIT(SCFI0); /* System Clock Frequency Integrator 0 */#define FN_2 (0x04) /* fDCOCLK = 1.4-12MHz*/#define FN_3 (0x08) /* fDCOCLK = 2.2-17Mhz*/#define FN_4 (0x10) /* fDCOCLK = 3.2-25Mhz*/#define FN_8 (0x20) /* fDCOCLK = 5-40Mhz*/#define FLLD0 (0x40) /* Loop Divider Bit : 0 */#define FLLD1 (0x80) /* Loop Divider Bit : 1 */#define FLLD_1 (0x00) /* Multiply Selected Loop Freq. By 1 */#define FLLD_2 (0x40) /* Multiply Selected Loop Freq. By 2 */#define FLLD_4 (0x80) /* Multiply Selected Loop Freq. By 4 */#define FLLD_8 (0xC0) /* Multiply Selected Loop Freq. By 8 */SFR_8BIT(SCFI1); /* System Clock Frequency Integrator 1 */SFR_8BIT(SCFQCTL); /* System Clock Frequency Control *//* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL *//* #define SCFQ_32K 0x00 fMCLK=1*fACLK only a range from */#define SCFQ_64K (0x01) /* fMCLK=2*fACLK 1+1 to 127+1 is possible */#define SCFQ_128K (0x03) /* fMCLK=4*fACLK */#define SCFQ_256K (0x07) /* fMCLK=8*fACLK */#define SCFQ_512K (0x0F) /* fMCLK=16*fACLK */#define SCFQ_1M (0x1F) /* fMCLK=32*fACLK */#define SCFQ_2M (0x3F) /* fMCLK=64*fACLK */#define SCFQ_4M (0x7F) /* fMCLK=128*fACLK */#define SCFQ_M (0x80) /* Modulation Disable */SFR_8BIT(FLL_CTL0); /* FLL+ Control 0 */#define DCOF (0x01) /* DCO Fault Flag */#define LFOF (0x02) /* Low Frequency Oscillator Fault Flag */#define XT1OF (0x04) /* High Frequency Oscillator 1 Fault Flag */#define XT2OF (0x08) /* High Frequency Oscillator 2 Fault Flag */#define OSCCAP0 (0x10) /* XIN/XOUT Cap 0 */#define OSCCAP1 (0x20) /* XIN/XOUT Cap 1 */#define XTS_FLL (0x40) /* 1: Selects high-freq. oscillator */#define DCOPLUS (0x80) /* DCO+ Enable */#define XCAP0PF (0x00) /* XIN Cap = XOUT Cap = 0pf */#define XCAP10PF (0x10) /* XIN Cap = XOUT Cap = 10pf */#define XCAP14PF (0x20) /* XIN Cap = XOUT Cap = 14pf */#define XCAP18PF (0x30) /* XIN Cap = XOUT Cap = 18pf */#define OSCCAP_0 (0x00) /* XIN Cap = XOUT Cap = 0pf */#define OSCCAP_1 (0x10) /* XIN Cap = XOUT Cap = 10pf */#define OSCCAP_2 (0x20) /* XIN Cap = XOUT Cap = 14pf */#define OSCCAP_3 (0x30) /* XIN Cap = XOUT Cap = 18pf */SFR_8BIT(FLL_CTL1); /* FLL+ Control 1 */#define FLL_DIV0 (0x01) /* FLL+ Divide Px.x/ACLK 0 */#define FLL_DIV1 (0x02) /* FLL+ Divide Px.x/ACLK 1 */#define SELS (0x04) /* Peripheral Module Clock Source (0: DCO, 1: XT2) */#define SELM0 (0x08) /* MCLK Source Select 0 */#define SELM1 (0x10) /* MCLK Source Select 1 */#define XT2OFF (0x20) /* High Frequency Oscillator 2 (XT2) disable */#define SMCLKOFF (0x40) /* Peripheral Module Clock (SMCLK) disable */#define FLL_DIV_1 (0x00) /* FLL+ Divide Px.x/ACLK By 1 */#define FLL_DIV_2 (0x01) /* FLL+ Divide Px.x/ACLK By 2 */#define FLL_DIV_4 (0x02) /* FLL+ Divide Px.x/ACLK By 4 */#define FLL_DIV_8 (0x03) /* FLL+ Divide Px.x/ACLK By 8 */#define SELM_DCO (0x00) /* Select DCO for CPU MCLK */#define SELM_XT2 (0x10) /* Select XT2 for CPU MCLK */#define SELM_A (0x18) /* Select A (from LFXT1) for CPU MCLK *//* INTERRUPT CONTROL BITS *//* These two bits are defined in the Special Function Registers *//* #define OFIFG 0x02 *//* #define OFIE 0x02 *//************************************************************* Brown-Out, Supply Voltage Supervision (SVS)************************************************************/#define __MSP430_HAS_SVS__ /* Definition to show that Module is available */SFR_8BIT(SVSCTL); /* SVS Control */#define SVSFG (0x01) /* SVS Flag */#define SVSOP (0x02) /* SVS output (read only) */#define SVSON (0x04) /* Switches the SVS on/off */#define PORON (0x08) /* Enable POR Generation if Low Voltage */#define VLD0 (0x10)#define VLD1 (0x20)#define VLD2 (0x40)#define VLD3 (0x80)#define VLDON (0x10)#define VLDOFF (0x00)#define VLD_1_8V (0x10)/************************************************************* LCD************************************************************/#define __MSP430_HAS_LCD4__ /* Definition to show that Module is available */SFR_8BIT(LCDCTL); /* LCD Control *//* the names of the mode bits are different from the spec */#define LCDON (0x01)//#define LCDLOWR (0x02)#define LCDSON (0x04)#define LCDMX0 (0x08)#define LCDMX1 (0x10)#define LCDP0 (0x20)#define LCDP1 (0x40)#define LCDP2 (0x80)/* Display modes coded with Bits 2-4 */#define LCDSTATIC (LCDSON)#define LCD2MUX (LCDMX0+LCDSON)#define LCD3MUX (LCDMX1+LCDSON)#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)/* Group select code with Bits 5-7 Seg.lines Dig.output */#define LCDSG0 (0x00) /* --------- Port Only (default) */#define LCDSG0_1 (LCDP0) /* S0 - S15 see Datasheet */#define LCDSG0_2 (LCDP1) /* S0 - S19 see Datasheet */#define LCDSG0_3 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */#define LCDSG0_4 (LCDP2) /* S0 - S27 see Datasheet */#define LCDSG0_5 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */#define LCDSG0_6 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */#define LCDSG0_7 (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet *//* NOTE: YOU CAN ONLY USE THE 'S' OR 'G' DECLARATIONS FOR A COMMAND *//* MOV #LCDSG0_3+LCDOG2_7,&LCDCTL ACTUALY MEANS MOV #LCDP1,&LCDCTL! */#define LCDOG1_7 (0x00) /* --------- Port Only (default) */#define LCDOG2_7 (LCDP0) /* S0 - S15 see Datasheet */#define LCDOG3_7 (LCDP1) /* S0 - S19 see Datasheet */#define LCDOG4_7 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */#define LCDOG5_7 (LCDP2) /* S0 - S27 see Datasheet */#define LCDOG6_7 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */#define LCDOG7 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */#define LCDOGOFF (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */#define LCDMEM_ (0x0091) /* LCD Memory */#ifdef __ASM_HEADER__#define LCDMEM (LCDMEM_) /* LCD Memory (for assembler) */#else#define LCDMEM ((char*) LCDMEM_) /* LCD Memory (for C) */#endifSFR_8BIT(LCDM1); /* LCD Memory 1 */SFR_8BIT(LCDM2); /* LCD Memory 2 */SFR_8BIT(LCDM3); /* LCD Memory 3 */SFR_8BIT(LCDM4); /* LCD Memory 4 */SFR_8BIT(LCDM5); /* LCD Memory 5 */SFR_8BIT(LCDM6); /* LCD Memory 6 */SFR_8BIT(LCDM7); /* LCD Memory 7 */SFR_8BIT(LCDM8); /* LCD Memory 8 */SFR_8BIT(LCDM9); /* LCD Memory 9 */SFR_8BIT(LCDM10); /* LCD Memory 10 */SFR_8BIT(LCDM11); /* LCD Memory 11 */SFR_8BIT(LCDM12); /* LCD Memory 12 */SFR_8BIT(LCDM13); /* LCD Memory 13 */SFR_8BIT(LCDM14); /* LCD Memory 14 */SFR_8BIT(LCDM15); /* LCD Memory 15 */SFR_8BIT(LCDM16); /* LCD Memory 16 */SFR_8BIT(LCDM17); /* LCD Memory 17 */SFR_8BIT(LCDM18); /* LCD Memory 18 */SFR_8BIT(LCDM19); /* LCD Memory 19 */SFR_8BIT(LCDM20); /* LCD Memory 20 */#define LCDMA (LCDM10) /* LCD Memory A */#define LCDMB (LCDM11) /* LCD Memory B */#define LCDMC (LCDM12) /* LCD Memory C */#define LCDMD (LCDM13) /* LCD Memory D */#define LCDME (LCDM14) /* LCD Memory E */#define LCDMF (LCDM15) /* LCD Memory F *//************************************************************* USART************************************************************//* UxCTL */#define PENA (0x80) /* Parity enable */#define PEV (0x40) /* Parity 0:odd / 1:even */#define SPB (0x20) /* Stop Bits 0:one / 1: two */#define CHAR (0x10) /* Data 0:7-bits / 1:8-bits */#define LISTEN (0x08) /* Listen mode */#define SYNC (0x04) /* UART / SPI mode */#define MM (0x02) /* Master Mode off/on */#define SWRST (0x01) /* USART Software Reset *//* UxTCTL */#define CKPH (0x80) /* SPI: Clock Phase */#define CKPL (0x40) /* Clock Polarity */#define SSEL1 (0x20) /* Clock Source Select 1 */#define SSEL0 (0x10) /* Clock Source Select 0 */#define URXSE (0x08) /* Receive Start edge select */#define TXWAKE (0x04) /* TX Wake up mode */#define STC (0x02) /* SPI: STC enable 0:on / 1:off */#define TXEPT (0x01) /* TX Buffer empty *//* UxRCTL */#define FE (0x80) /* Frame Error */#define PE (0x40) /* Parity Error */#define OE (0x20) /* Overrun Error */#define BRK (0x10) /* Break detected */#define URXEIE (0x08) /* RX Error interrupt enable */#define URXWIE (0x04) /* RX Wake up interrupt enable */#define RXWAKE (0x02) /* RX Wake up detect */#define RXERR (0x01) /* RX Error Error *//************************************************************* USART 0************************************************************/#define __MSP430_HAS_UART0__ /* Definition to show that Module is available */SFR_8BIT(U0CTL); /* USART 0 Control */SFR_8BIT(U0TCTL); /* USART 0 Transmit Control */SFR_8BIT(U0RCTL); /* USART 0 Receive Control */SFR_8BIT(U0MCTL); /* USART 0 Modulation Control */SFR_8BIT(U0BR0); /* USART 0 Baud Rate 0 */SFR_8BIT(U0BR1); /* USART 0 Baud Rate 1 */SFR_8BIT(U0RXBUF); /* USART 0 Receive Buffer */SFR_8BIT(U0TXBUF); /* USART 0 Transmit Buffer *//* Alternate register names */#define UCTL0 U0CTL /* USART 0 Control */#define UTCTL0 U0TCTL /* USART 0 Transmit Control */#define URCTL0 U0RCTL /* USART 0 Receive Control */#define UMCTL0 U0MCTL /* USART 0 Modulation Control */#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */#define UCTL0_ U0CTL_ /* USART 0 Control */#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */#define UCTL_0 U0CTL /* USART 0 Control */#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */#define URCTL_0 U0RCTL /* USART 0 Receive Control */#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */#define UCTL_0_ U0CTL_ /* USART 0 Control */#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer *//************************************************************* Timer A3************************************************************/#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */SFR_16BIT(TAIV); /* Timer A Interrupt Vector Word */SFR_16BIT(TACTL); /* Timer A Control */SFR_16BIT(TACCTL0); /* Timer A Capture/Compare Control 0 */SFR_16BIT(TACCTL1); /* Timer A Capture/Compare Control 1 */SFR_16BIT(TACCTL2); /* Timer A Capture/Compare Control 2 */SFR_16BIT(TAR); /* Timer A Counter Register */SFR_16BIT(TACCR0); /* Timer A Capture/Compare 0 */SFR_16BIT(TACCR1); /* Timer A Capture/Compare 1 */SFR_16BIT(TACCR2); /* Timer A Capture/Compare 2 *//* Alternate register names */#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 *//* Alternate register names - 5xx style */#define TA0IV TAIV /* Timer A Interrupt Vector Word */#define TA0CTL TACTL /* Timer A Control */#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */#define TA0R TAR /* Timer A Counter Register */#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */#define TA0CTL_ TACTL_ /* Timer A Control */#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */#define TA0R_ TAR_ /* Timer A Counter Register */#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */#define TASSEL1 (0x0200) /* Timer A clock source select 0 */#define TASSEL0 (0x0100) /* Timer A clock source select 1 */#define ID1 (0x0080) /* Timer A clock input divider 1 */#define ID0 (0x0040) /* Timer A clock input divider 0 */#define MC1 (0x0020) /* Timer A mode control 1 */#define MC0 (0x0010) /* Timer A mode control 0 */#define TACLR (0x0004) /* Timer A counter clear */#define TAIE (0x0002) /* Timer A counter interrupt enable */#define TAIFG (0x0001) /* Timer A counter interrupt flag */#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */#define CM1 (0x8000) /* Capture mode 1 */#define CM0 (0x4000) /* Capture mode 0 */#define CCIS1 (0x2000) /* Capture input select 1 */#define CCIS0 (0x1000) /* Capture input select 0 */#define SCS (0x0800) /* Capture sychronize */#define SCCI (0x0400) /* Latched capture signal (read) */#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */#define OUTMOD2 (0x0080) /* Output mode 2 */#define OUTMOD1 (0x0040) /* Output mode 1 */#define OUTMOD0 (0x0020) /* Output mode 0 */#define CCIE (0x0010) /* Capture/compare interrupt enable */#define CCI (0x0008) /* Capture input signal (read) */#define OUT (0x0004) /* PWM Output signal if output mode 0 */#define COV (0x0002) /* Capture/compare overflow flag */#define CCIFG (0x0001) /* Capture/compare interrupt flag */#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges *//* TA3IV Definitions */#define TAIV_NONE (0x0000) /* No Interrupt pending */#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */#define TAIV_6 (0x0006) /* Reserved */#define TAIV_8 (0x0008) /* Reserved */#define TAIV_TAIFG (0x000A) /* TAIFG *//************************************************************* Timer B3************************************************************/#define __MSP430_HAS_TB3__ /* Definition to show that Module is available */SFR_16BIT(TBIV); /* Timer B Interrupt Vector Word */SFR_16BIT(TBCTL); /* Timer B Control */SFR_16BIT(TBCCTL0); /* Timer B Capture/Compare Control 0 */SFR_16BIT(TBCCTL1); /* Timer B Capture/Compare Control 1 */SFR_16BIT(TBCCTL2); /* Timer B Capture/Compare Control 2 */SFR_16BIT(TBR); /* Timer B Counter Register */SFR_16BIT(TBCCR0); /* Timer B Capture/Compare 0 */SFR_16BIT(TBCCR1); /* Timer B Capture/Compare 1 */SFR_16BIT(TBCCR2); /* Timer B Capture/Compare 2 *//* Alternate register names - 5xx style */#define TB0IV TBIV /* Timer B Interrupt Vector Word */#define TB0CTL TBCTL /* Timer B Control */#define TB0CCTL0 TBCCTL0 /* Timer B Capture/Compare Control 0 */#define TB0CCTL1 TBCCTL1 /* Timer B Capture/Compare Control 1 */#define TB0CCTL2 TBCCTL2 /* Timer B Capture/Compare Control 2 */#define TB0R TBR /* Timer B Counter Register */#define TB0CCR0 TBCCR0 /* Timer B Capture/Compare 0 */#define TB0CCR1 TBCCR1 /* Timer B Capture/Compare 1 */#define TB0CCR2 TBCCR2 /* Timer B Capture/Compare 2 */#define TB0IV_ TBIV_ /* Timer B Interrupt Vector Word */#define TB0CTL_ TBCTL_ /* Timer B Control */#define TB0CCTL0_ TBCCTL0_ /* Timer B Capture/Compare Control 0 */#define TB0CCTL1_ TBCCTL1_ /* Timer B Capture/Compare Control 1 */#define TB0CCTL2_ TBCCTL2_ /* Timer B Capture/Compare Control 2 */#define TB0R_ TBR_ /* Timer B Counter Register */#define TB0CCR0_ TBCCR0_ /* Timer B Capture/Compare 0 */#define TB0CCR1_ TBCCR1_ /* Timer B Capture/Compare 1 */#define TB0CCR2_ TBCCR2_ /* Timer B Capture/Compare 2 */#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */#define CNTL1 (0x1000) /* Counter lenght 1 */#define CNTL0 (0x0800) /* Counter lenght 0 */#define TBSSEL1 (0x0200) /* Clock source 1 */#define TBSSEL0 (0x0100) /* Clock source 0 */#define TBCLR (0x0004) /* Timer B counter clear */#define TBIE (0x0002) /* Timer B interrupt enable */#define TBIFG (0x0001) /* Timer B interrupt flag */#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */#define SHR_0 (0*0x2000u) /* Timer B Group: 0 - individually */#define SHR_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */#define SHR_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/#define SHR_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */#define TBCLGRP_0 (0*0x2000u) /* Timer B Group: 0 - individually */#define TBCLGRP_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */#define TBCLGRP_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/#define TBCLGRP_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) *//* Additional Timer B Control Register bits are defined in Timer A */#define CLLD1 (0x0400) /* Compare latch load source 1 */#define CLLD0 (0x0200) /* Compare latch load source 0 */#define SLSHR1 (0x0400) /* Compare latch load source 1 */#define SLSHR0 (0x0200) /* Compare latch load source 0 */#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 *//* TB3IV Definitions */#define TBIV_NONE (0x0000) /* No Interrupt pending */#define TBIV_TBCCR1 (0x0002) /* TBCCR1_CCIFG */#define TBIV_TBCCR2 (0x0004) /* TBCCR2_CCIFG */#define TBIV_3 (0x0006) /* Reserved */#define TBIV_4 (0x0008) /* Reserved */#define TBIV_5 (0x000A) /* Reserved */#define TBIV_6 (0x000C) /* Reserved */#define TBIV_TBIFG (0x000E) /* TBIFG *//************************************************************** Flash Memory*************************************************************/#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */SFR_16BIT(FCTL1); /* FLASH Control 1 */SFR_16BIT(FCTL2); /* FLASH Control 2 */SFR_16BIT(FCTL3); /* FLASH Control 3 */#define FRKEY (0x9600) /* Flash key returned by read */#define FWKEY (0xA500) /* Flash key for write */#define FXKEY (0x3300) /* for use with XOR instruction */#define ERASE (0x0002) /* Enable bit for Flash segment erase */#define MERAS (0x0004) /* Enable bit for Flash mass erase */#define WRT (0x0040) /* Enable bit for Flash write */#define BLKWRT (0x0080) /* Enable bit for Flash segment write */#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */#ifndef FN2#define FN2 (0x0004)#endif#ifndef FN3#define FN3 (0x0008)#endif#ifndef FN4#define FN4 (0x0010)#endif#define FN5 (0x0020)#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */#define FSSEL1 (0x0080) /* Flash clock select 1 */#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */#define BUSY (0x0001) /* Flash busy: 1 */#define KEYV (0x0002) /* Flash Key violation flag */#define ACCVIFG (0x0004) /* Flash Access violation flag */#define WAIT (0x0008) /* Wait flag for segment write */#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */#define EMEX (0x0020) /* Flash Emergency Exit *//************************************************************* Comparator A************************************************************/#define __MSP430_HAS_COMPA__ /* Definition to show that Module is available */SFR_8BIT(CACTL1); /* Comparator A Control 1 */SFR_8BIT(CACTL2); /* Comparator A Control 2 */SFR_8BIT(CAPD); /* Comparator A Port Disable */#define CAIFG (0x01) /* Comp. A Interrupt Flag */#define CAIE (0x02) /* Comp. A Interrupt Enable */#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */#define CAON (0x08) /* Comp. A enable */#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */#define CARSEL (0x40) /* Comp. A Internal Reference Enable */#define CAEX (0x80) /* Comp. A Exchange Inputs */#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/#define CAOUT (0x01) /* Comp. A Output */#define CAF (0x02) /* Comp. A Enable Output Filter */#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */#define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */#define CACTL24 (0x10)#define CACTL25 (0x20)#define CACTL26 (0x40)#define CACTL27 (0x80)#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 *//************************************************************* ADC12************************************************************/#define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */SFR_16BIT(ADC12CTL0); /* ADC12 Control 0 */SFR_16BIT(ADC12CTL1); /* ADC12 Control 1 */SFR_16BIT(ADC12IFG); /* ADC12 Interrupt Flag */SFR_16BIT(ADC12IE); /* ADC12 Interrupt Enable */SFR_16BIT(ADC12IV); /* ADC12 Interrupt Vector Word */#define ADC12MEM_ (0x0140) /* ADC12 Conversion Memory */#ifdef __ASM_HEADER__#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */#else#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */#endifSFR_16BIT(ADC12MEM0); /* ADC12 Conversion Memory 0 */SFR_16BIT(ADC12MEM1); /* ADC12 Conversion Memory 1 */SFR_16BIT(ADC12MEM2); /* ADC12 Conversion Memory 2 */SFR_16BIT(ADC12MEM3); /* ADC12 Conversion Memory 3 */SFR_16BIT(ADC12MEM4); /* ADC12 Conversion Memory 4 */SFR_16BIT(ADC12MEM5); /* ADC12 Conversion Memory 5 */SFR_16BIT(ADC12MEM6); /* ADC12 Conversion Memory 6 */SFR_16BIT(ADC12MEM7); /* ADC12 Conversion Memory 7 */SFR_16BIT(ADC12MEM8); /* ADC12 Conversion Memory 8 */SFR_16BIT(ADC12MEM9); /* ADC12 Conversion Memory 9 */SFR_16BIT(ADC12MEM10); /* ADC12 Conversion Memory 10 */SFR_16BIT(ADC12MEM11); /* ADC12 Conversion Memory 11 */SFR_16BIT(ADC12MEM12); /* ADC12 Conversion Memory 12 */SFR_16BIT(ADC12MEM13); /* ADC12 Conversion Memory 13 */SFR_16BIT(ADC12MEM14); /* ADC12 Conversion Memory 14 */SFR_16BIT(ADC12MEM15); /* ADC12 Conversion Memory 15 */#define ADC12MCTL_ (0x0080) /* ADC12 Memory Control */#ifdef __ASM_HEADER__#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */#else#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */#endifSFR_8BIT(ADC12MCTL0); /* ADC12 Memory Control 0 */SFR_8BIT(ADC12MCTL1); /* ADC12 Memory Control 1 */SFR_8BIT(ADC12MCTL2); /* ADC12 Memory Control 2 */SFR_8BIT(ADC12MCTL3); /* ADC12 Memory Control 3 */SFR_8BIT(ADC12MCTL4); /* ADC12 Memory Control 4 */SFR_8BIT(ADC12MCTL5); /* ADC12 Memory Control 5 */SFR_8BIT(ADC12MCTL6); /* ADC12 Memory Control 6 */SFR_8BIT(ADC12MCTL7); /* ADC12 Memory Control 7 */SFR_8BIT(ADC12MCTL8); /* ADC12 Memory Control 8 */SFR_8BIT(ADC12MCTL9); /* ADC12 Memory Control 9 */SFR_8BIT(ADC12MCTL10); /* ADC12 Memory Control 10 */SFR_8BIT(ADC12MCTL11); /* ADC12 Memory Control 11 */SFR_8BIT(ADC12MCTL12); /* ADC12 Memory Control 12 */SFR_8BIT(ADC12MCTL13); /* ADC12 Memory Control 13 */SFR_8BIT(ADC12MCTL14); /* ADC12 Memory Control 14 */SFR_8BIT(ADC12MCTL15); /* ADC12 Memory Control 15 *//* ADC12CTL0 */#define ADC12SC (0x001) /* ADC12 Start Conversion */#define ENC (0x002) /* ADC12 Enable Conversion */#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */#define ADC12ON (0x010) /* ADC12 On/enable */#define REFON (0x020) /* ADC12 Reference on */#define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */#define MSC (0x080) /* ADC12 Multiple SampleConversion */#define SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */#define SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */#define SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */#define SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */#define SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */#define SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */#define SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */#define SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */#define MSH (0x080)#define SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */#define SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */#define SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */#define SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */#define SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */#define SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */#define SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */#define SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */#define SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */#define SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */#define SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */#define SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */#define SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */#define SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */#define SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */#define SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */#define SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */#define SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */#define SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */#define SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */#define SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */#define SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */#define SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */#define SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */#define SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */#define SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */#define SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */#define SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */#define SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */#define SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */#define SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */#define SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 *//* ADC12CTL1 */#define ADC12BUSY (0x0001) /* ADC12 Busy */#define CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */#define CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */#define ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */#define SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */#define SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */#define SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */#define CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */#define CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */#define CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */#define CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */#define CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */#define CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */#define CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */#define CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */#define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */#define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */#define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */#define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */#define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */#define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */#define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */#define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */#define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */#define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */#define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */#define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */#define SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */#define SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */#define SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */#define SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */#define CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */#define CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */#define CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */#define CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */#define CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */#define CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */#define CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */#define CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */#define CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */#define CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */#define CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */#define CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */#define CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */#define CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */#define CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */#define CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 *//* ADC12MCTLx */#define INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */#define INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */#define INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */#define INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */#define SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */#define SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */#define SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */#define EOS (0x0080) /* ADC12 End of Sequence */#define INCH_0 (0) /* ADC12 Input Channel 0 */#define INCH_1 (1) /* ADC12 Input Channel 1 */#define INCH_2 (2) /* ADC12 Input Channel 2 */#define INCH_3 (3) /* ADC12 Input Channel 3 */#define INCH_4 (4) /* ADC12 Input Channel 4 */#define INCH_5 (5) /* ADC12 Input Channel 5 */#define INCH_6 (6) /* ADC12 Input Channel 6 */#define INCH_7 (7) /* ADC12 Input Channel 7 */#define INCH_8 (8) /* ADC12 Input Channel 8 */#define INCH_9 (9) /* ADC12 Input Channel 9 */#define INCH_10 (10) /* ADC12 Input Channel 10 */#define INCH_11 (11) /* ADC12 Input Channel 11 */#define INCH_12 (12) /* ADC12 Input Channel 12 */#define INCH_13 (13) /* ADC12 Input Channel 13 */#define INCH_14 (14) /* ADC12 Input Channel 14 */#define INCH_15 (15) /* ADC12 Input Channel 15 */#define SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */#define SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */#define SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */#define SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */#define SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */#define SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */#define SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */#define SREF_7 (7*0x10u) /* ADC12 Select Reference 7 *//* ADC12IV Definitions */#define ADC12IV_NONE (0x0000) /* No Interrupt pending */#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 *//************************************************************* Interrupt Vectors (offset from 0xFFE0)************************************************************/#define VECTOR_NAME(name) name##_ptr#define EMIT_PRAGMA(x) _Pragma(#x)#define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \PLACE_VECTOR(VECTOR_NAME(func), offset)#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define BASICTIMER_VECTOR ".int00" /* 0xFFE0 Basic Timer */#else#define BASICTIMER_VECTOR (0 * 1u) /* 0xFFE0 Basic Timer *//*#define BASICTIMER_ISR(func) ISR_VECTOR(func, ".int00") */ /* 0xFFE0 Basic Timer */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define PORT2_VECTOR ".int01" /* 0xFFE2 Port 2 */#else#define PORT2_VECTOR (1 * 1u) /* 0xFFE2 Port 2 *//*#define PORT2_ISR(func) ISR_VECTOR(func, ".int01") */ /* 0xFFE2 Port 2 */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define PORT1_VECTOR ".int04" /* 0xFFE8 Port 1 */#else#define PORT1_VECTOR (4 * 1u) /* 0xFFE8 Port 1 *//*#define PORT1_ISR(func) ISR_VECTOR(func, ".int04") */ /* 0xFFE8 Port 1 */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define TIMERA1_VECTOR ".int05" /* 0xFFEA Timer A CC1-2, TA */#else#define TIMERA1_VECTOR (5 * 1u) /* 0xFFEA Timer A CC1-2, TA *//*#define TIMERA1_ISR(func) ISR_VECTOR(func, ".int05") */ /* 0xFFEA Timer A CC1-2, TA */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define TIMERA0_VECTOR ".int06" /* 0xFFEC Timer A CC0 */#else#define TIMERA0_VECTOR (6 * 1u) /* 0xFFEC Timer A CC0 *//*#define TIMERA0_ISR(func) ISR_VECTOR(func, ".int06") */ /* 0xFFEC Timer A CC0 */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define ADC12_VECTOR ".int07" /* 0xFFEE ADC */#else#define ADC12_VECTOR (7 * 1u) /* 0xFFEE ADC *//*#define ADC12_ISR(func) ISR_VECTOR(func, ".int07") */ /* 0xFFEE ADC */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define USART0TX_VECTOR ".int08" /* 0xFFF0 USART 0 Transmit */#else#define USART0TX_VECTOR (8 * 1u) /* 0xFFF0 USART 0 Transmit *//*#define USART0TX_ISR(func) ISR_VECTOR(func, ".int08") */ /* 0xFFF0 USART 0 Transmit */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define USART0RX_VECTOR ".int09" /* 0xFFF2 USART 0 Receive */#else#define USART0RX_VECTOR (9 * 1u) /* 0xFFF2 USART 0 Receive *//*#define USART0RX_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 USART 0 Receive */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define WDT_VECTOR ".int10" /* 0xFFF4 Watchdog Timer */#else#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer *//*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define COMPARATORA_VECTOR ".int11" /* 0xFFF6 Comparator A */#else#define COMPARATORA_VECTOR (11 * 1u) /* 0xFFF6 Comparator A *//*#define COMPARATORA_ISR(func) ISR_VECTOR(func, ".int11") */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define TIMERB1_VECTOR ".int12" /* 0xFFF8 Timer B CC1-2, TB */#else#define TIMERB1_VECTOR (12 * 1u) /* 0xFFF8 Timer B CC1-2, TB *//*#define TIMERB1_ISR(func) ISR_VECTOR(func, ".int12") */ /* 0xFFF8 Timer B CC1-2, TB */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define TIMERB0_VECTOR ".int13" /* 0xFFFA Timer B CC0 */#else#define TIMERB0_VECTOR (13 * 1u) /* 0xFFFA Timer B CC0 *//*#define TIMERB0_ISR(func) ISR_VECTOR(func, ".int13") */ /* 0xFFFA Timer B CC0 */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define NMI_VECTOR ".int14" /* 0xFFFC Non-maskable */#else#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable *//*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */#endif#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */#else#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] *//*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */#endif/************************************************************* End of Modules************************************************************/#ifdef __cplusplus}#endif /* extern "C" */#endif /* #ifndef __msp430x43x */