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2850 dpurdie 1 
/********************************************************************
2 
*
3 
* Standard register and bit definitions for the Texas Instruments
4 
* MSP430 microcontroller.
5 
*
6 
* This file supports assembler and C development for
7 
* MSP430x54x devices.
8 
*
9 
* Texas Instruments, Version 1.11
10 
*
11 
* Rev. 0.0, Setup
12 
* Rev. 0.1, updated PMM (now contains already new definitions with swapped IFG flags for SVSHIFG/SVSLIFG
13 
* Rev. 0.2, updated USCI/I2C Flags (UCBxIFG not used correctly)
14 
* Rev. 0.3, changed RTCEVIFG to RTCTEVIFG / changed RTIV to RTCIV
15 
* Rev. 0.4, added definitions for Interrupt Vectors xxIV
16 
* Rev. 0.5, changed 'void __data20 * volatile' definition
17 
* Rev. 1.0, fixed wrong bit definitions in FLLCTL7
18 
* Rev. 1.1, fixed wrong definitions for some PxDS addresses
19 
* Rev. 1.2, fixed wrong base address for RTC
20 
* Rev. 1.3, fixed SYSRSTIV Definitions
21 
* Rev. 1.4, removed some unused Definitions for PMM
22 
* Rev. 1.5, changed Definitions for TimerB to TimerB0
23 
*           added USCI word and RTxPS Definitions
24 
* Rev. 1.6, changed ADC12PDIF0 to ADC12PDIV
25 
*           added PMMLPM5IFG
26 
* Rev. 1.7, removed definitions for FLL unlock feature
27 
* Rev. 1.8, added TLV definitions
28 
* Rev. 1.9, added some more DMA Trigger definitions
29 
* Rev. 1.10, clean up of Flash section
30 
* Rev. 1.11, Changed access type of DMAxSZ registers to word only
31 
*
32 
********************************************************************/
33 
 
34 
#ifndef __msp430x54x
35 
#define __msp430x54x
36 
 
37 
#ifdef __cplusplus
38 
extern "C" {
39 
#endif
40 
 
41 
 
42 
/*----------------------------------------------------------------------------*/
43 
/* PERIPHERAL FILE MAP                                                        */
44 
/*----------------------------------------------------------------------------*/
45 
 
46 
/* External references resolved by a device-specific linker command file */
47 
#define SFR_8BIT(address)   extern volatile unsigned char address
48 
#define SFR_16BIT(address)  extern volatile unsigned int address
49 
//#define SFR_20BIT(address)  extern volatile unsigned int address
50 
typedef void (* __SFR_FARPTR)();
51 
#define SFR_20BIT(address) extern __SFR_FARPTR address
52 
#define SFR_32BIT(address)  extern volatile unsigned long address
53 
 
54 
 
55 
 
56 
/************************************************************
57 
* STANDARD BITS
58 
************************************************************/
59 
 
60 
#define BIT0                   (0x0001)
61 
#define BIT1                   (0x0002)
62 
#define BIT2                   (0x0004)
63 
#define BIT3                   (0x0008)
64 
#define BIT4                   (0x0010)
65 
#define BIT5                   (0x0020)
66 
#define BIT6                   (0x0040)
67 
#define BIT7                   (0x0080)
68 
#define BIT8                   (0x0100)
69 
#define BIT9                   (0x0200)
70 
#define BITA                   (0x0400)
71 
#define BITB                   (0x0800)
72 
#define BITC                   (0x1000)
73 
#define BITD                   (0x2000)
74 
#define BITE                   (0x4000)
75 
#define BITF                   (0x8000)
76 
 
77 
/************************************************************
78 
* STATUS REGISTER BITS
79 
************************************************************/
80 
 
81 
#define C                      (0x0001)
82 
#define Z                      (0x0002)
83 
#define N                      (0x0004)
84 
#define V                      (0x0100)
85 
#define GIE                    (0x0008)
86 
#define CPUOFF                 (0x0010)
87 
#define OSCOFF                 (0x0020)
88 
#define SCG0                   (0x0040)
89 
#define SCG1                   (0x0080)
90 
 
91 
/* Low Power Modes coded with Bits 4-7 in SR */
92 
 
93 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
94 
#define LPM0                   (CPUOFF)
95 
#define LPM1                   (SCG0+CPUOFF)
96 
#define LPM2                   (SCG1+CPUOFF)
97 
#define LPM3                   (SCG1+SCG0+CPUOFF)
98 
#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
99 
/* End #defines for assembler */
100 
 
101 
#else /* Begin #defines for C */
102 
#define LPM0_bits              (CPUOFF)
103 
#define LPM1_bits              (SCG0+CPUOFF)
104 
#define LPM2_bits              (SCG1+CPUOFF)
105 
#define LPM3_bits              (SCG1+SCG0+CPUOFF)
106 
#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
107 
 
108 
#include "in430.h"
109 
 
110 
#define LPM0         _bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
111 
#define LPM0_EXIT    _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
112 
#define LPM1         _bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
113 
#define LPM1_EXIT    _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
114 
#define LPM2         _bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
115 
#define LPM2_EXIT    _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
116 
#define LPM3         _bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
117 
#define LPM3_EXIT    _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
118 
#define LPM4         _bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
119 
#define LPM4_EXIT    _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
120 
#endif /* End #defines for C */
121 
 
122 
/************************************************************
123 
* CPU
124 
************************************************************/
125 
#define __MSP430_HAS_MSP430XV2_CPU__                /* Definition to show that it has MSP430XV2 CPU */
126 
 
127 
/************************************************************
128 
* PERIPHERAL FILE MAP
129 
************************************************************/
130 
 
131 
/************************************************************
132 
* ADC12 PLUS
133 
************************************************************/
134 
#define __MSP430_HAS_ADC12_PLUS__                /* Definition to show that Module is available */
135 
 
136 
SFR_16BIT(ADC12CTL0);                         /* ADC12+ Control 0 */
137 
SFR_8BIT(ADC12CTL0_L);                        /* ADC12+ Control 0 */
138 
SFR_8BIT(ADC12CTL0_H);                        /* ADC12+ Control 0 */
139 
SFR_16BIT(ADC12CTL1);                         /* ADC12+ Control 1 */
140 
SFR_8BIT(ADC12CTL1_L);                        /* ADC12+ Control 1 */
141 
SFR_8BIT(ADC12CTL1_H);                        /* ADC12+ Control 1 */
142 
SFR_16BIT(ADC12CTL2);                         /* ADC12+ Control 2 */
143 
SFR_8BIT(ADC12CTL2_L);                        /* ADC12+ Control 2 */
144 
SFR_8BIT(ADC12CTL2_H);                        /* ADC12+ Control 2 */
145 
SFR_16BIT(ADC12IFG);                          /* ADC12+ Interrupt Flag */
146 
SFR_8BIT(ADC12IFG_L);                         /* ADC12+ Interrupt Flag */
147 
SFR_8BIT(ADC12IFG_H);                         /* ADC12+ Interrupt Flag */
148 
SFR_16BIT(ADC12IE);                           /* ADC12+ Interrupt Enable */
149 
SFR_8BIT(ADC12IE_L);                          /* ADC12+ Interrupt Enable */
150 
SFR_8BIT(ADC12IE_H);                          /* ADC12+ Interrupt Enable */
151 
SFR_16BIT(ADC12IV);                           /* ADC12+ Interrupt Vector Word */
152 
SFR_8BIT(ADC12IV_L);                          /* ADC12+ Interrupt Vector Word */
153 
SFR_8BIT(ADC12IV_H);                          /* ADC12+ Interrupt Vector Word */
154 
 
155 
SFR_16BIT(ADC12MEM0);                         /* ADC12 Conversion Memory 0 */
156 
SFR_8BIT(ADC12MEM0_L);                        /* ADC12 Conversion Memory 0 */
157 
SFR_8BIT(ADC12MEM0_H);                        /* ADC12 Conversion Memory 0 */
158 
SFR_16BIT(ADC12MEM1);                         /* ADC12 Conversion Memory 1 */
159 
SFR_8BIT(ADC12MEM1_L);                        /* ADC12 Conversion Memory 1 */
160 
SFR_8BIT(ADC12MEM1_H);                        /* ADC12 Conversion Memory 1 */
161 
SFR_16BIT(ADC12MEM2);                         /* ADC12 Conversion Memory 2 */
162 
SFR_8BIT(ADC12MEM2_L);                        /* ADC12 Conversion Memory 2 */
163 
SFR_8BIT(ADC12MEM2_H);                        /* ADC12 Conversion Memory 2 */
164 
SFR_16BIT(ADC12MEM3);                         /* ADC12 Conversion Memory 3 */
165 
SFR_8BIT(ADC12MEM3_L);                        /* ADC12 Conversion Memory 3 */
166 
SFR_8BIT(ADC12MEM3_H);                        /* ADC12 Conversion Memory 3 */
167 
SFR_16BIT(ADC12MEM4);                         /* ADC12 Conversion Memory 4 */
168 
SFR_8BIT(ADC12MEM4_L);                        /* ADC12 Conversion Memory 4 */
169 
SFR_8BIT(ADC12MEM4_H);                        /* ADC12 Conversion Memory 4 */
170 
SFR_16BIT(ADC12MEM5);                         /* ADC12 Conversion Memory 5 */
171 
SFR_8BIT(ADC12MEM5_L);                        /* ADC12 Conversion Memory 5 */
172 
SFR_8BIT(ADC12MEM5_H);                        /* ADC12 Conversion Memory 5 */
173 
SFR_16BIT(ADC12MEM6);                         /* ADC12 Conversion Memory 6 */
174 
SFR_8BIT(ADC12MEM6_L);                        /* ADC12 Conversion Memory 6 */
175 
SFR_8BIT(ADC12MEM6_H);                        /* ADC12 Conversion Memory 6 */
176 
SFR_16BIT(ADC12MEM7);                         /* ADC12 Conversion Memory 7 */
177 
SFR_8BIT(ADC12MEM7_L);                        /* ADC12 Conversion Memory 7 */
178 
SFR_8BIT(ADC12MEM7_H);                        /* ADC12 Conversion Memory 7 */
179 
SFR_16BIT(ADC12MEM8);                         /* ADC12 Conversion Memory 8 */
180 
SFR_8BIT(ADC12MEM8_L);                        /* ADC12 Conversion Memory 8 */
181 
SFR_8BIT(ADC12MEM8_H);                        /* ADC12 Conversion Memory 8 */
182 
SFR_16BIT(ADC12MEM9);                         /* ADC12 Conversion Memory 9 */
183 
SFR_8BIT(ADC12MEM9_L);                        /* ADC12 Conversion Memory 9 */
184 
SFR_8BIT(ADC12MEM9_H);                        /* ADC12 Conversion Memory 9 */
185 
SFR_16BIT(ADC12MEM10);                        /* ADC12 Conversion Memory 10 */
186 
SFR_8BIT(ADC12MEM10_L);                       /* ADC12 Conversion Memory 10 */
187 
SFR_8BIT(ADC12MEM10_H);                       /* ADC12 Conversion Memory 10 */
188 
SFR_16BIT(ADC12MEM11);                        /* ADC12 Conversion Memory 11 */
189 
SFR_8BIT(ADC12MEM11_L);                       /* ADC12 Conversion Memory 11 */
190 
SFR_8BIT(ADC12MEM11_H);                       /* ADC12 Conversion Memory 11 */
191 
SFR_16BIT(ADC12MEM12);                        /* ADC12 Conversion Memory 12 */
192 
SFR_8BIT(ADC12MEM12_L);                       /* ADC12 Conversion Memory 12 */
193 
SFR_8BIT(ADC12MEM12_H);                       /* ADC12 Conversion Memory 12 */
194 
SFR_16BIT(ADC12MEM13);                        /* ADC12 Conversion Memory 13 */
195 
SFR_8BIT(ADC12MEM13_L);                       /* ADC12 Conversion Memory 13 */
196 
SFR_8BIT(ADC12MEM13_H);                       /* ADC12 Conversion Memory 13 */
197 
SFR_16BIT(ADC12MEM14);                        /* ADC12 Conversion Memory 14 */
198 
SFR_8BIT(ADC12MEM14_L);                       /* ADC12 Conversion Memory 14 */
199 
SFR_8BIT(ADC12MEM14_H);                       /* ADC12 Conversion Memory 14 */
200 
SFR_16BIT(ADC12MEM15);                        /* ADC12 Conversion Memory 15 */
201 
SFR_8BIT(ADC12MEM15_L);                       /* ADC12 Conversion Memory 15 */
202 
SFR_8BIT(ADC12MEM15_H);                       /* ADC12 Conversion Memory 15 */
203 
#define ADC12MEM_              ADC12MEM       /* ADC12 Conversion Memory */
204 
#ifdef __ASM_HEADER__
205 
#define ADC12MEM               ADC12MEM0      /* ADC12 Conversion Memory (for assembler) */
206 
#else
207 
#define ADC12MEM               ((int*)        &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
208 
#endif
209 
 
210 
SFR_8BIT(ADC12MCTL0);                         /* ADC12 Memory Control 0 */
211 
SFR_8BIT(ADC12MCTL1);                         /* ADC12 Memory Control 1 */
212 
SFR_8BIT(ADC12MCTL2);                         /* ADC12 Memory Control 2 */
213 
SFR_8BIT(ADC12MCTL3);                         /* ADC12 Memory Control 3 */
214 
SFR_8BIT(ADC12MCTL4);                         /* ADC12 Memory Control 4 */
215 
SFR_8BIT(ADC12MCTL5);                         /* ADC12 Memory Control 5 */
216 
SFR_8BIT(ADC12MCTL6);                         /* ADC12 Memory Control 6 */
217 
SFR_8BIT(ADC12MCTL7);                         /* ADC12 Memory Control 7 */
218 
SFR_8BIT(ADC12MCTL8);                         /* ADC12 Memory Control 8 */
219 
SFR_8BIT(ADC12MCTL9);                         /* ADC12 Memory Control 9 */
220 
SFR_8BIT(ADC12MCTL10);                        /* ADC12 Memory Control 10 */
221 
SFR_8BIT(ADC12MCTL11);                        /* ADC12 Memory Control 11 */
222 
SFR_8BIT(ADC12MCTL12);                        /* ADC12 Memory Control 12 */
223 
SFR_8BIT(ADC12MCTL13);                        /* ADC12 Memory Control 13 */
224 
SFR_8BIT(ADC12MCTL14);                        /* ADC12 Memory Control 14 */
225 
SFR_8BIT(ADC12MCTL15);                        /* ADC12 Memory Control 15 */
226 
#define ADC12MCTL_             ADC12MCTL      /* ADC12 Memory Control */
227 
#ifdef __ASM_HEADER__
228 
#define ADC12MCTL              ADC12MCTL0     /* ADC12 Memory Control (for assembler) */
229 
#else
230 
#define ADC12MCTL              ((char*)       ADC12MCTL0) /* ADC12 Memory Control (for C) */
231 
#endif
232 
 
233 
/* ADC12CTL0 Control Bits */
234 
#define ADC12SC                (0x0001)       /* ADC12 Start Conversion */
235 
#define ADC12ENC               (0x0002)       /* ADC12 Enable Conversion */
236 
#define ADC12TOVIE             (0x0004)       /* ADC12 Timer Overflow interrupt enable */
237 
#define ADC12OVIE              (0x0008)       /* ADC12 Overflow interrupt enable */
238 
#define ADC12ON                (0x0010)       /* ADC12 On/enable */
239 
#define ADC12REFON             (0x0020)       /* ADC12 Reference on */
240 
#define ADC12REF2_5V           (0x0040)       /* ADC12 Ref 0:1.5V / 1:2.5V */
241 
#define ADC12MSC               (0x0080)       /* ADC12 Multiple SampleConversion */
242 
#define ADC12SHT00             (0x0100)       /* ADC12 Sample Hold 0 Select Bit: 0 */
243 
#define ADC12SHT01             (0x0200)       /* ADC12 Sample Hold 0 Select Bit: 1 */
244 
#define ADC12SHT02             (0x0400)       /* ADC12 Sample Hold 0 Select Bit: 2 */
245 
#define ADC12SHT03             (0x0800)       /* ADC12 Sample Hold 0 Select Bit: 3 */
246 
#define ADC12SHT10             (0x1000)       /* ADC12 Sample Hold 1 Select Bit: 0 */
247 
#define ADC12SHT11             (0x2000)       /* ADC12 Sample Hold 1 Select Bit: 1 */
248 
#define ADC12SHT12             (0x4000)       /* ADC12 Sample Hold 1 Select Bit: 2 */
249 
#define ADC12SHT13             (0x8000)       /* ADC12 Sample Hold 1 Select Bit: 3 */
250 
 
251 
/* ADC12CTL0 Control Bits */
252 
#define ADC12SC_L              (0x0001)       /* ADC12 Start Conversion */
253 
#define ADC12ENC_L             (0x0002)       /* ADC12 Enable Conversion */
254 
#define ADC12TOVIE_L           (0x0004)       /* ADC12 Timer Overflow interrupt enable */
255 
#define ADC12OVIE_L            (0x0008)       /* ADC12 Overflow interrupt enable */
256 
#define ADC12ON_L              (0x0010)       /* ADC12 On/enable */
257 
#define ADC12REFON_L           (0x0020)       /* ADC12 Reference on */
258 
#define ADC12REF2_5V_L         (0x0040)       /* ADC12 Ref 0:1.5V / 1:2.5V */
259 
#define ADC12MSC_L             (0x0080)       /* ADC12 Multiple SampleConversion */
260 
 
261 
/* ADC12CTL0 Control Bits */
262 
#define ADC12SHT00_H           (0x0001)       /* ADC12 Sample Hold 0 Select Bit: 0 */
263 
#define ADC12SHT01_H           (0x0002)       /* ADC12 Sample Hold 0 Select Bit: 1 */
264 
#define ADC12SHT02_H           (0x0004)       /* ADC12 Sample Hold 0 Select Bit: 2 */
265 
#define ADC12SHT03_H           (0x0008)       /* ADC12 Sample Hold 0 Select Bit: 3 */
266 
#define ADC12SHT10_H           (0x0010)       /* ADC12 Sample Hold 1 Select Bit: 0 */
267 
#define ADC12SHT11_H           (0x0020)       /* ADC12 Sample Hold 1 Select Bit: 1 */
268 
#define ADC12SHT12_H           (0x0040)       /* ADC12 Sample Hold 1 Select Bit: 2 */
269 
#define ADC12SHT13_H           (0x0080)       /* ADC12 Sample Hold 1 Select Bit: 3 */
270 
 
271 
#define ADC12SHT0_0            (0*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 0 */
272 
#define ADC12SHT0_1            (1*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 1 */
273 
#define ADC12SHT0_2            (2*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 2 */
274 
#define ADC12SHT0_3            (3*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 3 */
275 
#define ADC12SHT0_4            (4*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 4 */
276 
#define ADC12SHT0_5            (5*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 5 */
277 
#define ADC12SHT0_6            (6*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 6 */
278 
#define ADC12SHT0_7            (7*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 7 */
279 
#define ADC12SHT0_8            (8*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 8 */
280 
#define ADC12SHT0_9            (9*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 9 */
281 
#define ADC12SHT0_10           (10*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 10 */
282 
#define ADC12SHT0_11           (11*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 11 */
283 
#define ADC12SHT0_12           (12*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 12 */
284 
#define ADC12SHT0_13           (13*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 13 */
285 
#define ADC12SHT0_14           (14*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 14 */
286 
#define ADC12SHT0_15           (15*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 15 */
287 
 
288 
#define ADC12SHT1_0            (0*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 0 */
289 
#define ADC12SHT1_1            (1*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 1 */
290 
#define ADC12SHT1_2            (2*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 2 */
291 
#define ADC12SHT1_3            (3*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 3 */
292 
#define ADC12SHT1_4            (4*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 4 */
293 
#define ADC12SHT1_5            (5*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 5 */
294 
#define ADC12SHT1_6            (6*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 6 */
295 
#define ADC12SHT1_7            (7*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 7 */
296 
#define ADC12SHT1_8            (8*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 8 */
297 
#define ADC12SHT1_9            (9*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 9 */
298 
#define ADC12SHT1_10           (10*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 10 */
299 
#define ADC12SHT1_11           (11*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 11 */
300 
#define ADC12SHT1_12           (12*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 12 */
301 
#define ADC12SHT1_13           (13*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 13 */
302 
#define ADC12SHT1_14           (14*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 14 */
303 
#define ADC12SHT1_15           (15*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 15 */
304 
 
305 
/* ADC12CTL1 Control Bits */
306 
#define ADC12BUSY              (0x0001)       /* ADC12 Busy */
307 
#define ADC12CONSEQ0           (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
308 
#define ADC12CONSEQ1           (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
309 
#define ADC12SSEL0             (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
310 
#define ADC12SSEL1             (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
311 
#define ADC12DIV0              (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
312 
#define ADC12DIV1              (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
313 
#define ADC12DIV2              (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
314 
#define ADC12ISSH              (0x0100)       /* ADC12 Invert Sample Hold Signal */
315 
#define ADC12SHP               (0x0200)       /* ADC12 Sample/Hold Pulse Mode */
316 
#define ADC12SHS0              (0x0400)       /* ADC12 Sample/Hold Source Bit: 0 */
317 
#define ADC12SHS1              (0x0800)       /* ADC12 Sample/Hold Source Bit: 1 */
318 
#define ADC12CSTARTADD0        (0x1000)       /* ADC12 Conversion Start Address Bit: 0 */
319 
#define ADC12CSTARTADD1        (0x2000)       /* ADC12 Conversion Start Address Bit: 1 */
320 
#define ADC12CSTARTADD2        (0x4000)       /* ADC12 Conversion Start Address Bit: 2 */
321 
#define ADC12CSTARTADD3        (0x8000)       /* ADC12 Conversion Start Address Bit: 3 */
322 
 
323 
/* ADC12CTL1 Control Bits */
324 
#define ADC12BUSY_L            (0x0001)       /* ADC12 Busy */
325 
#define ADC12CONSEQ0_L         (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
326 
#define ADC12CONSEQ1_L         (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
327 
#define ADC12SSEL0_L           (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
328 
#define ADC12SSEL1_L           (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
329 
#define ADC12DIV0_L            (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
330 
#define ADC12DIV1_L            (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
331 
#define ADC12DIV2_L            (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
332 
 
333 
/* ADC12CTL1 Control Bits */
334 
#define ADC12ISSH_H            (0x0001)       /* ADC12 Invert Sample Hold Signal */
335 
#define ADC12SHP_H             (0x0002)       /* ADC12 Sample/Hold Pulse Mode */
336 
#define ADC12SHS0_H            (0x0004)       /* ADC12 Sample/Hold Source Bit: 0 */
337 
#define ADC12SHS1_H            (0x0008)       /* ADC12 Sample/Hold Source Bit: 1 */
338 
#define ADC12CSTARTADD0_H      (0x0010)       /* ADC12 Conversion Start Address Bit: 0 */
339 
#define ADC12CSTARTADD1_H      (0x0020)       /* ADC12 Conversion Start Address Bit: 1 */
340 
#define ADC12CSTARTADD2_H      (0x0040)       /* ADC12 Conversion Start Address Bit: 2 */
341 
#define ADC12CSTARTADD3_H      (0x0080)       /* ADC12 Conversion Start Address Bit: 3 */
342 
 
343 
#define ADC12CONSEQ_0          (0*2u)         /* ADC12 Conversion Sequence Select: 0 */
344 
#define ADC12CONSEQ_1          (1*2u)         /* ADC12 Conversion Sequence Select: 1 */
345 
#define ADC12CONSEQ_2          (2*2u)         /* ADC12 Conversion Sequence Select: 2 */
346 
#define ADC12CONSEQ_3          (3*2u)         /* ADC12 Conversion Sequence Select: 3 */
347 
 
348 
#define ADC12SSEL_0            (0*8u)         /* ADC12 Clock Source Select: 0 */
349 
#define ADC12SSEL_1            (1*8u)         /* ADC12 Clock Source Select: 1 */
350 
#define ADC12SSEL_2            (2*8u)         /* ADC12 Clock Source Select: 2 */
351 
#define ADC12SSEL_3            (3*8u)         /* ADC12 Clock Source Select: 3 */
352 
 
353 
#define ADC12DIV_0             (0*0x20u)      /* ADC12 Clock Divider Select: 0 */
354 
#define ADC12DIV_1             (1*0x20u)      /* ADC12 Clock Divider Select: 1 */
355 
#define ADC12DIV_2             (2*0x20u)      /* ADC12 Clock Divider Select: 2 */
356 
#define ADC12DIV_3             (3*0x20u)      /* ADC12 Clock Divider Select: 3 */
357 
#define ADC12DIV_4             (4*0x20u)      /* ADC12 Clock Divider Select: 4 */
358 
#define ADC12DIV_5             (5*0x20u)      /* ADC12 Clock Divider Select: 5 */
359 
#define ADC12DIV_6             (6*0x20u)      /* ADC12 Clock Divider Select: 6 */
360 
#define ADC12DIV_7             (7*0x20u)      /* ADC12 Clock Divider Select: 7 */
361 
 
362 
#define ADC12SHS_0             (0*0x400u)     /* ADC12 Sample/Hold Source: 0 */
363 
#define ADC12SHS_1             (1*0x400u)     /* ADC12 Sample/Hold Source: 1 */
364 
#define ADC12SHS_2             (2*0x400u)     /* ADC12 Sample/Hold Source: 2 */
365 
#define ADC12SHS_3             (3*0x400u)     /* ADC12 Sample/Hold Source: 3 */
366 
 
367 
#define ADC12CSTARTADD_0       (0*0x1000u)    /* ADC12 Conversion Start Address: 0 */
368 
#define ADC12CSTARTADD_1       (1*0x1000u)    /* ADC12 Conversion Start Address: 1 */
369 
#define ADC12CSTARTADD_2       (2*0x1000u)    /* ADC12 Conversion Start Address: 2 */
370 
#define ADC12CSTARTADD_3       (3*0x1000u)    /* ADC12 Conversion Start Address: 3 */
371 
#define ADC12CSTARTADD_4       (4*0x1000u)    /* ADC12 Conversion Start Address: 4 */
372 
#define ADC12CSTARTADD_5       (5*0x1000u)    /* ADC12 Conversion Start Address: 5 */
373 
#define ADC12CSTARTADD_6       (6*0x1000u)    /* ADC12 Conversion Start Address: 6 */
374 
#define ADC12CSTARTADD_7       (7*0x1000u)    /* ADC12 Conversion Start Address: 7 */
375 
#define ADC12CSTARTADD_8       (8*0x1000u)    /* ADC12 Conversion Start Address: 8 */
376 
#define ADC12CSTARTADD_9       (9*0x1000u)    /* ADC12 Conversion Start Address: 9 */
377 
#define ADC12CSTARTADD_10      (10*0x1000u)   /* ADC12 Conversion Start Address: 10 */
378 
#define ADC12CSTARTADD_11      (11*0x1000u)   /* ADC12 Conversion Start Address: 11 */
379 
#define ADC12CSTARTADD_12      (12*0x1000u)   /* ADC12 Conversion Start Address: 12 */
380 
#define ADC12CSTARTADD_13      (13*0x1000u)   /* ADC12 Conversion Start Address: 13 */
381 
#define ADC12CSTARTADD_14      (14*0x1000u)   /* ADC12 Conversion Start Address: 14 */
382 
#define ADC12CSTARTADD_15      (15*0x1000u)   /* ADC12 Conversion Start Address: 15 */
383 
 
384 
/* ADC12CTL2 Control Bits */
385 
#define ADC12REFBURST          (0x0001)       /* ADC12+ Reference Burst */
386 
#define ADC12REFOUT            (0x0002)       /* ADC12+ Reference Out */
387 
#define ADC12SR                (0x0004)       /* ADC12+ Sampling Rate */
388 
#define ADC12DF                (0x0008)       /* ADC12+ Data Format */
389 
#define ADC12RES0              (0x0010)       /* ADC12+ Resolution Bit: 0 */
390 
#define ADC12RES1              (0x0020)       /* ADC12+ Resolution Bit: 1 */
391 
#define ADC12TCOFF             (0x0080)       /* ADC12+ Temperature Sensor Off */
392 
#define ADC12PDIV              (0x0100)       /* ADC12+ predivider 0:/1   1:/4 */
393 
 
394 
/* ADC12CTL2 Control Bits */
395 
#define ADC12REFBURST_L        (0x0001)       /* ADC12+ Reference Burst */
396 
#define ADC12REFOUT_L          (0x0002)       /* ADC12+ Reference Out */
397 
#define ADC12SR_L              (0x0004)       /* ADC12+ Sampling Rate */
398 
#define ADC12DF_L              (0x0008)       /* ADC12+ Data Format */
399 
#define ADC12RES0_L            (0x0010)       /* ADC12+ Resolution Bit: 0 */
400 
#define ADC12RES1_L            (0x0020)       /* ADC12+ Resolution Bit: 1 */
401 
#define ADC12TCOFF_L           (0x0080)       /* ADC12+ Temperature Sensor Off */
402 
 
403 
/* ADC12CTL2 Control Bits */
404 
#define ADC12PDIV_H            (0x0001)       /* ADC12+ predivider 0:/1   1:/4 */
405 
 
406 
#define ADC12RES_0             (0x0000)       /* ADC12+ Resolution : 8 Bit */
407 
#define ADC12RES_1             (0x0010)       /* ADC12+ Resolution : 10 Bit */
408 
#define ADC12RES_2             (0x0020)       /* ADC12+ Resolution : 12 Bit */
409 
#define ADC12RES_3             (0x0030)       /* ADC12+ Resolution : reserved */
410 
 
411 
/* ADC12MCTLx Control Bits */
412 
#define ADC12INCH0             (0x0001)       /* ADC12 Input Channel Select Bit 0 */
413 
#define ADC12INCH1             (0x0002)       /* ADC12 Input Channel Select Bit 1 */
414 
#define ADC12INCH2             (0x0004)       /* ADC12 Input Channel Select Bit 2 */
415 
#define ADC12INCH3             (0x0008)       /* ADC12 Input Channel Select Bit 3 */
416 
#define ADC12SREF0             (0x0010)       /* ADC12 Select Reference Bit 0 */
417 
#define ADC12SREF1             (0x0020)       /* ADC12 Select Reference Bit 1 */
418 
#define ADC12SREF2             (0x0040)       /* ADC12 Select Reference Bit 2 */
419 
#define ADC12EOS               (0x0080)       /* ADC12 End of Sequence */
420 
 
421 
#define ADC12INCH_0            (0x0000)       /* ADC12 Input Channel 0 */
422 
#define ADC12INCH_1            (0x0001)       /* ADC12 Input Channel 1 */
423 
#define ADC12INCH_2            (0x0002)       /* ADC12 Input Channel 2 */
424 
#define ADC12INCH_3            (0x0003)       /* ADC12 Input Channel 3 */
425 
#define ADC12INCH_4            (0x0004)       /* ADC12 Input Channel 4 */
426 
#define ADC12INCH_5            (0x0005)       /* ADC12 Input Channel 5 */
427 
#define ADC12INCH_6            (0x0006)       /* ADC12 Input Channel 6 */
428 
#define ADC12INCH_7            (0x0007)       /* ADC12 Input Channel 7 */
429 
#define ADC12INCH_8            (0x0008)       /* ADC12 Input Channel 8 */
430 
#define ADC12INCH_9            (0x0009)       /* ADC12 Input Channel 9 */
431 
#define ADC12INCH_10           (0x000A)       /* ADC12 Input Channel 10 */
432 
#define ADC12INCH_11           (0x000B)       /* ADC12 Input Channel 11 */
433 
#define ADC12INCH_12           (0x000C)       /* ADC12 Input Channel 12 */
434 
#define ADC12INCH_13           (0x000D)       /* ADC12 Input Channel 13 */
435 
#define ADC12INCH_14           (0x000E)       /* ADC12 Input Channel 14 */
436 
#define ADC12INCH_15           (0x000F)       /* ADC12 Input Channel 15 */
437 
 
438 
#define ADC12SREF_0            (0*0x10u)      /* ADC12 Select Reference 0 */
439 
#define ADC12SREF_1            (1*0x10u)      /* ADC12 Select Reference 1 */
440 
#define ADC12SREF_2            (2*0x10u)      /* ADC12 Select Reference 2 */
441 
#define ADC12SREF_3            (3*0x10u)      /* ADC12 Select Reference 3 */
442 
#define ADC12SREF_4            (4*0x10u)      /* ADC12 Select Reference 4 */
443 
#define ADC12SREF_5            (5*0x10u)      /* ADC12 Select Reference 5 */
444 
#define ADC12SREF_6            (6*0x10u)      /* ADC12 Select Reference 6 */
445 
#define ADC12SREF_7            (7*0x10u)      /* ADC12 Select Reference 7 */
446 
 
447 
#define ADC12IE0               (0x0001)       /* ADC12 Memory 0      Interrupt Enable */
448 
#define ADC12IE1               (0x0002)       /* ADC12 Memory 1      Interrupt Enable */
449 
#define ADC12IE2               (0x0004)       /* ADC12 Memory 2      Interrupt Enable */
450 
#define ADC12IE3               (0x0008)       /* ADC12 Memory 3      Interrupt Enable */
451 
#define ADC12IE4               (0x0010)       /* ADC12 Memory 4      Interrupt Enable */
452 
#define ADC12IE5               (0x0020)       /* ADC12 Memory 5      Interrupt Enable */
453 
#define ADC12IE6               (0x0040)       /* ADC12 Memory 6      Interrupt Enable */
454 
#define ADC12IE7               (0x0080)       /* ADC12 Memory 7      Interrupt Enable */
455 
#define ADC12IE8               (0x0100)       /* ADC12 Memory 8      Interrupt Enable */
456 
#define ADC12IE9               (0x0200)       /* ADC12 Memory 9      Interrupt Enable */
457 
#define ADC12IE10              (0x0400)       /* ADC12 Memory 10      Interrupt Enable */
458 
#define ADC12IE11              (0x0800)       /* ADC12 Memory 11      Interrupt Enable */
459 
#define ADC12IE12              (0x1000)       /* ADC12 Memory 12      Interrupt Enable */
460 
#define ADC12IE13              (0x2000)       /* ADC12 Memory 13      Interrupt Enable */
461 
#define ADC12IE14              (0x4000)       /* ADC12 Memory 14      Interrupt Enable */
462 
#define ADC12IE15              (0x8000)       /* ADC12 Memory 15      Interrupt Enable */
463 
 
464 
#define ADC12IE0_L             (0x0001)       /* ADC12 Memory 0      Interrupt Enable */
465 
#define ADC12IE1_L             (0x0002)       /* ADC12 Memory 1      Interrupt Enable */
466 
#define ADC12IE2_L             (0x0004)       /* ADC12 Memory 2      Interrupt Enable */
467 
#define ADC12IE3_L             (0x0008)       /* ADC12 Memory 3      Interrupt Enable */
468 
#define ADC12IE4_L             (0x0010)       /* ADC12 Memory 4      Interrupt Enable */
469 
#define ADC12IE5_L             (0x0020)       /* ADC12 Memory 5      Interrupt Enable */
470 
#define ADC12IE6_L             (0x0040)       /* ADC12 Memory 6      Interrupt Enable */
471 
#define ADC12IE7_L             (0x0080)       /* ADC12 Memory 7      Interrupt Enable */
472 
 
473 
#define ADC12IE8_H             (0x0001)       /* ADC12 Memory 8      Interrupt Enable */
474 
#define ADC12IE9_H             (0x0002)       /* ADC12 Memory 9      Interrupt Enable */
475 
#define ADC12IE10_H            (0x0004)       /* ADC12 Memory 10      Interrupt Enable */
476 
#define ADC12IE11_H            (0x0008)       /* ADC12 Memory 11      Interrupt Enable */
477 
#define ADC12IE12_H            (0x0010)       /* ADC12 Memory 12      Interrupt Enable */
478 
#define ADC12IE13_H            (0x0020)       /* ADC12 Memory 13      Interrupt Enable */
479 
#define ADC12IE14_H            (0x0040)       /* ADC12 Memory 14      Interrupt Enable */
480 
#define ADC12IE15_H            (0x0080)       /* ADC12 Memory 15      Interrupt Enable */
481 
 
482 
#define ADC12IFG0              (0x0001)       /* ADC12 Memory 0      Interrupt Flag */
483 
#define ADC12IFG1              (0x0002)       /* ADC12 Memory 1      Interrupt Flag */
484 
#define ADC12IFG2              (0x0004)       /* ADC12 Memory 2      Interrupt Flag */
485 
#define ADC12IFG3              (0x0008)       /* ADC12 Memory 3      Interrupt Flag */
486 
#define ADC12IFG4              (0x0010)       /* ADC12 Memory 4      Interrupt Flag */
487 
#define ADC12IFG5              (0x0020)       /* ADC12 Memory 5      Interrupt Flag */
488 
#define ADC12IFG6              (0x0040)       /* ADC12 Memory 6      Interrupt Flag */
489 
#define ADC12IFG7              (0x0080)       /* ADC12 Memory 7      Interrupt Flag */
490 
#define ADC12IFG8              (0x0100)       /* ADC12 Memory 8      Interrupt Flag */
491 
#define ADC12IFG9              (0x0200)       /* ADC12 Memory 9      Interrupt Flag */
492 
#define ADC12IFG10             (0x0400)       /* ADC12 Memory 10      Interrupt Flag */
493 
#define ADC12IFG11             (0x0800)       /* ADC12 Memory 11      Interrupt Flag */
494 
#define ADC12IFG12             (0x1000)       /* ADC12 Memory 12      Interrupt Flag */
495 
#define ADC12IFG13             (0x2000)       /* ADC12 Memory 13      Interrupt Flag */
496 
#define ADC12IFG14             (0x4000)       /* ADC12 Memory 14      Interrupt Flag */
497 
#define ADC12IFG15             (0x8000)       /* ADC12 Memory 15      Interrupt Flag */
498 
 
499 
#define ADC12IFG0_L            (0x0001)       /* ADC12 Memory 0      Interrupt Flag */
500 
#define ADC12IFG1_L            (0x0002)       /* ADC12 Memory 1      Interrupt Flag */
501 
#define ADC12IFG2_L            (0x0004)       /* ADC12 Memory 2      Interrupt Flag */
502 
#define ADC12IFG3_L            (0x0008)       /* ADC12 Memory 3      Interrupt Flag */
503 
#define ADC12IFG4_L            (0x0010)       /* ADC12 Memory 4      Interrupt Flag */
504 
#define ADC12IFG5_L            (0x0020)       /* ADC12 Memory 5      Interrupt Flag */
505 
#define ADC12IFG6_L            (0x0040)       /* ADC12 Memory 6      Interrupt Flag */
506 
#define ADC12IFG7_L            (0x0080)       /* ADC12 Memory 7      Interrupt Flag */
507 
 
508 
#define ADC12IFG8_H            (0x0001)       /* ADC12 Memory 8      Interrupt Flag */
509 
#define ADC12IFG9_H            (0x0002)       /* ADC12 Memory 9      Interrupt Flag */
510 
#define ADC12IFG10_H           (0x0004)       /* ADC12 Memory 10      Interrupt Flag */
511 
#define ADC12IFG11_H           (0x0008)       /* ADC12 Memory 11      Interrupt Flag */
512 
#define ADC12IFG12_H           (0x0010)       /* ADC12 Memory 12      Interrupt Flag */
513 
#define ADC12IFG13_H           (0x0020)       /* ADC12 Memory 13      Interrupt Flag */
514 
#define ADC12IFG14_H           (0x0040)       /* ADC12 Memory 14      Interrupt Flag */
515 
#define ADC12IFG15_H           (0x0080)       /* ADC12 Memory 15      Interrupt Flag */
516 
 
517 
/* ADC12IV Definitions */
518 
#define ADC12IV_NONE           (0x0000)       /* No Interrupt pending */
519 
#define ADC12IV_ADC12OVIFG     (0x0002)       /* ADC12OVIFG */
520 
#define ADC12IV_ADC12TOVIFG    (0x0004)       /* ADC12TOVIFG */
521 
#define ADC12IV_ADC12IFG0      (0x0006)       /* ADC12IFG0 */
522 
#define ADC12IV_ADC12IFG1      (0x0008)       /* ADC12IFG1 */
523 
#define ADC12IV_ADC12IFG2      (0x000A)       /* ADC12IFG2 */
524 
#define ADC12IV_ADC12IFG3      (0x000C)       /* ADC12IFG3 */
525 
#define ADC12IV_ADC12IFG4      (0x000E)       /* ADC12IFG4 */
526 
#define ADC12IV_ADC12IFG5      (0x0010)       /* ADC12IFG5 */
527 
#define ADC12IV_ADC12IFG6      (0x0012)       /* ADC12IFG6 */
528 
#define ADC12IV_ADC12IFG7      (0x0014)       /* ADC12IFG7 */
529 
#define ADC12IV_ADC12IFG8      (0x0016)       /* ADC12IFG8 */
530 
#define ADC12IV_ADC12IFG9      (0x0018)       /* ADC12IFG9 */
531 
#define ADC12IV_ADC12IFG10     (0x001A)       /* ADC12IFG10 */
532 
#define ADC12IV_ADC12IFG11     (0x001C)       /* ADC12IFG11 */
533 
#define ADC12IV_ADC12IFG12     (0x001E)       /* ADC12IFG12 */
534 
#define ADC12IV_ADC12IFG13     (0x0020)       /* ADC12IFG13 */
535 
#define ADC12IV_ADC12IFG14     (0x0022)       /* ADC12IFG14 */
536 
#define ADC12IV_ADC12IFG15     (0x0024)       /* ADC12IFG15 */
537 
 
538 
/*************************************************************
539 
* CRC Module
540 
*************************************************************/
541 
#define __MSP430_HAS_CRC__                    /* Definition to show that Module is available */
542 
 
543 
SFR_16BIT(CRCDI);                             /* CRC Data In Register */
544 
SFR_8BIT(CRCDI_L);                            /* CRC Data In Register */
545 
SFR_8BIT(CRCDI_H);                            /* CRC Data In Register */
546 
SFR_16BIT(CRCINIRES);                         /* CRC Initialisation Register and Result Register*/
547 
SFR_8BIT(CRCINIRES_L);                        /* CRC Initialisation Register and Result Register*/
548 
SFR_8BIT(CRCINIRES_H);                        /* CRC Initialisation Register and Result Register*/
549 
 
550 
/************************************************************
551 
* DMA_X
552 
************************************************************/
553 
#define __MSP430_HAS_DMAX_3__                 /* Definition to show that Module is available */
554 
 
555 
SFR_16BIT(DMACTL0);                           /* DMA Module Control 0 */
556 
SFR_8BIT(DMACTL0_L);                          /* DMA Module Control 0 */
557 
SFR_8BIT(DMACTL0_H);                          /* DMA Module Control 0 */
558 
SFR_16BIT(DMACTL1);                           /* DMA Module Control 1 */
559 
SFR_8BIT(DMACTL1_L);                          /* DMA Module Control 1 */
560 
SFR_8BIT(DMACTL1_H);                          /* DMA Module Control 1 */
561 
SFR_16BIT(DMACTL2);                           /* DMA Module Control 2 */
562 
SFR_8BIT(DMACTL2_L);                          /* DMA Module Control 2 */
563 
SFR_8BIT(DMACTL2_H);                          /* DMA Module Control 2 */
564 
SFR_16BIT(DMACTL3);                           /* DMA Module Control 3 */
565 
SFR_8BIT(DMACTL3_L);                          /* DMA Module Control 3 */
566 
SFR_8BIT(DMACTL3_H);                          /* DMA Module Control 3 */
567 
SFR_16BIT(DMACTL4);                           /* DMA Module Control 4 */
568 
SFR_8BIT(DMACTL4_L);                          /* DMA Module Control 4 */
569 
SFR_8BIT(DMACTL4_H);                          /* DMA Module Control 4 */
570 
SFR_16BIT(DMAIV);                             /* DMA Interrupt Vector Word */
571 
SFR_8BIT(DMAIV_L);                            /* DMA Interrupt Vector Word */
572 
SFR_8BIT(DMAIV_H);                            /* DMA Interrupt Vector Word */
573 
 
574 
SFR_16BIT(DMA0CTL);                           /* DMA Channel 0 Control */
575 
SFR_8BIT(DMA0CTL_L);                          /* DMA Channel 0 Control */
576 
SFR_8BIT(DMA0CTL_H);                          /* DMA Channel 0 Control */
577 
SFR_20BIT(DMA0SA);                            /* DMA Channel 0 Source Address */
578 
SFR_16BIT(DMA0SAL);                           /* DMA Channel 0 Source Address */
579 
SFR_20BIT(DMA0DA);                            /* DMA Channel 0 Destination Address */
580 
SFR_16BIT(DMA0DAL);                           /* DMA Channel 0 Destination Address */
581 
SFR_16BIT(DMA0SZ);                            /* DMA Channel 0 Transfer Size */
582 
 
583 
SFR_16BIT(DMA1CTL);                           /* DMA Channel 1 Control */
584 
SFR_8BIT(DMA1CTL_L);                          /* DMA Channel 1 Control */
585 
SFR_8BIT(DMA1CTL_H);                          /* DMA Channel 1 Control */
586 
SFR_20BIT(DMA1SA);                            /* DMA Channel 1 Source Address */
587 
SFR_16BIT(DMA1SAL);                           /* DMA Channel 1 Source Address */
588 
SFR_20BIT(DMA1DA);                            /* DMA Channel 1 Destination Address */
589 
SFR_16BIT(DMA1DAL);                           /* DMA Channel 1 Destination Address */
590 
SFR_16BIT(DMA1SZ);                            /* DMA Channel 1 Transfer Size */
591 
 
592 
SFR_16BIT(DMA2CTL);                           /* DMA Channel 2 Control */
593 
SFR_8BIT(DMA2CTL_L);                          /* DMA Channel 2 Control */
594 
SFR_8BIT(DMA2CTL_H);                          /* DMA Channel 2 Control */
595 
SFR_20BIT(DMA2SA);                            /* DMA Channel 2 Source Address */
596 
SFR_16BIT(DMA2SAL);                           /* DMA Channel 2 Source Address */
597 
SFR_20BIT(DMA2DA);                            /* DMA Channel 2 Destination Address */
598 
SFR_16BIT(DMA2DAL);                           /* DMA Channel 2 Destination Address */
599 
SFR_16BIT(DMA2SZ);                            /* DMA Channel 2 Transfer Size */
600 
 
601 
/* DMACTL0 Control Bits */
602 
#define DMA0TSEL0              (0x0001)       /* DMA channel 0 transfer select bit 0 */
603 
#define DMA0TSEL1              (0x0002)       /* DMA channel 0 transfer select bit 1 */
604 
#define DMA0TSEL2              (0x0004)       /* DMA channel 0 transfer select bit 2 */
605 
#define DMA0TSEL3              (0x0008)       /* DMA channel 0 transfer select bit 3 */
606 
#define DMA0TSEL4              (0x0010)       /* DMA channel 0 transfer select bit 4 */
607 
#define DMA1TSEL0              (0x0100)       /* DMA channel 1 transfer select bit 0 */
608 
#define DMA1TSEL1              (0x0200)       /* DMA channel 1 transfer select bit 1 */
609 
#define DMA1TSEL2              (0x0400)       /* DMA channel 1 transfer select bit 2 */
610 
#define DMA1TSEL3              (0x0800)       /* DMA channel 1 transfer select bit 3 */
611 
#define DMA1TSEL4              (0x1000)       /* DMA channel 1 transfer select bit 4 */
612 
 
613 
/* DMACTL0 Control Bits */
614 
#define DMA0TSEL0_L            (0x0001)       /* DMA channel 0 transfer select bit 0 */
615 
#define DMA0TSEL1_L            (0x0002)       /* DMA channel 0 transfer select bit 1 */
616 
#define DMA0TSEL2_L            (0x0004)       /* DMA channel 0 transfer select bit 2 */
617 
#define DMA0TSEL3_L            (0x0008)       /* DMA channel 0 transfer select bit 3 */
618 
#define DMA0TSEL4_L            (0x0010)       /* DMA channel 0 transfer select bit 4 */
619 
 
620 
/* DMACTL0 Control Bits */
621 
#define DMA1TSEL0_H            (0x0001)       /* DMA channel 1 transfer select bit 0 */
622 
#define DMA1TSEL1_H            (0x0002)       /* DMA channel 1 transfer select bit 1 */
623 
#define DMA1TSEL2_H            (0x0004)       /* DMA channel 1 transfer select bit 2 */
624 
#define DMA1TSEL3_H            (0x0008)       /* DMA channel 1 transfer select bit 3 */
625 
#define DMA1TSEL4_H            (0x0010)       /* DMA channel 1 transfer select bit 4 */
626 
 
627 
/* DMACTL01 Control Bits */
628 
#define DMA2TSEL0              (0x0001)       /* DMA channel 2 transfer select bit 0 */
629 
#define DMA2TSEL1              (0x0002)       /* DMA channel 2 transfer select bit 1 */
630 
#define DMA2TSEL2              (0x0004)       /* DMA channel 2 transfer select bit 2 */
631 
#define DMA2TSEL3              (0x0008)       /* DMA channel 2 transfer select bit 3 */
632 
#define DMA2TSEL4              (0x0010)       /* DMA channel 2 transfer select bit 4 */
633 
 
634 
/* DMACTL01 Control Bits */
635 
#define DMA2TSEL0_L            (0x0001)       /* DMA channel 2 transfer select bit 0 */
636 
#define DMA2TSEL1_L            (0x0002)       /* DMA channel 2 transfer select bit 1 */
637 
#define DMA2TSEL2_L            (0x0004)       /* DMA channel 2 transfer select bit 2 */
638 
#define DMA2TSEL3_L            (0x0008)       /* DMA channel 2 transfer select bit 3 */
639 
#define DMA2TSEL4_L            (0x0010)       /* DMA channel 2 transfer select bit 4 */
640 
 
641 
/* DMACTL01 Control Bits */
642 
 
643 
/* DMACTL4 Control Bits */
644 
#define ENNMI                  (0x0001)       /* Enable NMI interruption of DMA */
645 
#define ROUNDROBIN             (0x0002)       /* Round-Robin DMA channel priorities */
646 
#define DMARMWDIS              (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
647 
 
648 
/* DMACTL4 Control Bits */
649 
#define ENNMI_L                (0x0001)       /* Enable NMI interruption of DMA */
650 
#define ROUNDROBIN_L           (0x0002)       /* Round-Robin DMA channel priorities */
651 
#define DMARMWDIS_L            (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
652 
 
653 
/* DMACTL4 Control Bits */
654 
 
655 
/* DMAxCTL Control Bits */
656 
#define DMAREQ                 (0x0001)       /* Initiate DMA transfer with DMATSEL */
657 
#define DMAABORT               (0x0002)       /* DMA transfer aborted by NMI */
658 
#define DMAIE                  (0x0004)       /* DMA interrupt enable */
659 
#define DMAIFG                 (0x0008)       /* DMA interrupt flag */
660 
#define DMAEN                  (0x0010)       /* DMA enable */
661 
#define DMALEVEL               (0x0020)       /* DMA level sensitive trigger select */
662 
#define DMASRCBYTE             (0x0040)       /* DMA source byte */
663 
#define DMADSTBYTE             (0x0080)       /* DMA destination byte */
664 
#define DMASRCINCR0            (0x0100)       /* DMA source increment bit 0 */
665 
#define DMASRCINCR1            (0x0200)       /* DMA source increment bit 1 */
666 
#define DMADSTINCR0            (0x0400)       /* DMA destination increment bit 0 */
667 
#define DMADSTINCR1            (0x0800)       /* DMA destination increment bit 1 */
668 
#define DMADT0                 (0x1000)       /* DMA transfer mode bit 0 */
669 
#define DMADT1                 (0x2000)       /* DMA transfer mode bit 1 */
670 
#define DMADT2                 (0x4000)       /* DMA transfer mode bit 2 */
671 
 
672 
/* DMAxCTL Control Bits */
673 
#define DMAREQ_L               (0x0001)       /* Initiate DMA transfer with DMATSEL */
674 
#define DMAABORT_L             (0x0002)       /* DMA transfer aborted by NMI */
675 
#define DMAIE_L                (0x0004)       /* DMA interrupt enable */
676 
#define DMAIFG_L               (0x0008)       /* DMA interrupt flag */
677 
#define DMAEN_L                (0x0010)       /* DMA enable */
678 
#define DMALEVEL_L             (0x0020)       /* DMA level sensitive trigger select */
679 
#define DMASRCBYTE_L           (0x0040)       /* DMA source byte */
680 
#define DMADSTBYTE_L           (0x0080)       /* DMA destination byte */
681 
 
682 
/* DMAxCTL Control Bits */
683 
#define DMASRCINCR0_H          (0x0001)       /* DMA source increment bit 0 */
684 
#define DMASRCINCR1_H          (0x0002)       /* DMA source increment bit 1 */
685 
#define DMADSTINCR0_H          (0x0004)       /* DMA destination increment bit 0 */
686 
#define DMADSTINCR1_H          (0x0008)       /* DMA destination increment bit 1 */
687 
#define DMADT0_H               (0x0010)       /* DMA transfer mode bit 0 */
688 
#define DMADT1_H               (0x0020)       /* DMA transfer mode bit 1 */
689 
#define DMADT2_H               (0x0040)       /* DMA transfer mode bit 2 */
690 
 
691 
#define DMASWDW                (0*0x0040u)    /* DMA transfer: source word to destination word */
692 
#define DMASBDW                (1*0x0040u)    /* DMA transfer: source byte to destination word */
693 
#define DMASWDB                (2*0x0040u)    /* DMA transfer: source word to destination byte */
694 
#define DMASBDB                (3*0x0040u)    /* DMA transfer: source byte to destination byte */
695 
 
696 
#define DMASRCINCR_0           (0*0x0100u)    /* DMA source increment 0: source address unchanged */
697 
#define DMASRCINCR_1           (1*0x0100u)    /* DMA source increment 1: source address unchanged */
698 
#define DMASRCINCR_2           (2*0x0100u)    /* DMA source increment 2: source address decremented */
699 
#define DMASRCINCR_3           (3*0x0100u)    /* DMA source increment 3: source address incremented */
700 
 
701 
#define DMADSTINCR_0           (0*0x0400u)    /* DMA destination increment 0: destination address unchanged */
702 
#define DMADSTINCR_1           (1*0x0400u)    /* DMA destination increment 1: destination address unchanged */
703 
#define DMADSTINCR_2           (2*0x0400u)    /* DMA destination increment 2: destination address decremented */
704 
#define DMADSTINCR_3           (3*0x0400u)    /* DMA destination increment 3: destination address incremented */
705 
 
706 
#define DMADT_0                (0*0x1000u)    /* DMA transfer mode 0: Single transfer */
707 
#define DMADT_1                (1*0x1000u)    /* DMA transfer mode 1: Block transfer */
708 
#define DMADT_2                (2*0x1000u)    /* DMA transfer mode 2: Burst-Block transfer */
709 
#define DMADT_3                (3*0x1000u)    /* DMA transfer mode 3: Burst-Block transfer */
710 
#define DMADT_4                (4*0x1000u)    /* DMA transfer mode 4: Repeated Single transfer */
711 
#define DMADT_5                (5*0x1000u)    /* DMA transfer mode 5: Repeated Block transfer */
712 
#define DMADT_6                (6*0x1000u)    /* DMA transfer mode 6: Repeated Burst-Block transfer */
713 
#define DMADT_7                (7*0x1000u)    /* DMA transfer mode 7: Repeated Burst-Block transfer */
714 
 
715 
/* DMAIV Definitions */
716 
#define DMAIV_NONE             (0x0000)       /* No Interrupt pending */
717 
#define DMAIV_DMA0IFG          (0x0002)       /* DMA0IFG*/
718 
#define DMAIV_DMA1IFG          (0x0004)       /* DMA1IFG*/
719 
#define DMAIV_DMA2IFG          (0x0006)       /* DMA2IFG*/
720 
 
721 
#define DMA0TSEL_0             (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
722 
#define DMA0TSEL_1             (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
723 
#define DMA0TSEL_2             (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
724 
#define DMA0TSEL_3             (3*0x0001u)    /* DMA channel 0 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
725 
#define DMA0TSEL_4             (4*0x0001u)    /* DMA channel 0 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
726 
#define DMA0TSEL_5             (5*0x0001u)    /* DMA channel 0 transfer select 5:  TimerB (TB0CCR0.IFG) */
727 
#define DMA0TSEL_6             (6*0x0001u)    /* DMA channel 0 transfer select 6:  TimerB (TB0CCR2.IFG) */
728 
#define DMA0TSEL_7             (7*0x0001u)    /* DMA channel 0 transfer select 7:  Reserved */
729 
#define DMA0TSEL_8             (8*0x0001u)    /* DMA channel 0 transfer select 8:  Reserved */
730 
#define DMA0TSEL_9             (9*0x0001u)    /* DMA channel 0 transfer select 9:  Reserved */
731 
#define DMA0TSEL_10            (10*0x0001u)   /* DMA channel 0 transfer select 10: Reserved */
732 
#define DMA0TSEL_11            (11*0x0001u)   /* DMA channel 0 transfer select 11: Reserved */
733 
#define DMA0TSEL_12            (12*0x0001u)   /* DMA channel 0 transfer select 12: Reserved */
734 
#define DMA0TSEL_13            (13*0x0001u)   /* DMA channel 0 transfer select 13: Reserved */
735 
#define DMA0TSEL_14            (14*0x0001u)   /* DMA channel 0 transfer select 14: Reserved */
736 
#define DMA0TSEL_15            (15*0x0001u)   /* DMA channel 0 transfer select 15: Reserved */
737 
#define DMA0TSEL_16            (16*0x0001u)   /* DMA channel 0 transfer select 16: USCIA0 receive */
738 
#define DMA0TSEL_17            (17*0x0001u)   /* DMA channel 0 transfer select 17: USCIA0 transmit */
739 
#define DMA0TSEL_18            (18*0x0001u)   /* DMA channel 0 transfer select 18: USCIB0 receive */
740 
#define DMA0TSEL_19            (19*0x0001u)   /* DMA channel 0 transfer select 19: USCIB0 transmit */
741 
#define DMA0TSEL_20            (20*0x0001u)   /* DMA channel 0 transfer select 20: USCIA1 receive */
742 
#define DMA0TSEL_21            (21*0x0001u)   /* DMA channel 0 transfer select 21: USCIA1 transmit */
743 
#define DMA0TSEL_22            (22*0x0001u)   /* DMA channel 0 transfer select 22: USCIB1 receive */
744 
#define DMA0TSEL_23            (23*0x0001u)   /* DMA channel 0 transfer select 23: USCIB1 transmit */
745 
#define DMA0TSEL_24            (24*0x0001u)   /* DMA channel 0 transfer select 24: ADC12IFGx */
746 
#define DMA0TSEL_25            (25*0x0001u)   /* DMA channel 0 transfer select 25: Reserved */
747 
#define DMA0TSEL_26            (26*0x0001u)   /* DMA channel 0 transfer select 26: Reserved */
748 
#define DMA0TSEL_27            (27*0x0001u)   /* DMA channel 0 transfer select 27: Reserved */
749 
#define DMA0TSEL_28            (28*0x0001u)   /* DMA channel 0 transfer select 28: Reserved */
750 
#define DMA0TSEL_29            (29*0x0001u)   /* DMA channel 0 transfer select 29: Multiplier ready */
751 
#define DMA0TSEL_30            (30*0x0001u)   /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
752 
#define DMA0TSEL_31            (31*0x0001u)   /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
753 
 
754 
#define DMA1TSEL_0             (0*0x0100u)    /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
755 
#define DMA1TSEL_1             (1*0x0100u)    /* DMA channel 1 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
756 
#define DMA1TSEL_2             (2*0x0100u)    /* DMA channel 1 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
757 
#define DMA1TSEL_3             (3*0x0100u)    /* DMA channel 1 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
758 
#define DMA1TSEL_4             (4*0x0100u)    /* DMA channel 1 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
759 
#define DMA1TSEL_5             (5*0x0100u)    /* DMA channel 1 transfer select 5:  TimerB (TB0CCR0.IFG) */
760 
#define DMA1TSEL_6             (6*0x0100u)    /* DMA channel 1 transfer select 6:  TimerB (TB0CCR2.IFG) */
761 
#define DMA1TSEL_7             (7*0x0100u)    /* DMA channel 1 transfer select 7:  Reserved */
762 
#define DMA1TSEL_8             (8*0x0100u)    /* DMA channel 1 transfer select 8:  Reserved */
763 
#define DMA1TSEL_9             (9*0x0100u)    /* DMA channel 1 transfer select 9:  Reserved */
764 
#define DMA1TSEL_10            (10*0x0100u)   /* DMA channel 1 transfer select 10: Reserved */
765 
#define DMA1TSEL_11            (11*0x0100u)   /* DMA channel 1 transfer select 11: Reserved */
766 
#define DMA1TSEL_12            (12*0x0100u)   /* DMA channel 1 transfer select 12: Reserved */
767 
#define DMA1TSEL_13            (13*0x0100u)   /* DMA channel 1 transfer select 13: Reserved */
768 
#define DMA1TSEL_14            (14*0x0100u)   /* DMA channel 1 transfer select 14: Reserved */
769 
#define DMA1TSEL_15            (15*0x0100u)   /* DMA channel 1 transfer select 15: Reserved */
770 
#define DMA1TSEL_16            (16*0x0100u)   /* DMA channel 1 transfer select 16: USCIA0 receive */
771 
#define DMA1TSEL_17            (17*0x0100u)   /* DMA channel 1 transfer select 17: USCIA0 transmit */
772 
#define DMA1TSEL_18            (18*0x0100u)   /* DMA channel 1 transfer select 18: USCIB0 receive */
773 
#define DMA1TSEL_19            (19*0x0100u)   /* DMA channel 1 transfer select 19: USCIB0 transmit */
774 
#define DMA1TSEL_20            (20*0x0100u)   /* DMA channel 1 transfer select 20: USCIA1 receive */
775 
#define DMA1TSEL_21            (21*0x0100u)   /* DMA channel 1 transfer select 21: USCIA1 transmit */
776 
#define DMA1TSEL_22            (22*0x0100u)   /* DMA channel 1 transfer select 22: USCIB1 receive */
777 
#define DMA1TSEL_23            (23*0x0100u)   /* DMA channel 1 transfer select 23: USCIB1 transmit */
778 
#define DMA1TSEL_24            (24*0x0100u)   /* DMA channel 1 transfer select 24: ADC12IFGx */
779 
#define DMA1TSEL_25            (25*0x0100u)   /* DMA channel 1 transfer select 25: Reserved */
780 
#define DMA1TSEL_26            (26*0x0100u)   /* DMA channel 1 transfer select 26: Reserved */
781 
#define DMA1TSEL_27            (27*0x0100u)   /* DMA channel 1 transfer select 27: Reserved */
782 
#define DMA1TSEL_28            (28*0x0100u)   /* DMA channel 1 transfer select 28: Reserved */
783 
#define DMA1TSEL_29            (29*0x0100u)   /* DMA channel 1 transfer select 29: Multiplier ready */
784 
#define DMA1TSEL_30            (30*0x0100u)   /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
785 
#define DMA1TSEL_31            (31*0x0100u)   /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
786 
 
787 
#define DMA2TSEL_0             (0*0x0001u)    /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
788 
#define DMA2TSEL_1             (1*0x0001u)    /* DMA channel 2 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
789 
#define DMA2TSEL_2             (2*0x0001u)    /* DMA channel 2 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
790 
#define DMA2TSEL_3             (3*0x0001u)    /* DMA channel 2 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
791 
#define DMA2TSEL_4             (4*0x0001u)    /* DMA channel 2 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
792 
#define DMA2TSEL_5             (5*0x0001u)    /* DMA channel 2 transfer select 5:  TimerB (TB0CCR0.IFG) */
793 
#define DMA2TSEL_6             (6*0x0001u)    /* DMA channel 2 transfer select 6:  TimerB (TB0CCR2.IFG) */
794 
#define DMA2TSEL_7             (7*0x0001u)    /* DMA channel 2 transfer select 7:  Reserved */
795 
#define DMA2TSEL_8             (8*0x0001u)    /* DMA channel 2 transfer select 8:  Reserved */
796 
#define DMA2TSEL_9             (9*0x0001u)    /* DMA channel 2 transfer select 9:  Reserved */
797 
#define DMA2TSEL_10            (10*0x0001u)   /* DMA channel 2 transfer select 10: Reserved */
798 
#define DMA2TSEL_11            (11*0x0001u)   /* DMA channel 2 transfer select 11: Reserved */
799 
#define DMA2TSEL_12            (12*0x0001u)   /* DMA channel 2 transfer select 12: Reserved */
800 
#define DMA2TSEL_13            (13*0x0001u)   /* DMA channel 2 transfer select 13: Reserved */
801 
#define DMA2TSEL_14            (14*0x0001u)   /* DMA channel 2 transfer select 14: Reserved */
802 
#define DMA2TSEL_15            (15*0x0001u)   /* DMA channel 2 transfer select 15: Reserved */
803 
#define DMA2TSEL_16            (16*0x0001u)   /* DMA channel 2 transfer select 16: USCIA0 receive */
804 
#define DMA2TSEL_17            (17*0x0001u)   /* DMA channel 2 transfer select 17: USCIA0 transmit */
805 
#define DMA2TSEL_18            (18*0x0001u)   /* DMA channel 2 transfer select 18: USCIB0 receive */
806 
#define DMA2TSEL_19            (19*0x0001u)   /* DMA channel 2 transfer select 19: USCIB0 transmit */
807 
#define DMA2TSEL_20            (20*0x0001u)   /* DMA channel 2 transfer select 20: USCIA1 receive */
808 
#define DMA2TSEL_21            (21*0x0001u)   /* DMA channel 2 transfer select 21: USCIA1 transmit */
809 
#define DMA2TSEL_22            (22*0x0001u)   /* DMA channel 2 transfer select 22: USCIB1 receive */
810 
#define DMA2TSEL_23            (23*0x0001u)   /* DMA channel 2 transfer select 23: USCIB1 transmit */
811 
#define DMA2TSEL_24            (24*0x0001u)   /* DMA channel 2 transfer select 24: ADC12IFGx */
812 
#define DMA2TSEL_25            (25*0x0001u)   /* DMA channel 2 transfer select 25: Reserved */
813 
#define DMA2TSEL_26            (26*0x0001u)   /* DMA channel 2 transfer select 26: Reserved */
814 
#define DMA2TSEL_27            (27*0x0001u)   /* DMA channel 2 transfer select 27: Reserved */
815 
#define DMA2TSEL_28            (28*0x0001u)   /* DMA channel 2 transfer select 28: Reserved */
816 
#define DMA2TSEL_29            (29*0x0001u)   /* DMA channel 2 transfer select 29: Multiplier ready */
817 
#define DMA2TSEL_30            (30*0x0001u)   /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
818 
#define DMA2TSEL_31            (31*0x0001u)   /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
819 
 
820 
#define DMA0TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
821 
#define DMA0TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
822 
#define DMA0TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
823 
#define DMA0TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 0 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
824 
#define DMA0TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 0 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
825 
#define DMA0TSEL__TB0CCR0      (5*0x0001u)    /* DMA channel 0 transfer select 5:  TimerB (TB0CCR0.IFG) */
826 
#define DMA0TSEL__TB0CCR2      (6*0x0001u)    /* DMA channel 0 transfer select 6:  TimerB (TB0CCR2.IFG) */
827 
#define DMA0TSEL__RES7         (7*0x0001u)    /* DMA channel 0 transfer select 7:  Reserved */
828 
#define DMA0TSEL__RES8         (8*0x0001u)    /* DMA channel 0 transfer select 8:  Reserved */
829 
#define DMA0TSEL__RES9         (9*0x0001u)    /* DMA channel 0 transfer select 9:  Reserved */
830 
#define DMA0TSEL__RES10        (10*0x0001u)   /* DMA channel 0 transfer select 10: Reserved */
831 
#define DMA0TSEL__RES11        (11*0x0001u)   /* DMA channel 0 transfer select 11: Reserved */
832 
#define DMA0TSEL__RES12        (12*0x0001u)   /* DMA channel 0 transfer select 12: Reserved */
833 
#define DMA0TSEL__RES13        (13*0x0001u)   /* DMA channel 0 transfer select 13: Reserved */
834 
#define DMA0TSEL__RES14        (14*0x0001u)   /* DMA channel 0 transfer select 14: Reserved */
835 
#define DMA0TSEL__RES15        (15*0x0001u)   /* DMA channel 0 transfer select 15: Reserved */
836 
#define DMA0TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 0 transfer select 16: USCIA0 receive */
837 
#define DMA0TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 0 transfer select 17: USCIA0 transmit */
838 
#define DMA0TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 0 transfer select 18: USCIB0 receive */
839 
#define DMA0TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 0 transfer select 19: USCIB0 transmit */
840 
#define DMA0TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 0 transfer select 20: USCIA1 receive */
841 
#define DMA0TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 0 transfer select 21: USCIA1 transmit */
842 
#define DMA0TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 0 transfer select 22: USCIB1 receive */
843 
#define DMA0TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 0 transfer select 23: USCIB1 transmit */
844 
#define DMA0TSEL__ADC12IFG     (24*0x0001u)   /* DMA channel 0 transfer select 24: ADC12IFGx */
845 
#define DMA0TSEL__RES25        (25*0x0001u)   /* DMA channel 0 transfer select 25: Reserved */
846 
#define DMA0TSEL__RES26        (26*0x0001u)   /* DMA channel 0 transfer select 26: Reserved */
847 
#define DMA0TSEL__RES27        (27*0x0001u)   /* DMA channel 0 transfer select 27: Reserved */
848 
#define DMA0TSEL__RES28        (28*0x0001u)   /* DMA channel 0 transfer select 28: Reserved */
849 
#define DMA0TSEL__MPY          (29*0x0001u)   /* DMA channel 0 transfer select 29: Multiplier ready */
850 
#define DMA0TSEL__DMA2IFG      (30*0x0001u)   /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
851 
#define DMA0TSEL__DMAE0        (31*0x0001u)   /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
852 
 
853 
#define DMA1TSEL__DMA_REQ      (0*0x0100u)    /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
854 
#define DMA1TSEL__TA0CCR0      (1*0x0100u)    /* DMA channel 1 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
855 
#define DMA1TSEL__TA0CCR2      (2*0x0100u)    /* DMA channel 1 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
856 
#define DMA1TSEL__TA1CCR0      (3*0x0100u)    /* DMA channel 1 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
857 
#define DMA1TSEL__TA1CCR2      (4*0x0100u)    /* DMA channel 1 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
858 
#define DMA1TSEL__TB0CCR0      (5*0x0100u)    /* DMA channel 1 transfer select 5:  TimerB (TB0CCR0.IFG) */
859 
#define DMA1TSEL__TB0CCR2      (6*0x0100u)    /* DMA channel 1 transfer select 6:  TimerB (TB0CCR2.IFG) */
860 
#define DMA1TSEL__RES7         (7*0x0100u)    /* DMA channel 1 transfer select 7:  Reserved */
861 
#define DMA1TSEL__RES8         (8*0x0100u)    /* DMA channel 1 transfer select 8:  Reserved */
862 
#define DMA1TSEL__RES9         (9*0x0100u)    /* DMA channel 1 transfer select 9:  Reserved */
863 
#define DMA1TSEL__RES10        (10*0x0100u)   /* DMA channel 1 transfer select 10: Reserved */
864 
#define DMA1TSEL__RES11        (11*0x0100u)   /* DMA channel 1 transfer select 11: Reserved */
865 
#define DMA1TSEL__RES12        (12*0x0100u)   /* DMA channel 1 transfer select 12: Reserved */
866 
#define DMA1TSEL__RES13        (13*0x0100u)   /* DMA channel 1 transfer select 13: Reserved */
867 
#define DMA1TSEL__RES14        (14*0x0100u)   /* DMA channel 1 transfer select 14: Reserved */
868 
#define DMA1TSEL__RES15        (15*0x0100u)   /* DMA channel 1 transfer select 15: Reserved */
869 
#define DMA1TSEL__USCIA0RX     (16*0x0100u)   /* DMA channel 1 transfer select 16: USCIA0 receive */
870 
#define DMA1TSEL__USCIA0TX     (17*0x0100u)   /* DMA channel 1 transfer select 17: USCIA0 transmit */
871 
#define DMA1TSEL__USCIB0RX     (18*0x0100u)   /* DMA channel 1 transfer select 18: USCIB0 receive */
872 
#define DMA1TSEL__USCIB0TX     (19*0x0100u)   /* DMA channel 1 transfer select 19: USCIB0 transmit */
873 
#define DMA1TSEL__USCIA1RX     (20*0x0100u)   /* DMA channel 1 transfer select 20: USCIA1 receive */
874 
#define DMA1TSEL__USCIA1TX     (21*0x0100u)   /* DMA channel 1 transfer select 21: USCIA1 transmit */
875 
#define DMA1TSEL__USCIB1RX     (22*0x0100u)   /* DMA channel 1 transfer select 22: USCIB1 receive */
876 
#define DMA1TSEL__USCIB1TX     (23*0x0100u)   /* DMA channel 1 transfer select 23: USCIB1 transmit */
877 
#define DMA1TSEL__ADC12IFG     (24*0x0100u)   /* DMA channel 1 transfer select 24: ADC12IFGx */
878 
#define DMA1TSEL__RES25        (25*0x0100u)   /* DMA channel 1 transfer select 25: Reserved */
879 
#define DMA1TSEL__RES26        (26*0x0100u)   /* DMA channel 1 transfer select 26: Reserved */
880 
#define DMA1TSEL__RES27        (27*0x0100u)   /* DMA channel 1 transfer select 27: Reserved */
881 
#define DMA1TSEL__RES28        (28*0x0100u)   /* DMA channel 1 transfer select 28: Reserved */
882 
#define DMA1TSEL__MPY          (29*0x0100u)   /* DMA channel 1 transfer select 29: Multiplier ready */
883 
#define DMA1TSEL__DMA0IFG      (30*0x0100u)   /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
884 
#define DMA1TSEL__DMAE0        (31*0x0100u)   /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
885 
 
886 
#define DMA2TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
887 
#define DMA2TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 2 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
888 
#define DMA2TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 2 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
889 
#define DMA2TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 2 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
890 
#define DMA2TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 2 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
891 
#define DMA2TSEL__TB0CCR0      (5*0x0001u)    /* DMA channel 2 transfer select 5:  TimerB (TB0CCR0.IFG) */
892 
#define DMA2TSEL__TB0CCR2      (6*0x0001u)    /* DMA channel 2 transfer select 6:  TimerB (TB0CCR2.IFG) */
893 
#define DMA2TSEL__RES7         (7*0x0001u)    /* DMA channel 2 transfer select 7:  Reserved */
894 
#define DMA2TSEL__RES8         (8*0x0001u)    /* DMA channel 2 transfer select 8:  Reserved */
895 
#define DMA2TSEL__RES9         (9*0x0001u)    /* DMA channel 2 transfer select 9:  Reserved */
896 
#define DMA2TSEL__RES10        (10*0x0001u)   /* DMA channel 2 transfer select 10: Reserved */
897 
#define DMA2TSEL__RES11        (11*0x0001u)   /* DMA channel 2 transfer select 11: Reserved */
898 
#define DMA2TSEL__RES12        (12*0x0001u)   /* DMA channel 2 transfer select 12: Reserved */
899 
#define DMA2TSEL__RES13        (13*0x0001u)   /* DMA channel 2 transfer select 13: Reserved */
900 
#define DMA2TSEL__RES14        (14*0x0001u)   /* DMA channel 2 transfer select 14: Reserved */
901 
#define DMA2TSEL__RES15        (15*0x0001u)   /* DMA channel 2 transfer select 15: Reserved */
902 
#define DMA2TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 2 transfer select 16: USCIA0 receive */
903 
#define DMA2TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 2 transfer select 17: USCIA0 transmit */
904 
#define DMA2TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 2 transfer select 18: USCIB0 receive */
905 
#define DMA2TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 2 transfer select 19: USCIB0 transmit */
906 
#define DMA2TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 2 transfer select 20: USCIA1 receive */
907 
#define DMA2TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 2 transfer select 21: USCIA1 transmit */
908 
#define DMA2TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 2 transfer select 22: USCIB1 receive */
909 
#define DMA2TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 2 transfer select 23: USCIB1 transmit */
910 
#define DMA2TSEL__ADC12IFG     (24*0x0001u)   /* DMA channel 2 transfer select 24: ADC12IFGx */
911 
#define DMA2TSEL__RES25        (25*0x0001u)   /* DMA channel 2 transfer select 25: Reserved */
912 
#define DMA2TSEL__RES26        (26*0x0001u)   /* DMA channel 2 transfer select 26: Reserved */
913 
#define DMA2TSEL__RES27        (27*0x0001u)   /* DMA channel 2 transfer select 27: Reserved */
914 
#define DMA2TSEL__RES28        (28*0x0001u)   /* DMA channel 2 transfer select 28: Reserved */
915 
#define DMA2TSEL__MPY          (29*0x0001u)   /* DMA channel 2 transfer select 29: Multiplier ready */
916 
#define DMA2TSEL__DMA1IFG      (30*0x0001u)   /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
917 
#define DMA2TSEL__DMAE0        (31*0x0001u)   /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
918 
 
919 
/*************************************************************
920 
* Flash Memory
921 
*************************************************************/
922 
#define __MSP430_HAS_FLASH__                  /* Definition to show that Module is available */
923 
 
924 
SFR_16BIT(FCTL1);                             /* FLASH Control 1 */
925 
SFR_8BIT(FCTL1_L);                            /* FLASH Control 1 */
926 
SFR_8BIT(FCTL1_H);                            /* FLASH Control 1 */
927 
//sfrbw    FCTL2               (0x0142)  /* FLASH Control 2 */
928 
SFR_16BIT(FCTL3);                             /* FLASH Control 3 */
929 
SFR_8BIT(FCTL3_L);                            /* FLASH Control 3 */
930 
SFR_8BIT(FCTL3_H);                            /* FLASH Control 3 */
931 
SFR_16BIT(FCTL4);                             /* FLASH Control 4 */
932 
SFR_8BIT(FCTL4_L);                            /* FLASH Control 4 */
933 
SFR_8BIT(FCTL4_H);                            /* FLASH Control 4 */
934 
 
935 
#define FRPW                   (0x9600)       /* Flash password returned by read */
936 
#define FWPW                   (0xA500)       /* Flash password for write */
937 
#define FXPW                   (0x3300)       /* for use with XOR instruction */
938 
#define FRKEY                  (0x9600)       /* (legacy definition) Flash key returned by read */
939 
#define FWKEY                  (0xA500)       /* (legacy definition) Flash key for write */
940 
#define FXKEY                  (0x3300)       /* (legacy definition) for use with XOR instruction */
941 
 
942 
/* FCTL1 Control Bits */
943 
//#define RESERVED            (0x0001)  /* Reserved */
944 
#define ERASE                  (0x0002)       /* Enable bit for Flash segment erase */
945 
#define MERAS                  (0x0004)       /* Enable bit for Flash mass erase */
946 
//#define RESERVED            (0x0008)  /* Reserved */
947 
//#define RESERVED            (0x0010)  /* Reserved */
948 
#define SWRT                   (0x0020)       /* Smart Write enable */
949 
#define WRT                    (0x0040)       /* Enable bit for Flash write */
950 
#define BLKWRT                 (0x0080)       /* Enable bit for Flash segment write */
951 
 
952 
/* FCTL1 Control Bits */
953 
//#define RESERVED            (0x0001)  /* Reserved */
954 
#define ERASE_L                (0x0002)       /* Enable bit for Flash segment erase */
955 
#define MERAS_L                (0x0004)       /* Enable bit for Flash mass erase */
956 
//#define RESERVED            (0x0008)  /* Reserved */
957 
//#define RESERVED            (0x0010)  /* Reserved */
958 
#define SWRT_L                 (0x0020)       /* Smart Write enable */
959 
#define WRT_L                  (0x0040)       /* Enable bit for Flash write */
960 
#define BLKWRT_L               (0x0080)       /* Enable bit for Flash segment write */
961 
 
962 
/* FCTL1 Control Bits */
963 
//#define RESERVED            (0x0001)  /* Reserved */
964 
//#define RESERVED            (0x0008)  /* Reserved */
965 
//#define RESERVED            (0x0010)  /* Reserved */
966 
 
967 
/* FCTL3 Control Bits */
968 
#define BUSY                   (0x0001)       /* Flash busy: 1 */
969 
#define KEYV                   (0x0002)       /* Flash Key violation flag */
970 
#define ACCVIFG                (0x0004)       /* Flash Access violation flag */
971 
#define WAIT                   (0x0008)       /* Wait flag for segment write */
972 
#define LOCK                   (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
973 
#define EMEX                   (0x0020)       /* Flash Emergency Exit */
974 
#define LOCKA                  (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
975 
//#define RESERVED            (0x0080)  /* Reserved */
976 
 
977 
/* FCTL3 Control Bits */
978 
#define BUSY_L                 (0x0001)       /* Flash busy: 1 */
979 
#define KEYV_L                 (0x0002)       /* Flash Key violation flag */
980 
#define ACCVIFG_L              (0x0004)       /* Flash Access violation flag */
981 
#define WAIT_L                 (0x0008)       /* Wait flag for segment write */
982 
#define LOCK_L                 (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
983 
#define EMEX_L                 (0x0020)       /* Flash Emergency Exit */
984 
#define LOCKA_L                (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
985 
//#define RESERVED            (0x0080)  /* Reserved */
986 
 
987 
/* FCTL3 Control Bits */
988 
//#define RESERVED            (0x0080)  /* Reserved */
989 
 
990 
/* FCTL4 Control Bits */
991 
#define VPE                    (0x0001)       /* Voltage Changed during Program Error Flag */
992 
#define MGR0                   (0x0010)       /* Marginal read 0 mode. */
993 
#define MGR1                   (0x0020)       /* Marginal read 1 mode. */
994 
#define LOCKINFO               (0x0080)       /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
995 
 
996 
/* FCTL4 Control Bits */
997 
#define VPE_L                  (0x0001)       /* Voltage Changed during Program Error Flag */
998 
#define MGR0_L                 (0x0010)       /* Marginal read 0 mode. */
999 
#define MGR1_L                 (0x0020)       /* Marginal read 1 mode. */
1000 
#define LOCKINFO_L             (0x0080)       /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
1001 
 
1002 
/* FCTL4 Control Bits */
1003 
 
1004 
/************************************************************
1005 
* HARDWARE MULTIPLIER 32Bit
1006 
************************************************************/
1007 
#define __MSP430_HAS_MPY32__                  /* Definition to show that Module is available */
1008 
 
1009 
SFR_16BIT(MPY);                               /* Multiply Unsigned/Operand 1 */
1010 
SFR_8BIT(MPY_L);                              /* Multiply Unsigned/Operand 1 */
1011 
SFR_8BIT(MPY_H);                              /* Multiply Unsigned/Operand 1 */
1012 
SFR_16BIT(MPYS);                              /* Multiply Signed/Operand 1 */
1013 
SFR_8BIT(MPYS_L);                             /* Multiply Signed/Operand 1 */
1014 
SFR_8BIT(MPYS_H);                             /* Multiply Signed/Operand 1 */
1015 
SFR_16BIT(MAC);                               /* Multiply Unsigned and Accumulate/Operand 1 */
1016 
SFR_8BIT(MAC_L);                              /* Multiply Unsigned and Accumulate/Operand 1 */
1017 
SFR_8BIT(MAC_H);                              /* Multiply Unsigned and Accumulate/Operand 1 */
1018 
SFR_16BIT(MACS);                              /* Multiply Signed and Accumulate/Operand 1 */
1019 
SFR_8BIT(MACS_L);                             /* Multiply Signed and Accumulate/Operand 1 */
1020 
SFR_8BIT(MACS_H);                             /* Multiply Signed and Accumulate/Operand 1 */
1021 
SFR_16BIT(OP2);                               /* Operand 2 */
1022 
SFR_8BIT(OP2_L);                              /* Operand 2 */
1023 
SFR_8BIT(OP2_H);                              /* Operand 2 */
1024 
SFR_16BIT(RESLO);                             /* Result Low Word */
1025 
SFR_8BIT(RESLO_L);                            /* Result Low Word */
1026 
SFR_8BIT(RESLO_H);                            /* Result Low Word */
1027 
SFR_16BIT(RESHI);                             /* Result High Word */
1028 
SFR_8BIT(RESHI_L);                            /* Result High Word */
1029 
SFR_8BIT(RESHI_H);                            /* Result High Word */
1030 
SFR_16BIT(SUMEXT);                            /* Sum Extend */
1031 
SFR_8BIT(SUMEXT_L);                           /* Sum Extend */
1032 
SFR_8BIT(SUMEXT_H);                           /* Sum Extend */
1033 
 
1034 
SFR_16BIT(MPY32L);                            /* 32-bit operand 1 - multiply - low word */
1035 
SFR_8BIT(MPY32L_L);                           /* 32-bit operand 1 - multiply - low word */
1036 
SFR_8BIT(MPY32L_H);                           /* 32-bit operand 1 - multiply - low word */
1037 
SFR_16BIT(MPY32H);                            /* 32-bit operand 1 - multiply - high word */
1038 
SFR_8BIT(MPY32H_L);                           /* 32-bit operand 1 - multiply - high word */
1039 
SFR_8BIT(MPY32H_H);                           /* 32-bit operand 1 - multiply - high word */
1040 
SFR_16BIT(MPYS32L);                           /* 32-bit operand 1 - signed multiply - low word */
1041 
SFR_8BIT(MPYS32L_L);                          /* 32-bit operand 1 - signed multiply - low word */
1042 
SFR_8BIT(MPYS32L_H);                          /* 32-bit operand 1 - signed multiply - low word */
1043 
SFR_16BIT(MPYS32H);                           /* 32-bit operand 1 - signed multiply - high word */
1044 
SFR_8BIT(MPYS32H_L);                          /* 32-bit operand 1 - signed multiply - high word */
1045 
SFR_8BIT(MPYS32H_H);                          /* 32-bit operand 1 - signed multiply - high word */
1046 
SFR_16BIT(MAC32L);                            /* 32-bit operand 1 - multiply accumulate - low word */
1047 
SFR_8BIT(MAC32L_L);                           /* 32-bit operand 1 - multiply accumulate - low word */
1048 
SFR_8BIT(MAC32L_H);                           /* 32-bit operand 1 - multiply accumulate - low word */
1049 
SFR_16BIT(MAC32H);                            /* 32-bit operand 1 - multiply accumulate - high word */
1050 
SFR_8BIT(MAC32H_L);                           /* 32-bit operand 1 - multiply accumulate - high word */
1051 
SFR_8BIT(MAC32H_H);                           /* 32-bit operand 1 - multiply accumulate - high word */
1052 
SFR_16BIT(MACS32L);                           /* 32-bit operand 1 - signed multiply accumulate - low word */
1053 
SFR_8BIT(MACS32L_L);                          /* 32-bit operand 1 - signed multiply accumulate - low word */
1054 
SFR_8BIT(MACS32L_H);                          /* 32-bit operand 1 - signed multiply accumulate - low word */
1055 
SFR_16BIT(MACS32H);                           /* 32-bit operand 1 - signed multiply accumulate - high word */
1056 
SFR_8BIT(MACS32H_L);                          /* 32-bit operand 1 - signed multiply accumulate - high word */
1057 
SFR_8BIT(MACS32H_H);                          /* 32-bit operand 1 - signed multiply accumulate - high word */
1058 
SFR_16BIT(OP2L);                              /* 32-bit operand 2 - low word */
1059 
SFR_8BIT(OP2L_L);                             /* 32-bit operand 2 - low word */
1060 
SFR_8BIT(OP2L_H);                             /* 32-bit operand 2 - low word */
1061 
SFR_16BIT(OP2H);                              /* 32-bit operand 2 - high word */
1062 
SFR_8BIT(OP2H_L);                             /* 32-bit operand 2 - high word */
1063 
SFR_8BIT(OP2H_H);                             /* 32-bit operand 2 - high word */
1064 
SFR_16BIT(RES0);                              /* 32x32-bit result 0 - least significant word */
1065 
SFR_8BIT(RES0_L);                             /* 32x32-bit result 0 - least significant word */
1066 
SFR_8BIT(RES0_H);                             /* 32x32-bit result 0 - least significant word */
1067 
SFR_16BIT(RES1);                              /* 32x32-bit result 1 */
1068 
SFR_8BIT(RES1_L);                             /* 32x32-bit result 1 */
1069 
SFR_8BIT(RES1_H);                             /* 32x32-bit result 1 */
1070 
SFR_16BIT(RES2);                              /* 32x32-bit result 2 */
1071 
SFR_8BIT(RES2_L);                             /* 32x32-bit result 2 */
1072 
SFR_8BIT(RES2_H);                             /* 32x32-bit result 2 */
1073 
SFR_16BIT(RES3);                              /* 32x32-bit result 3 - most significant word */
1074 
SFR_8BIT(RES3_L);                             /* 32x32-bit result 3 - most significant word */
1075 
SFR_8BIT(RES3_H);                             /* 32x32-bit result 3 - most significant word */
1076 
SFR_16BIT(MPY32CTL0);                         /* MPY32 Control Register 0 */
1077 
SFR_8BIT(MPY32CTL0_L);                        /* MPY32 Control Register 0 */
1078 
SFR_8BIT(MPY32CTL0_H);                        /* MPY32 Control Register 0 */
1079 
 
1080 
#define MPY_B                  MPY_L          /* Multiply Unsigned/Operand 1 (Byte Access) */
1081 
#define MPYS_B                 MPYS_L         /* Multiply Signed/Operand 1 (Byte Access) */
1082 
#define MAC_B                  MAC_L          /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
1083 
#define MACS_B                 MACS_L         /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
1084 
#define OP2_B                  OP2_L          /* Operand 2 (Byte Access) */
1085 
#define MPY32L_B               MPY32L_L       /* 32-bit operand 1 - multiply - low word (Byte Access) */
1086 
#define MPY32H_B               MPY32H_L       /* 32-bit operand 1 - multiply - high word (Byte Access) */
1087 
#define MPYS32L_B              MPYS32L_L      /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
1088 
#define MPYS32H_B              MPYS32H_L      /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
1089 
#define MAC32L_B               MAC32L_L       /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
1090 
#define MAC32H_B               MAC32H_L       /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
1091 
#define MACS32L_B              MACS32L_L      /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
1092 
#define MACS32H_B              MACS32H_L      /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
1093 
#define OP2L_B                 OP2L_L         /* 32-bit operand 2 - low word (Byte Access) */
1094 
#define OP2H_B                 OP2H_L         /* 32-bit operand 2 - high word (Byte Access) */
1095 
 
1096 
/* MPY32CTL0 Control Bits */
1097 
#define MPYC                   (0x0001)       /* Carry of the multiplier */
1098 
//#define RESERVED            (0x0002)  /* Reserved */
1099 
#define MPYFRAC                (0x0004)       /* Fractional mode */
1100 
#define MPYSAT                 (0x0008)       /* Saturation mode */
1101 
#define MPYM0                  (0x0010)       /* Multiplier mode Bit:0 */
1102 
#define MPYM1                  (0x0020)       /* Multiplier mode Bit:1 */
1103 
#define OP1_32                 (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
1104 
#define OP2_32                 (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
1105 
#define MPYDLYWRTEN            (0x0100)       /* Delayed write enable */
1106 
#define MPYDLY32               (0x0200)       /* Delayed write mode */
1107 
 
1108 
/* MPY32CTL0 Control Bits */
1109 
#define MPYC_L                 (0x0001)       /* Carry of the multiplier */
1110 
//#define RESERVED            (0x0002)  /* Reserved */
1111 
#define MPYFRAC_L              (0x0004)       /* Fractional mode */
1112 
#define MPYSAT_L               (0x0008)       /* Saturation mode */
1113 
#define MPYM0_L                (0x0010)       /* Multiplier mode Bit:0 */
1114 
#define MPYM1_L                (0x0020)       /* Multiplier mode Bit:1 */
1115 
#define OP1_32_L               (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
1116 
#define OP2_32_L               (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
1117 
 
1118 
/* MPY32CTL0 Control Bits */
1119 
//#define RESERVED            (0x0002)  /* Reserved */
1120 
#define MPYDLYWRTEN_H          (0x0001)       /* Delayed write enable */
1121 
#define MPYDLY32_H             (0x0002)       /* Delayed write mode */
1122 
 
1123 
#define MPYM_0                 (0x0000)       /* Multiplier mode: MPY */
1124 
#define MPYM_1                 (0x0010)       /* Multiplier mode: MPYS */
1125 
#define MPYM_2                 (0x0020)       /* Multiplier mode: MAC */
1126 
#define MPYM_3                 (0x0030)       /* Multiplier mode: MACS */
1127 
#define MPYM__MPY              (0x0000)       /* Multiplier mode: MPY */
1128 
#define MPYM__MPYS             (0x0010)       /* Multiplier mode: MPYS */
1129 
#define MPYM__MAC              (0x0020)       /* Multiplier mode: MAC */
1130 
#define MPYM__MACS             (0x0030)       /* Multiplier mode: MACS */
1131 
 
1132 
/************************************************************
1133 
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
1134 
************************************************************/
1135 
#define __MSP430_HAS_PORT1_R__                /* Definition to show that Module is available */
1136 
#define __MSP430_HAS_PORT2_R__                /* Definition to show that Module is available */
1137 
#define __MSP430_HAS_PORTA_R__                /* Definition to show that Module is available */
1138 
 
1139 
SFR_16BIT(PAIN);                              /* Port A Input */
1140 
SFR_8BIT(PAIN_L);                             /* Port A Input */
1141 
SFR_8BIT(PAIN_H);                             /* Port A Input */
1142 
SFR_16BIT(PAOUT);                             /* Port A Output */
1143 
SFR_8BIT(PAOUT_L);                            /* Port A Output */
1144 
SFR_8BIT(PAOUT_H);                            /* Port A Output */
1145 
SFR_16BIT(PADIR);                             /* Port A Direction */
1146 
SFR_8BIT(PADIR_L);                            /* Port A Direction */
1147 
SFR_8BIT(PADIR_H);                            /* Port A Direction */
1148 
SFR_16BIT(PAREN);                             /* Port A Resistor Enable */
1149 
SFR_8BIT(PAREN_L);                            /* Port A Resistor Enable */
1150 
SFR_8BIT(PAREN_H);                            /* Port A Resistor Enable */
1151 
SFR_16BIT(PADS);                              /* Port A Resistor Drive Strenght */
1152 
SFR_8BIT(PADS_L);                             /* Port A Resistor Drive Strenght */
1153 
SFR_8BIT(PADS_H);                             /* Port A Resistor Drive Strenght */
1154 
SFR_16BIT(PASEL);                             /* Port A Selection */
1155 
SFR_8BIT(PASEL_L);                            /* Port A Selection */
1156 
SFR_8BIT(PASEL_H);                            /* Port A Selection */
1157 
SFR_16BIT(PAIES);                             /* Port A Interrupt Edge Select */
1158 
SFR_8BIT(PAIES_L);                            /* Port A Interrupt Edge Select */
1159 
SFR_8BIT(PAIES_H);                            /* Port A Interrupt Edge Select */
1160 
SFR_16BIT(PAIE);                              /* Port A Interrupt Enable */
1161 
SFR_8BIT(PAIE_L);                             /* Port A Interrupt Enable */
1162 
SFR_8BIT(PAIE_H);                             /* Port A Interrupt Enable */
1163 
SFR_16BIT(PAIFG);                             /* Port A Interrupt Flag */
1164 
SFR_8BIT(PAIFG_L);                            /* Port A Interrupt Flag */
1165 
SFR_8BIT(PAIFG_H);                            /* Port A Interrupt Flag */
1166 
 
1167 
 
1168 
SFR_16BIT(P1IV);                              /* Port 1 Interrupt Vector Word */
1169 
SFR_16BIT(P2IV);                              /* Port 2 Interrupt Vector Word */
1170 
#define P1IN                   (PAIN_L)       /* Port 1 Input */
1171 
#define P1OUT                  (PAOUT_L)      /* Port 1 Output */
1172 
#define P1DIR                  (PADIR_L)      /* Port 1 Direction */
1173 
#define P1REN                  (PAREN_L)      /* Port 1 Resistor Enable */
1174 
#define P1DS                   (PADS_L)       /* Port 1 Resistor Drive Strenght */
1175 
#define P1SEL                  (PASEL_L)      /* Port 1 Selection */
1176 
#define P1IES                  (PAIES_L)      /* Port 1 Interrupt Edge Select */
1177 
#define P1IE                   (PAIE_L)       /* Port 1 Interrupt Enable */
1178 
#define P1IFG                  (PAIFG_L)      /* Port 1 Interrupt Flag */
1179 
 
1180 
//Definitions for P1IV
1181 
#define P1IV_NONE              (0x0000)       /* No Interrupt pending */
1182 
#define P1IV_P1IFG0            (0x0002)       /* P1IV P1IFG.0 */
1183 
#define P1IV_P1IFG1            (0x0004)       /* P1IV P1IFG.1 */
1184 
#define P1IV_P1IFG2            (0x0006)       /* P1IV P1IFG.2 */
1185 
#define P1IV_P1IFG3            (0x0008)       /* P1IV P1IFG.3 */
1186 
#define P1IV_P1IFG4            (0x000A)       /* P1IV P1IFG.4 */
1187 
#define P1IV_P1IFG5            (0x000C)       /* P1IV P1IFG.5 */
1188 
#define P1IV_P1IFG6            (0x000E)       /* P1IV P1IFG.6 */
1189 
#define P1IV_P1IFG7            (0x0010)       /* P1IV P1IFG.7 */
1190 
 
1191 
#define P2IN                   (PAIN_H)       /* Port 2 Input */
1192 
#define P2OUT                  (PAOUT_H)      /* Port 2 Output */
1193 
#define P2DIR                  (PADIR_H)      /* Port 2 Direction */
1194 
#define P2REN                  (PAREN_H)      /* Port 2 Resistor Enable */
1195 
#define P2DS                   (PADS_H)       /* Port 2 Resistor Drive Strenght */
1196 
#define P2SEL                  (PASEL_H)      /* Port 2 Selection */
1197 
#define P2IES                  (PAIES_H)      /* Port 2 Interrupt Edge Select */
1198 
#define P2IE                   (PAIE_H)       /* Port 2 Interrupt Enable */
1199 
#define P2IFG                  (PAIFG_H)      /* Port 2 Interrupt Flag */
1200 
 
1201 
//Definitions for P2IV
1202 
#define P2IV_NONE              (0x0000)       /* No Interrupt pending */
1203 
#define P2IV_P2IFG0            (0x0002)       /* P2IV P2IFG.0 */
1204 
#define P2IV_P2IFG1            (0x0004)       /* P2IV P2IFG.1 */
1205 
#define P2IV_P2IFG2            (0x0006)       /* P2IV P2IFG.2 */
1206 
#define P2IV_P2IFG3            (0x0008)       /* P2IV P2IFG.3 */
1207 
#define P2IV_P2IFG4            (0x000A)       /* P2IV P2IFG.4 */
1208 
#define P2IV_P2IFG5            (0x000C)       /* P2IV P2IFG.5 */
1209 
#define P2IV_P2IFG6            (0x000E)       /* P2IV P2IFG.6 */
1210 
#define P2IV_P2IFG7            (0x0010)       /* P2IV P2IFG.7 */
1211 
 
1212 
 
1213 
/************************************************************
1214 
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
1215 
************************************************************/
1216 
#define __MSP430_HAS_PORT3_R__                /* Definition to show that Module is available */
1217 
#define __MSP430_HAS_PORT4_R__                /* Definition to show that Module is available */
1218 
#define __MSP430_HAS_PORTB_R__                /* Definition to show that Module is available */
1219 
 
1220 
SFR_16BIT(PBIN);                              /* Port B Input */
1221 
SFR_8BIT(PBIN_L);                             /* Port B Input */
1222 
SFR_8BIT(PBIN_H);                             /* Port B Input */
1223 
SFR_16BIT(PBOUT);                             /* Port B Output */
1224 
SFR_8BIT(PBOUT_L);                            /* Port B Output */
1225 
SFR_8BIT(PBOUT_H);                            /* Port B Output */
1226 
SFR_16BIT(PBDIR);                             /* Port B Direction */
1227 
SFR_8BIT(PBDIR_L);                            /* Port B Direction */
1228 
SFR_8BIT(PBDIR_H);                            /* Port B Direction */
1229 
SFR_16BIT(PBREN);                             /* Port B Resistor Enable */
1230 
SFR_8BIT(PBREN_L);                            /* Port B Resistor Enable */
1231 
SFR_8BIT(PBREN_H);                            /* Port B Resistor Enable */
1232 
SFR_16BIT(PBDS);                              /* Port B Resistor Drive Strenght */
1233 
SFR_8BIT(PBDS_L);                             /* Port B Resistor Drive Strenght */
1234 
SFR_8BIT(PBDS_H);                             /* Port B Resistor Drive Strenght */
1235 
SFR_16BIT(PBSEL);                             /* Port B Selection */
1236 
SFR_8BIT(PBSEL_L);                            /* Port B Selection */
1237 
SFR_8BIT(PBSEL_H);                            /* Port B Selection */
1238 
 
1239 
 
1240 
#define P3IN                   (PBIN_L)       /* Port 3 Input */
1241 
#define P3OUT                  (PBOUT_L)      /* Port 3 Output */
1242 
#define P3DIR                  (PBDIR_L)      /* Port 3 Direction */
1243 
#define P3REN                  (PBREN_L)      /* Port 3 Resistor Enable */
1244 
#define P3DS                   (PBDS_L)       /* Port 3 Resistor Drive Strenght */
1245 
#define P3SEL                  (PBSEL_L)      /* Port 3 Selection */
1246 
 
1247 
#define P4IN                   (PBIN_H)       /* Port 4 Input */
1248 
#define P4OUT                  (PBOUT_H)      /* Port 4 Output */
1249 
#define P4DIR                  (PBDIR_H)      /* Port 4 Direction */
1250 
#define P4REN                  (PBREN_H)      /* Port 4 Resistor Enable */
1251 
#define P4DS                   (PBDS_H)       /* Port 4 Resistor Drive Strenght */
1252 
#define P4SEL                  (PBSEL_H)      /* Port 4 Selection */
1253 
 
1254 
 
1255 
/************************************************************
1256 
* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
1257 
************************************************************/
1258 
#define __MSP430_HAS_PORT5_R__                /* Definition to show that Module is available */
1259 
#define __MSP430_HAS_PORT6_R__                /* Definition to show that Module is available */
1260 
#define __MSP430_HAS_PORTC_R__                /* Definition to show that Module is available */
1261 
 
1262 
SFR_16BIT(PCIN);                              /* Port C Input */
1263 
SFR_8BIT(PCIN_L);                             /* Port C Input */
1264 
SFR_8BIT(PCIN_H);                             /* Port C Input */
1265 
SFR_16BIT(PCOUT);                             /* Port C Output */
1266 
SFR_8BIT(PCOUT_L);                            /* Port C Output */
1267 
SFR_8BIT(PCOUT_H);                            /* Port C Output */
1268 
SFR_16BIT(PCDIR);                             /* Port C Direction */
1269 
SFR_8BIT(PCDIR_L);                            /* Port C Direction */
1270 
SFR_8BIT(PCDIR_H);                            /* Port C Direction */
1271 
SFR_16BIT(PCREN);                             /* Port C Resistor Enable */
1272 
SFR_8BIT(PCREN_L);                            /* Port C Resistor Enable */
1273 
SFR_8BIT(PCREN_H);                            /* Port C Resistor Enable */
1274 
SFR_16BIT(PCDS);                              /* Port C Resistor Drive Strenght */
1275 
SFR_8BIT(PCDS_L);                             /* Port C Resistor Drive Strenght */
1276 
SFR_8BIT(PCDS_H);                             /* Port C Resistor Drive Strenght */
1277 
SFR_16BIT(PCSEL);                             /* Port C Selection */
1278 
SFR_8BIT(PCSEL_L);                            /* Port C Selection */
1279 
SFR_8BIT(PCSEL_H);                            /* Port C Selection */
1280 
 
1281 
 
1282 
#define P5IN                   (PCIN_L)       /* Port 5 Input */
1283 
#define P5OUT                  (PCOUT_L)      /* Port 5 Output */
1284 
#define P5DIR                  (PCDIR_L)      /* Port 5 Direction */
1285 
#define P5REN                  (PCREN_L)      /* Port 5 Resistor Enable */
1286 
#define P5DS                   (PCDS_L)       /* Port 5 Resistor Drive Strenght */
1287 
#define P5SEL                  (PCSEL_L)      /* Port 5 Selection */
1288 
 
1289 
#define P6IN                   (PCIN_H)       /* Port 6 Input */
1290 
#define P6OUT                  (PCOUT_H)      /* Port 6 Output */
1291 
#define P6DIR                  (PCDIR_H)      /* Port 6 Direction */
1292 
#define P6REN                  (PCREN_H)      /* Port 6 Resistor Enable */
1293 
#define P6DS                   (PCDS_H)       /* Port 6 Resistor Drive Strenght */
1294 
#define P6SEL                  (PCSEL_H)      /* Port 6 Selection */
1295 
 
1296 
 
1297 
/************************************************************
1298 
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
1299 
************************************************************/
1300 
#define __MSP430_HAS_PORT7_R__                /* Definition to show that Module is available */
1301 
#define __MSP430_HAS_PORT8_R__                /* Definition to show that Module is available */
1302 
#define __MSP430_HAS_PORTD_R__                /* Definition to show that Module is available */
1303 
 
1304 
SFR_16BIT(PDIN);                              /* Port D Input */
1305 
SFR_8BIT(PDIN_L);                             /* Port D Input */
1306 
SFR_8BIT(PDIN_H);                             /* Port D Input */
1307 
SFR_16BIT(PDOUT);                             /* Port D Output */
1308 
SFR_8BIT(PDOUT_L);                            /* Port D Output */
1309 
SFR_8BIT(PDOUT_H);                            /* Port D Output */
1310 
SFR_16BIT(PDDIR);                             /* Port D Direction */
1311 
SFR_8BIT(PDDIR_L);                            /* Port D Direction */
1312 
SFR_8BIT(PDDIR_H);                            /* Port D Direction */
1313 
SFR_16BIT(PDREN);                             /* Port D Resistor Enable */
1314 
SFR_8BIT(PDREN_L);                            /* Port D Resistor Enable */
1315 
SFR_8BIT(PDREN_H);                            /* Port D Resistor Enable */
1316 
SFR_16BIT(PDDS);                              /* Port D Resistor Drive Strenght */
1317 
SFR_8BIT(PDDS_L);                             /* Port D Resistor Drive Strenght */
1318 
SFR_8BIT(PDDS_H);                             /* Port D Resistor Drive Strenght */
1319 
SFR_16BIT(PDSEL);                             /* Port D Selection */
1320 
SFR_8BIT(PDSEL_L);                            /* Port D Selection */
1321 
SFR_8BIT(PDSEL_H);                            /* Port D Selection */
1322 
 
1323 
 
1324 
#define P7IN                   (PDIN_L)       /* Port 7 Input */
1325 
#define P7OUT                  (PDOUT_L)      /* Port 7 Output */
1326 
#define P7DIR                  (PDDIR_L)      /* Port 7 Direction */
1327 
#define P7REN                  (PDREN_L)      /* Port 7 Resistor Enable */
1328 
#define P7DS                   (PDDS_L)       /* Port 7 Resistor Drive Strenght */
1329 
#define P7SEL                  (PDSEL_L)      /* Port 7 Selection */
1330 
 
1331 
#define P8IN                   (PDIN_H)       /* Port 8 Input */
1332 
#define P8OUT                  (PDOUT_H)      /* Port 8 Output */
1333 
#define P8DIR                  (PDDIR_H)      /* Port 8 Direction */
1334 
#define P8REN                  (PDREN_H)      /* Port 8 Resistor Enable */
1335 
#define P8DS                   (PDDS_H)       /* Port 8 Resistor Drive Strenght */
1336 
#define P8SEL                  (PDSEL_H)      /* Port 8 Selection */
1337 
 
1338 
 
1339 
/************************************************************
1340 
* DIGITAL I/O Port9/10 Pull up / Pull down Resistors
1341 
************************************************************/
1342 
#define __MSP430_HAS_PORT9_R__                /* Definition to show that Module is available */
1343 
#define __MSP430_HAS_PORT10_R__                /* Definition to show that Module is available */
1344 
#define __MSP430_HAS_PORTE_R__                /* Definition to show that Module is available */
1345 
 
1346 
SFR_16BIT(PEIN);                              /* Port E Input */
1347 
SFR_8BIT(PEIN_L);                             /* Port E Input */
1348 
SFR_8BIT(PEIN_H);                             /* Port E Input */
1349 
SFR_16BIT(PEOUT);                             /* Port E Output */
1350 
SFR_8BIT(PEOUT_L);                            /* Port E Output */
1351 
SFR_8BIT(PEOUT_H);                            /* Port E Output */
1352 
SFR_16BIT(PEDIR);                             /* Port E Direction */
1353 
SFR_8BIT(PEDIR_L);                            /* Port E Direction */
1354 
SFR_8BIT(PEDIR_H);                            /* Port E Direction */
1355 
SFR_16BIT(PEREN);                             /* Port E Resistor Enable */
1356 
SFR_8BIT(PEREN_L);                            /* Port E Resistor Enable */
1357 
SFR_8BIT(PEREN_H);                            /* Port E Resistor Enable */
1358 
SFR_16BIT(PEDS);                              /* Port E Resistor Drive Strenght */
1359 
SFR_8BIT(PEDS_L);                             /* Port E Resistor Drive Strenght */
1360 
SFR_8BIT(PEDS_H);                             /* Port E Resistor Drive Strenght */
1361 
SFR_16BIT(PESEL);                             /* Port E Selection */
1362 
SFR_8BIT(PESEL_L);                            /* Port E Selection */
1363 
SFR_8BIT(PESEL_H);                            /* Port E Selection */
1364 
 
1365 
 
1366 
#define P9IN                   (PEIN_L)       /* Port 9 Input */
1367 
#define P9OUT                  (PEOUT_L)      /* Port 9 Output */
1368 
#define P9DIR                  (PEDIR_L)      /* Port 9 Direction */
1369 
#define P9REN                  (PEREN_L)      /* Port 9 Resistor Enable */
1370 
#define P9DS                   (PEDS_L)       /* Port 9 Resistor Drive Strenght */
1371 
#define P9SEL                  (PESEL_L)      /* Port 9 Selection */
1372 
 
1373 
#define P10IN                  (PEIN_H)       /* Port 10 Input */
1374 
#define P10OUT                 (PEOUT_H)      /* Port 10 Output */
1375 
#define P10DIR                 (PEDIR_H)      /* Port 10 Direction */
1376 
#define P10REN                 (PEREN_H)      /* Port 10 Resistor Enable */
1377 
#define P10DS                  (PEDS_H)       /* Port 10 Resistor Drive Strenght */
1378 
#define P10SEL                 (PESEL_H)      /* Port 10 Selection */
1379 
 
1380 
 
1381 
/************************************************************
1382 
* DIGITAL I/O Port11 Pull up / Pull down Resistors
1383 
************************************************************/
1384 
#define __MSP430_HAS_PORT11_R__                /* Definition to show that Module is available */
1385 
#define __MSP430_HAS_PORTF_R__                /* Definition to show that Module is available */
1386 
 
1387 
SFR_16BIT(PFIN);                              /* Port F Input */
1388 
SFR_8BIT(PFIN_L);                             /* Port F Input */
1389 
SFR_8BIT(PFIN_H);                             /* Port F Input */
1390 
SFR_16BIT(PFOUT);                             /* Port F Output */
1391 
SFR_8BIT(PFOUT_L);                            /* Port F Output */
1392 
SFR_8BIT(PFOUT_H);                            /* Port F Output */
1393 
SFR_16BIT(PFDIR);                             /* Port F Direction */
1394 
SFR_8BIT(PFDIR_L);                            /* Port F Direction */
1395 
SFR_8BIT(PFDIR_H);                            /* Port F Direction */
1396 
SFR_16BIT(PFREN);                             /* Port F Resistor Enable */
1397 
SFR_8BIT(PFREN_L);                            /* Port F Resistor Enable */
1398 
SFR_8BIT(PFREN_H);                            /* Port F Resistor Enable */
1399 
SFR_16BIT(PFDS);                              /* Port F Resistor Drive Strenght */
1400 
SFR_8BIT(PFDS_L);                             /* Port F Resistor Drive Strenght */
1401 
SFR_8BIT(PFDS_H);                             /* Port F Resistor Drive Strenght */
1402 
SFR_16BIT(PFSEL);                             /* Port F Selection */
1403 
SFR_8BIT(PFSEL_L);                            /* Port F Selection */
1404 
SFR_8BIT(PFSEL_H);                            /* Port F Selection */
1405 
 
1406 
 
1407 
#define P11IN                  (PFIN_L)       /* Port 11 Input */
1408 
#define P11OUT                 (PFOUT_L)      /* Port 11 Output */
1409 
#define P11DIR                 (PFDIR_L)      /* Port 11 Direction */
1410 
#define P11REN                 (PFREN_L)      /* Port 11 Resistor Enable */
1411 
#define P11DS                  (PFDS_L)       /* Port 11 Resistor Drive Strenght */
1412 
#define P11SEL                 (PFSEL_L)      /* Port 11 Selection */
1413 
 
1414 
 
1415 
/************************************************************
1416 
* DIGITAL I/O PortJ Pull up / Pull down Resistors
1417 
************************************************************/
1418 
#define __MSP430_HAS_PORTJ_R__                /* Definition to show that Module is available */
1419 
 
1420 
SFR_16BIT(PJIN);                              /* Port J Input */
1421 
SFR_8BIT(PJIN_L);                             /* Port J Input */
1422 
SFR_8BIT(PJIN_H);                             /* Port J Input */
1423 
SFR_16BIT(PJOUT);                             /* Port J Output */
1424 
SFR_8BIT(PJOUT_L);                            /* Port J Output */
1425 
SFR_8BIT(PJOUT_H);                            /* Port J Output */
1426 
SFR_16BIT(PJDIR);                             /* Port J Direction */
1427 
SFR_8BIT(PJDIR_L);                            /* Port J Direction */
1428 
SFR_8BIT(PJDIR_H);                            /* Port J Direction */
1429 
SFR_16BIT(PJREN);                             /* Port J Resistor Enable */
1430 
SFR_8BIT(PJREN_L);                            /* Port J Resistor Enable */
1431 
SFR_8BIT(PJREN_H);                            /* Port J Resistor Enable */
1432 
SFR_16BIT(PJDS);                              /* Port J Resistor Drive Strenght */
1433 
SFR_8BIT(PJDS_L);                             /* Port J Resistor Drive Strenght */
1434 
SFR_8BIT(PJDS_H);                             /* Port J Resistor Drive Strenght */
1435 
 
1436 
/************************************************************
1437 
* PMM - Power Management System
1438 
************************************************************/
1439 
#define __MSP430_HAS_PMM__                    /* Definition to show that Module is available */
1440 
 
1441 
SFR_16BIT(PMMCTL0);                           /* PMM Control 0 */
1442 
SFR_8BIT(PMMCTL0_L);                          /* PMM Control 0 */
1443 
SFR_8BIT(PMMCTL0_H);                          /* PMM Control 0 */
1444 
SFR_16BIT(PMMCTL1);                           /* PMM Control 1 */
1445 
SFR_8BIT(PMMCTL1_L);                          /* PMM Control 1 */
1446 
SFR_8BIT(PMMCTL1_H);                          /* PMM Control 1 */
1447 
SFR_16BIT(SVSMHCTL);                          /* SVS and SVM high side control register */
1448 
SFR_8BIT(SVSMHCTL_L);                         /* SVS and SVM high side control register */
1449 
SFR_8BIT(SVSMHCTL_H);                         /* SVS and SVM high side control register */
1450 
SFR_16BIT(SVSMLCTL);                          /* SVS and SVM low side control register */
1451 
SFR_8BIT(SVSMLCTL_L);                         /* SVS and SVM low side control register */
1452 
SFR_8BIT(SVSMLCTL_H);                         /* SVS and SVM low side control register */
1453 
SFR_16BIT(SVSMIO);                            /* SVSIN and SVSOUT control register */
1454 
SFR_8BIT(SVSMIO_L);                           /* SVSIN and SVSOUT control register */
1455 
SFR_8BIT(SVSMIO_H);                           /* SVSIN and SVSOUT control register */
1456 
SFR_16BIT(PMMIFG);                            /* PMM Interrupt Flag */
1457 
SFR_8BIT(PMMIFG_L);                           /* PMM Interrupt Flag */
1458 
SFR_8BIT(PMMIFG_H);                           /* PMM Interrupt Flag */
1459 
SFR_16BIT(PMMRIE);                            /* PMM and RESET Interrupt Enable */
1460 
SFR_8BIT(PMMRIE_L);                           /* PMM and RESET Interrupt Enable */
1461 
SFR_8BIT(PMMRIE_H);                           /* PMM and RESET Interrupt Enable */
1462 
 
1463 
#define PMMPW                  (0xA500)       /* PMM Register Write Password */
1464 
#define PMMPW_H                (0xA5)         /* PMM Register Write Password for high word access */
1465 
 
1466 
/* PMMCTL0 Control Bits */
1467 
#define PMMCOREV0              (0x0001)       /* PMM Core Voltage Bit: 0 */
1468 
#define PMMCOREV1              (0x0002)       /* PMM Core Voltage Bit: 1 */
1469 
#define PMMSWBOR               (0x0004)       /* PMM Software BOR */
1470 
#define PMMSWPOR               (0x0008)       /* PMM Software POR */
1471 
#define PMMREGOFF              (0x0010)       /* PMM Turn Regulator off */
1472 
#define PMMHPMRE               (0x0080)       /* PMM Global High Power Module Request Enable */
1473 
 
1474 
/* PMMCTL0 Control Bits */
1475 
#define PMMCOREV0_L            (0x0001)       /* PMM Core Voltage Bit: 0 */
1476 
#define PMMCOREV1_L            (0x0002)       /* PMM Core Voltage Bit: 1 */
1477 
#define PMMSWBOR_L             (0x0004)       /* PMM Software BOR */
1478 
#define PMMSWPOR_L             (0x0008)       /* PMM Software POR */
1479 
#define PMMREGOFF_L            (0x0010)       /* PMM Turn Regulator off */
1480 
#define PMMHPMRE_L             (0x0080)       /* PMM Global High Power Module Request Enable */
1481 
 
1482 
/* PMMCTL0 Control Bits */
1483 
 
1484 
#define PMMCOREV_0             (0x0000)       /* PMM Core Voltage 0 (1.35V) */
1485 
#define PMMCOREV_1             (0x0001)       /* PMM Core Voltage 1 (1.55V) */
1486 
#define PMMCOREV_2             (0x0002)       /* PMM Core Voltage 2 (1.75V) */
1487 
#define PMMCOREV_3             (0x0003)       /* PMM Core Voltage 3 (1.85V) */
1488 
 
1489 
/* PMMCTL1 Control Bits */
1490 
#define PMMREFMD               (0x0001)       /* PMM Reference Mode */
1491 
#define PMMCMD0                (0x0010)       /* PMM Voltage Regulator Current Mode Bit: 0 */
1492 
#define PMMCMD1                (0x0020)       /* PMM Voltage Regulator Current Mode Bit: 1 */
1493 
 
1494 
/* PMMCTL1 Control Bits */
1495 
#define PMMREFMD_L             (0x0001)       /* PMM Reference Mode */
1496 
#define PMMCMD0_L              (0x0010)       /* PMM Voltage Regulator Current Mode Bit: 0 */
1497 
#define PMMCMD1_L              (0x0020)       /* PMM Voltage Regulator Current Mode Bit: 1 */
1498 
 
1499 
/* PMMCTL1 Control Bits */
1500 
 
1501 
/* SVSMHCTL Control Bits */
1502 
#define SVSMHRRL0              (0x0001)       /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
1503 
#define SVSMHRRL1              (0x0002)       /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
1504 
#define SVSMHRRL2              (0x0004)       /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
1505 
#define SVSMHDLYST             (0x0008)       /* SVS and SVM high side delay status */
1506 
#define SVSHMD                 (0x0010)       /* SVS high side mode */
1507 
#define SVSMHEVM               (0x0040)       /* SVS and SVM high side event mask */
1508 
#define SVSMHACE               (0x0080)       /* SVS and SVM high side auto control enable */
1509 
#define SVSHRVL0               (0x0100)       /* SVS high side reset voltage level Bit: 0 */
1510 
#define SVSHRVL1               (0x0200)       /* SVS high side reset voltage level Bit: 1 */
1511 
#define SVSHE                  (0x0400)       /* SVS high side enable */
1512 
#define SVSHFP                 (0x0800)       /* SVS high side full performace mode */
1513 
#define SVMHOVPE               (0x1000)       /* SVM high side over-voltage enable */
1514 
#define SVMHE                  (0x4000)       /* SVM high side enable */
1515 
#define SVMHFP                 (0x8000)       /* SVM high side full performace mode */
1516 
 
1517 
/* SVSMHCTL Control Bits */
1518 
#define SVSMHRRL0_L            (0x0001)       /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
1519 
#define SVSMHRRL1_L            (0x0002)       /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
1520 
#define SVSMHRRL2_L            (0x0004)       /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
1521 
#define SVSMHDLYST_L           (0x0008)       /* SVS and SVM high side delay status */
1522 
#define SVSHMD_L               (0x0010)       /* SVS high side mode */
1523 
#define SVSMHEVM_L             (0x0040)       /* SVS and SVM high side event mask */
1524 
#define SVSMHACE_L             (0x0080)       /* SVS and SVM high side auto control enable */
1525 
 
1526 
/* SVSMHCTL Control Bits */
1527 
#define SVSHRVL0_H             (0x0001)       /* SVS high side reset voltage level Bit: 0 */
1528 
#define SVSHRVL1_H             (0x0002)       /* SVS high side reset voltage level Bit: 1 */
1529 
#define SVSHE_H                (0x0004)       /* SVS high side enable */
1530 
#define SVSHFP_H               (0x0008)       /* SVS high side full performace mode */
1531 
#define SVMHOVPE_H             (0x0010)       /* SVM high side over-voltage enable */
1532 
#define SVMHE_H                (0x0040)       /* SVM high side enable */
1533 
#define SVMHFP_H               (0x0080)       /* SVM high side full performace mode */
1534 
 
1535 
#define SVSMHRRL_0             (0x0000)       /* SVS and SVM high side Reset Release Voltage Level 0 */
1536 
#define SVSMHRRL_1             (0x0001)       /* SVS and SVM high side Reset Release Voltage Level 1 */
1537 
#define SVSMHRRL_2             (0x0002)       /* SVS and SVM high side Reset Release Voltage Level 2 */
1538 
#define SVSMHRRL_3             (0x0003)       /* SVS and SVM high side Reset Release Voltage Level 3 */
1539 
#define SVSMHRRL_4             (0x0004)       /* SVS and SVM high side Reset Release Voltage Level 4 */
1540 
#define SVSMHRRL_5             (0x0005)       /* SVS and SVM high side Reset Release Voltage Level 5 */
1541 
#define SVSMHRRL_6             (0x0006)       /* SVS and SVM high side Reset Release Voltage Level 6 */
1542 
#define SVSMHRRL_7             (0x0007)       /* SVS and SVM high side Reset Release Voltage Level 7 */
1543 
 
1544 
#define SVSHRVL_0              (0x0000)       /* SVS high side Reset Release Voltage Level 0 */
1545 
#define SVSHRVL_1              (0x0100)       /* SVS high side Reset Release Voltage Level 1 */
1546 
#define SVSHRVL_2              (0x0200)       /* SVS high side Reset Release Voltage Level 2 */
1547 
#define SVSHRVL_3              (0x0300)       /* SVS high side Reset Release Voltage Level 3 */
1548 
 
1549 
/* SVSMLCTL Control Bits */
1550 
#define SVSMLRRL0              (0x0001)       /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
1551 
#define SVSMLRRL1              (0x0002)       /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
1552 
#define SVSMLRRL2              (0x0004)       /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
1553 
#define SVSMLDLYST             (0x0008)       /* SVS and SVM low side delay status */
1554 
#define SVSLMD                 (0x0010)       /* SVS low side mode */
1555 
#define SVSMLEVM               (0x0040)       /* SVS and SVM low side event mask */
1556 
#define SVSMLACE               (0x0080)       /* SVS and SVM low side auto control enable */
1557 
#define SVSLRVL0               (0x0100)       /* SVS low side reset voltage level Bit: 0 */
1558 
#define SVSLRVL1               (0x0200)       /* SVS low side reset voltage level Bit: 1 */
1559 
#define SVSLE                  (0x0400)       /* SVS low side enable */
1560 
#define SVSLFP                 (0x0800)       /* SVS low side full performace mode */
1561 
#define SVMLOVPE               (0x1000)       /* SVM low side over-voltage enable */
1562 
#define SVMLE                  (0x4000)       /* SVM low side enable */
1563 
#define SVMLFP                 (0x8000)       /* SVM low side full performace mode */
1564 
 
1565 
/* SVSMLCTL Control Bits */
1566 
#define SVSMLRRL0_L            (0x0001)       /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
1567 
#define SVSMLRRL1_L            (0x0002)       /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
1568 
#define SVSMLRRL2_L            (0x0004)       /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
1569 
#define SVSMLDLYST_L           (0x0008)       /* SVS and SVM low side delay status */
1570 
#define SVSLMD_L               (0x0010)       /* SVS low side mode */
1571 
#define SVSMLEVM_L             (0x0040)       /* SVS and SVM low side event mask */
1572 
#define SVSMLACE_L             (0x0080)       /* SVS and SVM low side auto control enable */
1573 
 
1574 
/* SVSMLCTL Control Bits */
1575 
#define SVSLRVL0_H             (0x0001)       /* SVS low side reset voltage level Bit: 0 */
1576 
#define SVSLRVL1_H             (0x0002)       /* SVS low side reset voltage level Bit: 1 */
1577 
#define SVSLE_H                (0x0004)       /* SVS low side enable */
1578 
#define SVSLFP_H               (0x0008)       /* SVS low side full performace mode */
1579 
#define SVMLOVPE_H             (0x0010)       /* SVM low side over-voltage enable */
1580 
#define SVMLE_H                (0x0040)       /* SVM low side enable */
1581 
#define SVMLFP_H               (0x0080)       /* SVM low side full performace mode */
1582 
 
1583 
#define SVSMLRRL_0             (0x0000)       /* SVS and SVM low side Reset Release Voltage Level 0 */
1584 
#define SVSMLRRL_1             (0x0001)       /* SVS and SVM low side Reset Release Voltage Level 1 */
1585 
#define SVSMLRRL_2             (0x0002)       /* SVS and SVM low side Reset Release Voltage Level 2 */
1586 
#define SVSMLRRL_3             (0x0003)       /* SVS and SVM low side Reset Release Voltage Level 3 */
1587 
#define SVSMLRRL_4             (0x0004)       /* SVS and SVM low side Reset Release Voltage Level 4 */
1588 
#define SVSMLRRL_5             (0x0005)       /* SVS and SVM low side Reset Release Voltage Level 5 */
1589 
#define SVSMLRRL_6             (0x0006)       /* SVS and SVM low side Reset Release Voltage Level 6 */
1590 
#define SVSMLRRL_7             (0x0007)       /* SVS and SVM low side Reset Release Voltage Level 7 */
1591 
 
1592 
#define SVSLRVL_0              (0x0000)       /* SVS low side Reset Release Voltage Level 0 */
1593 
#define SVSLRVL_1              (0x0100)       /* SVS low side Reset Release Voltage Level 1 */
1594 
#define SVSLRVL_2              (0x0200)       /* SVS low side Reset Release Voltage Level 2 */
1595 
#define SVSLRVL_3              (0x0300)       /* SVS low side Reset Release Voltage Level 3 */
1596 
 
1597 
/* SVSMIO Control Bits */
1598 
#define SVMLOE                 (0x0008)       /* SVM low side output enable */
1599 
#define SVMLVLROE              (0x0010)       /* SVM low side voltage level reached output enable */
1600 
#define SVMOUTPOL              (0x0020)       /* SVMOUT pin polarity */
1601 
#define SVMHOE                 (0x0800)       /* SVM high side output enable */
1602 
#define SVMHVLROE              (0x1000)       /* SVM high side voltage level reached output enable */
1603 
 
1604 
/* SVSMIO Control Bits */
1605 
#define SVMLOE_L               (0x0008)       /* SVM low side output enable */
1606 
#define SVMLVLROE_L            (0x0010)       /* SVM low side voltage level reached output enable */
1607 
#define SVMOUTPOL_L            (0x0020)       /* SVMOUT pin polarity */
1608 
 
1609 
/* SVSMIO Control Bits */
1610 
#define SVMHOE_H               (0x0008)       /* SVM high side output enable */
1611 
#define SVMHVLROE_H            (0x0010)       /* SVM high side voltage level reached output enable */
1612 
 
1613 
/* PMMIFG Control Bits */
1614 
#define SVSMLDLYIFG            (0x0001)       /* SVS and SVM low side Delay expired interrupt flag */
1615 
#define SVMLIFG                (0x0002)       /* SVM low side interrupt flag */
1616 
#define SVMLVLRIFG             (0x0004)       /* SVM low side Voltage Level Reached interrupt flag */
1617 
#define SVSMHDLYIFG            (0x0010)       /* SVS and SVM high side Delay expired interrupt flag */
1618 
#define SVMHIFG                (0x0020)       /* SVM high side interrupt flag */
1619 
#define SVMHVLRIFG             (0x0040)       /* SVM high side Voltage Level Reached interrupt flag */
1620 
#define PMMBORIFG              (0x0100)       /* PMM Software BOR interrupt flag */
1621 
#define PMMRSTIFG              (0x0200)       /* PMM RESET pin interrupt flag */
1622 
#define PMMPORIFG              (0x0400)       /* PMM Software POR interrupt flag */
1623 
#define SVSHIFG                (0x1000)       /* SVS low side interrupt flag */
1624 
#define SVSLIFG                (0x2000)       /* SVS high side interrupt flag */
1625 
#define PMMLPM5IFG             (0x8000)       /* LPM5 indication Flag */
1626 
 
1627 
/* PMMIFG Control Bits */
1628 
#define SVSMLDLYIFG_L          (0x0001)       /* SVS and SVM low side Delay expired interrupt flag */
1629 
#define SVMLIFG_L              (0x0002)       /* SVM low side interrupt flag */
1630 
#define SVMLVLRIFG_L           (0x0004)       /* SVM low side Voltage Level Reached interrupt flag */
1631 
#define SVSMHDLYIFG_L          (0x0010)       /* SVS and SVM high side Delay expired interrupt flag */
1632 
#define SVMHIFG_L              (0x0020)       /* SVM high side interrupt flag */
1633 
#define SVMHVLRIFG_L           (0x0040)       /* SVM high side Voltage Level Reached interrupt flag */
1634 
 
1635 
/* PMMIFG Control Bits */
1636 
#define PMMBORIFG_H            (0x0001)       /* PMM Software BOR interrupt flag */
1637 
#define PMMRSTIFG_H            (0x0002)       /* PMM RESET pin interrupt flag */
1638 
#define PMMPORIFG_H            (0x0004)       /* PMM Software POR interrupt flag */
1639 
#define SVSHIFG_H              (0x0010)       /* SVS low side interrupt flag */
1640 
#define SVSLIFG_H              (0x0020)       /* SVS high side interrupt flag */
1641 
#define PMMLPM5IFG_H           (0x0080)       /* LPM5 indication Flag */
1642 
 
1643 
#define PMMRSTLPM5IFG          PMMLPM5IFG     /* LPM5 indication Flag */
1644 
 
1645 
/* PMMIE and RESET Control Bits */
1646 
#define SVSMLDLYIE             (0x0001)       /* SVS and SVM low side Delay expired interrupt enable */
1647 
#define SVMLIE                 (0x0002)       /* SVM low side interrupt enable */
1648 
#define SVMLVLRIE              (0x0004)       /* SVM low side Voltage Level Reached interrupt enable */
1649 
#define SVSMHDLYIE             (0x0010)       /* SVS and SVM high side Delay expired interrupt enable */
1650 
#define SVMHIE                 (0x0020)       /* SVM high side interrupt enable */
1651 
#define SVMHVLRIE              (0x0040)       /* SVM high side Voltage Level Reached interrupt enable */
1652 
#define SVSLPE                 (0x0100)       /* SVS low side POR enable */
1653 
#define SVMLVLRPE              (0x0200)       /* SVM low side Voltage Level reached POR enable */
1654 
#define SVSHPE                 (0x1000)       /* SVS high side POR enable */
1655 
#define SVMHVLRPE              (0x2000)       /* SVM high side Voltage Level reached POR enable */
1656 
 
1657 
/* PMMIE and RESET Control Bits */
1658 
#define SVSMLDLYIE_L           (0x0001)       /* SVS and SVM low side Delay expired interrupt enable */
1659 
#define SVMLIE_L               (0x0002)       /* SVM low side interrupt enable */
1660 
#define SVMLVLRIE_L            (0x0004)       /* SVM low side Voltage Level Reached interrupt enable */
1661 
#define SVSMHDLYIE_L           (0x0010)       /* SVS and SVM high side Delay expired interrupt enable */
1662 
#define SVMHIE_L               (0x0020)       /* SVM high side interrupt enable */
1663 
#define SVMHVLRIE_L            (0x0040)       /* SVM high side Voltage Level Reached interrupt enable */
1664 
 
1665 
/* PMMIE and RESET Control Bits */
1666 
#define SVSLPE_H               (0x0001)       /* SVS low side POR enable */
1667 
#define SVMLVLRPE_H            (0x0002)       /* SVM low side Voltage Level reached POR enable */
1668 
#define SVSHPE_H               (0x0010)       /* SVS high side POR enable */
1669 
#define SVMHVLRPE_H            (0x0020)       /* SVM high side Voltage Level reached POR enable */
1670 
 
1671 
/*************************************************************
1672 
* RAM Control Module
1673 
*************************************************************/
1674 
#define __MSP430_HAS_RC__                     /* Definition to show that Module is available */
1675 
 
1676 
SFR_16BIT(RCCTL0);                            /* Ram Controller Control Register */
1677 
SFR_8BIT(RCCTL0_L);                           /* Ram Controller Control Register */
1678 
SFR_8BIT(RCCTL0_H);                           /* Ram Controller Control Register */
1679 
 
1680 
/* RCCTL0 Control Bits */
1681 
#define RCRS0OFF               (0x0001)       /* RAM Controller RAM Sector 0 Off */
1682 
#define RCRS1OFF               (0x0002)       /* RAM Controller RAM Sector 1 Off */
1683 
#define RCRS2OFF               (0x0004)       /* RAM Controller RAM Sector 2 Off */
1684 
#define RCRS3OFF               (0x0008)       /* RAM Controller RAM Sector 3 Off */
1685 
 
1686 
/* RCCTL0 Control Bits */
1687 
#define RCRS0OFF_L             (0x0001)       /* RAM Controller RAM Sector 0 Off */
1688 
#define RCRS1OFF_L             (0x0002)       /* RAM Controller RAM Sector 1 Off */
1689 
#define RCRS2OFF_L             (0x0004)       /* RAM Controller RAM Sector 2 Off */
1690 
#define RCRS3OFF_L             (0x0008)       /* RAM Controller RAM Sector 3 Off */
1691 
 
1692 
/* RCCTL0 Control Bits */
1693 
 
1694 
#define RCKEY                  (0x5A00)
1695 
 
1696 
/************************************************************
1697 
* Real Time Clock
1698 
************************************************************/
1699 
#define __MSP430_HAS_RTC__                    /* Definition to show that Module is available */
1700 
 
1701 
SFR_16BIT(RTCCTL01);                          /* Real Timer Control 0/1 */
1702 
SFR_8BIT(RTCCTL01_L);                         /* Real Timer Control 0/1 */
1703 
SFR_8BIT(RTCCTL01_H);                         /* Real Timer Control 0/1 */
1704 
SFR_16BIT(RTCCTL23);                          /* Real Timer Control 2/3 */
1705 
SFR_8BIT(RTCCTL23_L);                         /* Real Timer Control 2/3 */
1706 
SFR_8BIT(RTCCTL23_H);                         /* Real Timer Control 2/3 */
1707 
SFR_16BIT(RTCPS0CTL);                         /* Real Timer Prescale Timer 0 Control */
1708 
SFR_8BIT(RTCPS0CTL_L);                        /* Real Timer Prescale Timer 0 Control */
1709 
SFR_8BIT(RTCPS0CTL_H);                        /* Real Timer Prescale Timer 0 Control */
1710 
SFR_16BIT(RTCPS1CTL);                         /* Real Timer Prescale Timer 1 Control */
1711 
SFR_8BIT(RTCPS1CTL_L);                        /* Real Timer Prescale Timer 1 Control */
1712 
SFR_8BIT(RTCPS1CTL_H);                        /* Real Timer Prescale Timer 1 Control */
1713 
SFR_16BIT(RTCPS);                             /* Real Timer Prescale Timer Control */
1714 
SFR_8BIT(RTCPS_L);                            /* Real Timer Prescale Timer Control */
1715 
SFR_8BIT(RTCPS_H);                            /* Real Timer Prescale Timer Control */
1716 
SFR_16BIT(RTCIV);                             /* Real Time Clock Interrupt Vector */
1717 
SFR_16BIT(RTCTIM0);                           /* Real Time Clock Time 0 */
1718 
SFR_8BIT(RTCTIM0_L);                          /* Real Time Clock Time 0 */
1719 
SFR_8BIT(RTCTIM0_H);                          /* Real Time Clock Time 0 */
1720 
SFR_16BIT(RTCTIM1);                           /* Real Time Clock Time 1 */
1721 
SFR_8BIT(RTCTIM1_L);                          /* Real Time Clock Time 1 */
1722 
SFR_8BIT(RTCTIM1_H);                          /* Real Time Clock Time 1 */
1723 
SFR_16BIT(RTCDATE);                           /* Real Time Clock Date */
1724 
SFR_8BIT(RTCDATE_L);                          /* Real Time Clock Date */
1725 
SFR_8BIT(RTCDATE_H);                          /* Real Time Clock Date */
1726 
SFR_16BIT(RTCYEAR);                           /* Real Time Clock Year */
1727 
SFR_8BIT(RTCYEAR_L);                          /* Real Time Clock Year */
1728 
SFR_8BIT(RTCYEAR_H);                          /* Real Time Clock Year */
1729 
SFR_16BIT(RTCAMINHR);                         /* Real Time Clock Alarm Min/Hour */
1730 
SFR_8BIT(RTCAMINHR_L);                        /* Real Time Clock Alarm Min/Hour */
1731 
SFR_8BIT(RTCAMINHR_H);                        /* Real Time Clock Alarm Min/Hour */
1732 
SFR_16BIT(RTCADOWDAY);                        /* Real Time Clock Alarm day of week/day */
1733 
SFR_8BIT(RTCADOWDAY_L);                       /* Real Time Clock Alarm day of week/day */
1734 
SFR_8BIT(RTCADOWDAY_H);                       /* Real Time Clock Alarm day of week/day */
1735 
 
1736 
#define RTCCTL0                RTCCTL01_L     /* Real Time Clock Control 0 */
1737 
#define RTCCTL1                RTCCTL01_H     /* Real Time Clock Control 1 */
1738 
#define RTCCTL2                RTCCTL23_L     /* Real Time Clock Control 2 */
1739 
#define RTCCTL3                RTCCTL23_H     /* Real Time Clock Control 3 */
1740 
#define RTCNT12                RTCTIM0
1741 
#define RTCNT34                RTCTIM1
1742 
#define RTCNT1                 RTCTIM0_L
1743 
#define RTCNT2                 RTCTIM0_H
1744 
#define RTCNT3                 RTCTIM1_L
1745 
#define RTCNT4                 RTCTIM1_H
1746 
#define RTCSEC                 RTCTIM0_L
1747 
#define RTCMIN                 RTCTIM0_H
1748 
#define RTCHOUR                RTCTIM1_L
1749 
#define RTCDOW                 RTCTIM1_H
1750 
#define RTCDAY                 RTCDATE_L
1751 
#define RTCMON                 RTCDATE_H
1752 
#define RTCYEARL               RTCYEAR_L
1753 
#define RTCYEARH               RTCYEAR_H
1754 
#define RT0PS                  RTCPS_L
1755 
#define RT1PS                  RTCPS_H
1756 
#define RTCAMIN                RTCAMINHR_L    /* Real Time Clock Alarm Min */
1757 
#define RTCAHOUR               RTCAMINHR_H    /* Real Time Clock Alarm Hour */
1758 
#define RTCADOW                RTCADOWDAY_L   /* Real Time Clock Alarm day of week */
1759 
#define RTCADAY                RTCADOWDAY_H   /* Real Time Clock Alarm day */
1760 
 
1761 
/* RTCCTL01 Control Bits */
1762 
#define RTCBCD                 (0x8000)       /* RTC BCD  0:Binary / 1:BCD */
1763 
#define RTCHOLD                (0x4000)       /* RTC Hold */
1764 
#define RTCMODE                (0x2000)       /* RTC Mode 0:Counter / 1: Calendar */
1765 
#define RTCRDY                 (0x1000)       /* RTC Ready */
1766 
#define RTCSSEL1               (0x0800)       /* RTC Source Select 1 */
1767 
#define RTCSSEL0               (0x0400)       /* RTC Source Select 0 */
1768 
#define RTCTEV1                (0x0200)       /* RTC Time Event 1 */
1769 
#define RTCTEV0                (0x0100)       /* RTC Time Event 0 */
1770 
//#define Reserved          (0x0080)
1771 
#define RTCTEVIE               (0x0040)       /* RTC Time Event Interrupt Enable Flag */
1772 
#define RTCAIE                 (0x0020)       /* RTC Alarm Interrupt Enable Flag */
1773 
#define RTCRDYIE               (0x0010)       /* RTC Ready Interrupt Enable Flag */
1774 
//#define Reserved          (0x0008)
1775 
#define RTCTEVIFG              (0x0004)       /* RTC Time Event Interrupt Flag */
1776 
#define RTCAIFG                (0x0002)       /* RTC Alarm Interrupt Flag */
1777 
#define RTCRDYIFG              (0x0001)       /* RTC Ready Interrupt Flag */
1778 
 
1779 
/* RTCCTL01 Control Bits */
1780 
//#define Reserved          (0x0080)
1781 
#define RTCTEVIE_L             (0x0040)       /* RTC Time Event Interrupt Enable Flag */
1782 
#define RTCAIE_L               (0x0020)       /* RTC Alarm Interrupt Enable Flag */
1783 
#define RTCRDYIE_L             (0x0010)       /* RTC Ready Interrupt Enable Flag */
1784 
//#define Reserved          (0x0008)
1785 
#define RTCTEVIFG_L            (0x0004)       /* RTC Time Event Interrupt Flag */
1786 
#define RTCAIFG_L              (0x0002)       /* RTC Alarm Interrupt Flag */
1787 
#define RTCRDYIFG_L            (0x0001)       /* RTC Ready Interrupt Flag */
1788 
 
1789 
/* RTCCTL01 Control Bits */
1790 
#define RTCBCD_H               (0x0080)       /* RTC BCD  0:Binary / 1:BCD */
1791 
#define RTCHOLD_H              (0x0040)       /* RTC Hold */
1792 
#define RTCMODE_H              (0x0020)       /* RTC Mode 0:Counter / 1: Calendar */
1793 
#define RTCRDY_H               (0x0010)       /* RTC Ready */
1794 
#define RTCSSEL1_H             (0x0008)       /* RTC Source Select 1 */
1795 
#define RTCSSEL0_H             (0x0004)       /* RTC Source Select 0 */
1796 
#define RTCTEV1_H              (0x0002)       /* RTC Time Event 1 */
1797 
#define RTCTEV0_H              (0x0001)       /* RTC Time Event 0 */
1798 
//#define Reserved          (0x0080)
1799 
//#define Reserved          (0x0008)
1800 
 
1801 
#define RTCSSEL_0              (0x0000)       /* RTC Source Select ACLK */
1802 
#define RTCSSEL_1              (0x0400)       /* RTC Source Select SMCLK */
1803 
#define RTCSSEL_2              (0x0800)       /* RTC Source Select RT1PS */
1804 
#define RTCSSEL_3              (0x0C00)       /* RTC Source Select RT1PS */
1805 
#define RTCSSEL__ACLK          (0x0000)       /* RTC Source Select ACLK */
1806 
#define RTCSSEL__SMCLK         (0x0400)       /* RTC Source Select SMCLK */
1807 
#define RTCSSEL__RT1PS         (0x0800)       /* RTC Source Select RT1PS */
1808 
#define RTCTEV_0               (0x0000)       /* RTC Time Event: 0 (Min. changed) */
1809 
#define RTCTEV_1               (0x0100)       /* RTC Time Event: 1 (Hour changed) */
1810 
#define RTCTEV_2               (0x0200)       /* RTC Time Event: 2 (12:00 changed) */
1811 
#define RTCTEV_3               (0x0300)       /* RTC Time Event: 3 (00:00 changed) */
1812 
#define RTCTEV__MIN            (0x0000)       /* RTC Time Event: 0 (Min. changed) */
1813 
#define RTCTEV__HOUR           (0x0100)       /* RTC Time Event: 1 (Hour changed) */
1814 
#define RTCTEV__1200           (0x0200)       /* RTC Time Event: 2 (12:00 changed) */
1815 
#define RTCTEV__0000           (0x0300)       /* RTC Time Event: 3 (00:00 changed) */
1816 
 
1817 
/* RTCCTL23 Control Bits */
1818 
#define RTCCALF1               (0x0200)       /* RTC Calibration Frequency Bit 1 */
1819 
#define RTCCALF0               (0x0100)       /* RTC Calibration Frequency Bit 0 */
1820 
#define RTCCALS                (0x0080)       /* RTC Calibration Sign */
1821 
//#define Reserved          (0x0040)
1822 
#define RTCCAL5                (0x0020)       /* RTC Calibration Bit 5 */
1823 
#define RTCCAL4                (0x0010)       /* RTC Calibration Bit 4 */
1824 
#define RTCCAL3                (0x0008)       /* RTC Calibration Bit 3 */
1825 
#define RTCCAL2                (0x0004)       /* RTC Calibration Bit 2 */
1826 
#define RTCCAL1                (0x0002)       /* RTC Calibration Bit 1 */
1827 
#define RTCCAL0                (0x0001)       /* RTC Calibration Bit 0 */
1828 
 
1829 
/* RTCCTL23 Control Bits */
1830 
#define RTCCALS_L              (0x0080)       /* RTC Calibration Sign */
1831 
//#define Reserved          (0x0040)
1832 
#define RTCCAL5_L              (0x0020)       /* RTC Calibration Bit 5 */
1833 
#define RTCCAL4_L              (0x0010)       /* RTC Calibration Bit 4 */
1834 
#define RTCCAL3_L              (0x0008)       /* RTC Calibration Bit 3 */
1835 
#define RTCCAL2_L              (0x0004)       /* RTC Calibration Bit 2 */
1836 
#define RTCCAL1_L              (0x0002)       /* RTC Calibration Bit 1 */
1837 
#define RTCCAL0_L              (0x0001)       /* RTC Calibration Bit 0 */
1838 
 
1839 
/* RTCCTL23 Control Bits */
1840 
#define RTCCALF1_H             (0x0002)       /* RTC Calibration Frequency Bit 1 */
1841 
#define RTCCALF0_H             (0x0001)       /* RTC Calibration Frequency Bit 0 */
1842 
//#define Reserved          (0x0040)
1843 
 
1844 
#define RTCCALF_0              (0x0000)       /* RTC Calibration Frequency: No Output */
1845 
#define RTCCALF_1              (0x0100)       /* RTC Calibration Frequency: 512 Hz */
1846 
#define RTCCALF_2              (0x0200)       /* RTC Calibration Frequency: 256 Hz */
1847 
#define RTCCALF_3              (0x0300)       /* RTC Calibration Frequency: 1 Hz */
1848 
 
1849 
/* RTCPS0CTL Control Bits */
1850 
//#define Reserved          (0x8000)
1851 
#define RT0SSEL                (0x4000)       /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
1852 
#define RT0PSDIV2              (0x2000)       /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
1853 
#define RT0PSDIV1              (0x1000)       /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
1854 
#define RT0PSDIV0              (0x0800)       /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
1855 
//#define Reserved          (0x0400)
1856 
//#define Reserved          (0x0200)
1857 
#define RT0PSHOLD              (0x0100)       /* RTC Prescale Timer 0 Hold */
1858 
//#define Reserved          (0x0080)
1859 
//#define Reserved          (0x0040)
1860 
//#define Reserved          (0x0020)
1861 
#define RT0IP2                 (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
1862 
#define RT0IP1                 (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
1863 
#define RT0IP0                 (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
1864 
#define RT0PSIE                (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
1865 
#define RT0PSIFG               (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
1866 
 
1867 
/* RTCPS0CTL Control Bits */
1868 
//#define Reserved          (0x8000)
1869 
//#define Reserved          (0x0400)
1870 
//#define Reserved          (0x0200)
1871 
//#define Reserved          (0x0080)
1872 
//#define Reserved          (0x0040)
1873 
//#define Reserved          (0x0020)
1874 
#define RT0IP2_L               (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
1875 
#define RT0IP1_L               (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
1876 
#define RT0IP0_L               (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
1877 
#define RT0PSIE_L              (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
1878 
#define RT0PSIFG_L             (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
1879 
 
1880 
/* RTCPS0CTL Control Bits */
1881 
//#define Reserved          (0x8000)
1882 
#define RT0SSEL_H              (0x0040)       /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
1883 
#define RT0PSDIV2_H            (0x0020)       /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
1884 
#define RT0PSDIV1_H            (0x0010)       /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
1885 
#define RT0PSDIV0_H            (0x0008)       /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
1886 
//#define Reserved          (0x0400)
1887 
//#define Reserved          (0x0200)
1888 
#define RT0PSHOLD_H            (0x0001)       /* RTC Prescale Timer 0 Hold */
1889 
//#define Reserved          (0x0080)
1890 
//#define Reserved          (0x0040)
1891 
//#define Reserved          (0x0020)
1892 
 
1893 
#define RT0IP_0                (0x0000)       /* RTC Prescale Timer 0 Interrupt Interval /2 */
1894 
#define RT0IP_1                (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval /4 */
1895 
#define RT0IP_2                (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval /8 */
1896 
#define RT0IP_3                (0x000C)       /* RTC Prescale Timer 0 Interrupt Interval /16 */
1897 
#define RT0IP_4                (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval /32 */
1898 
#define RT0IP_5                (0x0014)       /* RTC Prescale Timer 0 Interrupt Interval /64 */
1899 
#define RT0IP_6                (0x0018)       /* RTC Prescale Timer 0 Interrupt Interval /128 */
1900 
#define RT0IP_7                (0x001C)       /* RTC Prescale Timer 0 Interrupt Interval /256 */
1901 
 
1902 
#define RT0PSDIV_0             (0x0000)       /* RTC Prescale Timer 0 Clock Divide /2 */
1903 
#define RT0PSDIV_1             (0x0800)       /* RTC Prescale Timer 0 Clock Divide /4 */
1904 
#define RT0PSDIV_2             (0x1000)       /* RTC Prescale Timer 0 Clock Divide /8 */
1905 
#define RT0PSDIV_3             (0x1800)       /* RTC Prescale Timer 0 Clock Divide /16 */
1906 
#define RT0PSDIV_4             (0x2000)       /* RTC Prescale Timer 0 Clock Divide /32 */
1907 
#define RT0PSDIV_5             (0x2800)       /* RTC Prescale Timer 0 Clock Divide /64 */
1908 
#define RT0PSDIV_6             (0x3000)       /* RTC Prescale Timer 0 Clock Divide /128 */
1909 
#define RT0PSDIV_7             (0x3800)       /* RTC Prescale Timer 0 Clock Divide /256 */
1910 
 
1911 
/* RTCPS1CTL Control Bits */
1912 
#define RT1SSEL1               (0x8000)       /* RTC Prescale Timer 1 Source Select Bit 1 */
1913 
#define RT1SSEL0               (0x4000)       /* RTC Prescale Timer 1 Source Select Bit 0 */
1914 
#define RT1PSDIV2              (0x2000)       /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
1915 
#define RT1PSDIV1              (0x1000)       /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
1916 
#define RT1PSDIV0              (0x0800)       /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
1917 
//#define Reserved          (0x0400)
1918 
//#define Reserved          (0x0200)
1919 
#define RT1PSHOLD              (0x0100)       /* RTC Prescale Timer 1 Hold */
1920 
//#define Reserved          (0x0080)
1921 
//#define Reserved          (0x0040)
1922 
//#define Reserved          (0x0020)
1923 
#define RT1IP2                 (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
1924 
#define RT1IP1                 (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
1925 
#define RT1IP0                 (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
1926 
#define RT1PSIE                (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
1927 
#define RT1PSIFG               (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
1928 
 
1929 
/* RTCPS1CTL Control Bits */
1930 
//#define Reserved          (0x0400)
1931 
//#define Reserved          (0x0200)
1932 
//#define Reserved          (0x0080)
1933 
//#define Reserved          (0x0040)
1934 
//#define Reserved          (0x0020)
1935 
#define RT1IP2_L               (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
1936 
#define RT1IP1_L               (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
1937 
#define RT1IP0_L               (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
1938 
#define RT1PSIE_L              (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
1939 
#define RT1PSIFG_L             (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
1940 
 
1941 
/* RTCPS1CTL Control Bits */
1942 
#define RT1SSEL1_H             (0x0080)       /* RTC Prescale Timer 1 Source Select Bit 1 */
1943 
#define RT1SSEL0_H             (0x0040)       /* RTC Prescale Timer 1 Source Select Bit 0 */
1944 
#define RT1PSDIV2_H            (0x0020)       /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
1945 
#define RT1PSDIV1_H            (0x0010)       /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
1946 
#define RT1PSDIV0_H            (0x0008)       /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
1947 
//#define Reserved          (0x0400)
1948 
//#define Reserved          (0x0200)
1949 
#define RT1PSHOLD_H            (0x0001)       /* RTC Prescale Timer 1 Hold */
1950 
//#define Reserved          (0x0080)
1951 
//#define Reserved          (0x0040)
1952 
//#define Reserved          (0x0020)
1953 
 
1954 
#define RT1IP_0                (0x0000)       /* RTC Prescale Timer 1 Interrupt Interval /2 */
1955 
#define RT1IP_1                (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval /4 */
1956 
#define RT1IP_2                (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval /8 */
1957 
#define RT1IP_3                (0x000C)       /* RTC Prescale Timer 1 Interrupt Interval /16 */
1958 
#define RT1IP_4                (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval /32 */
1959 
#define RT1IP_5                (0x0014)       /* RTC Prescale Timer 1 Interrupt Interval /64 */
1960 
#define RT1IP_6                (0x0018)       /* RTC Prescale Timer 1 Interrupt Interval /128 */
1961 
#define RT1IP_7                (0x001C)       /* RTC Prescale Timer 1 Interrupt Interval /256 */
1962 
 
1963 
#define RT1PSDIV_0             (0x0000)       /* RTC Prescale Timer 1 Clock Divide /2 */
1964 
#define RT1PSDIV_1             (0x0800)       /* RTC Prescale Timer 1 Clock Divide /4 */
1965 
#define RT1PSDIV_2             (0x1000)       /* RTC Prescale Timer 1 Clock Divide /8 */
1966 
#define RT1PSDIV_3             (0x1800)       /* RTC Prescale Timer 1 Clock Divide /16 */
1967 
#define RT1PSDIV_4             (0x2000)       /* RTC Prescale Timer 1 Clock Divide /32 */
1968 
#define RT1PSDIV_5             (0x2800)       /* RTC Prescale Timer 1 Clock Divide /64 */
1969 
#define RT1PSDIV_6             (0x3000)       /* RTC Prescale Timer 1 Clock Divide /128 */
1970 
#define RT1PSDIV_7             (0x3800)       /* RTC Prescale Timer 1 Clock Divide /256 */
1971 
 
1972 
#define RT1SSEL_0              (0x0000)       /* RTC Prescale Timer Source Select ACLK */
1973 
#define RT1SSEL_1              (0x4000)       /* RTC Prescale Timer Source Select SMCLK */
1974 
#define RT1SSEL_2              (0x8000)       /* RTC Prescale Timer Source Select RT0PS */
1975 
#define RT1SSEL_3              (0xC000)       /* RTC Prescale Timer Source Select RT0PS */
1976 
 
1977 
/* RTC Definitions */
1978 
#define RTC_NONE               (0x0000)       /* No Interrupt pending */
1979 
#define RTC_RTCRDYIFG          (0x0002)       /* RTC ready: RTCRDYIFG */
1980 
#define RTC_RTCTEVIFG          (0x0004)       /* RTC interval timer: RTCTEVIFG */
1981 
#define RTC_RTCAIFG            (0x0006)       /* RTC user alarm: RTCAIFG */
1982 
#define RTC_RT0PSIFG           (0x0008)       /* RTC prescaler 0: RT0PSIFG */
1983 
#define RTC_RT1PSIFG           (0x000A)       /* RTC prescaler 1: RT1PSIFG */
1984 
 
1985 
/************************************************************
1986 
* SFR - Special Function Register Module
1987 
************************************************************/
1988 
#define __MSP430_HAS_SFR__                    /* Definition to show that Module is available */
1989 
 
1990 
SFR_16BIT(SFRIE1);                            /* Interrupt Enable 1 */
1991 
SFR_8BIT(SFRIE1_L);                           /* Interrupt Enable 1 */
1992 
SFR_8BIT(SFRIE1_H);                           /* Interrupt Enable 1 */
1993 
 
1994 
/* SFRIE1 Control Bits */
1995 
#define WDTIE                  (0x0001)       /* WDT Interrupt Enable */
1996 
#define OFIE                   (0x0002)       /* Osc Fault Enable */
1997 
//#define Reserved          (0x0004)
1998 
#define VMAIE                  (0x0008)       /* Vacant Memory Interrupt Enable */
1999 
#define NMIIE                  (0x0010)       /* NMI Interrupt Enable */
2000 
#define ACCVIE                 (0x0020)       /* Flash Access Violation Interrupt Enable */
2001 
#define JMBINIE                (0x0040)       /* JTAG Mail Box input Interrupt Enable */
2002 
#define JMBOUTIE               (0x0080)       /* JTAG Mail Box output Interrupt Enable */
2003 
 
2004 
#define WDTIE_L                (0x0001)       /* WDT Interrupt Enable */
2005 
#define OFIE_L                 (0x0002)       /* Osc Fault Enable */
2006 
//#define Reserved          (0x0004)
2007 
#define VMAIE_L                (0x0008)       /* Vacant Memory Interrupt Enable */
2008 
#define NMIIE_L                (0x0010)       /* NMI Interrupt Enable */
2009 
#define ACCVIE_L               (0x0020)       /* Flash Access Violation Interrupt Enable */
2010 
#define JMBINIE_L              (0x0040)       /* JTAG Mail Box input Interrupt Enable */
2011 
#define JMBOUTIE_L             (0x0080)       /* JTAG Mail Box output Interrupt Enable */
2012 
 
2013 
//#define Reserved          (0x0004)
2014 
 
2015 
SFR_16BIT(SFRIFG1);                           /* Interrupt Flag 1 */
2016 
SFR_8BIT(SFRIFG1_L);                          /* Interrupt Flag 1 */
2017 
SFR_8BIT(SFRIFG1_H);                          /* Interrupt Flag 1 */
2018 
/* SFRIFG1 Control Bits */
2019 
#define WDTIFG                 (0x0001)       /* WDT Interrupt Flag */
2020 
#define OFIFG                  (0x0002)       /* Osc Fault Flag */
2021 
//#define Reserved          (0x0004)
2022 
#define VMAIFG                 (0x0008)       /* Vacant Memory Interrupt Flag */
2023 
#define NMIIFG                 (0x0010)       /* NMI Interrupt Flag */
2024 
//#define Reserved          (0x0020)
2025 
#define JMBINIFG               (0x0040)       /* JTAG Mail Box input Interrupt Flag */
2026 
#define JMBOUTIFG              (0x0080)       /* JTAG Mail Box output Interrupt Flag */
2027 
 
2028 
#define WDTIFG_L               (0x0001)       /* WDT Interrupt Flag */
2029 
#define OFIFG_L                (0x0002)       /* Osc Fault Flag */
2030 
//#define Reserved          (0x0004)
2031 
#define VMAIFG_L               (0x0008)       /* Vacant Memory Interrupt Flag */
2032 
#define NMIIFG_L               (0x0010)       /* NMI Interrupt Flag */
2033 
//#define Reserved          (0x0020)
2034 
#define JMBINIFG_L             (0x0040)       /* JTAG Mail Box input Interrupt Flag */
2035 
#define JMBOUTIFG_L            (0x0080)       /* JTAG Mail Box output Interrupt Flag */
2036 
 
2037 
//#define Reserved          (0x0004)
2038 
//#define Reserved          (0x0020)
2039 
 
2040 
SFR_16BIT(SFRRPCR);                           /* RESET Pin Control Register */
2041 
SFR_8BIT(SFRRPCR_L);                          /* RESET Pin Control Register */
2042 
SFR_8BIT(SFRRPCR_H);                          /* RESET Pin Control Register */
2043 
/* SFRRPCR Control Bits */
2044 
#define SYSNMI                 (0x0001)       /* NMI select */
2045 
#define SYSNMIIES              (0x0002)       /* NMI edge select */
2046 
#define SYSRSTUP               (0x0004)       /* RESET Pin pull down/up select */
2047 
#define SYSRSTRE               (0x0008)       /* RESET Pin Resistor enable */
2048 
 
2049 
#define SYSNMI_L               (0x0001)       /* NMI select */
2050 
#define SYSNMIIES_L            (0x0002)       /* NMI edge select */
2051 
#define SYSRSTUP_L             (0x0004)       /* RESET Pin pull down/up select */
2052 
#define SYSRSTRE_L             (0x0008)       /* RESET Pin Resistor enable */
2053 
 
2054 
/************************************************************
2055 
* SYS - System Module
2056 
************************************************************/
2057 
#define __MSP430_HAS_SYS__                    /* Definition to show that Module is available */
2058 
 
2059 
SFR_16BIT(SYSCTL);                            /* System control */
2060 
SFR_8BIT(SYSCTL_L);                           /* System control */
2061 
SFR_8BIT(SYSCTL_H);                           /* System control */
2062 
SFR_16BIT(SYSBSLC);                           /* Boot strap configuration area */
2063 
SFR_8BIT(SYSBSLC_L);                          /* Boot strap configuration area */
2064 
SFR_8BIT(SYSBSLC_H);                          /* Boot strap configuration area */
2065 
SFR_16BIT(SYSJMBC);                           /* JTAG mailbox control */
2066 
SFR_8BIT(SYSJMBC_L);                          /* JTAG mailbox control */
2067 
SFR_8BIT(SYSJMBC_H);                          /* JTAG mailbox control */
2068 
SFR_16BIT(SYSJMBI0);                          /* JTAG mailbox input 0 */
2069 
SFR_8BIT(SYSJMBI0_L);                         /* JTAG mailbox input 0 */
2070 
SFR_8BIT(SYSJMBI0_H);                         /* JTAG mailbox input 0 */
2071 
SFR_16BIT(SYSJMBI1);                          /* JTAG mailbox input 1 */
2072 
SFR_8BIT(SYSJMBI1_L);                         /* JTAG mailbox input 1 */
2073 
SFR_8BIT(SYSJMBI1_H);                         /* JTAG mailbox input 1 */
2074 
SFR_16BIT(SYSJMBO0);                          /* JTAG mailbox output 0 */
2075 
SFR_8BIT(SYSJMBO0_L);                         /* JTAG mailbox output 0 */
2076 
SFR_8BIT(SYSJMBO0_H);                         /* JTAG mailbox output 0 */
2077 
SFR_16BIT(SYSJMBO1);                          /* JTAG mailbox output 1 */
2078 
SFR_8BIT(SYSJMBO1_L);                         /* JTAG mailbox output 1 */
2079 
SFR_8BIT(SYSJMBO1_H);                         /* JTAG mailbox output 1 */
2080 
 
2081 
SFR_16BIT(SYSUNIV);                           /* User NMI vector generator */
2082 
SFR_8BIT(SYSUNIV_L);                          /* User NMI vector generator */
2083 
SFR_8BIT(SYSUNIV_H);                          /* User NMI vector generator */
2084 
SFR_16BIT(SYSSNIV);                           /* System NMI vector generator */
2085 
SFR_8BIT(SYSSNIV_L);                          /* System NMI vector generator */
2086 
SFR_8BIT(SYSSNIV_H);                          /* System NMI vector generator */
2087 
SFR_16BIT(SYSRSTIV);                          /* Reset vector generator */
2088 
SFR_8BIT(SYSRSTIV_L);                         /* Reset vector generator */
2089 
SFR_8BIT(SYSRSTIV_H);                         /* Reset vector generator */
2090 
 
2091 
/* SYSCTL Control Bits */
2092 
#define SYSRIVECT              (0x0001)       /* SYS - RAM based interrupt vectors */
2093 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2094 
#define SYSPMMPE               (0x0004)       /* SYS - PMM access protect */
2095 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2096 
#define SYSBSLIND              (0x0010)       /* SYS - TCK/RST indication detected */
2097 
#define SYSJTAGPIN             (0x0020)       /* SYS - Dedicated JTAG pins enabled */
2098 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2099 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2100 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2101 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2102 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2103 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2104 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2105 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2106 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2107 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2108 
 
2109 
/* SYSCTL Control Bits */
2110 
#define SYSRIVECT_L            (0x0001)       /* SYS - RAM based interrupt vectors */
2111 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2112 
#define SYSPMMPE_L             (0x0004)       /* SYS - PMM access protect */
2113 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2114 
#define SYSBSLIND_L            (0x0010)       /* SYS - TCK/RST indication detected */
2115 
#define SYSJTAGPIN_L           (0x0020)       /* SYS - Dedicated JTAG pins enabled */
2116 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2117 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2118 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2119 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2120 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2121 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2122 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2123 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2124 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2125 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2126 
 
2127 
/* SYSCTL Control Bits */
2128 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2129 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2130 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2131 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2132 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2133 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2134 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2135 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2136 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2137 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2138 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2139 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2140 
 
2141 
/* SYSBSLC Control Bits */
2142 
#define SYSBSLSIZE0            (0x0001)       /* SYS - BSL Protection Size 0 */
2143 
#define SYSBSLSIZE1            (0x0002)       /* SYS - BSL Protection Size 1 */
2144 
#define SYSBSLR                (0x0004)       /* SYS - RAM assigned to BSL */
2145 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2146 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
2147 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2148 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2149 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2150 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2151 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2152 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2153 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2154 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2155 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2156 
#define SYSBSLOFF              (0x4000)       /* SYS - BSL Memeory disabled */
2157 
#define SYSBSLPE               (0x8000)       /* SYS - BSL Memory protection enabled */
2158 
 
2159 
/* SYSBSLC Control Bits */
2160 
#define SYSBSLSIZE0_L          (0x0001)       /* SYS - BSL Protection Size 0 */
2161 
#define SYSBSLSIZE1_L          (0x0002)       /* SYS - BSL Protection Size 1 */
2162 
#define SYSBSLR_L              (0x0004)       /* SYS - RAM assigned to BSL */
2163 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2164 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
2165 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2166 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2167 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2168 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2169 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2170 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2171 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2172 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2173 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2174 
 
2175 
/* SYSBSLC Control Bits */
2176 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2177 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
2178 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2179 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2180 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2181 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2182 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2183 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2184 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2185 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2186 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2187 
#define SYSBSLOFF_H            (0x0040)       /* SYS - BSL Memeory disabled */
2188 
#define SYSBSLPE_H             (0x0080)       /* SYS - BSL Memory protection enabled */
2189 
 
2190 
/* SYSJMBC Control Bits */
2191 
#define JMBIN0FG               (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
2192 
#define JMBIN1FG               (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
2193 
#define JMBOUT0FG              (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
2194 
#define JMBOUT1FG              (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
2195 
#define JMBMODE                (0x0010)       /* SYS - JMB 16/32 Bit Mode */
2196 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2197 
#define JMBCLR0OFF             (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
2198 
#define JMBCLR1OFF             (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
2199 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2200 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2201 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2202 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2203 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2204 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2205 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2206 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2207 
 
2208 
/* SYSJMBC Control Bits */
2209 
#define JMBIN0FG_L             (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
2210 
#define JMBIN1FG_L             (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
2211 
#define JMBOUT0FG_L            (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
2212 
#define JMBOUT1FG_L            (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
2213 
#define JMBMODE_L              (0x0010)       /* SYS - JMB 16/32 Bit Mode */
2214 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2215 
#define JMBCLR0OFF_L           (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
2216 
#define JMBCLR1OFF_L           (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
2217 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2218 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2219 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2220 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2221 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2222 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2223 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2224 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2225 
 
2226 
/* SYSJMBC Control Bits */
2227 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2228 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2229 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2230 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2231 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2232 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2233 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2234 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2235 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2236 
 
2237 
/* SYSUNIV Definitions */
2238 
#define SYSUNIV_NONE           (0x0000)       /* No Interrupt pending */
2239 
#define SYSUNIV_NMIIFG         (0x0002)       /* SYSUNIV : NMIIFG */
2240 
#define SYSUNIV_OFIFG          (0x0004)       /* SYSUNIV : Osc. Fail - OFIFG */
2241 
#define SYSUNIV_ACCVIFG        (0x0006)       /* SYSUNIV : Access Violation - ACCVIFG */
2242 
#define SYSUNIV_SYSBERRIV      (0x0008)       /* SYSUNIV : Bus Error - SYSBERRIV */
2243 
 
2244 
/* SYSSNIV Definitions */
2245 
#define SYSSNIV_NONE           (0x0000)       /* No Interrupt pending */
2246 
#define SYSSNIV_SVMLIFG        (0x0002)       /* SYSSNIV : SVMLIFG */
2247 
#define SYSSNIV_SVMHIFG        (0x0004)       /* SYSSNIV : SVMHIFG */
2248 
#define SYSSNIV_DLYLIFG        (0x0006)       /* SYSSNIV : DLYLIFG */
2249 
#define SYSSNIV_DLYHIFG        (0x0008)       /* SYSSNIV : DLYHIFG */
2250 
#define SYSSNIV_VMAIFG         (0x000A)       /* SYSSNIV : VMAIFG */
2251 
#define SYSSNIV_JMBINIFG       (0x000C)       /* SYSSNIV : JMBINIFG */
2252 
#define SYSSNIV_JMBOUTIFG      (0x000E)       /* SYSSNIV : JMBOUTIFG */
2253 
#define SYSSNIV_VLRLIFG        (0x0010)       /* SYSSNIV : VLRLIFG */
2254 
#define SYSSNIV_VLRHIFG        (0x0012)       /* SYSSNIV : VLRHIFG */
2255 
 
2256 
/* SYSRSTIV Definitions */
2257 
#define SYSRSTIV_NONE          (0x0000)       /* No Interrupt pending */
2258 
#define SYSRSTIV_BOR           (0x0002)       /* SYSRSTIV : BOR */
2259 
#define SYSRSTIV_RSTNMI        (0x0004)       /* SYSRSTIV : RST/NMI */
2260 
#define SYSRSTIV_DOBOR         (0x0006)       /* SYSRSTIV : Do BOR */
2261 
#define SYSRSTIV_LPM5WU        (0x0008)       /* SYSRSTIV : Port LPM5 Wake Up */
2262 
#define SYSRSTIV_SECYV         (0x000A)       /* SYSRSTIV : Security violation */
2263 
#define SYSRSTIV_SVSL          (0x000C)       /* SYSRSTIV : SVSL */
2264 
#define SYSRSTIV_SVSH          (0x000E)       /* SYSRSTIV : SVSH */
2265 
#define SYSRSTIV_SVML_OVP      (0x0010)       /* SYSRSTIV : SVML_OVP */
2266 
#define SYSRSTIV_SVMH_OVP      (0x0012)       /* SYSRSTIV : SVMH_OVP */
2267 
#define SYSRSTIV_DOPOR         (0x0014)       /* SYSRSTIV : Do POR */
2268 
#define SYSRSTIV_WDTTO         (0x0016)       /* SYSRSTIV : WDT Time out */
2269 
#define SYSRSTIV_WDTKEY        (0x0018)       /* SYSRSTIV : WDTKEY violation */
2270 
#define SYSRSTIV_KEYV          (0x001A)       /* SYSRSTIV : Flash Key violation */
2271 
#define SYSRSTIV_PLLUL         (0x001C)       /* SYSRSTIV : PLL unlock */
2272 
#define SYSRSTIV_PERF          (0x001E)       /* SYSRSTIV : peripheral/config area fetch */
2273 
#define SYSRSTIV_PSSKEY        (0x0020)       /* SYSRSTIV : PSSKEY violation */
2274 
 
2275 
/************************************************************
2276 
* Timer0_A5
2277 
************************************************************/
2278 
#define __MSP430_HAS_T0A5__                   /* Definition to show that Module is available */
2279 
 
2280 
SFR_16BIT(TA0CTL);                            /* Timer0_A5 Control */
2281 
SFR_8BIT(TA0CTL_L);                           /* Timer0_A5 Control */
2282 
SFR_8BIT(TA0CTL_H);                           /* Timer0_A5 Control */
2283 
SFR_16BIT(TA0CCTL0);                          /* Timer0_A5 Capture/Compare Control 0 */
2284 
SFR_8BIT(TA0CCTL0_L);                         /* Timer0_A5 Capture/Compare Control 0 */
2285 
SFR_8BIT(TA0CCTL0_H);                         /* Timer0_A5 Capture/Compare Control 0 */
2286 
SFR_16BIT(TA0CCTL1);                          /* Timer0_A5 Capture/Compare Control 1 */
2287 
SFR_8BIT(TA0CCTL1_L);                         /* Timer0_A5 Capture/Compare Control 1 */
2288 
SFR_8BIT(TA0CCTL1_H);                         /* Timer0_A5 Capture/Compare Control 1 */
2289 
SFR_16BIT(TA0CCTL2);                          /* Timer0_A5 Capture/Compare Control 2 */
2290 
SFR_8BIT(TA0CCTL2_L);                         /* Timer0_A5 Capture/Compare Control 2 */
2291 
SFR_8BIT(TA0CCTL2_H);                         /* Timer0_A5 Capture/Compare Control 2 */
2292 
SFR_16BIT(TA0CCTL3);                          /* Timer0_A5 Capture/Compare Control 3 */
2293 
SFR_8BIT(TA0CCTL3_L);                         /* Timer0_A5 Capture/Compare Control 3 */
2294 
SFR_8BIT(TA0CCTL3_H);                         /* Timer0_A5 Capture/Compare Control 3 */
2295 
SFR_16BIT(TA0CCTL4);                          /* Timer0_A5 Capture/Compare Control 4 */
2296 
SFR_8BIT(TA0CCTL4_L);                         /* Timer0_A5 Capture/Compare Control 4 */
2297 
SFR_8BIT(TA0CCTL4_H);                         /* Timer0_A5 Capture/Compare Control 4 */
2298 
SFR_16BIT(TA0R);                              /* Timer0_A5 */
2299 
SFR_8BIT(TA0R_L);                             /* Timer0_A5 */
2300 
SFR_8BIT(TA0R_H);                             /* Timer0_A5 */
2301 
SFR_16BIT(TA0CCR0);                           /* Timer0_A5 Capture/Compare 0 */
2302 
SFR_8BIT(TA0CCR0_L);                          /* Timer0_A5 Capture/Compare 0 */
2303 
SFR_8BIT(TA0CCR0_H);                          /* Timer0_A5 Capture/Compare 0 */
2304 
SFR_16BIT(TA0CCR1);                           /* Timer0_A5 Capture/Compare 1 */
2305 
SFR_8BIT(TA0CCR1_L);                          /* Timer0_A5 Capture/Compare 1 */
2306 
SFR_8BIT(TA0CCR1_H);                          /* Timer0_A5 Capture/Compare 1 */
2307 
SFR_16BIT(TA0CCR2);                           /* Timer0_A5 Capture/Compare 2 */
2308 
SFR_8BIT(TA0CCR2_L);                          /* Timer0_A5 Capture/Compare 2 */
2309 
SFR_8BIT(TA0CCR2_H);                          /* Timer0_A5 Capture/Compare 2 */
2310 
SFR_16BIT(TA0CCR3);                           /* Timer0_A5 Capture/Compare 3 */
2311 
SFR_8BIT(TA0CCR3_L);                          /* Timer0_A5 Capture/Compare 3 */
2312 
SFR_8BIT(TA0CCR3_H);                          /* Timer0_A5 Capture/Compare 3 */
2313 
SFR_16BIT(TA0CCR4);                           /* Timer0_A5 Capture/Compare 4 */
2314 
SFR_8BIT(TA0CCR4_L);                          /* Timer0_A5 Capture/Compare 4 */
2315 
SFR_8BIT(TA0CCR4_H);                          /* Timer0_A5 Capture/Compare 4 */
2316 
SFR_16BIT(TA0IV);                             /* Timer0_A5 Interrupt Vector Word */
2317 
SFR_8BIT(TA0IV_L);                            /* Timer0_A5 Interrupt Vector Word */
2318 
SFR_8BIT(TA0IV_H);                            /* Timer0_A5 Interrupt Vector Word */
2319 
SFR_16BIT(TA0EX0);                            /* Timer0_A5 Expansion Register 0 */
2320 
SFR_8BIT(TA0EX0_L);                           /* Timer0_A5 Expansion Register 0 */
2321 
SFR_8BIT(TA0EX0_H);                           /* Timer0_A5 Expansion Register 0 */
2322 
 
2323 
/* TAxCTL Control Bits */
2324 
#define TASSEL1                (0x0200)       /* Timer A clock source select 0 */
2325 
#define TASSEL0                (0x0100)       /* Timer A clock source select 1 */
2326 
#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
2327 
#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
2328 
#define MC1                    (0x0020)       /* Timer A mode control 1 */
2329 
#define MC0                    (0x0010)       /* Timer A mode control 0 */
2330 
#define TACLR                  (0x0004)       /* Timer A counter clear */
2331 
#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
2332 
#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
2333 
 
2334 
/* TAxCTL Control Bits */
2335 
#define ID1_L                  (0x0080)       /* Timer A clock input divider 1 */
2336 
#define ID0_L                  (0x0040)       /* Timer A clock input divider 0 */
2337 
#define MC1_L                  (0x0020)       /* Timer A mode control 1 */
2338 
#define MC0_L                  (0x0010)       /* Timer A mode control 0 */
2339 
#define TACLR_L                (0x0004)       /* Timer A counter clear */
2340 
#define TAIE_L                 (0x0002)       /* Timer A counter interrupt enable */
2341 
#define TAIFG_L                (0x0001)       /* Timer A counter interrupt flag */
2342 
 
2343 
/* TAxCTL Control Bits */
2344 
#define TASSEL1_H              (0x0002)       /* Timer A clock source select 0 */
2345 
#define TASSEL0_H              (0x0001)       /* Timer A clock source select 1 */
2346 
 
2347 
#define MC_0                   (0*0x10u)      /* Timer A mode control: 0 - Stop */
2348 
#define MC_1                   (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
2349 
#define MC_2                   (2*0x10u)      /* Timer A mode control: 2 - Continous up */
2350 
#define MC_3                   (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
2351 
#define ID_0                   (0*0x40u)      /* Timer A input divider: 0 - /1 */
2352 
#define ID_1                   (1*0x40u)      /* Timer A input divider: 1 - /2 */
2353 
#define ID_2                   (2*0x40u)      /* Timer A input divider: 2 - /4 */
2354 
#define ID_3                   (3*0x40u)      /* Timer A input divider: 3 - /8 */
2355 
#define TASSEL_0               (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
2356 
#define TASSEL_1               (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
2357 
#define TASSEL_2               (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
2358 
#define TASSEL_3               (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
2359 
#define MC__STOP               (0*0x10u)      /* Timer A mode control: 0 - Stop */
2360 
#define MC__UP                 (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
2361 
#define MC__CONTINOUS          (2*0x10u)      /* Timer A mode control: 2 - Continous up */
2362 
#define MC__UPDOWN             (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
2363 
#define ID__1                  (0*0x40u)      /* Timer A input divider: 0 - /1 */
2364 
#define ID__2                  (1*0x40u)      /* Timer A input divider: 1 - /2 */
2365 
#define ID__4                  (2*0x40u)      /* Timer A input divider: 2 - /4 */
2366 
#define ID__8                  (3*0x40u)      /* Timer A input divider: 3 - /8 */
2367 
#define TASSEL__TACLK          (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
2368 
#define TASSEL__ACLK           (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
2369 
#define TASSEL__SMCLK          (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
2370 
#define TASSEL__INCLK          (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
2371 
 
2372 
/* TAxCCTLx Control Bits */
2373 
#define CM1                    (0x8000)       /* Capture mode 1 */
2374 
#define CM0                    (0x4000)       /* Capture mode 0 */
2375 
#define CCIS1                  (0x2000)       /* Capture input select 1 */
2376 
#define CCIS0                  (0x1000)       /* Capture input select 0 */
2377 
#define SCS                    (0x0800)       /* Capture sychronize */
2378 
#define SCCI                   (0x0400)       /* Latched capture signal (read) */
2379 
#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
2380 
#define OUTMOD2                (0x0080)       /* Output mode 2 */
2381 
#define OUTMOD1                (0x0040)       /* Output mode 1 */
2382 
#define OUTMOD0                (0x0020)       /* Output mode 0 */
2383 
#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
2384 
#define CCI                    (0x0008)       /* Capture input signal (read) */
2385 
#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
2386 
#define COV                    (0x0002)       /* Capture/compare overflow flag */
2387 
#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
2388 
 
2389 
/* TAxCCTLx Control Bits */
2390 
#define OUTMOD2_L              (0x0080)       /* Output mode 2 */
2391 
#define OUTMOD1_L              (0x0040)       /* Output mode 1 */
2392 
#define OUTMOD0_L              (0x0020)       /* Output mode 0 */
2393 
#define CCIE_L                 (0x0010)       /* Capture/compare interrupt enable */
2394 
#define CCI_L                  (0x0008)       /* Capture input signal (read) */
2395 
#define OUT_L                  (0x0004)       /* PWM Output signal if output mode 0 */
2396 
#define COV_L                  (0x0002)       /* Capture/compare overflow flag */
2397 
#define CCIFG_L                (0x0001)       /* Capture/compare interrupt flag */
2398 
 
2399 
/* TAxCCTLx Control Bits */
2400 
#define CM1_H                  (0x0080)       /* Capture mode 1 */
2401 
#define CM0_H                  (0x0040)       /* Capture mode 0 */
2402 
#define CCIS1_H                (0x0020)       /* Capture input select 1 */
2403 
#define CCIS0_H                (0x0010)       /* Capture input select 0 */
2404 
#define SCS_H                  (0x0008)       /* Capture sychronize */
2405 
#define SCCI_H                 (0x0004)       /* Latched capture signal (read) */
2406 
#define CAP_H                  (0x0001)       /* Capture mode: 1 /Compare mode : 0 */
2407 
 
2408 
#define OUTMOD_0               (0*0x20u)      /* PWM output mode: 0 - output only */
2409 
#define OUTMOD_1               (1*0x20u)      /* PWM output mode: 1 - set */
2410 
#define OUTMOD_2               (2*0x20u)      /* PWM output mode: 2 - PWM toggle/reset */
2411 
#define OUTMOD_3               (3*0x20u)      /* PWM output mode: 3 - PWM set/reset */
2412 
#define OUTMOD_4               (4*0x20u)      /* PWM output mode: 4 - toggle */
2413 
#define OUTMOD_5               (5*0x20u)      /* PWM output mode: 5 - Reset */
2414 
#define OUTMOD_6               (6*0x20u)      /* PWM output mode: 6 - PWM toggle/set */
2415 
#define OUTMOD_7               (7*0x20u)      /* PWM output mode: 7 - PWM reset/set */
2416 
#define CCIS_0                 (0*0x1000u)    /* Capture input select: 0 - CCIxA */
2417 
#define CCIS_1                 (1*0x1000u)    /* Capture input select: 1 - CCIxB */
2418 
#define CCIS_2                 (2*0x1000u)    /* Capture input select: 2 - GND */
2419 
#define CCIS_3                 (3*0x1000u)    /* Capture input select: 3 - Vcc */
2420 
#define CM_0                   (0*0x4000u)    /* Capture mode: 0 - disabled */
2421 
#define CM_1                   (1*0x4000u)    /* Capture mode: 1 - pos. edge */
2422 
#define CM_2                   (2*0x4000u)    /* Capture mode: 1 - neg. edge */
2423 
#define CM_3                   (3*0x4000u)    /* Capture mode: 1 - both edges */
2424 
 
2425 
/* TAxEX0 Control Bits */
2426 
#define TAIDEX0                (0x0001)       /* Timer A Input divider expansion Bit: 0 */
2427 
#define TAIDEX1                (0x0002)       /* Timer A Input divider expansion Bit: 1 */
2428 
#define TAIDEX2                (0x0004)       /* Timer A Input divider expansion Bit: 2 */
2429 
 
2430 
/* TAxEX0 Control Bits */
2431 
#define TAIDEX0_L              (0x0001)       /* Timer A Input divider expansion Bit: 0 */
2432 
#define TAIDEX1_L              (0x0002)       /* Timer A Input divider expansion Bit: 1 */
2433 
#define TAIDEX2_L              (0x0004)       /* Timer A Input divider expansion Bit: 2 */
2434 
 
2435 
/* TAxEX0 Control Bits */
2436 
 
2437 
#define TAIDEX_0               (0*0x0001u)    /* Timer A Input divider expansion : /1 */
2438 
#define TAIDEX_1               (1*0x0001u)    /* Timer A Input divider expansion : /2 */
2439 
#define TAIDEX_2               (2*0x0001u)    /* Timer A Input divider expansion : /3 */
2440 
#define TAIDEX_3               (3*0x0001u)    /* Timer A Input divider expansion : /4 */
2441 
#define TAIDEX_4               (4*0x0001u)    /* Timer A Input divider expansion : /5 */
2442 
#define TAIDEX_5               (5*0x0001u)    /* Timer A Input divider expansion : /6 */
2443 
#define TAIDEX_6               (6*0x0001u)    /* Timer A Input divider expansion : /7 */
2444 
#define TAIDEX_7               (7*0x0001u)    /* Timer A Input divider expansion : /8 */
2445 
 
2446 
/* T0A5IV Definitions */
2447 
#define TA0IV_NONE             (0x0000)       /* No Interrupt pending */
2448 
#define TA0IV_TA0CCR1          (0x0002)       /* TA0CCR1_CCIFG */
2449 
#define TA0IV_TA0CCR2          (0x0004)       /* TA0CCR2_CCIFG */
2450 
#define TA0IV_TA0CCR3          (0x0006)       /* TA0CCR3_CCIFG */
2451 
#define TA0IV_TA0CCR4          (0x0008)       /* TA0CCR4_CCIFG */
2452 
#define TA0IV_5                (0x000A)       /* Reserved */
2453 
#define TA0IV_6                (0x000C)       /* Reserved */
2454 
#define TA0IV_TA0IFG           (0x000E)       /* TA0IFG */
2455 
 
2456 
/************************************************************
2457 
* Timer1_A3
2458 
************************************************************/
2459 
#define __MSP430_HAS_T1A3__                   /* Definition to show that Module is available */
2460 
 
2461 
SFR_16BIT(TA1CTL);                            /* Timer1_A3 Control */
2462 
SFR_8BIT(TA1CTL_L);                           /* Timer1_A3 Control */
2463 
SFR_8BIT(TA1CTL_H);                           /* Timer1_A3 Control */
2464 
SFR_16BIT(TA1CCTL0);                          /* Timer1_A3 Capture/Compare Control 0 */
2465 
SFR_8BIT(TA1CCTL0_L);                         /* Timer1_A3 Capture/Compare Control 0 */
2466 
SFR_8BIT(TA1CCTL0_H);                         /* Timer1_A3 Capture/Compare Control 0 */
2467 
SFR_16BIT(TA1CCTL1);                          /* Timer1_A3 Capture/Compare Control 1 */
2468 
SFR_8BIT(TA1CCTL1_L);                         /* Timer1_A3 Capture/Compare Control 1 */
2469 
SFR_8BIT(TA1CCTL1_H);                         /* Timer1_A3 Capture/Compare Control 1 */
2470 
SFR_16BIT(TA1CCTL2);                          /* Timer1_A3 Capture/Compare Control 2 */
2471 
SFR_8BIT(TA1CCTL2_L);                         /* Timer1_A3 Capture/Compare Control 2 */
2472 
SFR_8BIT(TA1CCTL2_H);                         /* Timer1_A3 Capture/Compare Control 2 */
2473 
SFR_16BIT(TA1R);                              /* Timer1_A3 */
2474 
SFR_8BIT(TA1R_L);                             /* Timer1_A3 */
2475 
SFR_8BIT(TA1R_H);                             /* Timer1_A3 */
2476 
SFR_16BIT(TA1CCR0);                           /* Timer1_A3 Capture/Compare 0 */
2477 
SFR_8BIT(TA1CCR0_L);                          /* Timer1_A3 Capture/Compare 0 */
2478 
SFR_8BIT(TA1CCR0_H);                          /* Timer1_A3 Capture/Compare 0 */
2479 
SFR_16BIT(TA1CCR1);                           /* Timer1_A3 Capture/Compare 1 */
2480 
SFR_8BIT(TA1CCR1_L);                          /* Timer1_A3 Capture/Compare 1 */
2481 
SFR_8BIT(TA1CCR1_H);                          /* Timer1_A3 Capture/Compare 1 */
2482 
SFR_16BIT(TA1CCR2);                           /* Timer1_A3 Capture/Compare 2 */
2483 
SFR_8BIT(TA1CCR2_L);                          /* Timer1_A3 Capture/Compare 2 */
2484 
SFR_8BIT(TA1CCR2_H);                          /* Timer1_A3 Capture/Compare 2 */
2485 
SFR_16BIT(TA1IV);                             /* Timer1_A3 Interrupt Vector Word */
2486 
SFR_8BIT(TA1IV_L);                            /* Timer1_A3 Interrupt Vector Word */
2487 
SFR_8BIT(TA1IV_H);                            /* Timer1_A3 Interrupt Vector Word */
2488 
SFR_16BIT(TA1EX0);                            /* Timer1_A3 Expansion Register 0 */
2489 
SFR_8BIT(TA1EX0_L);                           /* Timer1_A3 Expansion Register 0 */
2490 
SFR_8BIT(TA1EX0_H);                           /* Timer1_A3 Expansion Register 0 */
2491 
 
2492 
/* Bits are already defined within the Timer0_Ax */
2493 
 
2494 
/* TA1IV Definitions */
2495 
#define TA1IV_NONE             (0x0000)       /* No Interrupt pending */
2496 
#define TA1IV_TA1CCR1          (0x0002)       /* TA1CCR1_CCIFG */
2497 
#define TA1IV_TA1CCR2          (0x0004)       /* TA1CCR2_CCIFG */
2498 
#define TA1IV_3                (0x0006)       /* Reserved */
2499 
#define TA1IV_4                (0x0008)       /* Reserved */
2500 
#define TA1IV_5                (0x000A)       /* Reserved */
2501 
#define TA1IV_6                (0x000C)       /* Reserved */
2502 
#define TA1IV_TA1IFG           (0x000E)       /* TA1IFG */
2503 
 
2504 
/************************************************************
2505 
* Timer0_B7
2506 
************************************************************/
2507 
#define __MSP430_HAS_T0B7__                   /* Definition to show that Module is available */
2508 
 
2509 
SFR_16BIT(TB0CTL);                            /* Timer0_B7 Control */
2510 
SFR_8BIT(TB0CTL_L);                           /* Timer0_B7 Control */
2511 
SFR_8BIT(TB0CTL_H);                           /* Timer0_B7 Control */
2512 
SFR_16BIT(TB0CCTL0);                          /* Timer0_B7 Capture/Compare Control 0 */
2513 
SFR_8BIT(TB0CCTL0_L);                         /* Timer0_B7 Capture/Compare Control 0 */
2514 
SFR_8BIT(TB0CCTL0_H);                         /* Timer0_B7 Capture/Compare Control 0 */
2515 
SFR_16BIT(TB0CCTL1);                          /* Timer0_B7 Capture/Compare Control 1 */
2516 
SFR_8BIT(TB0CCTL1_L);                         /* Timer0_B7 Capture/Compare Control 1 */
2517 
SFR_8BIT(TB0CCTL1_H);                         /* Timer0_B7 Capture/Compare Control 1 */
2518 
SFR_16BIT(TB0CCTL2);                          /* Timer0_B7 Capture/Compare Control 2 */
2519 
SFR_8BIT(TB0CCTL2_L);                         /* Timer0_B7 Capture/Compare Control 2 */
2520 
SFR_8BIT(TB0CCTL2_H);                         /* Timer0_B7 Capture/Compare Control 2 */
2521 
SFR_16BIT(TB0CCTL3);                          /* Timer0_B7 Capture/Compare Control 3 */
2522 
SFR_8BIT(TB0CCTL3_L);                         /* Timer0_B7 Capture/Compare Control 3 */
2523 
SFR_8BIT(TB0CCTL3_H);                         /* Timer0_B7 Capture/Compare Control 3 */
2524 
SFR_16BIT(TB0CCTL4);                          /* Timer0_B7 Capture/Compare Control 4 */
2525 
SFR_8BIT(TB0CCTL4_L);                         /* Timer0_B7 Capture/Compare Control 4 */
2526 
SFR_8BIT(TB0CCTL4_H);                         /* Timer0_B7 Capture/Compare Control 4 */
2527 
SFR_16BIT(TB0CCTL5);                          /* Timer0_B7 Capture/Compare Control 5 */
2528 
SFR_8BIT(TB0CCTL5_L);                         /* Timer0_B7 Capture/Compare Control 5 */
2529 
SFR_8BIT(TB0CCTL5_H);                         /* Timer0_B7 Capture/Compare Control 5 */
2530 
SFR_16BIT(TB0CCTL6);                          /* Timer0_B7 Capture/Compare Control 6 */
2531 
SFR_8BIT(TB0CCTL6_L);                         /* Timer0_B7 Capture/Compare Control 6 */
2532 
SFR_8BIT(TB0CCTL6_H);                         /* Timer0_B7 Capture/Compare Control 6 */
2533 
SFR_16BIT(TB0R);                              /* Timer0_B7 */
2534 
SFR_8BIT(TB0R_L);                             /* Timer0_B7 */
2535 
SFR_8BIT(TB0R_H);                             /* Timer0_B7 */
2536 
SFR_16BIT(TB0CCR0);                           /* Timer0_B7 Capture/Compare 0 */
2537 
SFR_8BIT(TB0CCR0_L);                          /* Timer0_B7 Capture/Compare 0 */
2538 
SFR_8BIT(TB0CCR0_H);                          /* Timer0_B7 Capture/Compare 0 */
2539 
SFR_16BIT(TB0CCR1);                           /* Timer0_B7 Capture/Compare 1 */
2540 
SFR_8BIT(TB0CCR1_L);                          /* Timer0_B7 Capture/Compare 1 */
2541 
SFR_8BIT(TB0CCR1_H);                          /* Timer0_B7 Capture/Compare 1 */
2542 
SFR_16BIT(TB0CCR2);                           /* Timer0_B7 Capture/Compare 2 */
2543 
SFR_8BIT(TB0CCR2_L);                          /* Timer0_B7 Capture/Compare 2 */
2544 
SFR_8BIT(TB0CCR2_H);                          /* Timer0_B7 Capture/Compare 2 */
2545 
SFR_16BIT(TB0CCR3);                           /* Timer0_B7 Capture/Compare 3 */
2546 
SFR_8BIT(TB0CCR3_L);                          /* Timer0_B7 Capture/Compare 3 */
2547 
SFR_8BIT(TB0CCR3_H);                          /* Timer0_B7 Capture/Compare 3 */
2548 
SFR_16BIT(TB0CCR4);                           /* Timer0_B7 Capture/Compare 4 */
2549 
SFR_8BIT(TB0CCR4_L);                          /* Timer0_B7 Capture/Compare 4 */
2550 
SFR_8BIT(TB0CCR4_H);                          /* Timer0_B7 Capture/Compare 4 */
2551 
SFR_16BIT(TB0CCR5);                           /* Timer0_B7 Capture/Compare 5 */
2552 
SFR_8BIT(TB0CCR5_L);                          /* Timer0_B7 Capture/Compare 5 */
2553 
SFR_8BIT(TB0CCR5_H);                          /* Timer0_B7 Capture/Compare 5 */
2554 
SFR_16BIT(TB0CCR6);                           /* Timer0_B7 Capture/Compare 6 */
2555 
SFR_8BIT(TB0CCR6_L);                          /* Timer0_B7 Capture/Compare 6 */
2556 
SFR_8BIT(TB0CCR6_H);                          /* Timer0_B7 Capture/Compare 6 */
2557 
SFR_16BIT(TB0EX0);                            /* Timer0_B7 Expansion Register 0 */
2558 
SFR_8BIT(TB0EX0_L);                           /* Timer0_B7 Expansion Register 0 */
2559 
SFR_8BIT(TB0EX0_H);                           /* Timer0_B7 Expansion Register 0 */
2560 
SFR_16BIT(TB0IV);                             /* Timer0_B7 Interrupt Vector Word */
2561 
SFR_8BIT(TB0IV_L);                            /* Timer0_B7 Interrupt Vector Word */
2562 
SFR_8BIT(TB0IV_H);                            /* Timer0_B7 Interrupt Vector Word */
2563 
 
2564 
/* Legacy Type Definitions for TimerB */
2565 
#define TBCTL                  TB0CTL         /* Timer0_B7 Control */
2566 
#define TBCCTL0                TB0CCTL0       /* Timer0_B7 Capture/Compare Control 0 */
2567 
#define TBCCTL1                TB0CCTL1       /* Timer0_B7 Capture/Compare Control 1 */
2568 
#define TBCCTL2                TB0CCTL2       /* Timer0_B7 Capture/Compare Control 2 */
2569 
#define TBCCTL3                TB0CCTL3       /* Timer0_B7 Capture/Compare Control 3 */
2570 
#define TBCCTL4                TB0CCTL4       /* Timer0_B7 Capture/Compare Control 4 */
2571 
#define TBCCTL5                TB0CCTL5       /* Timer0_B7 Capture/Compare Control 5 */
2572 
#define TBCCTL6                TB0CCTL6       /* Timer0_B7 Capture/Compare Control 6 */
2573 
#define TBR                    TB0R           /* Timer0_B7 */
2574 
#define TBCCR0                 TB0CCR0        /* Timer0_B7 Capture/Compare 0 */
2575 
#define TBCCR1                 TB0CCR1        /* Timer0_B7 Capture/Compare 1 */
2576 
#define TBCCR2                 TB0CCR2        /* Timer0_B7 Capture/Compare 2 */
2577 
#define TBCCR3                 TB0CCR3        /* Timer0_B7 Capture/Compare 3 */
2578 
#define TBCCR4                 TB0CCR4        /* Timer0_B7 Capture/Compare 4 */
2579 
#define TBCCR5                 TB0CCR5        /* Timer0_B7 Capture/Compare 5 */
2580 
#define TBCCR6                 TB0CCR6        /* Timer0_B7 Capture/Compare 6 */
2581 
#define TBEX0                  TB0EX0         /* Timer0_B7 Expansion Register 0 */
2582 
#define TBIV                   TB0IV          /* Timer0_B7 Interrupt Vector Word */
2583 
#define TIMERB1_VECTOR       TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
2584 
#define TIMERB0_VECTOR       TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
2585 
 
2586 
/* TBxCTL Control Bits */
2587 
#define TBCLGRP1               (0x4000)       /* Timer0_B7 Compare latch load group 1 */
2588 
#define TBCLGRP0               (0x2000)       /* Timer0_B7 Compare latch load group 0 */
2589 
#define CNTL1                  (0x1000)       /* Counter lenght 1 */
2590 
#define CNTL0                  (0x0800)       /* Counter lenght 0 */
2591 
#define TBSSEL1                (0x0200)       /* Clock source 1 */
2592 
#define TBSSEL0                (0x0100)       /* Clock source 0 */
2593 
#define TBCLR                  (0x0004)       /* Timer0_B7 counter clear */
2594 
#define TBIE                   (0x0002)       /* Timer0_B7 interrupt enable */
2595 
#define TBIFG                  (0x0001)       /* Timer0_B7 interrupt flag */
2596 
 
2597 
/* TBxCTL Control Bits */
2598 
#define TBCLR_L                (0x0004)       /* Timer0_B7 counter clear */
2599 
#define TBIE_L                 (0x0002)       /* Timer0_B7 interrupt enable */
2600 
#define TBIFG_L                (0x0001)       /* Timer0_B7 interrupt flag */
2601 
 
2602 
/* TBxCTL Control Bits */
2603 
#define TBCLGRP1_H             (0x0040)       /* Timer0_B7 Compare latch load group 1 */
2604 
#define TBCLGRP0_H             (0x0020)       /* Timer0_B7 Compare latch load group 0 */
2605 
#define CNTL1_H                (0x0010)       /* Counter lenght 1 */
2606 
#define CNTL0_H                (0x0008)       /* Counter lenght 0 */
2607 
#define TBSSEL1_H              (0x0002)       /* Clock source 1 */
2608 
#define TBSSEL0_H              (0x0001)       /* Clock source 0 */
2609 
 
2610 
#define SHR1                   (0x4000)       /* Timer0_B7 Compare latch load group 1 */
2611 
#define SHR0                   (0x2000)       /* Timer0_B7 Compare latch load group 0 */
2612 
 
2613 
#define TBSSEL_0               (0*0x0100u)    /* Clock Source: TBCLK */
2614 
#define TBSSEL_1               (1*0x0100u)    /* Clock Source: ACLK  */
2615 
#define TBSSEL_2               (2*0x0100u)    /* Clock Source: SMCLK */
2616 
#define TBSSEL_3               (3*0x0100u)    /* Clock Source: INCLK */
2617 
#define CNTL_0                 (0*0x0800u)    /* Counter lenght: 16 bit */
2618 
#define CNTL_1                 (1*0x0800u)    /* Counter lenght: 12 bit */
2619 
#define CNTL_2                 (2*0x0800u)    /* Counter lenght: 10 bit */
2620 
#define CNTL_3                 (3*0x0800u)    /* Counter lenght:  8 bit */
2621 
#define SHR_0                  (0*0x2000u)    /* Timer0_B7 Group: 0 - individually */
2622 
#define SHR_1                  (1*0x2000u)    /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
2623 
#define SHR_2                  (2*0x2000u)    /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
2624 
#define SHR_3                  (3*0x2000u)    /* Timer0_B7 Group: 3 - 1 group (all) */
2625 
#define TBCLGRP_0              (0*0x2000u)    /* Timer0_B7 Group: 0 - individually */
2626 
#define TBCLGRP_1              (1*0x2000u)    /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
2627 
#define TBCLGRP_2              (2*0x2000u)    /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
2628 
#define TBCLGRP_3              (3*0x2000u)    /* Timer0_B7 Group: 3 - 1 group (all) */
2629 
#define TBSSEL__TACLK          (0*0x100u)     /* Timer0_B7 clock source select: 0 - TACLK */
2630 
#define TBSSEL__ACLK           (1*0x100u)     /* Timer0_B7 clock source select: 1 - ACLK  */
2631 
#define TBSSEL__SMCLK          (2*0x100u)     /* Timer0_B7 clock source select: 2 - SMCLK */
2632 
#define TBSSEL__INCLK          (3*0x100u)     /* Timer0_B7 clock source select: 3 - INCLK */
2633 
#define CNTL__16               (0*0x0800u)    /* Counter lenght: 16 bit */
2634 
#define CNTL__12               (1*0x0800u)    /* Counter lenght: 12 bit */
2635 
#define CNTL__10               (2*0x0800u)    /* Counter lenght: 10 bit */
2636 
#define CNTL__8                (3*0x0800u)    /* Counter lenght:  8 bit */
2637 
 
2638 
/* Additional Timer B Control Register bits are defined in Timer A */
2639 
/* TBxCCTLx Control Bits */
2640 
#define CLLD1                  (0x0400)       /* Compare latch load source 1 */
2641 
#define CLLD0                  (0x0200)       /* Compare latch load source 0 */
2642 
 
2643 
/* TBxCCTLx Control Bits */
2644 
 
2645 
/* TBxCCTLx Control Bits */
2646 
#define CLLD1_H                (0x0004)       /* Compare latch load source 1 */
2647 
#define CLLD0_H                (0x0002)       /* Compare latch load source 0 */
2648 
 
2649 
#define SLSHR1                 (0x0400)       /* Compare latch load source 1 */
2650 
#define SLSHR0                 (0x0200)       /* Compare latch load source 0 */
2651 
 
2652 
#define SLSHR_0                (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
2653 
#define SLSHR_1                (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
2654 
#define SLSHR_2                (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
2655 
#define SLSHR_3                (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
2656 
 
2657 
#define CLLD_0                 (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
2658 
#define CLLD_1                 (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
2659 
#define CLLD_2                 (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
2660 
#define CLLD_3                 (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
2661 
 
2662 
/* TBxEX0 Control Bits */
2663 
#define TBIDEX0                (0x0001)       /* Timer0_B7 Input divider expansion Bit: 0 */
2664 
#define TBIDEX1                (0x0002)       /* Timer0_B7 Input divider expansion Bit: 1 */
2665 
#define TBIDEX2                (0x0004)       /* Timer0_B7 Input divider expansion Bit: 2 */
2666 
 
2667 
/* TBxEX0 Control Bits */
2668 
#define TBIDEX0_L              (0x0001)       /* Timer0_B7 Input divider expansion Bit: 0 */
2669 
#define TBIDEX1_L              (0x0002)       /* Timer0_B7 Input divider expansion Bit: 1 */
2670 
#define TBIDEX2_L              (0x0004)       /* Timer0_B7 Input divider expansion Bit: 2 */
2671 
 
2672 
/* TBxEX0 Control Bits */
2673 
 
2674 
#define TBIDEX_0               (0*0x0001u)    /* Timer0_B7 Input divider expansion : /1 */
2675 
#define TBIDEX_1               (1*0x0001u)    /* Timer0_B7 Input divider expansion : /2 */
2676 
#define TBIDEX_2               (2*0x0001u)    /* Timer0_B7 Input divider expansion : /3 */
2677 
#define TBIDEX_3               (3*0x0001u)    /* Timer0_B7 Input divider expansion : /4 */
2678 
#define TBIDEX_4               (4*0x0001u)    /* Timer0_B7 Input divider expansion : /5 */
2679 
#define TBIDEX_5               (5*0x0001u)    /* Timer0_B7 Input divider expansion : /6 */
2680 
#define TBIDEX_6               (6*0x0001u)    /* Timer0_B7 Input divider expansion : /7 */
2681 
#define TBIDEX_7               (7*0x0001u)    /* Timer0_B7 Input divider expansion : /8 */
2682 
#define TBIDEX__1              (0*0x0001u)    /* Timer0_B7 Input divider expansion : /1 */
2683 
#define TBIDEX__2              (1*0x0001u)    /* Timer0_B7 Input divider expansion : /2 */
2684 
#define TBIDEX__3              (2*0x0001u)    /* Timer0_B7 Input divider expansion : /3 */
2685 
#define TBIDEX__4              (3*0x0001u)    /* Timer0_B7 Input divider expansion : /4 */
2686 
#define TBIDEX__5              (4*0x0001u)    /* Timer0_B7 Input divider expansion : /5 */
2687 
#define TBIDEX__6              (5*0x0001u)    /* Timer0_B7 Input divider expansion : /6 */
2688 
#define TBIDEX__7              (6*0x0001u)    /* Timer0_B7 Input divider expansion : /7 */
2689 
#define TBIDEX__8              (7*0x0001u)    /* Timer0_B7 Input divider expansion : /8 */
2690 
 
2691 
/* TB0IV Definitions */
2692 
#define TB0IV_NONE             (0x0000)       /* No Interrupt pending */
2693 
#define TB0IV_TB1CCR1          (0x0002)       /* TBCCR1_CCIFG */
2694 
#define TB0IV_TB1CCR2          (0x0004)       /* TBCCR2_CCIFG */
2695 
#define TB0IV_3                (0x0006)       /* Reserved */
2696 
#define TB0IV_4                (0x0008)       /* Reserved */
2697 
#define TB0IV_5                (0x000A)       /* Reserved */
2698 
#define TB0IV_6                (0x000C)       /* Reserved */
2699 
#define TB0IV_TB0IFG           (0x000E)       /* TBIFG */
2700 
 
2701 
 
2702 
/************************************************************
2703 
* UNIFIED CLOCK SYSTEM
2704 
************************************************************/
2705 
#define __MSP430_HAS_UCS__                    /* Definition to show that Module is available */
2706 
 
2707 
SFR_16BIT(UCSCTL0);                           /* UCS Control Register 0 */
2708 
SFR_8BIT(UCSCTL0_L);                          /* UCS Control Register 0 */
2709 
SFR_8BIT(UCSCTL0_H);                          /* UCS Control Register 0 */
2710 
SFR_16BIT(UCSCTL1);                           /* UCS Control Register 1 */
2711 
SFR_8BIT(UCSCTL1_L);                          /* UCS Control Register 1 */
2712 
SFR_8BIT(UCSCTL1_H);                          /* UCS Control Register 1 */
2713 
SFR_16BIT(UCSCTL2);                           /* UCS Control Register 2 */
2714 
SFR_8BIT(UCSCTL2_L);                          /* UCS Control Register 2 */
2715 
SFR_8BIT(UCSCTL2_H);                          /* UCS Control Register 2 */
2716 
SFR_16BIT(UCSCTL3);                           /* UCS Control Register 3 */
2717 
SFR_8BIT(UCSCTL3_L);                          /* UCS Control Register 3 */
2718 
SFR_8BIT(UCSCTL3_H);                          /* UCS Control Register 3 */
2719 
SFR_16BIT(UCSCTL4);                           /* UCS Control Register 4 */
2720 
SFR_8BIT(UCSCTL4_L);                          /* UCS Control Register 4 */
2721 
SFR_8BIT(UCSCTL4_H);                          /* UCS Control Register 4 */
2722 
SFR_16BIT(UCSCTL5);                           /* UCS Control Register 5 */
2723 
SFR_8BIT(UCSCTL5_L);                          /* UCS Control Register 5 */
2724 
SFR_8BIT(UCSCTL5_H);                          /* UCS Control Register 5 */
2725 
SFR_16BIT(UCSCTL6);                           /* UCS Control Register 6 */
2726 
SFR_8BIT(UCSCTL6_L);                          /* UCS Control Register 6 */
2727 
SFR_8BIT(UCSCTL6_H);                          /* UCS Control Register 6 */
2728 
SFR_16BIT(UCSCTL7);                           /* UCS Control Register 7 */
2729 
SFR_8BIT(UCSCTL7_L);                          /* UCS Control Register 7 */
2730 
SFR_8BIT(UCSCTL7_H);                          /* UCS Control Register 7 */
2731 
SFR_16BIT(UCSCTL8);                           /* UCS Control Register 8 */
2732 
SFR_8BIT(UCSCTL8_L);                          /* UCS Control Register 8 */
2733 
SFR_8BIT(UCSCTL8_H);                          /* UCS Control Register 8 */
2734 
 
2735 
/* UCSCTL0 Control Bits */
2736 
//#define RESERVED            (0x0001)    /* RESERVED */
2737 
//#define RESERVED            (0x0002)    /* RESERVED */
2738 
//#define RESERVED            (0x0004)    /* RESERVED */
2739 
#define MOD0                   (0x0008)       /* Modulation Bit Counter Bit : 0 */
2740 
#define MOD1                   (0x0010)       /* Modulation Bit Counter Bit : 1 */
2741 
#define MOD2                   (0x0020)       /* Modulation Bit Counter Bit : 2 */
2742 
#define MOD3                   (0x0040)       /* Modulation Bit Counter Bit : 3 */
2743 
#define MOD4                   (0x0080)       /* Modulation Bit Counter Bit : 4 */
2744 
#define DCO0                   (0x0100)       /* DCO TAP Bit : 0 */
2745 
#define DCO1                   (0x0200)       /* DCO TAP Bit : 1 */
2746 
#define DCO2                   (0x0400)       /* DCO TAP Bit : 2 */
2747 
#define DCO3                   (0x0800)       /* DCO TAP Bit : 3 */
2748 
#define DCO4                   (0x1000)       /* DCO TAP Bit : 4 */
2749 
//#define RESERVED            (0x2000)    /* RESERVED */
2750 
//#define RESERVED            (0x4000)    /* RESERVED */
2751 
//#define RESERVED            (0x8000)    /* RESERVED */
2752 
 
2753 
/* UCSCTL0 Control Bits */
2754 
//#define RESERVED            (0x0001)    /* RESERVED */
2755 
//#define RESERVED            (0x0002)    /* RESERVED */
2756 
//#define RESERVED            (0x0004)    /* RESERVED */
2757 
#define MOD0_L                 (0x0008)       /* Modulation Bit Counter Bit : 0 */
2758 
#define MOD1_L                 (0x0010)       /* Modulation Bit Counter Bit : 1 */
2759 
#define MOD2_L                 (0x0020)       /* Modulation Bit Counter Bit : 2 */
2760 
#define MOD3_L                 (0x0040)       /* Modulation Bit Counter Bit : 3 */
2761 
#define MOD4_L                 (0x0080)       /* Modulation Bit Counter Bit : 4 */
2762 
//#define RESERVED            (0x2000)    /* RESERVED */
2763 
//#define RESERVED            (0x4000)    /* RESERVED */
2764 
//#define RESERVED            (0x8000)    /* RESERVED */
2765 
 
2766 
/* UCSCTL0 Control Bits */
2767 
//#define RESERVED            (0x0001)    /* RESERVED */
2768 
//#define RESERVED            (0x0002)    /* RESERVED */
2769 
//#define RESERVED            (0x0004)    /* RESERVED */
2770 
#define DCO0_H                 (0x0001)       /* DCO TAP Bit : 0 */
2771 
#define DCO1_H                 (0x0002)       /* DCO TAP Bit : 1 */
2772 
#define DCO2_H                 (0x0004)       /* DCO TAP Bit : 2 */
2773 
#define DCO3_H                 (0x0008)       /* DCO TAP Bit : 3 */
2774 
#define DCO4_H                 (0x0010)       /* DCO TAP Bit : 4 */
2775 
//#define RESERVED            (0x2000)    /* RESERVED */
2776 
//#define RESERVED            (0x4000)    /* RESERVED */
2777 
//#define RESERVED            (0x8000)    /* RESERVED */
2778 
 
2779 
/* UCSCTL1 Control Bits */
2780 
#define DISMOD                 (0x0001)       /* Disable Modulation */
2781 
#define DCOR                   (0x0002)       /* DCO External Resistor Select */
2782 
//#define RESERVED            (0x0004)    /* RESERVED */
2783 
//#define RESERVED            (0x0008)    /* RESERVED */
2784 
#define DCORSEL0               (0x0010)       /* DCO Freq. Range Select Bit : 0 */
2785 
#define DCORSEL1               (0x0020)       /* DCO Freq. Range Select Bit : 1 */
2786 
#define DCORSEL2               (0x0040)       /* DCO Freq. Range Select Bit : 2 */
2787 
//#define RESERVED            (0x0080)    /* RESERVED */
2788 
//#define RESERVED            (0x0100)    /* RESERVED */
2789 
//#define RESERVED            (0x0200)    /* RESERVED */
2790 
//#define RESERVED            (0x0400)    /* RESERVED */
2791 
//#define RESERVED            (0x0800)    /* RESERVED */
2792 
//#define RESERVED            (0x1000)    /* RESERVED */
2793 
//#define RESERVED            (0x2000)    /* RESERVED */
2794 
//#define RESERVED            (0x4000)    /* RESERVED */
2795 
//#define RESERVED            (0x8000)    /* RESERVED */
2796 
 
2797 
/* UCSCTL1 Control Bits */
2798 
#define DISMOD_L               (0x0001)       /* Disable Modulation */
2799 
#define DCOR_L                 (0x0002)       /* DCO External Resistor Select */
2800 
//#define RESERVED            (0x0004)    /* RESERVED */
2801 
//#define RESERVED            (0x0008)    /* RESERVED */
2802 
#define DCORSEL0_L             (0x0010)       /* DCO Freq. Range Select Bit : 0 */
2803 
#define DCORSEL1_L             (0x0020)       /* DCO Freq. Range Select Bit : 1 */
2804 
#define DCORSEL2_L             (0x0040)       /* DCO Freq. Range Select Bit : 2 */
2805 
//#define RESERVED            (0x0080)    /* RESERVED */
2806 
//#define RESERVED            (0x0100)    /* RESERVED */
2807 
//#define RESERVED            (0x0200)    /* RESERVED */
2808 
//#define RESERVED            (0x0400)    /* RESERVED */
2809 
//#define RESERVED            (0x0800)    /* RESERVED */
2810 
//#define RESERVED            (0x1000)    /* RESERVED */
2811 
//#define RESERVED            (0x2000)    /* RESERVED */
2812 
//#define RESERVED            (0x4000)    /* RESERVED */
2813 
//#define RESERVED            (0x8000)    /* RESERVED */
2814 
 
2815 
/* UCSCTL1 Control Bits */
2816 
//#define RESERVED            (0x0004)    /* RESERVED */
2817 
//#define RESERVED            (0x0008)    /* RESERVED */
2818 
//#define RESERVED            (0x0080)    /* RESERVED */
2819 
//#define RESERVED            (0x0100)    /* RESERVED */
2820 
//#define RESERVED            (0x0200)    /* RESERVED */
2821 
//#define RESERVED            (0x0400)    /* RESERVED */
2822 
//#define RESERVED            (0x0800)    /* RESERVED */
2823 
//#define RESERVED            (0x1000)    /* RESERVED */
2824 
//#define RESERVED            (0x2000)    /* RESERVED */
2825 
//#define RESERVED            (0x4000)    /* RESERVED */
2826 
//#define RESERVED            (0x8000)    /* RESERVED */
2827 
 
2828 
#define DCORSEL_0              (0x0000)       /* DCO RSEL 0 */
2829 
#define DCORSEL_1              (0x0010)       /* DCO RSEL 1 */
2830 
#define DCORSEL_2              (0x0020)       /* DCO RSEL 2 */
2831 
#define DCORSEL_3              (0x0030)       /* DCO RSEL 3 */
2832 
#define DCORSEL_4              (0x0040)       /* DCO RSEL 4 */
2833 
#define DCORSEL_5              (0x0050)       /* DCO RSEL 5 */
2834 
#define DCORSEL_6              (0x0060)       /* DCO RSEL 6 */
2835 
#define DCORSEL_7              (0x0070)       /* DCO RSEL 7 */
2836 
 
2837 
/* UCSCTL2 Control Bits */
2838 
#define FLLN0                  (0x0001)       /* FLL Multipier Bit : 0 */
2839 
#define FLLN1                  (0x0002)       /* FLL Multipier Bit : 1 */
2840 
#define FLLN2                  (0x0004)       /* FLL Multipier Bit : 2 */
2841 
#define FLLN3                  (0x0008)       /* FLL Multipier Bit : 3 */
2842 
#define FLLN4                  (0x0010)       /* FLL Multipier Bit : 4 */
2843 
#define FLLN5                  (0x0020)       /* FLL Multipier Bit : 5 */
2844 
#define FLLN6                  (0x0040)       /* FLL Multipier Bit : 6 */
2845 
#define FLLN7                  (0x0080)       /* FLL Multipier Bit : 7 */
2846 
#define FLLN8                  (0x0100)       /* FLL Multipier Bit : 8 */
2847 
#define FLLN9                  (0x0200)       /* FLL Multipier Bit : 9 */
2848 
//#define RESERVED            (0x0400)    /* RESERVED */
2849 
//#define RESERVED            (0x0800)    /* RESERVED */
2850 
#define FLLD0                  (0x1000)       /* Loop Divider Bit : 0 */
2851 
#define FLLD1                  (0x2000)       /* Loop Divider Bit : 1 */
2852 
#define FLLD2                  (0x4000)       /* Loop Divider Bit : 1 */
2853 
//#define RESERVED            (0x8000)    /* RESERVED */
2854 
 
2855 
/* UCSCTL2 Control Bits */
2856 
#define FLLN0_L                (0x0001)       /* FLL Multipier Bit : 0 */
2857 
#define FLLN1_L                (0x0002)       /* FLL Multipier Bit : 1 */
2858 
#define FLLN2_L                (0x0004)       /* FLL Multipier Bit : 2 */
2859 
#define FLLN3_L                (0x0008)       /* FLL Multipier Bit : 3 */
2860 
#define FLLN4_L                (0x0010)       /* FLL Multipier Bit : 4 */
2861 
#define FLLN5_L                (0x0020)       /* FLL Multipier Bit : 5 */
2862 
#define FLLN6_L                (0x0040)       /* FLL Multipier Bit : 6 */
2863 
#define FLLN7_L                (0x0080)       /* FLL Multipier Bit : 7 */
2864 
//#define RESERVED            (0x0400)    /* RESERVED */
2865 
//#define RESERVED            (0x0800)    /* RESERVED */
2866 
//#define RESERVED            (0x8000)    /* RESERVED */
2867 
 
2868 
/* UCSCTL2 Control Bits */
2869 
#define FLLN8_H                (0x0001)       /* FLL Multipier Bit : 8 */
2870 
#define FLLN9_H                (0x0002)       /* FLL Multipier Bit : 9 */
2871 
//#define RESERVED            (0x0400)    /* RESERVED */
2872 
//#define RESERVED            (0x0800)    /* RESERVED */
2873 
#define FLLD0_H                (0x0010)       /* Loop Divider Bit : 0 */
2874 
#define FLLD1_H                (0x0020)       /* Loop Divider Bit : 1 */
2875 
#define FLLD2_H                (0x0040)       /* Loop Divider Bit : 1 */
2876 
//#define RESERVED            (0x8000)    /* RESERVED */
2877 
 
2878 
#define FLLD_0                 (0x0000)       /* Multiply Selected Loop Freq. 1 */
2879 
#define FLLD_1                 (0x1000)       /* Multiply Selected Loop Freq. 2 */
2880 
#define FLLD_2                 (0x2000)       /* Multiply Selected Loop Freq. 4 */
2881 
#define FLLD_3                 (0x3000)       /* Multiply Selected Loop Freq. 8 */
2882 
#define FLLD_4                 (0x4000)       /* Multiply Selected Loop Freq. 16 */
2883 
#define FLLD_5                 (0x5000)       /* Multiply Selected Loop Freq. 32 */
2884 
#define FLLD_6                 (0x6000)       /* Multiply Selected Loop Freq. 32 */
2885 
#define FLLD_7                 (0x7000)       /* Multiply Selected Loop Freq. 32 */
2886 
#define FLLD__1                (0x0000)       /* Multiply Selected Loop Freq. By 1 */
2887 
#define FLLD__2                (0x1000)       /* Multiply Selected Loop Freq. By 2 */
2888 
#define FLLD__4                (0x2000)       /* Multiply Selected Loop Freq. By 4 */
2889 
#define FLLD__8                (0x3000)       /* Multiply Selected Loop Freq. By 8 */
2890 
#define FLLD__16               (0x4000)       /* Multiply Selected Loop Freq. By 16 */
2891 
#define FLLD__32               (0x5000)       /* Multiply Selected Loop Freq. By 32 */
2892 
 
2893 
/* UCSCTL3 Control Bits */
2894 
#define FLLREFDIV0             (0x0001)       /* Reference Divider Bit : 0 */
2895 
#define FLLREFDIV1             (0x0002)       /* Reference Divider Bit : 1 */
2896 
#define FLLREFDIV2             (0x0004)       /* Reference Divider Bit : 2 */
2897 
//#define RESERVED            (0x0008)    /* RESERVED */
2898 
#define SELREF0                (0x0010)       /* FLL Reference Clock Select Bit : 0 */
2899 
#define SELREF1                (0x0020)       /* FLL Reference Clock Select Bit : 1 */
2900 
#define SELREF2                (0x0040)       /* FLL Reference Clock Select Bit : 2 */
2901 
//#define RESERVED            (0x0080)    /* RESERVED */
2902 
//#define RESERVED            (0x0100)    /* RESERVED */
2903 
//#define RESERVED            (0x0200)    /* RESERVED */
2904 
//#define RESERVED            (0x0400)    /* RESERVED */
2905 
//#define RESERVED            (0x0800)    /* RESERVED */
2906 
//#define RESERVED            (0x1000)    /* RESERVED */
2907 
//#define RESERVED            (0x2000)    /* RESERVED */
2908 
//#define RESERVED            (0x4000)    /* RESERVED */
2909 
//#define RESERVED            (0x8000)    /* RESERVED */
2910 
 
2911 
/* UCSCTL3 Control Bits */
2912 
#define FLLREFDIV0_L           (0x0001)       /* Reference Divider Bit : 0 */
2913 
#define FLLREFDIV1_L           (0x0002)       /* Reference Divider Bit : 1 */
2914 
#define FLLREFDIV2_L           (0x0004)       /* Reference Divider Bit : 2 */
2915 
//#define RESERVED            (0x0008)    /* RESERVED */
2916 
#define SELREF0_L              (0x0010)       /* FLL Reference Clock Select Bit : 0 */
2917 
#define SELREF1_L              (0x0020)       /* FLL Reference Clock Select Bit : 1 */
2918 
#define SELREF2_L              (0x0040)       /* FLL Reference Clock Select Bit : 2 */
2919 
//#define RESERVED            (0x0080)    /* RESERVED */
2920 
//#define RESERVED            (0x0100)    /* RESERVED */
2921 
//#define RESERVED            (0x0200)    /* RESERVED */
2922 
//#define RESERVED            (0x0400)    /* RESERVED */
2923 
//#define RESERVED            (0x0800)    /* RESERVED */
2924 
//#define RESERVED            (0x1000)    /* RESERVED */
2925 
//#define RESERVED            (0x2000)    /* RESERVED */
2926 
//#define RESERVED            (0x4000)    /* RESERVED */
2927 
//#define RESERVED            (0x8000)    /* RESERVED */
2928 
 
2929 
/* UCSCTL3 Control Bits */
2930 
//#define RESERVED            (0x0008)    /* RESERVED */
2931 
//#define RESERVED            (0x0080)    /* RESERVED */
2932 
//#define RESERVED            (0x0100)    /* RESERVED */
2933 
//#define RESERVED            (0x0200)    /* RESERVED */
2934 
//#define RESERVED            (0x0400)    /* RESERVED */
2935 
//#define RESERVED            (0x0800)    /* RESERVED */
2936 
//#define RESERVED            (0x1000)    /* RESERVED */
2937 
//#define RESERVED            (0x2000)    /* RESERVED */
2938 
//#define RESERVED            (0x4000)    /* RESERVED */
2939 
//#define RESERVED            (0x8000)    /* RESERVED */
2940 
 
2941 
#define FLLREFDIV_0            (0x0000)       /* Reference Divider: f(LFCLK)/1 */
2942 
#define FLLREFDIV_1            (0x0001)       /* Reference Divider: f(LFCLK)/2 */
2943 
#define FLLREFDIV_2            (0x0002)       /* Reference Divider: f(LFCLK)/4 */
2944 
#define FLLREFDIV_3            (0x0003)       /* Reference Divider: f(LFCLK)/8 */
2945 
#define FLLREFDIV_4            (0x0004)       /* Reference Divider: f(LFCLK)/12 */
2946 
#define FLLREFDIV_5            (0x0005)       /* Reference Divider: f(LFCLK)/16 */
2947 
#define FLLREFDIV_6            (0x0006)       /* Reference Divider: f(LFCLK)/16 */
2948 
#define FLLREFDIV_7            (0x0007)       /* Reference Divider: f(LFCLK)/16 */
2949 
#define FLLREFDIV__1           (0x0000)       /* Reference Divider: f(LFCLK)/1 */
2950 
#define FLLREFDIV__2           (0x0001)       /* Reference Divider: f(LFCLK)/2 */
2951 
#define FLLREFDIV__4           (0x0002)       /* Reference Divider: f(LFCLK)/4 */
2952 
#define FLLREFDIV__8           (0x0003)       /* Reference Divider: f(LFCLK)/8 */
2953 
#define FLLREFDIV__12          (0x0004)       /* Reference Divider: f(LFCLK)/12 */
2954 
#define FLLREFDIV__16          (0x0005)       /* Reference Divider: f(LFCLK)/16 */
2955 
#define SELREF_0               (0x0000)       /* FLL Reference Clock Select 0 */
2956 
#define SELREF_1               (0x0010)       /* FLL Reference Clock Select 1 */
2957 
#define SELREF_2               (0x0020)       /* FLL Reference Clock Select 2 */
2958 
#define SELREF_3               (0x0030)       /* FLL Reference Clock Select 3 */
2959 
#define SELREF_4               (0x0040)       /* FLL Reference Clock Select 4 */
2960 
#define SELREF_5               (0x0050)       /* FLL Reference Clock Select 5 */
2961 
#define SELREF_6               (0x0060)       /* FLL Reference Clock Select 6 */
2962 
#define SELREF_7               (0x0070)       /* FLL Reference Clock Select 7 */
2963 
#define SELREF__XT1CLK         (0x0000)       /* Multiply Selected Loop Freq. By XT1CLK */
2964 
#define SELREF__REFOCLK        (0x0020)       /* Multiply Selected Loop Freq. By REFOCLK */
2965 
#define SELREF__XT2CLK         (0x0050)       /* Multiply Selected Loop Freq. By XT2CLK */
2966 
 
2967 
/* UCSCTL4 Control Bits */
2968 
#define SELM0                  (0x0001)       /* MCLK Source Select Bit: 0 */
2969 
#define SELM1                  (0x0002)       /* MCLK Source Select Bit: 1 */
2970 
#define SELM2                  (0x0004)       /* MCLK Source Select Bit: 2 */
2971 
//#define RESERVED            (0x0008)    /* RESERVED */
2972 
#define SELS0                  (0x0010)       /* SMCLK Source Select Bit: 0 */
2973 
#define SELS1                  (0x0020)       /* SMCLK Source Select Bit: 1 */
2974 
#define SELS2                  (0x0040)       /* SMCLK Source Select Bit: 2 */
2975 
//#define RESERVED            (0x0080)    /* RESERVED */
2976 
#define SELA0                  (0x0100)       /* ACLK Source Select Bit: 0 */
2977 
#define SELA1                  (0x0200)       /* ACLK Source Select Bit: 1 */
2978 
#define SELA2                  (0x0400)       /* ACLK Source Select Bit: 2 */
2979 
//#define RESERVED            (0x0800)    /* RESERVED */
2980 
//#define RESERVED            (0x1000)    /* RESERVED */
2981 
//#define RESERVED            (0x2000)    /* RESERVED */
2982 
//#define RESERVED            (0x4000)    /* RESERVED */
2983 
//#define RESERVED            (0x8000)    /* RESERVED */
2984 
 
2985 
/* UCSCTL4 Control Bits */
2986 
#define SELM0_L                (0x0001)       /* MCLK Source Select Bit: 0 */
2987 
#define SELM1_L                (0x0002)       /* MCLK Source Select Bit: 1 */
2988 
#define SELM2_L                (0x0004)       /* MCLK Source Select Bit: 2 */
2989 
//#define RESERVED            (0x0008)    /* RESERVED */
2990 
#define SELS0_L                (0x0010)       /* SMCLK Source Select Bit: 0 */
2991 
#define SELS1_L                (0x0020)       /* SMCLK Source Select Bit: 1 */
2992 
#define SELS2_L                (0x0040)       /* SMCLK Source Select Bit: 2 */
2993 
//#define RESERVED            (0x0080)    /* RESERVED */
2994 
//#define RESERVED            (0x0800)    /* RESERVED */
2995 
//#define RESERVED            (0x1000)    /* RESERVED */
2996 
//#define RESERVED            (0x2000)    /* RESERVED */
2997 
//#define RESERVED            (0x4000)    /* RESERVED */
2998 
//#define RESERVED            (0x8000)    /* RESERVED */
2999 
 
3000 
/* UCSCTL4 Control Bits */
3001 
//#define RESERVED            (0x0008)    /* RESERVED */
3002 
//#define RESERVED            (0x0080)    /* RESERVED */
3003 
#define SELA0_H                (0x0001)       /* ACLK Source Select Bit: 0 */
3004 
#define SELA1_H                (0x0002)       /* ACLK Source Select Bit: 1 */
3005 
#define SELA2_H                (0x0004)       /* ACLK Source Select Bit: 2 */
3006 
//#define RESERVED            (0x0800)    /* RESERVED */
3007 
//#define RESERVED            (0x1000)    /* RESERVED */
3008 
//#define RESERVED            (0x2000)    /* RESERVED */
3009 
//#define RESERVED            (0x4000)    /* RESERVED */
3010 
//#define RESERVED            (0x8000)    /* RESERVED */
3011 
 
3012 
#define SELM_0                 (0x0000)       /* MCLK Source Select 0 */
3013 
#define SELM_1                 (0x0001)       /* MCLK Source Select 1 */
3014 
#define SELM_2                 (0x0002)       /* MCLK Source Select 2 */
3015 
#define SELM_3                 (0x0003)       /* MCLK Source Select 3 */
3016 
#define SELM_4                 (0x0004)       /* MCLK Source Select 4 */
3017 
#define SELM_5                 (0x0005)       /* MCLK Source Select 5 */
3018 
#define SELM_6                 (0x0006)       /* MCLK Source Select 6 */
3019 
#define SELM_7                 (0x0007)       /* MCLK Source Select 7 */
3020 
#define SELM__XT1CLK           (0x0000)       /* MCLK Source Select XT1CLK */
3021 
#define SELM__VLOCLK           (0x0001)       /* MCLK Source Select VLOCLK */
3022 
#define SELM__REFOCLK          (0x0002)       /* MCLK Source Select REFOCLK */
3023 
#define SELM__DCOCLK           (0x0003)       /* MCLK Source Select DCOCLK */
3024 
#define SELM__DCOCLKDIV        (0x0004)       /* MCLK Source Select DCOCLKDIV */
3025 
#define SELM__XT2CLK           (0x0005)       /* MCLK Source Select XT2CLK */
3026 
 
3027 
#define SELS_0                 (0x0000)       /* SMCLK Source Select 0 */
3028 
#define SELS_1                 (0x0010)       /* SMCLK Source Select 1 */
3029 
#define SELS_2                 (0x0020)       /* SMCLK Source Select 2 */
3030 
#define SELS_3                 (0x0030)       /* SMCLK Source Select 3 */
3031 
#define SELS_4                 (0x0040)       /* SMCLK Source Select 4 */
3032 
#define SELS_5                 (0x0050)       /* SMCLK Source Select 5 */
3033 
#define SELS_6                 (0x0060)       /* SMCLK Source Select 6 */
3034 
#define SELS_7                 (0x0070)       /* SMCLK Source Select 7 */
3035 
#define SELS__XT1CLK           (0x0000)       /* SMCLK Source Select XT1CLK */
3036 
#define SELS__VLOCLK           (0x0010)       /* SMCLK Source Select VLOCLK */
3037 
#define SELS__REFOCLK          (0x0020)       /* SMCLK Source Select REFOCLK */
3038 
#define SELS__DCOCLK           (0x0030)       /* SMCLK Source Select DCOCLK */
3039 
#define SELS__DCOCLKDIV        (0x0040)       /* SMCLK Source Select DCOCLKDIV */
3040 
#define SELS__XT2CLK           (0x0050)       /* SMCLK Source Select XT2CLK */
3041 
 
3042 
#define SELA_0                 (0x0000)       /* ACLK Source Select 0 */
3043 
#define SELA_1                 (0x0100)       /* ACLK Source Select 1 */
3044 
#define SELA_2                 (0x0200)       /* ACLK Source Select 2 */
3045 
#define SELA_3                 (0x0300)       /* ACLK Source Select 3 */
3046 
#define SELA_4                 (0x0400)       /* ACLK Source Select 4 */
3047 
#define SELA_5                 (0x0500)       /* ACLK Source Select 5 */
3048 
#define SELA_6                 (0x0600)       /* ACLK Source Select 6 */
3049 
#define SELA_7                 (0x0700)       /* ACLK Source Select 7 */
3050 
#define SELA__XT1CLK           (0x0000)       /* ACLK Source Select XT1CLK */
3051 
#define SELA__VLOCLK           (0x0100)       /* ACLK Source Select VLOCLK */
3052 
#define SELA__REFOCLK          (0x0200)       /* ACLK Source Select REFOCLK */
3053 
#define SELA__DCOCLK           (0x0300)       /* ACLK Source Select DCOCLK */
3054 
#define SELA__DCOCLKDIV        (0x0400)       /* ACLK Source Select DCOCLKDIV */
3055 
#define SELA__XT2CLK           (0x0500)       /* ACLK Source Select XT2CLK */
3056 
 
3057 
/* UCSCTL5 Control Bits */
3058 
#define DIVM0                  (0x0001)       /* MCLK Divider Bit: 0 */
3059 
#define DIVM1                  (0x0002)       /* MCLK Divider Bit: 1 */
3060 
#define DIVM2                  (0x0004)       /* MCLK Divider Bit: 2 */
3061 
//#define RESERVED            (0x0008)    /* RESERVED */
3062 
#define DIVS0                  (0x0010)       /* SMCLK Divider Bit: 0 */
3063 
#define DIVS1                  (0x0020)       /* SMCLK Divider Bit: 1 */
3064 
#define DIVS2                  (0x0040)       /* SMCLK Divider Bit: 2 */
3065 
//#define RESERVED            (0x0080)    /* RESERVED */
3066 
#define DIVA0                  (0x0100)       /* ACLK Divider Bit: 0 */
3067 
#define DIVA1                  (0x0200)       /* ACLK Divider Bit: 1 */
3068 
#define DIVA2                  (0x0400)       /* ACLK Divider Bit: 2 */
3069 
//#define RESERVED            (0x0800)    /* RESERVED */
3070 
#define DIVPA0                 (0x1000)       /* ACLK from Pin Divider Bit: 0 */
3071 
#define DIVPA1                 (0x2000)       /* ACLK from Pin Divider Bit: 1 */
3072 
#define DIVPA2                 (0x4000)       /* ACLK from Pin Divider Bit: 2 */
3073 
//#define RESERVED            (0x8000)    /* RESERVED */
3074 
 
3075 
/* UCSCTL5 Control Bits */
3076 
#define DIVM0_L                (0x0001)       /* MCLK Divider Bit: 0 */
3077 
#define DIVM1_L                (0x0002)       /* MCLK Divider Bit: 1 */
3078 
#define DIVM2_L                (0x0004)       /* MCLK Divider Bit: 2 */
3079 
//#define RESERVED            (0x0008)    /* RESERVED */
3080 
#define DIVS0_L                (0x0010)       /* SMCLK Divider Bit: 0 */
3081 
#define DIVS1_L                (0x0020)       /* SMCLK Divider Bit: 1 */
3082 
#define DIVS2_L                (0x0040)       /* SMCLK Divider Bit: 2 */
3083 
//#define RESERVED            (0x0080)    /* RESERVED */
3084 
//#define RESERVED            (0x0800)    /* RESERVED */
3085 
//#define RESERVED            (0x8000)    /* RESERVED */
3086 
 
3087 
/* UCSCTL5 Control Bits */
3088 
//#define RESERVED            (0x0008)    /* RESERVED */
3089 
//#define RESERVED            (0x0080)    /* RESERVED */
3090 
#define DIVA0_H                (0x0001)       /* ACLK Divider Bit: 0 */
3091 
#define DIVA1_H                (0x0002)       /* ACLK Divider Bit: 1 */
3092 
#define DIVA2_H                (0x0004)       /* ACLK Divider Bit: 2 */
3093 
//#define RESERVED            (0x0800)    /* RESERVED */
3094 
#define DIVPA0_H               (0x0010)       /* ACLK from Pin Divider Bit: 0 */
3095 
#define DIVPA1_H               (0x0020)       /* ACLK from Pin Divider Bit: 1 */
3096 
#define DIVPA2_H               (0x0040)       /* ACLK from Pin Divider Bit: 2 */
3097 
//#define RESERVED            (0x8000)    /* RESERVED */
3098 
 
3099 
#define DIVM_0                 (0x0000)       /* MCLK Source Divider 0 */
3100 
#define DIVM_1                 (0x0001)       /* MCLK Source Divider 1 */
3101 
#define DIVM_2                 (0x0002)       /* MCLK Source Divider 2 */
3102 
#define DIVM_3                 (0x0003)       /* MCLK Source Divider 3 */
3103 
#define DIVM_4                 (0x0004)       /* MCLK Source Divider 4 */
3104 
#define DIVM_5                 (0x0005)       /* MCLK Source Divider 5 */
3105 
#define DIVM_6                 (0x0006)       /* MCLK Source Divider 6 */
3106 
#define DIVM_7                 (0x0007)       /* MCLK Source Divider 7 */
3107 
#define DIVM__1                (0x0000)       /* MCLK Source Divider f(MCLK)/1 */
3108 
#define DIVM__2                (0x0001)       /* MCLK Source Divider f(MCLK)/2 */
3109 
#define DIVM__4                (0x0002)       /* MCLK Source Divider f(MCLK)/4 */
3110 
#define DIVM__8                (0x0003)       /* MCLK Source Divider f(MCLK)/8 */
3111 
#define DIVM__16               (0x0004)       /* MCLK Source Divider f(MCLK)/16 */
3112 
#define DIVM__32               (0x0005)       /* MCLK Source Divider f(MCLK)/32 */
3113 
 
3114 
#define DIVS_0                 (0x0000)       /* SMCLK Source Divider 0 */
3115 
#define DIVS_1                 (0x0010)       /* SMCLK Source Divider 1 */
3116 
#define DIVS_2                 (0x0020)       /* SMCLK Source Divider 2 */
3117 
#define DIVS_3                 (0x0030)       /* SMCLK Source Divider 3 */
3118 
#define DIVS_4                 (0x0040)       /* SMCLK Source Divider 4 */
3119 
#define DIVS_5                 (0x0050)       /* SMCLK Source Divider 5 */
3120 
#define DIVS_6                 (0x0060)       /* SMCLK Source Divider 6 */
3121 
#define DIVS_7                 (0x0070)       /* SMCLK Source Divider 7 */
3122 
#define DIVS__1                (0x0000)       /* SMCLK Source Divider f(SMCLK)/1 */
3123 
#define DIVS__2                (0x0010)       /* SMCLK Source Divider f(SMCLK)/2 */
3124 
#define DIVS__4                (0x0020)       /* SMCLK Source Divider f(SMCLK)/4 */
3125 
#define DIVS__8                (0x0030)       /* SMCLK Source Divider f(SMCLK)/8 */
3126 
#define DIVS__16               (0x0040)       /* SMCLK Source Divider f(SMCLK)/16 */
3127 
#define DIVS__32               (0x0050)       /* SMCLK Source Divider f(SMCLK)/32 */
3128 
 
3129 
#define DIVA_0                 (0x0000)       /* ACLK Source Divider 0 */
3130 
#define DIVA_1                 (0x0100)       /* ACLK Source Divider 1 */
3131 
#define DIVA_2                 (0x0200)       /* ACLK Source Divider 2 */
3132 
#define DIVA_3                 (0x0300)       /* ACLK Source Divider 3 */
3133 
#define DIVA_4                 (0x0400)       /* ACLK Source Divider 4 */
3134 
#define DIVA_5                 (0x0500)       /* ACLK Source Divider 5 */
3135 
#define DIVA_6                 (0x0600)       /* ACLK Source Divider 6 */
3136 
#define DIVA_7                 (0x0700)       /* ACLK Source Divider 7 */
3137 
#define DIVA__1                (0x0000)       /* ACLK Source Divider f(ACLK)/1 */
3138 
#define DIVA__2                (0x0100)       /* ACLK Source Divider f(ACLK)/2 */
3139 
#define DIVA__4                (0x0200)       /* ACLK Source Divider f(ACLK)/4 */
3140 
#define DIVA__8                (0x0300)       /* ACLK Source Divider f(ACLK)/8 */
3141 
#define DIVA__16               (0x0400)       /* ACLK Source Divider f(ACLK)/16 */
3142 
#define DIVA__32               (0x0500)       /* ACLK Source Divider f(ACLK)/32 */
3143 
 
3144 
#define DIVPA_0                (0x0000)       /* ACLK from Pin Source Divider 0 */
3145 
#define DIVPA_1                (0x1000)       /* ACLK from Pin Source Divider 1 */
3146 
#define DIVPA_2                (0x2000)       /* ACLK from Pin Source Divider 2 */
3147 
#define DIVPA_3                (0x3000)       /* ACLK from Pin Source Divider 3 */
3148 
#define DIVPA_4                (0x4000)       /* ACLK from Pin Source Divider 4 */
3149 
#define DIVPA_5                (0x5000)       /* ACLK from Pin Source Divider 5 */
3150 
#define DIVPA_6                (0x6000)       /* ACLK from Pin Source Divider 6 */
3151 
#define DIVPA_7                (0x7000)       /* ACLK from Pin Source Divider 7 */
3152 
#define DIVPA__1               (0x0000)       /* ACLK from Pin Source Divider f(ACLK)/1 */
3153 
#define DIVPA__2               (0x1000)       /* ACLK from Pin Source Divider f(ACLK)/2 */
3154 
#define DIVPA__4               (0x2000)       /* ACLK from Pin Source Divider f(ACLK)/4 */
3155 
#define DIVPA__8               (0x3000)       /* ACLK from Pin Source Divider f(ACLK)/8 */
3156 
#define DIVPA__16              (0x4000)       /* ACLK from Pin Source Divider f(ACLK)/16 */
3157 
#define DIVPA__32              (0x5000)       /* ACLK from Pin Source Divider f(ACLK)/32 */
3158 
 
3159 
/* UCSCTL6 Control Bits */
3160 
#define XT1OFF                 (0x0001)       /* High Frequency Oscillator 1 (XT1) disable */
3161 
#define SMCLKOFF               (0x0002)       /* SMCLK Off */
3162 
#define XCAP0                  (0x0004)       /* XIN/XOUT Cap Bit: 0 */
3163 
#define XCAP1                  (0x0008)       /* XIN/XOUT Cap Bit: 1 */
3164 
#define XT1BYPASS              (0x0010)       /* XT1 bypass mode : 0: internal 1:sourced from external pin */
3165 
#define XTS                    (0x0020)       /* 1: Selects high-freq. oscillator */
3166 
#define XT1DRIVE0              (0x0040)       /* XT1 Drive Level mode Bit 0 */
3167 
#define XT1DRIVE1              (0x0080)       /* XT1 Drive Level mode Bit 1 */
3168 
#define XT2OFF                 (0x0100)       /* High Frequency Oscillator 2 (XT2) disable */
3169 
//#define RESERVED            (0x0200)    /* RESERVED */
3170 
//#define RESERVED            (0x0400)    /* RESERVED */
3171 
//#define RESERVED            (0x0800)    /* RESERVED */
3172 
#define XT2BYPASS              (0x1000)       /* XT2 bypass mode : 0: internal 1:sourced from external pin */
3173 
//#define RESERVED            (0x2000)    /* RESERVED */
3174 
#define XT2DRIVE0              (0x4000)       /* XT2 Drive Level mode Bit 0 */
3175 
#define XT2DRIVE1              (0x8000)       /* XT2 Drive Level mode Bit 1 */
3176 
 
3177 
/* UCSCTL6 Control Bits */
3178 
#define XT1OFF_L               (0x0001)       /* High Frequency Oscillator 1 (XT1) disable */
3179 
#define SMCLKOFF_L             (0x0002)       /* SMCLK Off */
3180 
#define XCAP0_L                (0x0004)       /* XIN/XOUT Cap Bit: 0 */
3181 
#define XCAP1_L                (0x0008)       /* XIN/XOUT Cap Bit: 1 */
3182 
#define XT1BYPASS_L            (0x0010)       /* XT1 bypass mode : 0: internal 1:sourced from external pin */
3183 
#define XTS_L                  (0x0020)       /* 1: Selects high-freq. oscillator */
3184 
#define XT1DRIVE0_L            (0x0040)       /* XT1 Drive Level mode Bit 0 */
3185 
#define XT1DRIVE1_L            (0x0080)       /* XT1 Drive Level mode Bit 1 */
3186 
//#define RESERVED            (0x0200)    /* RESERVED */
3187 
//#define RESERVED            (0x0400)    /* RESERVED */
3188 
//#define RESERVED            (0x0800)    /* RESERVED */
3189 
//#define RESERVED            (0x2000)    /* RESERVED */
3190 
 
3191 
/* UCSCTL6 Control Bits */
3192 
#define XT2OFF_H               (0x0001)       /* High Frequency Oscillator 2 (XT2) disable */
3193 
//#define RESERVED            (0x0200)    /* RESERVED */
3194 
//#define RESERVED            (0x0400)    /* RESERVED */
3195 
//#define RESERVED            (0x0800)    /* RESERVED */
3196 
#define XT2BYPASS_H            (0x0010)       /* XT2 bypass mode : 0: internal 1:sourced from external pin */
3197 
//#define RESERVED            (0x2000)    /* RESERVED */
3198 
#define XT2DRIVE0_H            (0x0040)       /* XT2 Drive Level mode Bit 0 */
3199 
#define XT2DRIVE1_H            (0x0080)       /* XT2 Drive Level mode Bit 1 */
3200 
 
3201 
#define XCAP_0                 (0x0000)       /* XIN/XOUT Cap 0 */
3202 
#define XCAP_1                 (0x0004)       /* XIN/XOUT Cap 1 */
3203 
#define XCAP_2                 (0x0008)       /* XIN/XOUT Cap 2 */
3204 
#define XCAP_3                 (0x000C)       /* XIN/XOUT Cap 3 */
3205 
#define XT1DRIVE_0             (0x0000)       /* XT1 Drive Level mode: 0 */
3206 
#define XT1DRIVE_1             (0x0040)       /* XT1 Drive Level mode: 1 */
3207 
#define XT1DRIVE_2             (0x0080)       /* XT1 Drive Level mode: 2 */
3208 
#define XT1DRIVE_3             (0x00C0)       /* XT1 Drive Level mode: 3 */
3209 
#define XT2DRIVE_0             (0x0000)       /* XT2 Drive Level mode: 0 */
3210 
#define XT2DRIVE_1             (0x4000)       /* XT2 Drive Level mode: 1 */
3211 
#define XT2DRIVE_2             (0x8000)       /* XT2 Drive Level mode: 2 */
3212 
#define XT2DRIVE_3             (0xC000)       /* XT2 Drive Level mode: 3 */
3213 
 
3214 
/* UCSCTL7 Control Bits */
3215 
#define DCOFFG                 (0x0001)       /* DCO Fault Flag */
3216 
#define XT1LFOFFG              (0x0002)       /* XT1 Low Frequency Oscillator Fault Flag */
3217 
#define XT1HFOFFG              (0x0004)       /* XT1 High Frequency Oscillator 1 Fault Flag */
3218 
#define XT2OFFG                (0x0008)       /* High Frequency Oscillator 2 Fault Flag */
3219 
//#define RESERVED            (0x0010)    /* RESERVED */
3220 
//#define RESERVED            (0x0020)    /* RESERVED */
3221 
//#define RESERVED            (0x0040)    /* RESERVED */
3222 
//#define RESERVED            (0x0080)    /* RESERVED */
3223 
//#define RESERVED            (0x0100)    /* RESERVED */
3224 
//#define RESERVED            (0x0200)    /* RESERVED */
3225 
//#define RESERVED            (0x0400)    /* RESERVED */
3226 
//#define RESERVED            (0x0800)    /* RESERVED */
3227 
//#define RESERVED            (0x1000)    /* RESERVED */
3228 
//#define RESERVED            (0x2000)    /* RESERVED */
3229 
//#define RESERVED            (0x4000)    /* RESERVED */
3230 
//#define RESERVED            (0x8000)    /* RESERVED */
3231 
 
3232 
/* UCSCTL7 Control Bits */
3233 
#define DCOFFG_L               (0x0001)       /* DCO Fault Flag */
3234 
#define XT1LFOFFG_L            (0x0002)       /* XT1 Low Frequency Oscillator Fault Flag */
3235 
#define XT1HFOFFG_L            (0x0004)       /* XT1 High Frequency Oscillator 1 Fault Flag */
3236 
#define XT2OFFG_L              (0x0008)       /* High Frequency Oscillator 2 Fault Flag */
3237 
//#define RESERVED            (0x0010)    /* RESERVED */
3238 
//#define RESERVED            (0x0020)    /* RESERVED */
3239 
//#define RESERVED            (0x0040)    /* RESERVED */
3240 
//#define RESERVED            (0x0080)    /* RESERVED */
3241 
//#define RESERVED            (0x0100)    /* RESERVED */
3242 
//#define RESERVED            (0x0200)    /* RESERVED */
3243 
//#define RESERVED            (0x0400)    /* RESERVED */
3244 
//#define RESERVED            (0x0800)    /* RESERVED */
3245 
//#define RESERVED            (0x1000)    /* RESERVED */
3246 
//#define RESERVED            (0x2000)    /* RESERVED */
3247 
//#define RESERVED            (0x4000)    /* RESERVED */
3248 
//#define RESERVED            (0x8000)    /* RESERVED */
3249 
 
3250 
/* UCSCTL7 Control Bits */
3251 
//#define RESERVED            (0x0010)    /* RESERVED */
3252 
//#define RESERVED            (0x0020)    /* RESERVED */
3253 
//#define RESERVED            (0x0040)    /* RESERVED */
3254 
//#define RESERVED            (0x0080)    /* RESERVED */
3255 
//#define RESERVED            (0x0100)    /* RESERVED */
3256 
//#define RESERVED            (0x0200)    /* RESERVED */
3257 
//#define RESERVED            (0x0400)    /* RESERVED */
3258 
//#define RESERVED            (0x0800)    /* RESERVED */
3259 
//#define RESERVED            (0x1000)    /* RESERVED */
3260 
//#define RESERVED            (0x2000)    /* RESERVED */
3261 
//#define RESERVED            (0x4000)    /* RESERVED */
3262 
//#define RESERVED            (0x8000)    /* RESERVED */
3263 
 
3264 
/* UCSCTL8 Control Bits */
3265 
#define ACLKREQEN              (0x0001)       /* ACLK Clock Request Enable */
3266 
#define MCLKREQEN              (0x0002)       /* MCLK Clock Request Enable */
3267 
#define SMCLKREQEN             (0x0004)       /* SMCLK Clock Request Enable */
3268 
#define MODOSCREQEN            (0x0008)       /* MODOSC Clock Request Enable */
3269 
//#define RESERVED            (0x0010)    /* RESERVED */
3270 
//#define RESERVED            (0x0020)    /* RESERVED */
3271 
//#define RESERVED            (0x0040)    /* RESERVED */
3272 
//#define RESERVED            (0x0080)    /* RESERVED */
3273 
//#define RESERVED            (0x0100)    /* RESERVED */
3274 
//#define RESERVED            (0x0200)    /* RESERVED */
3275 
//#define RESERVED            (0x0400)    /* RESERVED */
3276 
//#define RESERVED            (0x0800)    /* RESERVED */
3277 
//#define RESERVED            (0x1000)    /* RESERVED */
3278 
//#define RESERVED            (0x2000)    /* RESERVED */
3279 
//#define RESERVED            (0x4000)    /* RESERVED */
3280 
//#define RESERVED            (0x8000)    /* RESERVED */
3281 
 
3282 
/* UCSCTL8 Control Bits */
3283 
#define ACLKREQEN_L            (0x0001)       /* ACLK Clock Request Enable */
3284 
#define MCLKREQEN_L            (0x0002)       /* MCLK Clock Request Enable */
3285 
#define SMCLKREQEN_L           (0x0004)       /* SMCLK Clock Request Enable */
3286 
#define MODOSCREQEN_L          (0x0008)       /* MODOSC Clock Request Enable */
3287 
//#define RESERVED            (0x0010)    /* RESERVED */
3288 
//#define RESERVED            (0x0020)    /* RESERVED */
3289 
//#define RESERVED            (0x0040)    /* RESERVED */
3290 
//#define RESERVED            (0x0080)    /* RESERVED */
3291 
//#define RESERVED            (0x0100)    /* RESERVED */
3292 
//#define RESERVED            (0x0200)    /* RESERVED */
3293 
//#define RESERVED            (0x0400)    /* RESERVED */
3294 
//#define RESERVED            (0x0800)    /* RESERVED */
3295 
//#define RESERVED            (0x1000)    /* RESERVED */
3296 
//#define RESERVED            (0x2000)    /* RESERVED */
3297 
//#define RESERVED            (0x4000)    /* RESERVED */
3298 
//#define RESERVED            (0x8000)    /* RESERVED */
3299 
 
3300 
/* UCSCTL8 Control Bits */
3301 
//#define RESERVED            (0x0010)    /* RESERVED */
3302 
//#define RESERVED            (0x0020)    /* RESERVED */
3303 
//#define RESERVED            (0x0040)    /* RESERVED */
3304 
//#define RESERVED            (0x0080)    /* RESERVED */
3305 
//#define RESERVED            (0x0100)    /* RESERVED */
3306 
//#define RESERVED            (0x0200)    /* RESERVED */
3307 
//#define RESERVED            (0x0400)    /* RESERVED */
3308 
//#define RESERVED            (0x0800)    /* RESERVED */
3309 
//#define RESERVED            (0x1000)    /* RESERVED */
3310 
//#define RESERVED            (0x2000)    /* RESERVED */
3311 
//#define RESERVED            (0x4000)    /* RESERVED */
3312 
//#define RESERVED            (0x8000)    /* RESERVED */
3313 
 
3314 
/************************************************************
3315 
* USCI A0
3316 
************************************************************/
3317 
#define __MSP430_HAS_USCI_A0__                /* Definition to show that Module is available */
3318 
 
3319 
SFR_16BIT(UCA0CTLW0);                         /* USCI A0 Control Word Register 0 */
3320 
SFR_8BIT(UCA0CTLW0_L);                        /* USCI A0 Control Word Register 0 */
3321 
SFR_8BIT(UCA0CTLW0_H);                        /* USCI A0 Control Word Register 0 */
3322 
#define UCA0CTL1               UCA0CTLW0_L    /* USCI A0 Control Register 1 */
3323 
#define UCA0CTL0               UCA0CTLW0_H    /* USCI A0 Control Register 0 */
3324 
SFR_16BIT(UCA0BRW);                           /* USCI A0 Baud Word Rate 0 */
3325 
SFR_8BIT(UCA0BRW_L);                          /* USCI A0 Baud Word Rate 0 */
3326 
SFR_8BIT(UCA0BRW_H);                          /* USCI A0 Baud Word Rate 0 */
3327 
#define UCA0BR0                UCA0BRW_L      /* USCI A0 Baud Rate 0 */
3328 
#define UCA0BR1                UCA0BRW_H      /* USCI A0 Baud Rate 1 */
3329 
SFR_8BIT(UCA0MCTL);                           /* USCI A0 Modulation Control */
3330 
SFR_8BIT(UCA0STAT);                           /* USCI A0 Status Register */
3331 
SFR_8BIT(UCA0RXBUF);                          /* USCI A0 Receive Buffer */
3332 
SFR_8BIT(UCA0TXBUF);                          /* USCI A0 Transmit Buffer */
3333 
SFR_8BIT(UCA0ABCTL);                          /* USCI A0 LIN Control */
3334 
SFR_16BIT(UCA0IRCTL);                         /* USCI A0 IrDA Transmit Control */
3335 
SFR_8BIT(UCA0IRCTL_L);                        /* USCI A0 IrDA Transmit Control */
3336 
SFR_8BIT(UCA0IRCTL_H);                        /* USCI A0 IrDA Transmit Control */
3337 
#define UCA0IRTCTL             UCA0IRCTL_L    /* USCI A0 IrDA Transmit Control */
3338 
#define UCA0IRRCTL             UCA0IRCTL_H    /* USCI A0 IrDA Receive Control */
3339 
SFR_16BIT(UCA0ICTL);                          /* USCI A0 Interrupt Enable Register */
3340 
SFR_8BIT(UCA0ICTL_L);                         /* USCI A0 Interrupt Enable Register */
3341 
SFR_8BIT(UCA0ICTL_H);                         /* USCI A0 Interrupt Enable Register */
3342 
#define UCA0IE                 UCA0ICTL_L     /* USCI A0 Interrupt Enable Register */
3343 
#define UCA0IFG                UCA0ICTL_H     /* USCI A0 Interrupt Flags Register */
3344 
SFR_16BIT(UCA0IV);                            /* USCI A0 Interrupt Vector Register */
3345 
 
3346 
 
3347 
/************************************************************
3348 
* USCI B0
3349 
************************************************************/
3350 
#define __MSP430_HAS_USCI_B0__                /* Definition to show that Module is available */
3351 
 
3352 
 
3353 
SFR_16BIT(UCB0CTLW0);                         /* USCI B0 Control Word Register 0 */
3354 
SFR_8BIT(UCB0CTLW0_L);                        /* USCI B0 Control Word Register 0 */
3355 
SFR_8BIT(UCB0CTLW0_H);                        /* USCI B0 Control Word Register 0 */
3356 
#define UCB0CTL1               UCB0CTLW0_L    /* USCI B0 Control Register 1 */
3357 
#define UCB0CTL0               UCB0CTLW0_H    /* USCI B0 Control Register 0 */
3358 
SFR_16BIT(UCB0BRW);                           /* USCI B0 Baud Word Rate 0 */
3359 
SFR_8BIT(UCB0BRW_L);                          /* USCI B0 Baud Word Rate 0 */
3360 
SFR_8BIT(UCB0BRW_H);                          /* USCI B0 Baud Word Rate 0 */
3361 
#define UCB0BR0                UCB0BRW_L      /* USCI B0 Baud Rate 0 */
3362 
#define UCB0BR1                UCB0BRW_H      /* USCI B0 Baud Rate 1 */
3363 
SFR_8BIT(UCB0STAT);                           /* USCI B0 Status Register */
3364 
SFR_8BIT(UCB0RXBUF);                          /* USCI B0 Receive Buffer */
3365 
SFR_8BIT(UCB0TXBUF);                          /* USCI B0 Transmit Buffer */
3366 
SFR_16BIT(UCB0I2COA);                         /* USCI B0 I2C Own Address */
3367 
SFR_8BIT(UCB0I2COA_L);                        /* USCI B0 I2C Own Address */
3368 
SFR_8BIT(UCB0I2COA_H);                        /* USCI B0 I2C Own Address */
3369 
SFR_16BIT(UCB0I2CSA);                         /* USCI B0 I2C Slave Address */
3370 
SFR_8BIT(UCB0I2CSA_L);                        /* USCI B0 I2C Slave Address */
3371 
SFR_8BIT(UCB0I2CSA_H);                        /* USCI B0 I2C Slave Address */
3372 
SFR_16BIT(UCB0ICTL);                          /* USCI B0 Interrupt Enable Register */
3373 
SFR_8BIT(UCB0ICTL_L);                         /* USCI B0 Interrupt Enable Register */
3374 
SFR_8BIT(UCB0ICTL_H);                         /* USCI B0 Interrupt Enable Register */
3375 
#define UCB0IE                 UCB0ICTL_L     /* USCI B0 Interrupt Enable Register */
3376 
#define UCB0IFG                UCB0ICTL_H     /* USCI B0 Interrupt Flags Register */
3377 
SFR_16BIT(UCB0IV);                            /* USCI B0 Interrupt Vector Register */
3378 
 
3379 
// UCAxCTL0 UART-Mode Control Bits
3380 
#define UCPEN                  (0x80)         /* Async. Mode: Parity enable */
3381 
#define UCPAR                  (0x40)         /* Async. Mode: Parity     0:odd / 1:even */
3382 
#define UCMSB                  (0x20)         /* Async. Mode: MSB first  0:LSB / 1:MSB */
3383 
#define UC7BIT                 (0x10)         /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
3384 
#define UCSPB                  (0x08)         /* Async. Mode: Stop Bits  0:one / 1: two */
3385 
#define UCMODE1                (0x04)         /* Async. Mode: USCI Mode 1 */
3386 
#define UCMODE0                (0x02)         /* Async. Mode: USCI Mode 0 */
3387 
#define UCSYNC                 (0x01)         /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
3388 
 
3389 
// UCxxCTL0 SPI-Mode Control Bits
3390 
#define UCCKPH                 (0x80)         /* Sync. Mode: Clock Phase */
3391 
#define UCCKPL                 (0x40)         /* Sync. Mode: Clock Polarity */
3392 
#define UCMST                  (0x08)         /* Sync. Mode: Master Select */
3393 
 
3394 
// UCBxCTL0 I2C-Mode Control Bits
3395 
#define UCA10                  (0x80)         /* 10-bit Address Mode */
3396 
#define UCSLA10                (0x40)         /* 10-bit Slave Address Mode */
3397 
#define UCMM                   (0x20)         /* Multi-Master Environment */
3398 
//#define res               (0x10)    /* reserved */
3399 
#define UCMODE_0               (0x00)         /* Sync. Mode: USCI Mode: 0 */
3400 
#define UCMODE_1               (0x02)         /* Sync. Mode: USCI Mode: 1 */
3401 
#define UCMODE_2               (0x04)         /* Sync. Mode: USCI Mode: 2 */
3402 
#define UCMODE_3               (0x06)         /* Sync. Mode: USCI Mode: 3 */
3403 
 
3404 
// UCAxCTL1 UART-Mode Control Bits
3405 
#define UCSSEL1                (0x80)         /* USCI 0 Clock Source Select 1 */
3406 
#define UCSSEL0                (0x40)         /* USCI 0 Clock Source Select 0 */
3407 
#define UCRXEIE                (0x20)         /* RX Error interrupt enable */
3408 
#define UCBRKIE                (0x10)         /* Break interrupt enable */
3409 
#define UCDORM                 (0x08)         /* Dormant (Sleep) Mode */
3410 
#define UCTXADDR               (0x04)         /* Send next Data as Address */
3411 
#define UCTXBRK                (0x02)         /* Send next Data as Break */
3412 
#define UCSWRST                (0x01)         /* USCI Software Reset */
3413 
 
3414 
// UCxxCTL1 SPI-Mode Control Bits
3415 
//#define res               (0x20)    /* reserved */
3416 
//#define res               (0x10)    /* reserved */
3417 
//#define res               (0x08)    /* reserved */
3418 
//#define res               (0x04)    /* reserved */
3419 
//#define res               (0x02)    /* reserved */
3420 
 
3421 
// UCBxCTL1 I2C-Mode Control Bits
3422 
//#define res               (0x20)    /* reserved */
3423 
#define UCTR                   (0x10)         /* Transmit/Receive Select/Flag */
3424 
#define UCTXNACK               (0x08)         /* Transmit NACK */
3425 
#define UCTXSTP                (0x04)         /* Transmit STOP */
3426 
#define UCTXSTT                (0x02)         /* Transmit START */
3427 
#define UCSSEL_0               (0x00)         /* USCI 0 Clock Source: 0 */
3428 
#define UCSSEL_1               (0x40)         /* USCI 0 Clock Source: 1 */
3429 
#define UCSSEL_2               (0x80)         /* USCI 0 Clock Source: 2 */
3430 
#define UCSSEL_3               (0xC0)         /* USCI 0 Clock Source: 3 */
3431 
#define UCSSEL__UCLK           (0x00)         /* USCI 0 Clock Source: UCLK */
3432 
#define UCSSEL__ACLK           (0x40)         /* USCI 0 Clock Source: ACLK */
3433 
#define UCSSEL__SMCLK          (0x80)         /* USCI 0 Clock Source: SMCLK */
3434 
 
3435 
/* UCAxMCTL Control Bits */
3436 
#define UCBRF3                 (0x80)         /* USCI First Stage Modulation Select 3 */
3437 
#define UCBRF2                 (0x40)         /* USCI First Stage Modulation Select 2 */
3438 
#define UCBRF1                 (0x20)         /* USCI First Stage Modulation Select 1 */
3439 
#define UCBRF0                 (0x10)         /* USCI First Stage Modulation Select 0 */
3440 
#define UCBRS2                 (0x08)         /* USCI Second Stage Modulation Select 2 */
3441 
#define UCBRS1                 (0x04)         /* USCI Second Stage Modulation Select 1 */
3442 
#define UCBRS0                 (0x02)         /* USCI Second Stage Modulation Select 0 */
3443 
#define UCOS16                 (0x01)         /* USCI 16-times Oversampling enable */
3444 
 
3445 
#define UCBRF_0                (0x00)         /* USCI First Stage Modulation: 0 */
3446 
#define UCBRF_1                (0x10)         /* USCI First Stage Modulation: 1 */
3447 
#define UCBRF_2                (0x20)         /* USCI First Stage Modulation: 2 */
3448 
#define UCBRF_3                (0x30)         /* USCI First Stage Modulation: 3 */
3449 
#define UCBRF_4                (0x40)         /* USCI First Stage Modulation: 4 */
3450 
#define UCBRF_5                (0x50)         /* USCI First Stage Modulation: 5 */
3451 
#define UCBRF_6                (0x60)         /* USCI First Stage Modulation: 6 */
3452 
#define UCBRF_7                (0x70)         /* USCI First Stage Modulation: 7 */
3453 
#define UCBRF_8                (0x80)         /* USCI First Stage Modulation: 8 */
3454 
#define UCBRF_9                (0x90)         /* USCI First Stage Modulation: 9 */
3455 
#define UCBRF_10               (0xA0)         /* USCI First Stage Modulation: A */
3456 
#define UCBRF_11               (0xB0)         /* USCI First Stage Modulation: B */
3457 
#define UCBRF_12               (0xC0)         /* USCI First Stage Modulation: C */
3458 
#define UCBRF_13               (0xD0)         /* USCI First Stage Modulation: D */
3459 
#define UCBRF_14               (0xE0)         /* USCI First Stage Modulation: E */
3460 
#define UCBRF_15               (0xF0)         /* USCI First Stage Modulation: F */
3461 
 
3462 
#define UCBRS_0                (0x00)         /* USCI Second Stage Modulation: 0 */
3463 
#define UCBRS_1                (0x02)         /* USCI Second Stage Modulation: 1 */
3464 
#define UCBRS_2                (0x04)         /* USCI Second Stage Modulation: 2 */
3465 
#define UCBRS_3                (0x06)         /* USCI Second Stage Modulation: 3 */
3466 
#define UCBRS_4                (0x08)         /* USCI Second Stage Modulation: 4 */
3467 
#define UCBRS_5                (0x0A)         /* USCI Second Stage Modulation: 5 */
3468 
#define UCBRS_6                (0x0C)         /* USCI Second Stage Modulation: 6 */
3469 
#define UCBRS_7                (0x0E)         /* USCI Second Stage Modulation: 7 */
3470 
 
3471 
/* UCAxSTAT Control Bits */
3472 
#define UCLISTEN               (0x80)         /* USCI Listen mode */
3473 
#define UCFE                   (0x40)         /* USCI Frame Error Flag */
3474 
#define UCOE                   (0x20)         /* USCI Overrun Error Flag */
3475 
#define UCPE                   (0x10)         /* USCI Parity Error Flag */
3476 
#define UCBRK                  (0x08)         /* USCI Break received */
3477 
#define UCRXERR                (0x04)         /* USCI RX Error Flag */
3478 
#define UCADDR                 (0x02)         /* USCI Address received Flag */
3479 
#define UCBUSY                 (0x01)         /* USCI Busy Flag */
3480 
#define UCIDLE                 (0x02)         /* USCI Idle line detected Flag */
3481 
 
3482 
/* UCBxSTAT Control Bits */
3483 
#define UCSCLLOW               (0x40)         /* SCL low */
3484 
#define UCGC                   (0x20)         /* General Call address received Flag */
3485 
#define UCBBUSY                (0x10)         /* Bus Busy Flag */
3486 
 
3487 
/* UCAxIRTCTL Control Bits */
3488 
#define UCIRTXPL5              (0x80)         /* IRDA Transmit Pulse Length 5 */
3489 
#define UCIRTXPL4              (0x40)         /* IRDA Transmit Pulse Length 4 */
3490 
#define UCIRTXPL3              (0x20)         /* IRDA Transmit Pulse Length 3 */
3491 
#define UCIRTXPL2              (0x10)         /* IRDA Transmit Pulse Length 2 */
3492 
#define UCIRTXPL1              (0x08)         /* IRDA Transmit Pulse Length 1 */
3493 
#define UCIRTXPL0              (0x04)         /* IRDA Transmit Pulse Length 0 */
3494 
#define UCIRTXCLK              (0x02)         /* IRDA Transmit Pulse Clock Select */
3495 
#define UCIREN                 (0x01)         /* IRDA Encoder/Decoder enable */
3496 
 
3497 
/* UCAxIRRCTL Control Bits */
3498 
#define UCIRRXFL5              (0x80)         /* IRDA Receive Filter Length 5 */
3499 
#define UCIRRXFL4              (0x40)         /* IRDA Receive Filter Length 4 */
3500 
#define UCIRRXFL3              (0x20)         /* IRDA Receive Filter Length 3 */
3501 
#define UCIRRXFL2              (0x10)         /* IRDA Receive Filter Length 2 */
3502 
#define UCIRRXFL1              (0x08)         /* IRDA Receive Filter Length 1 */
3503 
#define UCIRRXFL0              (0x04)         /* IRDA Receive Filter Length 0 */
3504 
#define UCIRRXPL               (0x02)         /* IRDA Receive Input Polarity */
3505 
#define UCIRRXFE               (0x01)         /* IRDA Receive Filter enable */
3506 
 
3507 
/* UCAxABCTL Control Bits */
3508 
//#define res               (0x80)    /* reserved */
3509 
//#define res               (0x40)    /* reserved */
3510 
#define UCDELIM1               (0x20)         /* Break Sync Delimiter 1 */
3511 
#define UCDELIM0               (0x10)         /* Break Sync Delimiter 0 */
3512 
#define UCSTOE                 (0x08)         /* Sync-Field Timeout error */
3513 
#define UCBTOE                 (0x04)         /* Break Timeout error */
3514 
//#define res               (0x02)    /* reserved */
3515 
#define UCABDEN                (0x01)         /* Auto Baud Rate detect enable */
3516 
 
3517 
/* UCBxI2COA Control Bits */
3518 
#define UCGCEN                 (0x8000)       /* I2C General Call enable */
3519 
#define UCOA9                  (0x0200)       /* I2C Own Address 9 */
3520 
#define UCOA8                  (0x0100)       /* I2C Own Address 8 */
3521 
#define UCOA7                  (0x0080)       /* I2C Own Address 7 */
3522 
#define UCOA6                  (0x0040)       /* I2C Own Address 6 */
3523 
#define UCOA5                  (0x0020)       /* I2C Own Address 5 */
3524 
#define UCOA4                  (0x0010)       /* I2C Own Address 4 */
3525 
#define UCOA3                  (0x0008)       /* I2C Own Address 3 */
3526 
#define UCOA2                  (0x0004)       /* I2C Own Address 2 */
3527 
#define UCOA1                  (0x0002)       /* I2C Own Address 1 */
3528 
#define UCOA0                  (0x0001)       /* I2C Own Address 0 */
3529 
 
3530 
/* UCBxI2COA Control Bits */
3531 
#define UCOA7_L                (0x0080)       /* I2C Own Address 7 */
3532 
#define UCOA6_L                (0x0040)       /* I2C Own Address 6 */
3533 
#define UCOA5_L                (0x0020)       /* I2C Own Address 5 */
3534 
#define UCOA4_L                (0x0010)       /* I2C Own Address 4 */
3535 
#define UCOA3_L                (0x0008)       /* I2C Own Address 3 */
3536 
#define UCOA2_L                (0x0004)       /* I2C Own Address 2 */
3537 
#define UCOA1_L                (0x0002)       /* I2C Own Address 1 */
3538 
#define UCOA0_L                (0x0001)       /* I2C Own Address 0 */
3539 
 
3540 
/* UCBxI2COA Control Bits */
3541 
#define UCGCEN_H               (0x0080)       /* I2C General Call enable */
3542 
#define UCOA9_H                (0x0002)       /* I2C Own Address 9 */
3543 
#define UCOA8_H                (0x0001)       /* I2C Own Address 8 */
3544 
 
3545 
/* UCBxI2CSA Control Bits */
3546 
#define UCSA9                  (0x0200)       /* I2C Slave Address 9 */
3547 
#define UCSA8                  (0x0100)       /* I2C Slave Address 8 */
3548 
#define UCSA7                  (0x0080)       /* I2C Slave Address 7 */
3549 
#define UCSA6                  (0x0040)       /* I2C Slave Address 6 */
3550 
#define UCSA5                  (0x0020)       /* I2C Slave Address 5 */
3551 
#define UCSA4                  (0x0010)       /* I2C Slave Address 4 */
3552 
#define UCSA3                  (0x0008)       /* I2C Slave Address 3 */
3553 
#define UCSA2                  (0x0004)       /* I2C Slave Address 2 */
3554 
#define UCSA1                  (0x0002)       /* I2C Slave Address 1 */
3555 
#define UCSA0                  (0x0001)       /* I2C Slave Address 0 */
3556 
 
3557 
/* UCBxI2CSA Control Bits */
3558 
#define UCSA7_L                (0x0080)       /* I2C Slave Address 7 */
3559 
#define UCSA6_L                (0x0040)       /* I2C Slave Address 6 */
3560 
#define UCSA5_L                (0x0020)       /* I2C Slave Address 5 */
3561 
#define UCSA4_L                (0x0010)       /* I2C Slave Address 4 */
3562 
#define UCSA3_L                (0x0008)       /* I2C Slave Address 3 */
3563 
#define UCSA2_L                (0x0004)       /* I2C Slave Address 2 */
3564 
#define UCSA1_L                (0x0002)       /* I2C Slave Address 1 */
3565 
#define UCSA0_L                (0x0001)       /* I2C Slave Address 0 */
3566 
 
3567 
/* UCBxI2CSA Control Bits */
3568 
#define UCSA9_H                (0x0002)       /* I2C Slave Address 9 */
3569 
#define UCSA8_H                (0x0001)       /* I2C Slave Address 8 */
3570 
 
3571 
/* UCAxIE Control Bits */
3572 
#define UCTXIE                 (0x0002)       /* USCI Transmit Interrupt Enable */
3573 
#define UCRXIE                 (0x0001)       /* USCI Receive Interrupt Enable */
3574 
 
3575 
/* UCBxIE Control Bits */
3576 
#define UCNACKIE               (0x0020)       /* NACK Condition interrupt enable */
3577 
#define UCALIE                 (0x0010)       /* Arbitration Lost interrupt enable */
3578 
#define UCSTPIE                (0x0008)       /* STOP Condition interrupt enable */
3579 
#define UCSTTIE                (0x0004)       /* START Condition interrupt enable */
3580 
#define UCTXIE                 (0x0002)       /* USCI Transmit Interrupt Enable */
3581 
#define UCRXIE                 (0x0001)       /* USCI Receive Interrupt Enable */
3582 
 
3583 
/* UCAxIFG Control Bits */
3584 
#define UCTXIFG                (0x0002)       /* USCI Transmit Interrupt Flag */
3585 
#define UCRXIFG                (0x0001)       /* USCI Receive Interrupt Flag */
3586 
 
3587 
/* UCBxIFG Control Bits */
3588 
#define UCNACKIFG              (0x0020)       /* NAK Condition interrupt Flag */
3589 
#define UCALIFG                (0x0010)       /* Arbitration Lost interrupt Flag */
3590 
#define UCSTPIFG               (0x0008)       /* STOP Condition interrupt Flag */
3591 
#define UCSTTIFG               (0x0004)       /* START Condition interrupt Flag */
3592 
#define UCTXIFG                (0x0002)       /* USCI Transmit Interrupt Flag */
3593 
#define UCRXIFG                (0x0001)       /* USCI Receive Interrupt Flag */
3594 
 
3595 
/* USCI Definitions */
3596 
#define USCI_NONE              (0x0000)       /* No Interrupt pending */
3597 
#define USCI_UCRXIFG           (0x0002)       /* USCI UCRXIFG */
3598 
#define USCI_UCTXIFG           (0x0004)       /* USCI UCTXIFG */
3599 
#define USCI_I2C_UCALIFG       (0x0002)       /* USCI I2C Mode: UCALIFG */
3600 
#define USCI_I2C_UCNACKIFG     (0x0004)       /* USCI I2C Mode: UCNACKIFG */
3601 
#define USCI_I2C_UCSTTIFG      (0x0006)       /* USCI I2C Mode: UCSTTIFG*/
3602 
#define USCI_I2C_UCSTPIFG      (0x0008)       /* USCI I2C Mode: UCSTPIFG*/
3603 
#define USCI_I2C_UCRXIFG       (0x000A)       /* USCI I2C Mode: UCRXIFG */
3604 
#define USCI_I2C_UCTXIFG       (0x000C)       /* USCI I2C Mode: UCTXIFG */
3605 
 
3606 
/************************************************************
3607 
* USCI A1
3608 
************************************************************/
3609 
#define __MSP430_HAS_USCI_A1__                /* Definition to show that Module is available */
3610 
 
3611 
SFR_16BIT(UCA1CTLW0);                         /* USCI A1 Control Word Register 0 */
3612 
SFR_8BIT(UCA1CTLW0_L);                        /* USCI A1 Control Word Register 0 */
3613 
SFR_8BIT(UCA1CTLW0_H);                        /* USCI A1 Control Word Register 0 */
3614 
#define UCA1CTL1               UCA1CTLW0_L    /* USCI A1 Control Register 1 */
3615 
#define UCA1CTL0               UCA1CTLW0_H    /* USCI A1 Control Register 0 */
3616 
SFR_16BIT(UCA1BRW);                           /* USCI A1 Baud Word Rate 0 */
3617 
SFR_8BIT(UCA1BRW_L);                          /* USCI A1 Baud Word Rate 0 */
3618 
SFR_8BIT(UCA1BRW_H);                          /* USCI A1 Baud Word Rate 0 */
3619 
#define UCA1BR0                UCA1BRW_L      /* USCI A1 Baud Rate 0 */
3620 
#define UCA1BR1                UCA1BRW_H      /* USCI A1 Baud Rate 1 */
3621 
SFR_8BIT(UCA1MCTL);                           /* USCI A1 Modulation Control */
3622 
SFR_8BIT(UCA1STAT);                           /* USCI A1 Status Register */
3623 
SFR_8BIT(UCA1RXBUF);                          /* USCI A1 Receive Buffer */
3624 
SFR_8BIT(UCA1TXBUF);                          /* USCI A1 Transmit Buffer */
3625 
SFR_8BIT(UCA1ABCTL);                          /* USCI A1 LIN Control */
3626 
SFR_16BIT(UCA1IRCTL);                         /* USCI A1 IrDA Transmit Control */
3627 
SFR_8BIT(UCA1IRCTL_L);                        /* USCI A1 IrDA Transmit Control */
3628 
SFR_8BIT(UCA1IRCTL_H);                        /* USCI A1 IrDA Transmit Control */
3629 
#define UCA1IRTCTL             UCA1IRCTL_L    /* USCI A1 IrDA Transmit Control */
3630 
#define UCA1IRRCTL             UCA1IRCTL_H    /* USCI A1 IrDA Receive Control */
3631 
SFR_16BIT(UCA1ICTL);                          /* USCI A1 Interrupt Enable Register */
3632 
SFR_8BIT(UCA1ICTL_L);                         /* USCI A1 Interrupt Enable Register */
3633 
SFR_8BIT(UCA1ICTL_H);                         /* USCI A1 Interrupt Enable Register */
3634 
#define UCA1IE                 UCA1ICTL_L     /* USCI A1 Interrupt Enable Register */
3635 
#define UCA1IFG                UCA1ICTL_H     /* USCI A1 Interrupt Flags Register */
3636 
SFR_16BIT(UCA1IV);                            /* USCI A1 Interrupt Vector Register */
3637 
 
3638 
 
3639 
/************************************************************
3640 
* USCI B1
3641 
************************************************************/
3642 
#define __MSP430_HAS_USCI_B1__                /* Definition to show that Module is available */
3643 
 
3644 
 
3645 
SFR_16BIT(UCB1CTLW0);                         /* USCI B1 Control Word Register 0 */
3646 
SFR_8BIT(UCB1CTLW0_L);                        /* USCI B1 Control Word Register 0 */
3647 
SFR_8BIT(UCB1CTLW0_H);                        /* USCI B1 Control Word Register 0 */
3648 
#define UCB1CTL1               UCB1CTLW0_L    /* USCI B1 Control Register 1 */
3649 
#define UCB1CTL0               UCB1CTLW0_H    /* USCI B1 Control Register 0 */
3650 
SFR_16BIT(UCB1BRW);                           /* USCI B1 Baud Word Rate 0 */
3651 
SFR_8BIT(UCB1BRW_L);                          /* USCI B1 Baud Word Rate 0 */
3652 
SFR_8BIT(UCB1BRW_H);                          /* USCI B1 Baud Word Rate 0 */
3653 
#define UCB1BR0                UCB1BRW_L      /* USCI B1 Baud Rate 0 */
3654 
#define UCB1BR1                UCB1BRW_H      /* USCI B1 Baud Rate 1 */
3655 
SFR_8BIT(UCB1STAT);                           /* USCI B1 Status Register */
3656 
SFR_8BIT(UCB1RXBUF);                          /* USCI B1 Receive Buffer */
3657 
SFR_8BIT(UCB1TXBUF);                          /* USCI B1 Transmit Buffer */
3658 
SFR_16BIT(UCB1I2COA);                         /* USCI B1 I2C Own Address */
3659 
SFR_8BIT(UCB1I2COA_L);                        /* USCI B1 I2C Own Address */
3660 
SFR_8BIT(UCB1I2COA_H);                        /* USCI B1 I2C Own Address */
3661 
SFR_16BIT(UCB1I2CSA);                         /* USCI B1 I2C Slave Address */
3662 
SFR_8BIT(UCB1I2CSA_L);                        /* USCI B1 I2C Slave Address */
3663 
SFR_8BIT(UCB1I2CSA_H);                        /* USCI B1 I2C Slave Address */
3664 
SFR_16BIT(UCB1ICTL);                          /* USCI B1 Interrupt Enable Register */
3665 
SFR_8BIT(UCB1ICTL_L);                         /* USCI B1 Interrupt Enable Register */
3666 
SFR_8BIT(UCB1ICTL_H);                         /* USCI B1 Interrupt Enable Register */
3667 
#define UCB1IE                 UCB1ICTL_L     /* USCI B1 Interrupt Enable Register */
3668 
#define UCB1IFG                UCB1ICTL_H     /* USCI B1 Interrupt Flags Register */
3669 
SFR_16BIT(UCB1IV);                            /* USCI B1 Interrupt Vector Register */
3670 
 
3671 
/************************************************************
3672 
* USCI A2
3673 
************************************************************/
3674 
#define __MSP430_HAS_USCI_A2__                /* Definition to show that Module is available */
3675 
 
3676 
SFR_16BIT(UCA2CTLW0);                         /* USCI A2 Control Word Register 0 */
3677 
SFR_8BIT(UCA2CTLW0_L);                        /* USCI A2 Control Word Register 0 */
3678 
SFR_8BIT(UCA2CTLW0_H);                        /* USCI A2 Control Word Register 0 */
3679 
#define UCA2CTL1               UCA2CTLW0_L    /* USCI A2 Control Register 1 */
3680 
#define UCA2CTL0               UCA2CTLW0_H    /* USCI A2 Control Register 0 */
3681 
SFR_16BIT(UCA2BRW);                           /* USCI A2 Baud Word Rate 0 */
3682 
SFR_8BIT(UCA2BRW_L);                          /* USCI A2 Baud Word Rate 0 */
3683 
SFR_8BIT(UCA2BRW_H);                          /* USCI A2 Baud Word Rate 0 */
3684 
#define UCA2BR0                UCA2BRW_L      /* USCI A2 Baud Rate 0 */
3685 
#define UCA2BR1                UCA2BRW_H      /* USCI A2 Baud Rate 1 */
3686 
SFR_8BIT(UCA2MCTL);                           /* USCI A2 Modulation Control */
3687 
SFR_8BIT(UCA2STAT);                           /* USCI A2 Status Register */
3688 
SFR_8BIT(UCA2RXBUF);                          /* USCI A2 Receive Buffer */
3689 
SFR_8BIT(UCA2TXBUF);                          /* USCI A2 Transmit Buffer */
3690 
SFR_8BIT(UCA2ABCTL);                          /* USCI A2 LIN Control */
3691 
SFR_16BIT(UCA2IRCTL);                         /* USCI A2 IrDA Transmit Control */
3692 
SFR_8BIT(UCA2IRCTL_L);                        /* USCI A2 IrDA Transmit Control */
3693 
SFR_8BIT(UCA2IRCTL_H);                        /* USCI A2 IrDA Transmit Control */
3694 
#define UCA2IRTCTL             UCA2IRCTL_L    /* USCI A2 IrDA Transmit Control */
3695 
#define UCA2IRRCTL             UCA2IRCTL_H    /* USCI A2 IrDA Receive Control */
3696 
SFR_16BIT(UCA2ICTL);                          /* USCI A2 Interrupt Enable Register */
3697 
SFR_8BIT(UCA2ICTL_L);                         /* USCI A2 Interrupt Enable Register */
3698 
SFR_8BIT(UCA2ICTL_H);                         /* USCI A2 Interrupt Enable Register */
3699 
#define UCA2IE                 UCA2ICTL_L     /* USCI A2 Interrupt Enable Register */
3700 
#define UCA2IFG                UCA2ICTL_H     /* USCI A2 Interrupt Flags Register */
3701 
SFR_16BIT(UCA2IV);                            /* USCI A2 Interrupt Vector Register */
3702 
 
3703 
 
3704 
/************************************************************
3705 
* USCI B2
3706 
************************************************************/
3707 
#define __MSP430_HAS_USCI_B2__                /* Definition to show that Module is available */
3708 
 
3709 
 
3710 
SFR_16BIT(UCB2CTLW0);                         /* USCI B2 Control Word Register 0 */
3711 
SFR_8BIT(UCB2CTLW0_L);                        /* USCI B2 Control Word Register 0 */
3712 
SFR_8BIT(UCB2CTLW0_H);                        /* USCI B2 Control Word Register 0 */
3713 
#define UCB2CTL1               UCB2CTLW0_L    /* USCI B2 Control Register 1 */
3714 
#define UCB2CTL0               UCB2CTLW0_H    /* USCI B2 Control Register 0 */
3715 
SFR_16BIT(UCB2BRW);                           /* USCI B2 Baud Word Rate 0 */
3716 
SFR_8BIT(UCB2BRW_L);                          /* USCI B2 Baud Word Rate 0 */
3717 
SFR_8BIT(UCB2BRW_H);                          /* USCI B2 Baud Word Rate 0 */
3718 
#define UCB2BR0                UCB2BRW_L      /* USCI B2 Baud Rate 0 */
3719 
#define UCB2BR1                UCB2BRW_H      /* USCI B2 Baud Rate 1 */
3720 
SFR_8BIT(UCB2STAT);                           /* USCI B2 Status Register */
3721 
SFR_8BIT(UCB2RXBUF);                          /* USCI B2 Receive Buffer */
3722 
SFR_8BIT(UCB2TXBUF);                          /* USCI B2 Transmit Buffer */
3723 
SFR_16BIT(UCB2I2COA);                         /* USCI B2 I2C Own Address */
3724 
SFR_8BIT(UCB2I2COA_L);                        /* USCI B2 I2C Own Address */
3725 
SFR_8BIT(UCB2I2COA_H);                        /* USCI B2 I2C Own Address */
3726 
SFR_16BIT(UCB2I2CSA);                         /* USCI B2 I2C Slave Address */
3727 
SFR_8BIT(UCB2I2CSA_L);                        /* USCI B2 I2C Slave Address */
3728 
SFR_8BIT(UCB2I2CSA_H);                        /* USCI B2 I2C Slave Address */
3729 
SFR_16BIT(UCB2ICTL);                          /* USCI B2 Interrupt Enable Register */
3730 
SFR_8BIT(UCB2ICTL_L);                         /* USCI B2 Interrupt Enable Register */
3731 
SFR_8BIT(UCB2ICTL_H);                         /* USCI B2 Interrupt Enable Register */
3732 
#define UCB2IE                 UCB2ICTL_L     /* USCI B2 Interrupt Enable Register */
3733 
#define UCB2IFG                UCB2ICTL_H     /* USCI B2 Interrupt Flags Register */
3734 
SFR_16BIT(UCB2IV);                            /* USCI B2 Interrupt Vector Register */
3735 
 
3736 
/************************************************************
3737 
* USCI A3
3738 
************************************************************/
3739 
#define __MSP430_HAS_USCI_A3__                /* Definition to show that Module is available */
3740 
 
3741 
SFR_16BIT(UCA3CTLW0);                         /* USCI A3 Control Word Register 0 */
3742 
SFR_8BIT(UCA3CTLW0_L);                        /* USCI A3 Control Word Register 0 */
3743 
SFR_8BIT(UCA3CTLW0_H);                        /* USCI A3 Control Word Register 0 */
3744 
#define UCA3CTL1               UCA3CTLW0_L    /* USCI A3 Control Register 1 */
3745 
#define UCA3CTL0               UCA3CTLW0_H    /* USCI A3 Control Register 0 */
3746 
SFR_16BIT(UCA3BRW);                           /* USCI A3 Baud Word Rate 0 */
3747 
SFR_8BIT(UCA3BRW_L);                          /* USCI A3 Baud Word Rate 0 */
3748 
SFR_8BIT(UCA3BRW_H);                          /* USCI A3 Baud Word Rate 0 */
3749 
#define UCA3BR0                UCA3BRW_L      /* USCI A3 Baud Rate 0 */
3750 
#define UCA3BR1                UCA3BRW_H      /* USCI A3 Baud Rate 1 */
3751 
SFR_8BIT(UCA3MCTL);                           /* USCI A3 Modulation Control */
3752 
SFR_8BIT(UCA3STAT);                           /* USCI A3 Status Register */
3753 
SFR_8BIT(UCA3RXBUF);                          /* USCI A3 Receive Buffer */
3754 
SFR_8BIT(UCA3TXBUF);                          /* USCI A3 Transmit Buffer */
3755 
SFR_8BIT(UCA3ABCTL);                          /* USCI A3 LIN Control */
3756 
SFR_16BIT(UCA3IRCTL);                         /* USCI A3 IrDA Transmit Control */
3757 
SFR_8BIT(UCA3IRCTL_L);                        /* USCI A3 IrDA Transmit Control */
3758 
SFR_8BIT(UCA3IRCTL_H);                        /* USCI A3 IrDA Transmit Control */
3759 
#define UCA3IRTCTL             UCA3IRCTL_L    /* USCI A3 IrDA Transmit Control */
3760 
#define UCA3IRRCTL             UCA3IRCTL_H    /* USCI A3 IrDA Receive Control */
3761 
SFR_16BIT(UCA3ICTL);                          /* USCI A3 Interrupt Enable Register */
3762 
SFR_8BIT(UCA3ICTL_L);                         /* USCI A3 Interrupt Enable Register */
3763 
SFR_8BIT(UCA3ICTL_H);                         /* USCI A3 Interrupt Enable Register */
3764 
#define UCA3IE                 UCA3ICTL_L     /* USCI A3 Interrupt Enable Register */
3765 
#define UCA3IFG                UCA3ICTL_H     /* USCI A3 Interrupt Flags Register */
3766 
SFR_16BIT(UCA3IV);                            /* USCI A3 Interrupt Vector Register */
3767 
 
3768 
 
3769 
/************************************************************
3770 
* USCI B3
3771 
************************************************************/
3772 
#define __MSP430_HAS_USCI_B3__                /* Definition to show that Module is available */
3773 
 
3774 
 
3775 
SFR_16BIT(UCB3CTLW0);                         /* USCI B3 Control Word Register 0 */
3776 
SFR_8BIT(UCB3CTLW0_L);                        /* USCI B3 Control Word Register 0 */
3777 
SFR_8BIT(UCB3CTLW0_H);                        /* USCI B3 Control Word Register 0 */
3778 
#define UCB3CTL1               UCB3CTLW0_L    /* USCI B3 Control Register 1 */
3779 
#define UCB3CTL0               UCB3CTLW0_H    /* USCI B3 Control Register 0 */
3780 
SFR_16BIT(UCB3BRW);                           /* USCI B3 Baud Word Rate 0 */
3781 
SFR_8BIT(UCB3BRW_L);                          /* USCI B3 Baud Word Rate 0 */
3782 
SFR_8BIT(UCB3BRW_H);                          /* USCI B3 Baud Word Rate 0 */
3783 
#define UCB3BR0                UCB3BRW_L      /* USCI B3 Baud Rate 0 */
3784 
#define UCB3BR1                UCB3BRW_H      /* USCI B3 Baud Rate 1 */
3785 
SFR_8BIT(UCB3STAT);                           /* USCI B3 Status Register */
3786 
SFR_8BIT(UCB3RXBUF);                          /* USCI B3 Receive Buffer */
3787 
SFR_8BIT(UCB3TXBUF);                          /* USCI B3 Transmit Buffer */
3788 
SFR_16BIT(UCB3I2COA);                         /* USCI B3 I2C Own Address */
3789 
SFR_8BIT(UCB3I2COA_L);                        /* USCI B3 I2C Own Address */
3790 
SFR_8BIT(UCB3I2COA_H);                        /* USCI B3 I2C Own Address */
3791 
SFR_16BIT(UCB3I2CSA);                         /* USCI B3 I2C Slave Address */
3792 
SFR_8BIT(UCB3I2CSA_L);                        /* USCI B3 I2C Slave Address */
3793 
SFR_8BIT(UCB3I2CSA_H);                        /* USCI B3 I2C Slave Address */
3794 
SFR_16BIT(UCB3ICTL);                          /* USCI B3 Interrupt Enable Register */
3795 
SFR_8BIT(UCB3ICTL_L);                         /* USCI B3 Interrupt Enable Register */
3796 
SFR_8BIT(UCB3ICTL_H);                         /* USCI B3 Interrupt Enable Register */
3797 
#define UCB3IE                 UCB3ICTL_L     /* USCI B3 Interrupt Enable Register */
3798 
#define UCB3IFG                UCB3ICTL_H     /* USCI B3 Interrupt Flags Register */
3799 
SFR_16BIT(UCB3IV);                            /* USCI B3 Interrupt Vector Register */
3800 
 
3801 
/************************************************************
3802 
* WATCHDOG TIMER A
3803 
************************************************************/
3804 
#define __MSP430_HAS_WDT_A__                  /* Definition to show that Module is available */
3805 
 
3806 
SFR_16BIT(WDTCTL);                            /* Watchdog Timer Control */
3807 
SFR_8BIT(WDTCTL_L);                           /* Watchdog Timer Control */
3808 
SFR_8BIT(WDTCTL_H);                           /* Watchdog Timer Control */
3809 
/* The bit names have been prefixed with "WDT" */
3810 
/* WDTCTL Control Bits */
3811 
#define WDTIS0                 (0x0001)       /* WDT - Timer Interval Select 0 */
3812 
#define WDTIS1                 (0x0002)       /* WDT - Timer Interval Select 1 */
3813 
#define WDTIS2                 (0x0004)       /* WDT - Timer Interval Select 2 */
3814 
#define WDTCNTCL               (0x0008)       /* WDT - Timer Clear */
3815 
#define WDTTMSEL               (0x0010)       /* WDT - Timer Mode Select */
3816 
#define WDTSSEL0               (0x0020)       /* WDT - Timer Clock Source Select 0 */
3817 
#define WDTSSEL1               (0x0040)       /* WDT - Timer Clock Source Select 1 */
3818 
#define WDTHOLD                (0x0080)       /* WDT - Timer hold */
3819 
 
3820 
/* WDTCTL Control Bits */
3821 
#define WDTIS0_L               (0x0001)       /* WDT - Timer Interval Select 0 */
3822 
#define WDTIS1_L               (0x0002)       /* WDT - Timer Interval Select 1 */
3823 
#define WDTIS2_L               (0x0004)       /* WDT - Timer Interval Select 2 */
3824 
#define WDTCNTCL_L             (0x0008)       /* WDT - Timer Clear */
3825 
#define WDTTMSEL_L             (0x0010)       /* WDT - Timer Mode Select */
3826 
#define WDTSSEL0_L             (0x0020)       /* WDT - Timer Clock Source Select 0 */
3827 
#define WDTSSEL1_L             (0x0040)       /* WDT - Timer Clock Source Select 1 */
3828 
#define WDTHOLD_L              (0x0080)       /* WDT - Timer hold */
3829 
 
3830 
/* WDTCTL Control Bits */
3831 
 
3832 
#define WDTPW                  (0x5A00)
3833 
 
3834 
#define WDTIS_0                (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
3835 
#define WDTIS_1                (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
3836 
#define WDTIS_2                (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
3837 
#define WDTIS_3                (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
3838 
#define WDTIS_4                (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
3839 
#define WDTIS_5                (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
3840 
#define WDTIS_6                (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
3841 
#define WDTIS_7                (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
3842 
#define WDTIS__2G              (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
3843 
#define WDTIS__128M            (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
3844 
#define WDTIS__8192K           (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
3845 
#define WDTIS__512K            (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
3846 
#define WDTIS__32K             (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
3847 
#define WDTIS__8192            (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
3848 
#define WDTIS__512             (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
3849 
#define WDTIS__64              (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
3850 
 
3851 
#define WDTSSEL_0              (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
3852 
#define WDTSSEL_1              (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
3853 
#define WDTSSEL_2              (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
3854 
#define WDTSSEL_3              (3*0x0020u)    /* WDT - Timer Clock Source Select: reserved */
3855 
#define WDTSSEL__SMCLK         (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
3856 
#define WDTSSEL__ACLK          (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
3857 
#define WDTSSEL__VLO           (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
3858 
 
3859 
/* WDT-interval times [1ms] coded with Bits 0-2 */
3860 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
3861 
#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2)                         /* 32ms interval (default) */
3862 
#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0)                  /* 8ms     " */
3863 
#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1)                  /* 0.5ms   " */
3864 
#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)           /* 0.064ms " */
3865 
/* WDT is clocked by fACLK (assumed 32KHz) */
3866 
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)                /* 1000ms  " */
3867 
#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0)         /* 250ms   " */
3868 
#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1)         /* 16ms    " */
3869 
#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0)  /* 1.9ms   " */
3870 
/* Watchdog mode -> reset after expired time */
3871 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
3872 
#define WDT_MRST_32         (WDTPW+WDTCNTCL+WDTIS2)                                  /* 32ms interval (default) */
3873 
#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS2+WDTIS0)                           /* 8ms     " */
3874 
#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS2+WDTIS1)                           /* 0.5ms   " */
3875 
#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)                    /* 0.064ms " */
3876 
/* WDT is clocked by fACLK (assumed 32KHz) */
3877 
#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2)                         /* 1000ms  " */
3878 
#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0)                  /* 250ms   " */
3879 
#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1)                  /* 16ms    " */
3880 
#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0)           /* 1.9ms   " */
3881 
 
3882 
 
3883 
/************************************************************
3884 
* TLV Descriptors
3885 
************************************************************/
3886 
#define __MSP430_HAS_TLV__                    /* Definition to show that Module is available */
3887 
 
3888 
#define TLV_START              (0x1A08)       /* Start Address of the TLV structure */
3889 
#define TLV_END                (0x1AFF)       /* End Address of the TLV structure */
3890 
 
3891 
#define TLV_LDTAG              (0x01)         /*  Legacy descriptor (1xx, 2xx, 4xx families) */
3892 
#define TLV_PDTAG              (0x02)         /*  Peripheral discovery descriptor */
3893 
#define TLV_Reserved3          (0x03)         /*  Future usage */
3894 
#define TLV_Reserved4          (0x04)         /*  Future usage */
3895 
#define TLV_BLANK              (0x05)         /*  Blank descriptor */
3896 
#define TLV_Reserved6          (0x06)         /*  Future usage */
3897 
#define TLV_Reserved7          (0x07)         /*  Serial Number */
3898 
#define TLV_DIERECORD          (0x08)         /*  Die Record  */
3899 
#define TLV_ADCCAL             (0x11)         /*  ADC calibration */
3900 
#define TLV_REFCAL             (0x12)         /*  REF calibration */
3901 
#define TLV_TAGEXT             (0xFE)         /*  Tag extender */
3902 
#define TLV_TAGEND             (0xFF)         //  Tag End of Table
3903 
 
3904 
/************************************************************
3905 
* Interrupt Vectors (offset from 0xFF80)
3906 
************************************************************/
3907 
 
3908 
#pragma diag_suppress 1107
3909 
#define VECTOR_NAME(name)             name##_ptr
3910 
#define EMIT_PRAGMA(x)                _Pragma(#x)
3911 
#define CREATE_VECTOR(name)           void * const VECTOR_NAME(name) = (void *)(long)&name
3912 
#define PLACE_VECTOR(vector,section)  EMIT_PRAGMA(DATA_SECTION(vector,section))
3913 
#define PLACE_INTERRUPT(func)         EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
3914 
#define ISR_VECTOR(func,offset)       CREATE_VECTOR(func); \
3915 
                                      PLACE_VECTOR(VECTOR_NAME(func), offset) \
3916 
                                      PLACE_INTERRUPT(func)
3917 
 
3918 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3919 
#define RTC_VECTOR              ".int41"                    /* 0xFFD2 RTC */
3920 
#else
3921 
#define RTC_VECTOR              (41 * 1u)                    /* 0xFFD2 RTC */
3922 
/*#define RTC_ISR(func)           ISR_VECTOR(func, ".int41")  */ /* 0xFFD2 RTC */ /* CCE V2 Style */
3923 
#endif
3924 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3925 
#define PORT2_VECTOR            ".int42"                    /* 0xFFD4 Port 2 */
3926 
#else
3927 
#define PORT2_VECTOR            (42 * 1u)                    /* 0xFFD4 Port 2 */
3928 
/*#define PORT2_ISR(func)         ISR_VECTOR(func, ".int42")  */ /* 0xFFD4 Port 2 */ /* CCE V2 Style */
3929 
#endif
3930 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3931 
#define USCI_B3_VECTOR          ".int43"                    /* 0xFFD6 USCI B3 Receive/Transmit */
3932 
#else
3933 
#define USCI_B3_VECTOR          (43 * 1u)                    /* 0xFFD6 USCI B3 Receive/Transmit */
3934 
/*#define USCI_B3_ISR(func)       ISR_VECTOR(func, ".int43")  */ /* 0xFFD6 USCI B3 Receive/Transmit */ /* CCE V2 Style */
3935 
#endif
3936 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3937 
#define USCI_A3_VECTOR          ".int44"                    /* 0xFFD8 USCI A3 Receive/Transmit */
3938 
#else
3939 
#define USCI_A3_VECTOR          (44 * 1u)                    /* 0xFFD8 USCI A3 Receive/Transmit */
3940 
/*#define USCI_A3_ISR(func)       ISR_VECTOR(func, ".int44")  */ /* 0xFFD8 USCI A3 Receive/Transmit */ /* CCE V2 Style */
3941 
#endif
3942 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3943 
#define USCI_B1_VECTOR          ".int45"                    /* 0xFFDA USCI B1 Receive/Transmit */
3944 
#else
3945 
#define USCI_B1_VECTOR          (45 * 1u)                    /* 0xFFDA USCI B1 Receive/Transmit */
3946 
/*#define USCI_B1_ISR(func)       ISR_VECTOR(func, ".int45")  */ /* 0xFFDA USCI B1 Receive/Transmit */ /* CCE V2 Style */
3947 
#endif
3948 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3949 
#define USCI_A1_VECTOR          ".int46"                    /* 0xFFDC USCI A1 Receive/Transmit */
3950 
#else
3951 
#define USCI_A1_VECTOR          (46 * 1u)                    /* 0xFFDC USCI A1 Receive/Transmit */
3952 
/*#define USCI_A1_ISR(func)       ISR_VECTOR(func, ".int46")  */ /* 0xFFDC USCI A1 Receive/Transmit */ /* CCE V2 Style */
3953 
#endif
3954 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3955 
#define PORT1_VECTOR            ".int47"                    /* 0xFFDE Port 1 */
3956 
#else
3957 
#define PORT1_VECTOR            (47 * 1u)                    /* 0xFFDE Port 1 */
3958 
/*#define PORT1_ISR(func)         ISR_VECTOR(func, ".int47")  */ /* 0xFFDE Port 1 */ /* CCE V2 Style */
3959 
#endif
3960 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3961 
#define TIMER1_A1_VECTOR        ".int48"                    /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
3962 
#else
3963 
#define TIMER1_A1_VECTOR        (48 * 1u)                    /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
3964 
/*#define TIMER1_A1_ISR(func)     ISR_VECTOR(func, ".int48")  */ /* 0xFFE0 Timer1_A3 CC1-2, TA1 */ /* CCE V2 Style */
3965 
#endif
3966 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3967 
#define TIMER1_A0_VECTOR        ".int49"                    /* 0xFFE2 Timer1_A3 CC0 */
3968 
#else
3969 
#define TIMER1_A0_VECTOR        (49 * 1u)                    /* 0xFFE2 Timer1_A3 CC0 */
3970 
/*#define TIMER1_A0_ISR(func)     ISR_VECTOR(func, ".int49")  */ /* 0xFFE2 Timer1_A3 CC0 */ /* CCE V2 Style */
3971 
#endif
3972 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3973 
#define DMA_VECTOR              ".int50"                    /* 0xFFE4 DMA */
3974 
#else
3975 
#define DMA_VECTOR              (50 * 1u)                    /* 0xFFE4 DMA */
3976 
/*#define DMA_ISR(func)           ISR_VECTOR(func, ".int50")  */ /* 0xFFE4 DMA */ /* CCE V2 Style */
3977 
#endif
3978 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3979 
#define USCI_B2_VECTOR          ".int51"                    /* 0xFFE6 USCI B2 Receive/Transmit */
3980 
#else
3981 
#define USCI_B2_VECTOR          (51 * 1u)                    /* 0xFFE6 USCI B2 Receive/Transmit */
3982 
/*#define USCI_B2_ISR(func)       ISR_VECTOR(func, ".int51")  */ /* 0xFFE6 USCI B2 Receive/Transmit */ /* CCE V2 Style */
3983 
#endif
3984 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3985 
#define USCI_A2_VECTOR          ".int52"                    /* 0xFFE8 USCI A2 Receive/Transmit */
3986 
#else
3987 
#define USCI_A2_VECTOR          (52 * 1u)                    /* 0xFFE8 USCI A2 Receive/Transmit */
3988 
/*#define USCI_A2_ISR(func)       ISR_VECTOR(func, ".int52")  */ /* 0xFFE8 USCI A2 Receive/Transmit */ /* CCE V2 Style */
3989 
#endif
3990 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3991 
#define TIMER0_A1_VECTOR        ".int53"                    /* 0xFFEA Timer0_A5 CC1-4, TA */
3992 
#else
3993 
#define TIMER0_A1_VECTOR        (53 * 1u)                    /* 0xFFEA Timer0_A5 CC1-4, TA */
3994 
/*#define TIMER0_A1_ISR(func)     ISR_VECTOR(func, ".int53")  */ /* 0xFFEA Timer0_A5 CC1-4, TA */ /* CCE V2 Style */
3995 
#endif
3996 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3997 
#define TIMER0_A0_VECTOR        ".int54"                    /* 0xFFEC Timer0_A5 CC0 */
3998 
#else
3999 
#define TIMER0_A0_VECTOR        (54 * 1u)                    /* 0xFFEC Timer0_A5 CC0 */
4000 
/*#define TIMER0_A0_ISR(func)     ISR_VECTOR(func, ".int54")  */ /* 0xFFEC Timer0_A5 CC0 */ /* CCE V2 Style */
4001 
#endif
4002 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4003 
#define ADC12_VECTOR            ".int55"                    /* 0xFFEE ADC */
4004 
#else
4005 
#define ADC12_VECTOR            (55 * 1u)                    /* 0xFFEE ADC */
4006 
/*#define ADC12_ISR(func)         ISR_VECTOR(func, ".int55")  */ /* 0xFFEE ADC */ /* CCE V2 Style */
4007 
#endif
4008 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4009 
#define USCI_B0_VECTOR          ".int56"                    /* 0xFFF0 USCI B0 Receive/Transmit */
4010 
#else
4011 
#define USCI_B0_VECTOR          (56 * 1u)                    /* 0xFFF0 USCI B0 Receive/Transmit */
4012 
/*#define USCI_B0_ISR(func)       ISR_VECTOR(func, ".int56")  */ /* 0xFFF0 USCI B0 Receive/Transmit */ /* CCE V2 Style */
4013 
#endif
4014 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4015 
#define USCI_A0_VECTOR          ".int57"                    /* 0xFFF2 USCI A0 Receive/Transmit */
4016 
#else
4017 
#define USCI_A0_VECTOR          (57 * 1u)                    /* 0xFFF2 USCI A0 Receive/Transmit */
4018 
/*#define USCI_A0_ISR(func)       ISR_VECTOR(func, ".int57")  */ /* 0xFFF2 USCI A0 Receive/Transmit */ /* CCE V2 Style */
4019 
#endif
4020 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4021 
#define WDT_VECTOR              ".int58"                    /* 0xFFF4 Watchdog Timer */
4022 
#else
4023 
#define WDT_VECTOR              (58 * 1u)                    /* 0xFFF4 Watchdog Timer */
4024 
/*#define WDT_ISR(func)           ISR_VECTOR(func, ".int58")  */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
4025 
#endif
4026 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4027 
#define TIMER0_B1_VECTOR        ".int59"                    /* 0xFFF6 Timer0_B7 CC1-6, TB */
4028 
#else
4029 
#define TIMER0_B1_VECTOR        (59 * 1u)                    /* 0xFFF6 Timer0_B7 CC1-6, TB */
4030 
/*#define TIMER0_B1_ISR(func)     ISR_VECTOR(func, ".int59")  */ /* 0xFFF6 Timer0_B7 CC1-6, TB */ /* CCE V2 Style */
4031 
#endif
4032 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4033 
#define TIMER0_B0_VECTOR        ".int60"                    /* 0xFFF8 Timer0_B7 CC0 */
4034 
#else
4035 
#define TIMER0_B0_VECTOR        (60 * 1u)                    /* 0xFFF8 Timer0_B7 CC0 */
4036 
/*#define TIMER0_B0_ISR(func)     ISR_VECTOR(func, ".int60")  */ /* 0xFFF8 Timer0_B7 CC0 */ /* CCE V2 Style */
4037 
#endif
4038 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4039 
#define UNMI_VECTOR             ".int61"                    /* 0xFFFA User Non-maskable */
4040 
#else
4041 
#define UNMI_VECTOR             (61 * 1u)                    /* 0xFFFA User Non-maskable */
4042 
/*#define UNMI_ISR(func)          ISR_VECTOR(func, ".int61")  */ /* 0xFFFA User Non-maskable */ /* CCE V2 Style */
4043 
#endif
4044 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4045 
#define SYSNMI_VECTOR           ".int62"                    /* 0xFFFC System Non-maskable */
4046 
#else
4047 
#define SYSNMI_VECTOR           (62 * 1u)                    /* 0xFFFC System Non-maskable */
4048 
/*#define SYSNMI_ISR(func)        ISR_VECTOR(func, ".int62")  */ /* 0xFFFC System Non-maskable */ /* CCE V2 Style */
4049 
#endif
4050 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4051 
#define RESET_VECTOR            ".reset"                    /* 0xFFFE Reset [Highest Priority] */
4052 
#else
4053 
#define RESET_VECTOR            (63 * 1u)                    /* 0xFFFE Reset [Highest Priority] */
4054 
/*#define RESET_ISR(func)         ISR_VECTOR(func, ".int63")  */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
4055 
#endif
4056 
 
4057 
/************************************************************
4058 
* End of Modules
4059 
************************************************************/
4060 
 
4061 
#ifdef __cplusplus
4062 
}
4063 
#endif /* extern "C" */
4064 
 
4065 
#endif /* #ifndef __msp430x54x */
4066