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2850 dpurdie 1 
/******************************************************************************/
2 
/* Legacy Header File                                                         */
3 
/* Not recommended for use in new projects.                                   */
4 
/* Please use the msp430.h file or the device specific header file            */
5 
/******************************************************************************/
6 
 
7 
/********************************************************************
8 
*
9 
* Standard register and bit definitions for the Texas Instruments
10 
* MSP430 microcontroller.
11 
*
12 
* This file supports assembler and C development for
13 
* MSP430xG46x devices.
14 
*
15 
* Texas Instruments, Version 1.7
16 
*
17 
* Rev. 1.0, Setup
18 
* Rev. 1.1, Fixed Names for USCI an settings for DMA
19 
* Rev. 1.2, Added VLD bits in SVS module
20 
* Rev. 1.3, Removed definitions for BTRESET
21 
*           Fixed swapped definition of RTCxxx
22 
* Rev. 1.4, Removed unused ME1 definition
23 
* Rev. 1.5, added definitions for Interrupt Vectors xxIV
24 
* Rev. 1.6, changed 'void __data20 * volatile' definition
25 
* Rev. 1.6, added LFXT1DIG
26 
*
27 
*
28 
********************************************************************/
29 
 
30 
#ifndef __msp430xG46x
31 
#define __msp430xG46x
32 
 
33 
#ifdef __cplusplus
34 
extern "C" {
35 
#endif
36 
 
37 
 
38 
/*----------------------------------------------------------------------------*/
39 
/* PERIPHERAL FILE MAP                                                        */
40 
/*----------------------------------------------------------------------------*/
41 
 
42 
/* External references resolved by a device-specific linker command file */
43 
#define SFR_8BIT(address)   extern volatile unsigned char address
44 
#define SFR_16BIT(address)  extern volatile unsigned int address
45 
//#define SFR_20BIT(address)  extern volatile unsigned int address
46 
typedef void (* __SFR_FARPTR)();
47 
#define SFR_20BIT(address) extern __SFR_FARPTR address
48 
#define SFR_32BIT(address)  extern volatile unsigned long address
49 
 
50 
 
51 
 
52 
/************************************************************
53 
* STANDARD BITS
54 
************************************************************/
55 
 
56 
#define BIT0                   (0x0001)
57 
#define BIT1                   (0x0002)
58 
#define BIT2                   (0x0004)
59 
#define BIT3                   (0x0008)
60 
#define BIT4                   (0x0010)
61 
#define BIT5                   (0x0020)
62 
#define BIT6                   (0x0040)
63 
#define BIT7                   (0x0080)
64 
#define BIT8                   (0x0100)
65 
#define BIT9                   (0x0200)
66 
#define BITA                   (0x0400)
67 
#define BITB                   (0x0800)
68 
#define BITC                   (0x1000)
69 
#define BITD                   (0x2000)
70 
#define BITE                   (0x4000)
71 
#define BITF                   (0x8000)
72 
 
73 
/************************************************************
74 
* STATUS REGISTER BITS
75 
************************************************************/
76 
 
77 
#define C                      (0x0001)
78 
#define Z                      (0x0002)
79 
#define N                      (0x0004)
80 
#define V                      (0x0100)
81 
#define GIE                    (0x0008)
82 
#define CPUOFF                 (0x0010)
83 
#define OSCOFF                 (0x0020)
84 
#define SCG0                   (0x0040)
85 
#define SCG1                   (0x0080)
86 
 
87 
/* Low Power Modes coded with Bits 4-7 in SR */
88 
 
89 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
90 
#define LPM0                   (CPUOFF)
91 
#define LPM1                   (SCG0+CPUOFF)
92 
#define LPM2                   (SCG1+CPUOFF)
93 
#define LPM3                   (SCG1+SCG0+CPUOFF)
94 
#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
95 
/* End #defines for assembler */
96 
 
97 
#else /* Begin #defines for C */
98 
#define LPM0_bits              (CPUOFF)
99 
#define LPM1_bits              (SCG0+CPUOFF)
100 
#define LPM2_bits              (SCG1+CPUOFF)
101 
#define LPM3_bits              (SCG1+SCG0+CPUOFF)
102 
#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
103 
 
104 
#include "in430.h"
105 
 
106 
#define LPM0         _bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
107 
#define LPM0_EXIT    _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
108 
#define LPM1         _bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
109 
#define LPM1_EXIT    _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
110 
#define LPM2         _bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
111 
#define LPM2_EXIT    _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
112 
#define LPM3         _bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
113 
#define LPM3_EXIT    _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
114 
#define LPM4         _bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
115 
#define LPM4_EXIT    _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
116 
#endif /* End #defines for C */
117 
 
118 
/************************************************************
119 
* CPU
120 
************************************************************/
121 
#define __MSP430_HAS_MSP430X_CPU__                /* Definition to show that it has MSP430X CPU */
122 
 
123 
/************************************************************
124 
* PERIPHERAL FILE MAP
125 
************************************************************/
126 
 
127 
/************************************************************
128 
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
129 
************************************************************/
130 
 
131 
SFR_8BIT(IE1);                                /* Interrupt Enable 1 */
132 
#define WDTIE                  (0x01)
133 
#define OFIE                   (0x02)
134 
#define NMIIE                  (0x10)
135 
#define ACCVIE                 (0x20)
136 
 
137 
SFR_8BIT(IFG1);                               /* Interrupt Flag 1 */
138 
#define WDTIFG                 (0x01)
139 
#define OFIFG                  (0x02)
140 
#define NMIIFG                 (0x10)
141 
 
142 
SFR_8BIT(IE2);                                /* Interrupt Enable 2 */
143 
#define U1IE                   IE2            /* UART1 Interrupt Enable Register */
144 
#define UC0IE                  IE2
145 
#define UCA0RXIE               (0x01)
146 
#define UCA0TXIE               (0x02)
147 
#define UCB0RXIE               (0x04)
148 
#define UCB0TXIE               (0x08)
149 
#define URXIE1                 (0x10)
150 
#define UTXIE1                 (0x20)
151 
#define BTIE                   (0x80)
152 
 
153 
SFR_8BIT(IFG2);                               /* Interrupt Flag 2 */
154 
#define U1IFG                  IFG2           /* UART1 Interrupt Flag Register */
155 
#define UC0IFG                 IFG2
156 
#define UCA0RXIFG              (0x01)
157 
#define UCA0TXIFG              (0x02)
158 
#define UCB0RXIFG              (0x04)
159 
#define UCB0TXIFG              (0x08)
160 
#define URXIFG1                (0x10)
161 
#define UTXIFG1                (0x20)
162 
#define BTIFG                  (0x80)
163 
 
164 
SFR_8BIT(ME2);                                /* Module Enable 2 */
165 
#define U1ME                   ME2            /* UART1 Module Enable Register */
166 
#define URXE1                  (0x10)
167 
#define UTXE1                  (0x20)
168 
#define USPIE1                 (0x10)
169 
 
170 
/************************************************************
171 
* ADC12
172 
************************************************************/
173 
#define __MSP430_HAS_ADC12__                  /* Definition to show that Module is available */
174 
 
175 
SFR_16BIT(ADC12CTL0);                         /* ADC12 Control 0 */
176 
SFR_16BIT(ADC12CTL1);                         /* ADC12 Control 1 */
177 
SFR_16BIT(ADC12IFG);                          /* ADC12 Interrupt Flag */
178 
SFR_16BIT(ADC12IE);                           /* ADC12 Interrupt Enable */
179 
SFR_16BIT(ADC12IV);                           /* ADC12 Interrupt Vector Word */
180 
 
181 
#define ADC12MEM_              (0x0140)       /* ADC12 Conversion Memory */
182 
#ifdef __ASM_HEADER__
183 
#define ADC12MEM               (ADC12MEM_)    /* ADC12 Conversion Memory (for assembler) */
184 
#else
185 
#define ADC12MEM               ((int*)        ADC12MEM_) /* ADC12 Conversion Memory (for C) */
186 
#endif
187 
SFR_16BIT(ADC12MEM0);                         /* ADC12 Conversion Memory 0 */
188 
SFR_16BIT(ADC12MEM1);                         /* ADC12 Conversion Memory 1 */
189 
SFR_16BIT(ADC12MEM2);                         /* ADC12 Conversion Memory 2 */
190 
SFR_16BIT(ADC12MEM3);                         /* ADC12 Conversion Memory 3 */
191 
SFR_16BIT(ADC12MEM4);                         /* ADC12 Conversion Memory 4 */
192 
SFR_16BIT(ADC12MEM5);                         /* ADC12 Conversion Memory 5 */
193 
SFR_16BIT(ADC12MEM6);                         /* ADC12 Conversion Memory 6 */
194 
SFR_16BIT(ADC12MEM7);                         /* ADC12 Conversion Memory 7 */
195 
SFR_16BIT(ADC12MEM8);                         /* ADC12 Conversion Memory 8 */
196 
SFR_16BIT(ADC12MEM9);                         /* ADC12 Conversion Memory 9 */
197 
SFR_16BIT(ADC12MEM10);                        /* ADC12 Conversion Memory 10 */
198 
SFR_16BIT(ADC12MEM11);                        /* ADC12 Conversion Memory 11 */
199 
SFR_16BIT(ADC12MEM12);                        /* ADC12 Conversion Memory 12 */
200 
SFR_16BIT(ADC12MEM13);                        /* ADC12 Conversion Memory 13 */
201 
SFR_16BIT(ADC12MEM14);                        /* ADC12 Conversion Memory 14 */
202 
SFR_16BIT(ADC12MEM15);                        /* ADC12 Conversion Memory 15 */
203 
 
204 
#define ADC12MCTL_             (0x0080)       /* ADC12 Memory Control */
205 
#ifdef __ASM_HEADER__
206 
#define ADC12MCTL              (ADC12MCTL_)   /* ADC12 Memory Control (for assembler) */
207 
#else
208 
#define ADC12MCTL              ((char*)       ADC12MCTL_) /* ADC12 Memory Control (for C) */
209 
#endif
210 
SFR_8BIT(ADC12MCTL0);                         /* ADC12 Memory Control 0 */
211 
SFR_8BIT(ADC12MCTL1);                         /* ADC12 Memory Control 1 */
212 
SFR_8BIT(ADC12MCTL2);                         /* ADC12 Memory Control 2 */
213 
SFR_8BIT(ADC12MCTL3);                         /* ADC12 Memory Control 3 */
214 
SFR_8BIT(ADC12MCTL4);                         /* ADC12 Memory Control 4 */
215 
SFR_8BIT(ADC12MCTL5);                         /* ADC12 Memory Control 5 */
216 
SFR_8BIT(ADC12MCTL6);                         /* ADC12 Memory Control 6 */
217 
SFR_8BIT(ADC12MCTL7);                         /* ADC12 Memory Control 7 */
218 
SFR_8BIT(ADC12MCTL8);                         /* ADC12 Memory Control 8 */
219 
SFR_8BIT(ADC12MCTL9);                         /* ADC12 Memory Control 9 */
220 
SFR_8BIT(ADC12MCTL10);                        /* ADC12 Memory Control 10 */
221 
SFR_8BIT(ADC12MCTL11);                        /* ADC12 Memory Control 11 */
222 
SFR_8BIT(ADC12MCTL12);                        /* ADC12 Memory Control 12 */
223 
SFR_8BIT(ADC12MCTL13);                        /* ADC12 Memory Control 13 */
224 
SFR_8BIT(ADC12MCTL14);                        /* ADC12 Memory Control 14 */
225 
SFR_8BIT(ADC12MCTL15);                        /* ADC12 Memory Control 15 */
226 
 
227 
/* ADC12CTL0 */
228 
#define ADC12SC                (0x001)        /* ADC12 Start Conversion */
229 
#define ENC                    (0x002)        /* ADC12 Enable Conversion */
230 
#define ADC12TOVIE             (0x004)        /* ADC12 Timer Overflow interrupt enable */
231 
#define ADC12OVIE              (0x008)        /* ADC12 Overflow interrupt enable */
232 
#define ADC12ON                (0x010)        /* ADC12 On/enable */
233 
#define REFON                  (0x020)        /* ADC12 Reference on */
234 
#define REF2_5V                (0x040)        /* ADC12 Ref 0:1.5V / 1:2.5V */
235 
#define MSC                    (0x080)        /* ADC12 Multiple SampleConversion */
236 
#define SHT00                  (0x0100)       /* ADC12 Sample Hold 0 Select 0 */
237 
#define SHT01                  (0x0200)       /* ADC12 Sample Hold 0 Select 1 */
238 
#define SHT02                  (0x0400)       /* ADC12 Sample Hold 0 Select 2 */
239 
#define SHT03                  (0x0800)       /* ADC12 Sample Hold 0 Select 3 */
240 
#define SHT10                  (0x1000)       /* ADC12 Sample Hold 0 Select 0 */
241 
#define SHT11                  (0x2000)       /* ADC12 Sample Hold 1 Select 1 */
242 
#define SHT12                  (0x4000)       /* ADC12 Sample Hold 2 Select 2 */
243 
#define SHT13                  (0x8000)       /* ADC12 Sample Hold 3 Select 3 */
244 
#define MSH                    (0x080)
245 
 
246 
#define SHT0_0                 (0*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 0 */
247 
#define SHT0_1                 (1*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 1 */
248 
#define SHT0_2                 (2*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 2 */
249 
#define SHT0_3                 (3*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 3 */
250 
#define SHT0_4                 (4*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 4 */
251 
#define SHT0_5                 (5*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 5 */
252 
#define SHT0_6                 (6*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 6 */
253 
#define SHT0_7                 (7*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 7 */
254 
#define SHT0_8                 (8*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 8 */
255 
#define SHT0_9                 (9*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 9 */
256 
#define SHT0_10                (10*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 10 */
257 
#define SHT0_11                (11*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 11 */
258 
#define SHT0_12                (12*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 12 */
259 
#define SHT0_13                (13*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 13 */
260 
#define SHT0_14                (14*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 14 */
261 
#define SHT0_15                (15*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 15 */
262 
 
263 
#define SHT1_0                 (0*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 0 */
264 
#define SHT1_1                 (1*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 1 */
265 
#define SHT1_2                 (2*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 2 */
266 
#define SHT1_3                 (3*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 3 */
267 
#define SHT1_4                 (4*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 4 */
268 
#define SHT1_5                 (5*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 5 */
269 
#define SHT1_6                 (6*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 6 */
270 
#define SHT1_7                 (7*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 7 */
271 
#define SHT1_8                 (8*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 8 */
272 
#define SHT1_9                 (9*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 9 */
273 
#define SHT1_10                (10*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 10 */
274 
#define SHT1_11                (11*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 11 */
275 
#define SHT1_12                (12*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 12 */
276 
#define SHT1_13                (13*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 13 */
277 
#define SHT1_14                (14*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 14 */
278 
#define SHT1_15                (15*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 15 */
279 
 
280 
/* ADC12CTL1 */
281 
#define ADC12BUSY              (0x0001)       /* ADC12 Busy */
282 
#define CONSEQ0                (0x0002)       /* ADC12 Conversion Sequence Select 0 */
283 
#define CONSEQ1                (0x0004)       /* ADC12 Conversion Sequence Select 1 */
284 
#define ADC12SSEL0             (0x0008)       /* ADC12 Clock Source Select 0 */
285 
#define ADC12SSEL1             (0x0010)       /* ADC12 Clock Source Select 1 */
286 
#define ADC12DIV0              (0x0020)       /* ADC12 Clock Divider Select 0 */
287 
#define ADC12DIV1              (0x0040)       /* ADC12 Clock Divider Select 1 */
288 
#define ADC12DIV2              (0x0080)       /* ADC12 Clock Divider Select 2 */
289 
#define ISSH                   (0x0100)       /* ADC12 Invert Sample Hold Signal */
290 
#define SHP                    (0x0200)       /* ADC12 Sample/Hold Pulse Mode */
291 
#define SHS0                   (0x0400)       /* ADC12 Sample/Hold Source 0 */
292 
#define SHS1                   (0x0800)       /* ADC12 Sample/Hold Source 1 */
293 
#define CSTARTADD0             (0x1000)       /* ADC12 Conversion Start Address 0 */
294 
#define CSTARTADD1             (0x2000)       /* ADC12 Conversion Start Address 1 */
295 
#define CSTARTADD2             (0x4000)       /* ADC12 Conversion Start Address 2 */
296 
#define CSTARTADD3             (0x8000)       /* ADC12 Conversion Start Address 3 */
297 
 
298 
#define CONSEQ_0               (0*2u)         /* ADC12 Conversion Sequence Select: 0 */
299 
#define CONSEQ_1               (1*2u)         /* ADC12 Conversion Sequence Select: 1 */
300 
#define CONSEQ_2               (2*2u)         /* ADC12 Conversion Sequence Select: 2 */
301 
#define CONSEQ_3               (3*2u)         /* ADC12 Conversion Sequence Select: 3 */
302 
#define ADC12SSEL_0            (0*8u)         /* ADC12 Clock Source Select: 0 */
303 
#define ADC12SSEL_1            (1*8u)         /* ADC12 Clock Source Select: 1 */
304 
#define ADC12SSEL_2            (2*8u)         /* ADC12 Clock Source Select: 2 */
305 
#define ADC12SSEL_3            (3*8u)         /* ADC12 Clock Source Select: 3 */
306 
#define ADC12DIV_0             (0*0x20u)      /* ADC12 Clock Divider Select: 0 */
307 
#define ADC12DIV_1             (1*0x20u)      /* ADC12 Clock Divider Select: 1 */
308 
#define ADC12DIV_2             (2*0x20u)      /* ADC12 Clock Divider Select: 2 */
309 
#define ADC12DIV_3             (3*0x20u)      /* ADC12 Clock Divider Select: 3 */
310 
#define ADC12DIV_4             (4*0x20u)      /* ADC12 Clock Divider Select: 4 */
311 
#define ADC12DIV_5             (5*0x20u)      /* ADC12 Clock Divider Select: 5 */
312 
#define ADC12DIV_6             (6*0x20u)      /* ADC12 Clock Divider Select: 6 */
313 
#define ADC12DIV_7             (7*0x20u)      /* ADC12 Clock Divider Select: 7 */
314 
#define SHS_0                  (0*0x400u)     /* ADC12 Sample/Hold Source: 0 */
315 
#define SHS_1                  (1*0x400u)     /* ADC12 Sample/Hold Source: 1 */
316 
#define SHS_2                  (2*0x400u)     /* ADC12 Sample/Hold Source: 2 */
317 
#define SHS_3                  (3*0x400u)     /* ADC12 Sample/Hold Source: 3 */
318 
#define CSTARTADD_0            (0*0x1000u)    /* ADC12 Conversion Start Address: 0 */
319 
#define CSTARTADD_1            (1*0x1000u)    /* ADC12 Conversion Start Address: 1 */
320 
#define CSTARTADD_2            (2*0x1000u)    /* ADC12 Conversion Start Address: 2 */
321 
#define CSTARTADD_3            (3*0x1000u)    /* ADC12 Conversion Start Address: 3 */
322 
#define CSTARTADD_4            (4*0x1000u)    /* ADC12 Conversion Start Address: 4 */
323 
#define CSTARTADD_5            (5*0x1000u)    /* ADC12 Conversion Start Address: 5 */
324 
#define CSTARTADD_6            (6*0x1000u)    /* ADC12 Conversion Start Address: 6 */
325 
#define CSTARTADD_7            (7*0x1000u)    /* ADC12 Conversion Start Address: 7 */
326 
#define CSTARTADD_8            (8*0x1000u)    /* ADC12 Conversion Start Address: 8 */
327 
#define CSTARTADD_9            (9*0x1000u)    /* ADC12 Conversion Start Address: 9 */
328 
#define CSTARTADD_10           (10*0x1000u)   /* ADC12 Conversion Start Address: 10 */
329 
#define CSTARTADD_11           (11*0x1000u)   /* ADC12 Conversion Start Address: 11 */
330 
#define CSTARTADD_12           (12*0x1000u)   /* ADC12 Conversion Start Address: 12 */
331 
#define CSTARTADD_13           (13*0x1000u)   /* ADC12 Conversion Start Address: 13 */
332 
#define CSTARTADD_14           (14*0x1000u)   /* ADC12 Conversion Start Address: 14 */
333 
#define CSTARTADD_15           (15*0x1000u)   /* ADC12 Conversion Start Address: 15 */
334 
 
335 
/* ADC12MCTLx */
336 
#define INCH0                  (0x0001)       /* ADC12 Input Channel Select Bit 0 */
337 
#define INCH1                  (0x0002)       /* ADC12 Input Channel Select Bit 1 */
338 
#define INCH2                  (0x0004)       /* ADC12 Input Channel Select Bit 2 */
339 
#define INCH3                  (0x0008)       /* ADC12 Input Channel Select Bit 3 */
340 
#define SREF0                  (0x0010)       /* ADC12 Select Reference Bit 0 */
341 
#define SREF1                  (0x0020)       /* ADC12 Select Reference Bit 1 */
342 
#define SREF2                  (0x0040)       /* ADC12 Select Reference Bit 2 */
343 
#define EOS                    (0x0080)       /* ADC12 End of Sequence */
344 
 
345 
#define INCH_0                 (0)            /* ADC12 Input Channel 0 */
346 
#define INCH_1                 (1)            /* ADC12 Input Channel 1 */
347 
#define INCH_2                 (2)            /* ADC12 Input Channel 2 */
348 
#define INCH_3                 (3)            /* ADC12 Input Channel 3 */
349 
#define INCH_4                 (4)            /* ADC12 Input Channel 4 */
350 
#define INCH_5                 (5)            /* ADC12 Input Channel 5 */
351 
#define INCH_6                 (6)            /* ADC12 Input Channel 6 */
352 
#define INCH_7                 (7)            /* ADC12 Input Channel 7 */
353 
#define INCH_8                 (8)            /* ADC12 Input Channel 8 */
354 
#define INCH_9                 (9)            /* ADC12 Input Channel 9 */
355 
#define INCH_10                (10)           /* ADC12 Input Channel 10 */
356 
#define INCH_11                (11)           /* ADC12 Input Channel 11 */
357 
#define INCH_12                (12)           /* ADC12 Input Channel 12 */
358 
#define INCH_13                (13)           /* ADC12 Input Channel 13 */
359 
#define INCH_14                (14)           /* ADC12 Input Channel 14 */
360 
#define INCH_15                (15)           /* ADC12 Input Channel 15 */
361 
 
362 
#define SREF_0                 (0*0x10u)      /* ADC12 Select Reference 0 */
363 
#define SREF_1                 (1*0x10u)      /* ADC12 Select Reference 1 */
364 
#define SREF_2                 (2*0x10u)      /* ADC12 Select Reference 2 */
365 
#define SREF_3                 (3*0x10u)      /* ADC12 Select Reference 3 */
366 
#define SREF_4                 (4*0x10u)      /* ADC12 Select Reference 4 */
367 
#define SREF_5                 (5*0x10u)      /* ADC12 Select Reference 5 */
368 
#define SREF_6                 (6*0x10u)      /* ADC12 Select Reference 6 */
369 
#define SREF_7                 (7*0x10u)      /* ADC12 Select Reference 7 */
370 
 
371 
/* ADC12IV Definitions */
372 
#define ADC12IV_NONE           (0x0000)       /* No Interrupt pending */
373 
#define ADC12IV_ADC12OVIFG     (0x0002)       /* ADC12OVIFG */
374 
#define ADC12IV_ADC12TOVIFG    (0x0004)       /* ADC12TOVIFG */
375 
#define ADC12IV_ADC12IFG0      (0x0006)       /* ADC12IFG0 */
376 
#define ADC12IV_ADC12IFG1      (0x0008)       /* ADC12IFG1 */
377 
#define ADC12IV_ADC12IFG2      (0x000A)       /* ADC12IFG2 */
378 
#define ADC12IV_ADC12IFG3      (0x000C)       /* ADC12IFG3 */
379 
#define ADC12IV_ADC12IFG4      (0x000E)       /* ADC12IFG4 */
380 
#define ADC12IV_ADC12IFG5      (0x0010)       /* ADC12IFG5 */
381 
#define ADC12IV_ADC12IFG6      (0x0012)       /* ADC12IFG6 */
382 
#define ADC12IV_ADC12IFG7      (0x0014)       /* ADC12IFG7 */
383 
#define ADC12IV_ADC12IFG8      (0x0016)       /* ADC12IFG8 */
384 
#define ADC12IV_ADC12IFG9      (0x0018)       /* ADC12IFG9 */
385 
#define ADC12IV_ADC12IFG10     (0x001A)       /* ADC12IFG10 */
386 
#define ADC12IV_ADC12IFG11     (0x001C)       /* ADC12IFG11 */
387 
#define ADC12IV_ADC12IFG12     (0x001E)       /* ADC12IFG12 */
388 
#define ADC12IV_ADC12IFG13     (0x0020)       /* ADC12IFG13 */
389 
#define ADC12IV_ADC12IFG14     (0x0022)       /* ADC12IFG14 */
390 
#define ADC12IV_ADC12IFG15     (0x0024)       /* ADC12IFG15 */
391 
 
392 
/************************************************************
393 
* BASIC TIMER with Real Time Clock
394 
************************************************************/
395 
#define __MSP430_HAS_BT_RTC__                 /* Definition to show that Module is available */
396 
 
397 
SFR_8BIT(BTCTL);                              /* Basic Timer Control */
398 
SFR_8BIT(RTCCTL);                             /* Real Time Clock Control */
399 
SFR_8BIT(RTCNT1);                             /* Real Time Counter 1 */
400 
SFR_8BIT(RTCNT2);                             /* Real Time Counter 2 */
401 
SFR_8BIT(RTCNT3);                             /* Real Time Counter 3 */
402 
SFR_8BIT(RTCNT4);                             /* Real Time Counter 4 */
403 
SFR_8BIT(BTCNT1);                             /* Basic Timer Count 1 */
404 
SFR_8BIT(BTCNT2);                             /* Basic Timer Count 2 */
405 
SFR_8BIT(RTCDAY);                             /* Real Time Clock Day */
406 
SFR_8BIT(RTCMON);                             /* Real Time Clock Month */
407 
SFR_8BIT(RTCYEARL);                           /* Real Time Clock Year (Low Byte) */
408 
SFR_8BIT(RTCYEARH);                           /* Real Time Clock Year (High Byte) */
409 
#define RTCSEC                 RTCNT1
410 
#define RTCMIN                 RTCNT2
411 
#define RTCHOUR                RTCNT3
412 
#define RTCDOW                 RTCNT4
413 
 
414 
SFR_16BIT(RTCTL);                             /* Basic/Real Timer Control */
415 
SFR_16BIT(RTCTIM0);                           /* Real Time Clock Time 0 */
416 
SFR_16BIT(RTCTIM1);                           /* Real Time Clock Time 1 */
417 
SFR_16BIT(BTCNT12);                           /* Basic Timer Count 1/2 */
418 
SFR_16BIT(RTCDATE);                           /* Real Time Clock Date */
419 
SFR_16BIT(RTCYEAR);                           /* Real Time Clock Year */
420 
#define RTCNT12                RTCTIM0
421 
#define RTCNT34                RTCTIM1
422 
 
423 
#define BTSSEL                 (0x80)         /* fBT = fMCLK (main clock) */
424 
#define BTHOLD                 (0x40)         /* BT1 is held if this bit is set */
425 
#define BTDIV                  (0x20)         /* fCLK2 = ACLK:256 */
426 
//#define res               (0x10)
427 
//#define res               (0x08)
428 
#define BTIP2                  (0x04)
429 
#define BTIP1                  (0x02)
430 
#define BTIP0                  (0x01)
431 
 
432 
#define RTCBCD                 (0x80)         /* RTC BCD Select */
433 
#define RTCHOLD                (0x40)         /* RTC Hold */
434 
#define RTCMODE1               (0x20)         /* RTC Mode 1 */
435 
#define RTCMODE0               (0x10)         /* RTC Mode 0 */
436 
#define RTCTEV1                (0x08)         /* RTC Time Event 1 */
437 
#define RTCTEV0                (0x04)         /* RTC Time Event 0 */
438 
#define RTCIE                  (0x02)         /* RTC Interrupt Enable */
439 
#define RTCFG                  (0x01)         /* RTC Event Flag */
440 
 
441 
#define RTCTEV_0               (0x00)         /* RTC Time Event: 0 */
442 
#define RTCTEV_1               (0x04)         /* RTC Time Event: 1 */
443 
#define RTCTEV_2               (0x08)         /* RTC Time Event: 2 */
444 
#define RTCTEV_3               (0x0C)         /* RTC Time Event: 3 */
445 
#define RTCMODE_0              (0x00)         /* RTC Mode: 0 */
446 
#define RTCMODE_1              (0x10)         /* RTC Mode: 1 */
447 
#define RTCMODE_2              (0x20)         /* RTC Mode: 2 */
448 
#define RTCMODE_3              (0x30)         /* RTC Mode: 3 */
449 
 
450 
/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
451 
#define BT_fCLK2_ACLK          (0x00)
452 
#define BT_fCLK2_ACLK_DIV256   (BTDIV)
453 
#define BT_fCLK2_MCLK          (BTSSEL)
454 
 
455 
/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
456 
#define BT_fCLK2_DIV2          (0x00)         /* fINT = fCLK2:2 (default) */
457 
#define BT_fCLK2_DIV4          (BTIP0)        /* fINT = fCLK2:4 */
458 
#define BT_fCLK2_DIV8          (BTIP1)        /* fINT = fCLK2:8 */
459 
#define BT_fCLK2_DIV16         (BTIP1+BTIP0)  /* fINT = fCLK2:16 */
460 
#define BT_fCLK2_DIV32         (BTIP2)        /* fINT = fCLK2:32 */
461 
#define BT_fCLK2_DIV64         (BTIP2+BTIP0)  /* fINT = fCLK2:64 */
462 
#define BT_fCLK2_DIV128        (BTIP2+BTIP1)  /* fINT = fCLK2:128 */
463 
#define BT_fCLK2_DIV256     (BTIP2+BTIP1+BTIP0)       /* fINT = fCLK2:256 */
464 
 
465 
/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
466 
/* fBT=fACLK is thought for longer interval times */
467 
#define BT_ADLY_0_064          (0x00)         /* 0.064ms interval (default) */
468 
#define BT_ADLY_0_125          (BTIP0)        /* 0.125ms    " */
469 
#define BT_ADLY_0_25           (BTIP1)        /* 0.25ms     " */
470 
#define BT_ADLY_0_5            (BTIP1+BTIP0)  /* 0.5ms      " */
471 
#define BT_ADLY_1              (BTIP2)        /* 1ms        " */
472 
#define BT_ADLY_2              (BTIP2+BTIP0)  /* 2ms        " */
473 
#define BT_ADLY_4              (BTIP2+BTIP1)  /* 4ms        " */
474 
#define BT_ADLY_8           (BTIP2+BTIP1+BTIP0)       /* 8ms        " */
475 
#define BT_ADLY_16             (BTDIV)        /* 16ms       " */
476 
#define BT_ADLY_32             (BTDIV+BTIP0)  /* 32ms       " */
477 
#define BT_ADLY_64             (BTDIV+BTIP1)  /* 64ms       " */
478 
#define BT_ADLY_125         (BTDIV+BTIP1+BTIP0)       /* 125ms      " */
479 
#define BT_ADLY_250            (BTDIV+BTIP2)  /* 250ms      " */
480 
#define BT_ADLY_500         (BTDIV+BTIP2+BTIP0)       /* 500ms      " */
481 
#define BT_ADLY_1000        (BTDIV+BTIP2+BTIP1)       /* 1000ms     " */
482 
#define BT_ADLY_2000        (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms     " */
483 
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
484 
/* the timing for short intervals is more precise than ACLK */
485 
/* NOTE */
486 
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
487 
/* Too low interval time results in interrupts too frequent for the processor to handle! */
488 
#define BT_MDLY_0_002          (BTSSEL)       /* 0.002ms interval       *** interval times */
489 
#define BT_MDLY_0_004          (BTSSEL+BTIP0) /* 0.004ms    "           *** too short for */
490 
#define BT_MDLY_0_008          (BTSSEL+BTIP1) /* 0.008ms    "           *** interrupt */
491 
#define BT_MDLY_0_016       (BTSSEL+BTIP1+BTIP0)      /* 0.016ms    "           *** handling */
492 
#define BT_MDLY_0_032          (BTSSEL+BTIP2) /* 0.032ms    " */
493 
#define BT_MDLY_0_064       (BTSSEL+BTIP2+BTIP0)      /* 0.064ms    " */
494 
#define BT_MDLY_0_125       (BTSSEL+BTIP2+BTIP1)      /* 0.125ms    " */
495 
#define BT_MDLY_0_25        (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms     " */
496 
 
497 
/* Hold coded with Bits 6-7 in BT(1)CTL */
498 
/* this is for BT */
499 
#define BTHOLD_CNT1            (BTHOLD)       /* BTCNT1 is held while BTHOLD is set */
500 
#define BTHOLD_CNT1_2          (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
501 
 
502 
/* INTERRUPT CONTROL BITS */
503 
/* #define BTIE                0x80 */
504 
/* #define BTIFG               0x80 */
505 
 
506 
/************************************************************
507 
* Comparator A
508 
************************************************************/
509 
#define __MSP430_HAS_COMPA__                  /* Definition to show that Module is available */
510 
 
511 
SFR_8BIT(CACTL1);                             /* Comparator A Control 1 */
512 
SFR_8BIT(CACTL2);                             /* Comparator A Control 2 */
513 
SFR_8BIT(CAPD);                               /* Comparator A Port Disable */
514 
 
515 
#define CAIFG                  (0x01)         /* Comp. A Interrupt Flag */
516 
#define CAIE                   (0x02)         /* Comp. A Interrupt Enable */
517 
#define CAIES                  (0x04)         /* Comp. A Int. Edge Select: 0:rising / 1:falling */
518 
#define CAON                   (0x08)         /* Comp. A enable */
519 
#define CAREF0                 (0x10)         /* Comp. A Internal Reference Select 0 */
520 
#define CAREF1                 (0x20)         /* Comp. A Internal Reference Select 1 */
521 
#define CARSEL                 (0x40)         /* Comp. A Internal Reference Enable */
522 
#define CAEX                   (0x80)         /* Comp. A Exchange Inputs */
523 
 
524 
#define CAREF_0                (0x00)         /* Comp. A Int. Ref. Select 0 : Off */
525 
#define CAREF_1                (0x10)         /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
526 
#define CAREF_2                (0x20)         /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
527 
#define CAREF_3                (0x30)         /* Comp. A Int. Ref. Select 3 : Vt*/
528 
 
529 
#define CAOUT                  (0x01)         /* Comp. A Output */
530 
#define CAF                    (0x02)         /* Comp. A Enable Output Filter */
531 
#define P2CA0                  (0x04)         /* Comp. A Connect External Signal to CA0 : 1 */
532 
#define P2CA1                  (0x08)         /* Comp. A Connect External Signal to CA1 : 1 */
533 
#define CACTL24                (0x10)
534 
#define CACTL25                (0x20)
535 
#define CACTL26                (0x40)
536 
#define CACTL27                (0x80)
537 
 
538 
#define CAPD0                  (0x01)         /* Comp. A Disable Input Buffer of Port Register .0 */
539 
#define CAPD1                  (0x02)         /* Comp. A Disable Input Buffer of Port Register .1 */
540 
#define CAPD2                  (0x04)         /* Comp. A Disable Input Buffer of Port Register .2 */
541 
#define CAPD3                  (0x08)         /* Comp. A Disable Input Buffer of Port Register .3 */
542 
#define CAPD4                  (0x10)         /* Comp. A Disable Input Buffer of Port Register .4 */
543 
#define CAPD5                  (0x20)         /* Comp. A Disable Input Buffer of Port Register .5 */
544 
#define CAPD6                  (0x40)         /* Comp. A Disable Input Buffer of Port Register .6 */
545 
#define CAPD7                  (0x80)         /* Comp. A Disable Input Buffer of Port Register .7 */
546 
 
547 
/************************************************************
548 
* DAC12
549 
************************************************************/
550 
#define __MSP430_HAS_DAC12_2__                /* Definition to show that Module is available */
551 
 
552 
SFR_16BIT(DAC12_0CTL);                        /* DAC12_0 Control */
553 
SFR_16BIT(DAC12_1CTL);                        /* DAC12_1 Control */
554 
 
555 
#define DAC12GRP               (0x0001)       /* DAC12 group */
556 
#define DAC12ENC               (0x0002)       /* DAC12 enable conversion */
557 
#define DAC12IFG               (0x0004)       /* DAC12 interrupt flag */
558 
#define DAC12IE                (0x0008)       /* DAC12 interrupt enable */
559 
#define DAC12DF                (0x0010)       /* DAC12 data format */
560 
#define DAC12AMP0              (0x0020)       /* DAC12 amplifier bit 0 */
561 
#define DAC12AMP1              (0x0040)       /* DAC12 amplifier bit 1 */
562 
#define DAC12AMP2              (0x0080)       /* DAC12 amplifier bit 2 */
563 
#define DAC12IR                (0x0100)       /* DAC12 input reference and output range */
564 
#define DAC12CALON             (0x0200)       /* DAC12 calibration */
565 
#define DAC12LSEL0             (0x0400)       /* DAC12 load select bit 0 */
566 
#define DAC12LSEL1             (0x0800)       /* DAC12 load select bit 1 */
567 
#define DAC12RES               (0x1000)       /* DAC12 resolution */
568 
#define DAC12SREF0             (0x2000)       /* DAC12 reference bit 0 */
569 
#define DAC12SREF1             (0x4000)       /* DAC12 reference bit 1 */
570 
#define DAC12OPS               (0x8000)       /* DAC12 Operation Amp. */
571 
 
572 
#define DAC12AMP_0             (0*0x0020u)    /* DAC12 amplifier 0: off,    3-state */
573 
#define DAC12AMP_1             (1*0x0020u)    /* DAC12 amplifier 1: off,    off */
574 
#define DAC12AMP_2             (2*0x0020u)    /* DAC12 amplifier 2: low,    low */
575 
#define DAC12AMP_3             (3*0x0020u)    /* DAC12 amplifier 3: low,    medium */
576 
#define DAC12AMP_4             (4*0x0020u)    /* DAC12 amplifier 4: low,    high */
577 
#define DAC12AMP_5             (5*0x0020u)    /* DAC12 amplifier 5: medium, medium */
578 
#define DAC12AMP_6             (6*0x0020u)    /* DAC12 amplifier 6: medium, high */
579 
#define DAC12AMP_7             (7*0x0020u)    /* DAC12 amplifier 7: high,   high */
580 
 
581 
#define DAC12LSEL_0            (0*0x0400u)    /* DAC12 load select 0: direct */
582 
#define DAC12LSEL_1            (1*0x0400u)    /* DAC12 load select 1: latched with DAT */
583 
#define DAC12LSEL_2            (2*0x0400u)    /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */
584 
#define DAC12LSEL_3            (3*0x0400u)    /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */
585 
 
586 
#define DAC12SREF_0            (0*0x2000u)    /* DAC12 reference 0: Vref+ */
587 
#define DAC12SREF_1            (1*0x2000u)    /* DAC12 reference 1: Vref+ */
588 
#define DAC12SREF_2            (2*0x2000u)    /* DAC12 reference 2: Veref+ */
589 
#define DAC12SREF_3            (3*0x2000u)    /* DAC12 reference 3: Veref+ */
590 
 
591 
SFR_16BIT(DAC12_0DAT);                        /* DAC12_0 Data */
592 
SFR_16BIT(DAC12_1DAT);                        /* DAC12_1 Data */
593 
/************************************************************
594 
* DMA_X
595 
************************************************************/
596 
#define __MSP430_HAS_DMAX_3__                 /* Definition to show that Module is available */
597 
 
598 
SFR_16BIT(DMACTL0);                           /* DMA Module Control 0 */
599 
#define DMA0TSEL0              (0x0001)       /* DMA channel 0 transfer select bit 0 */
600 
#define DMA0TSEL1              (0x0002)       /* DMA channel 0 transfer select bit 1 */
601 
#define DMA0TSEL2              (0x0004)       /* DMA channel 0 transfer select bit 2 */
602 
#define DMA0TSEL3              (0x0008)       /* DMA channel 0 transfer select bit 3 */
603 
#define DMA1TSEL0              (0x0010)       /* DMA channel 1 transfer select bit 0 */
604 
#define DMA1TSEL1              (0x0020)       /* DMA channel 1 transfer select bit 1 */
605 
#define DMA1TSEL2              (0x0040)       /* DMA channel 1 transfer select bit 2 */
606 
#define DMA1TSEL3              (0x0080)       /* DMA channel 1 transfer select bit 3 */
607 
#define DMA2TSEL0              (0x0100)       /* DMA channel 2 transfer select bit 0 */
608 
#define DMA2TSEL1              (0x0200)       /* DMA channel 2 transfer select bit 1 */
609 
#define DMA2TSEL2              (0x0400)       /* DMA channel 2 transfer select bit 2 */
610 
#define DMA2TSEL3              (0x0800)       /* DMA channel 2 transfer select bit 3 */
611 
 
612 
#define DMA0TSEL_0             (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw)*/
613 
#define DMA0TSEL_1             (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer_A (TACCR2.IFG) */
614 
#define DMA0TSEL_2             (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer_B (TBCCR2.IFG) */
615 
#define DMA0TSEL_3             (3*0x0001u)    /* DMA channel 0 transfer select 3:  USCIA receive */
616 
#define DMA0TSEL_4             (4*0x0001u)    /* DMA channel 0 transfer select 4:  USCIA transmit */
617 
#define DMA0TSEL_5             (5*0x0001u)    /* DMA channel 0 transfer select 5:  DAC12_0CTL.DAC12IFG */
618 
#define DMA0TSEL_6             (6*0x0001u)    /* DMA channel 0 transfer select 6:  ADC12 (ADC12IFG) */
619 
#define DMA0TSEL_7             (7*0x0001u)    /* DMA channel 0 transfer select 7:  Timer_A (TACCR0.IFG) */
620 
#define DMA0TSEL_8             (8*0x0001u)    /* DMA channel 0 transfer select 8:  Timer_B (TBCCR0.IFG) */
621 
#define DMA0TSEL_9             (9*0x0001u)    /* DMA channel 0 transfer select 9:  UART1 receive */
622 
#define DMA0TSEL_10            (10*0x0001u)   /* DMA channel 0 transfer select 10: UART1 transmit */
623 
#define DMA0TSEL_11            (11*0x0001u)   /* DMA channel 0 transfer select 11: Multiplier ready */
624 
#define DMA0TSEL_12            (12*0x0001u)   /* DMA channel 0 transfer select 12: USCIB receive */
625 
#define DMA0TSEL_13            (13*0x0001u)   /* DMA channel 0 transfer select 13: USCIB transmit */
626 
#define DMA0TSEL_14            (14*0x0001u)   /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */
627 
#define DMA0TSEL_15            (15*0x0001u)   /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */
628 
 
629 
#define DMA1TSEL_0             (0*0x0010u)    /* DMA channel 1 transfer select 0:  DMA_REQ */
630 
#define DMA1TSEL_1             (1*0x0010u)    /* DMA channel 1 transfer select 1:  Timer_A CCRIFG.2 */
631 
#define DMA1TSEL_2             (2*0x0010u)    /* DMA channel 1 transfer select 2:  Timer_B CCRIFG.2 */
632 
#define DMA1TSEL_3             (3*0x0010u)    /* DMA channel 1 transfer select 3:  USCIA receive */
633 
#define DMA1TSEL_4             (4*0x0010u)    /* DMA channel 1 transfer select 4:  USCIA transmit */
634 
#define DMA1TSEL_5             (5*0x0010u)    /* DMA channel 1 transfer select 5:  DAC12.0IFG */
635 
#define DMA1TSEL_6             (6*0x0010u)    /* DMA channel 1 transfer select 6:  ADC12 (ADC12IFG) */
636 
#define DMA1TSEL_7             (7*0x0010u)    /* DMA channel 1 transfer select 7:  Timer_A (TACCR0.IFG) */
637 
#define DMA1TSEL_8             (8*0x0010u)    /* DMA channel 1 transfer select 8:  Timer_B (TBCCR0.IFG) */
638 
#define DMA1TSEL_9             (9*0x0010u)    /* DMA channel 1 transfer select 9:  UART1 receive */
639 
#define DMA1TSEL_10            (10*0x0010u)   /* DMA channel 1 transfer select 10: UART1 transmit */
640 
#define DMA1TSEL_11            (11*0x0010u)   /* DMA channel 1 transfer select 11: Multiplier ready */
641 
#define DMA1TSEL_12            (12*0x0010u)   /* DMA channel 1 transfer select 12: USCIB receive */
642 
#define DMA1TSEL_13            (13*0x0010u)   /* DMA channel 1 transfer select 13: USCIB transmit */
643 
#define DMA1TSEL_14            (14*0x0010u)   /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */
644 
#define DMA1TSEL_15            (15*0x0010u)   /* DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */
645 
 
646 
#define DMA2TSEL_0             (0*0x0100u)    /* DMA channel 2 transfer select 0:  DMA_REQ */
647 
#define DMA2TSEL_1             (1*0x0100u)    /* DMA channel 2 transfer select 1:  Timer_A CCRIFG.2 */
648 
#define DMA2TSEL_2             (2*0x0100u)    /* DMA channel 2 transfer select 2:  Timer_B CCRIFG.2 */
649 
#define DMA2TSEL_3             (3*0x0100u)    /* DMA channel 2 transfer select 3:  USCIA receive */
650 
#define DMA2TSEL_4             (4*0x0100u)    /* DMA channel 2 transfer select 4:  USCIA transmit */
651 
#define DMA2TSEL_5             (5*0x0100u)    /* DMA channel 2 transfer select 5:  DAC12.0IFG */
652 
#define DMA2TSEL_6             (6*0x0100u)    /* DMA channel 2 transfer select 6:  ADC12 (ADC12IFG) */
653 
#define DMA2TSEL_7             (7*0x0100u)    /* DMA channel 2 transfer select 7:  Timer_A (TACCR0.IFG) */
654 
#define DMA2TSEL_8             (8*0x0100u)    /* DMA channel 2 transfer select 8:  Timer_B (TBCCR0.IFG) */
655 
#define DMA2TSEL_9             (9*0x0100u)    /* DMA channel 2 transfer select 9:  UART1 receive */
656 
#define DMA2TSEL_10            (10*0x0100u)   /* DMA channel 2 transfer select 10: UART1 transmit */
657 
#define DMA2TSEL_11            (11*0x0100u)   /* DMA channel 2 transfer select 11: Multiplier ready */
658 
#define DMA2TSEL_12            (12*0x0100u)   /* DMA channel 2 transfer select 12: USCIB receive */
659 
#define DMA2TSEL_13            (13*0x0100u)   /* DMA channel 2 transfer select 13: USCIB transmit */
660 
#define DMA2TSEL_14            (14*0x0100u)   /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */
661 
#define DMA2TSEL_15            (15*0x0100u)   /* DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */
662 
 
663 
SFR_16BIT(DMACTL1);                           /* DMA Module Control 1 */
664 
#define ENNMI                  (0x0001)       /* Enable NMI interruption of DMA */
665 
#define ROUNDROBIN             (0x0002)       /* Round-Robin DMA channel priorities */
666 
#define DMAONFETCH             (0x0004)       /* DMA transfer on instruction fetch */
667 
 
668 
SFR_16BIT(DMAIV);                             /* DMA Interrupt Vector Word */
669 
SFR_16BIT(DMA0CTL);                           /* DMA Channel 0 Control */
670 
SFR_16BIT(DMA1CTL);                           /* DMA Channel 1 Control */
671 
SFR_16BIT(DMA2CTL);                           /* DMA Channel 2 Control */
672 
 
673 
#define DMAREQ                 (0x0001)       /* Initiate DMA transfer with DMATSEL */
674 
#define DMAABORT               (0x0002)       /* DMA transfer aborted by NMI */
675 
#define DMAIE                  (0x0004)       /* DMA interrupt enable */
676 
#define DMAIFG                 (0x0008)       /* DMA interrupt flag */
677 
#define DMAEN                  (0x0010)       /* DMA enable */
678 
#define DMALEVEL               (0x0020)       /* DMA level sensitive trigger select */
679 
#define DMASRCBYTE             (0x0040)       /* DMA source byte */
680 
#define DMADSTBYTE             (0x0080)       /* DMA destination byte */
681 
#define DMASRCINCR0            (0x0100)       /* DMA source increment bit 0 */
682 
#define DMASRCINCR1            (0x0200)       /* DMA source increment bit 1 */
683 
#define DMADSTINCR0            (0x0400)       /* DMA destination increment bit 0 */
684 
#define DMADSTINCR1            (0x0800)       /* DMA destination increment bit 1 */
685 
#define DMADT0                 (0x1000)       /* DMA transfer mode bit 0 */
686 
#define DMADT1                 (0x2000)       /* DMA transfer mode bit 1 */
687 
#define DMADT2                 (0x4000)       /* DMA transfer mode bit 2 */
688 
 
689 
#define DMASWDW                (0*0x0040u)    /* DMA transfer: source word to destination word */
690 
#define DMASBDW                (1*0x0040u)    /* DMA transfer: source byte to destination word */
691 
#define DMASWDB                (2*0x0040u)    /* DMA transfer: source word to destination byte */
692 
#define DMASBDB                (3*0x0040u)    /* DMA transfer: source byte to destination byte */
693 
 
694 
#define DMASRCINCR_0           (0*0x0100u)    /* DMA source increment 0: source address unchanged */
695 
#define DMASRCINCR_1           (1*0x0100u)    /* DMA source increment 1: source address unchanged */
696 
#define DMASRCINCR_2           (2*0x0100u)    /* DMA source increment 2: source address decremented */
697 
#define DMASRCINCR_3           (3*0x0100u)    /* DMA source increment 3: source address incremented */
698 
 
699 
#define DMADSTINCR_0           (0*0x0400u)    /* DMA destination increment 0: destination address unchanged */
700 
#define DMADSTINCR_1           (1*0x0400u)    /* DMA destination increment 1: destination address unchanged */
701 
#define DMADSTINCR_2           (2*0x0400u)    /* DMA destination increment 2: destination address decremented */
702 
#define DMADSTINCR_3           (3*0x0400u)    /* DMA destination increment 3: destination address incremented */
703 
 
704 
#define DMADT_0                (0*0x1000u)    /* DMA transfer mode 0: single */
705 
#define DMADT_1                (1*0x1000u)    /* DMA transfer mode 1: block */
706 
#define DMADT_2                (2*0x1000u)    /* DMA transfer mode 2: interleaved */
707 
#define DMADT_3                (3*0x1000u)    /* DMA transfer mode 3: interleaved */
708 
#define DMADT_4                (4*0x1000u)    /* DMA transfer mode 4: single, repeat */
709 
#define DMADT_5                (5*0x1000u)    /* DMA transfer mode 5: block, repeat */
710 
#define DMADT_6                (6*0x1000u)    /* DMA transfer mode 6: interleaved, repeat */
711 
#define DMADT_7                (7*0x1000u)    /* DMA transfer mode 7: interleaved, repeat */
712 
 
713 
SFR_20BIT(DMA0SA);                            /* DMA Channel 0 Source Address */
714 
SFR_16BIT(DMA0SAL);                           /* DMA Channel 0 Source Address */
715 
SFR_20BIT(DMA0DA);                            /* DMA Channel 0 Destination Address */
716 
SFR_16BIT(DMA0DAL);                           /* DMA Channel 0 Destination Address */
717 
SFR_16BIT(DMA0SZ);                            /* DMA Channel 0 Transfer Size */
718 
SFR_20BIT(DMA1SA);                            /* DMA Channel 1 Source Address */
719 
SFR_16BIT(DMA1SAL);                           /* DMA Channel 1 Source Address */
720 
SFR_20BIT(DMA1DA);                            /* DMA Channel 1 Destination Address */
721 
SFR_16BIT(DMA1DAL);                           /* DMA Channel 1 Destination Address */
722 
SFR_16BIT(DMA1SZ);                            /* DMA Channel 1 Transfer Size */
723 
SFR_20BIT(DMA2SA);                            /* DMA Channel 2 Source Address */
724 
SFR_16BIT(DMA2SAL);                           /* DMA Channel 2 Source Address */
725 
SFR_20BIT(DMA2DA);                            /* DMA Channel 2 Destination Address */
726 
SFR_16BIT(DMA2DAL);                           /* DMA Channel 2 Destination Address */
727 
SFR_16BIT(DMA2SZ);                            /* DMA Channel 2 Transfer Size */
728 
 
729 
/* DMAIV Definitions */
730 
#define DMAIV_NONE             (0x0000)       /* No Interrupt pending */
731 
#define DMAIV_DMA0IFG          (0x0002)       /* DMA0IFG */
732 
#define DMAIV_DMA1IFG          (0x0004)       /* DMA1IFG */
733 
#define DMAIV_DMA2IFG          (0x0006)       /* DMA2IFG */
734 
 
735 
/*************************************************************
736 
* Flash Memory
737 
*************************************************************/
738 
#define __MSP430_HAS_FLASH__                  /* Definition to show that Module is available */
739 
#define __MSP430_HAS_2FLASH_IP__                /* Definition to show that Module is available */
740 
 
741 
SFR_16BIT(FCTL1);                             /* FLASH Control 1 */
742 
SFR_16BIT(FCTL2);                             /* FLASH Control 2 */
743 
SFR_16BIT(FCTL3);                             /* FLASH Control 3 */
744 
 
745 
#define FRKEY                  (0x9600)       /* Flash key returned by read */
746 
#define FWKEY                  (0xA500)       /* Flash key for write */
747 
#define FXKEY                  (0x3300)       /* for use with XOR instruction */
748 
 
749 
#define ERASE                  (0x0002)       /* Enable bit for Flash segment erase */
750 
#define MERAS                  (0x0004)       /* Enable bit for Flash mass erase */
751 
#define GMERAS                 (0x0008)       /* Enable bit for Flash global mass erase */
752 
#define CPUEX                  (0x0010)       /* Enable bit for CPU Execution during Flash write/erase */
753 
#define WRT                    (0x0040)       /* Enable bit for Flash write */
754 
#define BLKWRT                 (0x0080)       /* Enable bit for Flash segment write */
755 
#define SEGWRT                 (0x0080)       /* old definition */ /* Enable bit for Flash segment write */
756 
 
757 
#define FN0                    (0x0001)       /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
758 
#define FN1                    (0x0002)       /*  32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
759 
#ifndef FN2
760 
#define FN2                    (0x0004)
761 
#endif
762 
#ifndef FN3
763 
#define FN3                    (0x0008)
764 
#endif
765 
#ifndef FN4
766 
#define FN4                    (0x0010)
767 
#endif
768 
#define FN5                    (0x0020)
769 
#define FSSEL0                 (0x0040)       /* Flash clock select 0 */        /* to distinguish from USART SSELx */
770 
#define FSSEL1                 (0x0080)       /* Flash clock select 1 */
771 
 
772 
#define FSSEL_0                (0x0000)       /* Flash clock select: 0 - ACLK */
773 
#define FSSEL_1                (0x0040)       /* Flash clock select: 1 - MCLK */
774 
#define FSSEL_2                (0x0080)       /* Flash clock select: 2 - SMCLK */
775 
#define FSSEL_3                (0x00C0)       /* Flash clock select: 3 - SMCLK */
776 
 
777 
#define BUSY                   (0x0001)       /* Flash busy: 1 */
778 
#define KEYV                   (0x0002)       /* Flash Key violation flag */
779 
#define ACCVIFG                (0x0004)       /* Flash Access violation flag */
780 
#define WAIT                   (0x0008)       /* Wait flag for segment write */
781 
#define LOCK                   (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
782 
#define EMEX                   (0x0020)       /* Flash Emergency Exit */
783 
 
784 
/************************************************************
785 
* SYSTEM CLOCK, FLL+
786 
************************************************************/
787 
#define __MSP430_HAS_FLLPLUS__                /* Definition to show that Module is available */
788 
 
789 
SFR_8BIT(SCFI0);                              /* System Clock Frequency Integrator 0 */
790 
#define FN_2                   (0x04)         /* fDCOCLK =   1.4-12MHz*/
791 
#define FN_3                   (0x08)         /* fDCOCLK =   2.2-17Mhz*/
792 
#define FN_4                   (0x10)         /* fDCOCLK =   3.2-25Mhz*/
793 
#define FN_8                   (0x20)         /* fDCOCLK =     5-40Mhz*/
794 
#define FLLD0                  (0x40)         /* Loop Divider Bit : 0 */
795 
#define FLLD1                  (0x80)         /* Loop Divider Bit : 1 */
796 
 
797 
#define FLLD_1                 (0x00)         /* Multiply Selected Loop Freq. By 1 */
798 
#define FLLD_2                 (0x40)         /* Multiply Selected Loop Freq. By 2 */
799 
#define FLLD_4                 (0x80)         /* Multiply Selected Loop Freq. By 4 */
800 
#define FLLD_8                 (0xC0)         /* Multiply Selected Loop Freq. By 8 */
801 
 
802 
SFR_8BIT(SCFI1);                              /* System Clock Frequency Integrator 1 */
803 
SFR_8BIT(SCFQCTL);                            /* System Clock Frequency Control */
804 
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
805 
/* #define SCFQ_32K            0x00                        fMCLK=1*fACLK       only a range from */
806 
#define SCFQ_64K               (0x01)         /* fMCLK=2*fACLK          1+1 to 127+1 is possible */
807 
#define SCFQ_128K              (0x03)         /* fMCLK=4*fACLK */
808 
#define SCFQ_256K              (0x07)         /* fMCLK=8*fACLK */
809 
#define SCFQ_512K              (0x0F)         /* fMCLK=16*fACLK */
810 
#define SCFQ_1M                (0x1F)         /* fMCLK=32*fACLK */
811 
#define SCFQ_2M                (0x3F)         /* fMCLK=64*fACLK */
812 
#define SCFQ_4M                (0x7F)         /* fMCLK=128*fACLK */
813 
#define SCFQ_M                 (0x80)         /* Modulation Disable */
814 
 
815 
SFR_8BIT(FLL_CTL0);                           /* FLL+ Control 0 */
816 
#define DCOF                   (0x01)         /* DCO Fault Flag */
817 
#define LFOF                   (0x02)         /* Low Frequency Oscillator Fault Flag */
818 
#define XT1OF                  (0x04)         /* High Frequency Oscillator 1 Fault Flag */
819 
#define XT2OF                  (0x08)         /* High Frequency Oscillator 2 Fault Flag */
820 
#define OSCCAP0                (0x10)         /* XIN/XOUT Cap 0 */
821 
#define OSCCAP1                (0x20)         /* XIN/XOUT Cap 1 */
822 
#define XTS_FLL                (0x40)         /* 1: Selects high-freq. oscillator */
823 
#define DCOPLUS                (0x80)         /* DCO+ Enable */
824 
 
825 
#define XCAP0PF                (0x00)         /* XIN Cap = XOUT Cap = 0pf */
826 
#define XCAP10PF               (0x10)         /* XIN Cap = XOUT Cap = 10pf */
827 
#define XCAP14PF               (0x20)         /* XIN Cap = XOUT Cap = 14pf */
828 
#define XCAP18PF               (0x30)         /* XIN Cap = XOUT Cap = 18pf */
829 
#define OSCCAP_0               (0x00)         /* XIN Cap = XOUT Cap = 0pf */
830 
#define OSCCAP_1               (0x10)         /* XIN Cap = XOUT Cap = 10pf */
831 
#define OSCCAP_2               (0x20)         /* XIN Cap = XOUT Cap = 14pf */
832 
#define OSCCAP_3               (0x30)         /* XIN Cap = XOUT Cap = 18pf */
833 
 
834 
SFR_8BIT(FLL_CTL1);                           /* FLL+ Control 1 */
835 
#define FLL_DIV0               (0x01)         /* FLL+ Divide Px.x/ACLK 0 */
836 
#define FLL_DIV1               (0x02)         /* FLL+ Divide Px.x/ACLK 1 */
837 
#define SELS                   (0x04)         /* Peripheral Module Clock Source (0: DCO, 1: XT2) */
838 
#define SELM0                  (0x08)         /* MCLK Source Select 0 */
839 
#define SELM1                  (0x10)         /* MCLK Source Select 1 */
840 
#define XT2OFF                 (0x20)         /* High Frequency Oscillator 2 (XT2) disable */
841 
#define SMCLKOFF               (0x40)         /* Peripheral Module Clock (SMCLK) disable */
842 
#define LFXT1DIG               (0x80)         /* Enable Digital input for LF clock */
843 
 
844 
#define FLL_DIV_1              (0x00)         /* FLL+ Divide Px.x/ACLK By 1 */
845 
#define FLL_DIV_2              (0x01)         /* FLL+ Divide Px.x/ACLK By 2 */
846 
#define FLL_DIV_4              (0x02)         /* FLL+ Divide Px.x/ACLK By 4 */
847 
#define FLL_DIV_8              (0x03)         /* FLL+ Divide Px.x/ACLK By 8 */
848 
 
849 
#define SELM_DCO               (0x00)         /* Select DCO for CPU MCLK */
850 
#define SELM_XT2               (0x10)         /* Select XT2 for CPU MCLK */
851 
#define SELM_A                 (0x18)         /* Select A (from LFXT1) for CPU MCLK */
852 
 
853 
/* INTERRUPT CONTROL BITS */
854 
/* These two bits are defined in the Special Function Registers */
855 
/* #define OFIFG               0x02 */
856 
/* #define OFIE                0x02 */
857 
 
858 
/************************************************************
859 
* LCD_A
860 
************************************************************/
861 
#define __MSP430_HAS_LCD_A__                  /* Definition to show that Module is available */
862 
 
863 
SFR_8BIT(LCDACTL);                            /* LCD_A Control Register */
864 
#define LCDON                  (0x01)
865 
#define LCDSON                 (0x04)
866 
#define LCDMX0                 (0x08)
867 
#define LCDMX1                 (0x10)
868 
#define LCDFREQ0               (0x20)
869 
#define LCDFREQ1               (0x40)
870 
#define LCDFREQ2               (0x80)
871 
/* Display modes coded with Bits 2-4 */
872 
#define LCDSTATIC              (LCDSON)
873 
#define LCD2MUX                (LCDMX0+LCDSON)
874 
#define LCD3MUX                (LCDMX1+LCDSON)
875 
#define LCD4MUX                (LCDMX1+LCDMX0+LCDSON)
876 
/* Frequency select code with Bits 5-7 */
877 
#define LCDFREQ_32             (0x00)         /* LCD Freq: ACLK divided by 32 */
878 
#define LCDFREQ_64             (0x20)         /* LCD Freq: ACLK divided by 64 */
879 
#define LCDFREQ_96             (0x40)         /* LCD Freq: ACLK divided by 96 */
880 
#define LCDFREQ_128            (0x60)         /* LCD Freq: ACLK divided by 128 */
881 
#define LCDFREQ_192            (0x80)         /* LCD Freq: ACLK divided by 192 */
882 
#define LCDFREQ_256            (0xA0)         /* LCD Freq: ACLK divided by 256 */
883 
#define LCDFREQ_384            (0xC0)         /* LCD Freq: ACLK divided by 384 */
884 
#define LCDFREQ_512            (0xE0)         /* LCD Freq: ACLK divided by 512 */
885 
 
886 
SFR_8BIT(LCDAPCTL0);                          /* LCD_A Port Control Register 0 */
887 
#define LCDS0                  (0x01)         /* LCD Segment  0 to  3 Enable. */
888 
#define LCDS4                  (0x02)         /* LCD Segment  4 to  7 Enable. */
889 
#define LCDS8                  (0x04)         /* LCD Segment  8 to 11 Enable. */
890 
#define LCDS12                 (0x08)         /* LCD Segment 12 to 15 Enable. */
891 
#define LCDS16                 (0x10)         /* LCD Segment 16 to 19 Enable. */
892 
#define LCDS20                 (0x20)         /* LCD Segment 20 to 23 Enable. */
893 
#define LCDS24                 (0x40)         /* LCD Segment 24 to 27 Enable. */
894 
#define LCDS28                 (0x80)         /* LCD Segment 28 to 31 Enable. */
895 
 
896 
SFR_8BIT(LCDAPCTL1);                          /* LCD_A Port Control Register 1 */
897 
#define LCDS32                 (0x01)         /* LCD Segment 32 to 35 Enable. */
898 
#define LCDS36                 (0x02)         /* LCD Segment 36 to 39 Enable. */
899 
 
900 
SFR_8BIT(LCDAVCTL0);                          /* LCD_A Voltage Control Register 0 */
901 
#define LCD2B                  (0x01)         /* Selects 1/2 bias. */
902 
#define VLCDREF0               (0x02)         /* Selects reference voltage for regulated charge pump: 0 */
903 
#define VLCDREF1               (0x04)         /* Selects reference voltage for regulated charge pump: 1 */
904 
#define LCDCPEN                (0x08)         /* LCD Voltage Charge Pump Enable. */
905 
#define VLCDEXT                (0x10)         /* Select external source for VLCD. */
906 
#define LCDREXT                (0x20)         /* Selects external connections for LCD mid voltages. */
907 
#define LCDR03EXT              (0x40)         /* Selects external connection for lowest LCD voltage. */
908 
 
909 
/* Reference voltage source select for the regulated charge pump */
910 
#define VLCDREF_0              (0<<1)         /* Internal */
911 
#define VLCDREF_1              (1<<1)         /* External */
912 
#define VLCDREF_2              (2<<1)         /* Reserved */
913 
#define VLCDREF_3              (3<<1)         /* Reserved */
914 
 
915 
SFR_8BIT(LCDAVCTL1);                          /* LCD_A Voltage Control Register 1 */
916 
#define VLCD0                  (0x02)         /* VLCD select: 0 */
917 
#define VLCD1                  (0x04)         /* VLCD select: 1 */
918 
#define VLCD2                  (0x08)         /* VLCD select: 2 */
919 
#define VLCD3                  (0x10)         /* VLCD select: 3 */
920 
 
921 
/* Charge pump voltage selections */
922 
#define VLCD_0                 (0<<1)         /* Charge pump disabled */
923 
#define VLCD_1                 (1<<1)         /* VLCD = 2.60V */
924 
#define VLCD_2                 (2<<1)         /* VLCD = 2.66V */
925 
#define VLCD_3                 (3<<1)         /* VLCD = 2.72V */
926 
#define VLCD_4                 (4<<1)         /* VLCD = 2.78V */
927 
#define VLCD_5                 (5<<1)         /* VLCD = 2.84V */
928 
#define VLCD_6                 (6<<1)         /* VLCD = 2.90V */
929 
#define VLCD_7                 (7<<1)         /* VLCD = 2.96V */
930 
#define VLCD_8                 (8<<1)         /* VLCD = 3.02V */
931 
#define VLCD_9                 (9<<1)         /* VLCD = 3.08V */
932 
#define VLCD_10                (10<<1)        /* VLCD = 3.14V */
933 
#define VLCD_11                (11<<1)        /* VLCD = 3.20V */
934 
#define VLCD_12                (12<<1)        /* VLCD = 3.26V */
935 
#define VLCD_13                (12<<1)        /* VLCD = 3.32V */
936 
#define VLCD_14                (13<<1)        /* VLCD = 3.38V */
937 
#define VLCD_15                (15<<1)        /* VLCD = 3.44V */
938 
 
939 
#define VLCD_DISABLED          (0<<1)         /* Charge pump disabled */
940 
#define VLCD_2_60              (1<<1)         /* VLCD = 2.60V */
941 
#define VLCD_2_66              (2<<1)         /* VLCD = 2.66V */
942 
#define VLCD_2_72              (3<<1)         /* VLCD = 2.72V */
943 
#define VLCD_2_78              (4<<1)         /* VLCD = 2.78V */
944 
#define VLCD_2_84              (5<<1)         /* VLCD = 2.84V */
945 
#define VLCD_2_90              (6<<1)         /* VLCD = 2.90V */
946 
#define VLCD_2_96              (7<<1)         /* VLCD = 2.96V */
947 
#define VLCD_3_02              (8<<1)         /* VLCD = 3.02V */
948 
#define VLCD_3_08              (9<<1)         /* VLCD = 3.08V */
949 
#define VLCD_3_14              (10<<1)        /* VLCD = 3.14V */
950 
#define VLCD_3_20              (11<<1)        /* VLCD = 3.20V */
951 
#define VLCD_3_26              (12<<1)        /* VLCD = 3.26V */
952 
#define VLCD_3_32              (12<<1)        /* VLCD = 3.32V */
953 
#define VLCD_3_38              (13<<1)        /* VLCD = 3.38V */
954 
#define VLCD_3_44              (15<<1)        /* VLCD = 3.44V */
955 
 
956 
#define LCDMEM_                (0x0091)       /* LCD Memory */
957 
#ifdef __ASM_HEADER__
958 
#define LCDMEM                 (LCDMEM_)      /* LCD Memory (for assembler) */
959 
#else
960 
#define LCDMEM                 ((char*)       LCDMEM_) /* LCD Memory (for C) */
961 
#endif
962 
SFR_8BIT(LCDM1);                              /* LCD Memory 1 */
963 
SFR_8BIT(LCDM2);                              /* LCD Memory 2 */
964 
SFR_8BIT(LCDM3);                              /* LCD Memory 3 */
965 
SFR_8BIT(LCDM4);                              /* LCD Memory 4 */
966 
SFR_8BIT(LCDM5);                              /* LCD Memory 5 */
967 
SFR_8BIT(LCDM6);                              /* LCD Memory 6 */
968 
SFR_8BIT(LCDM7);                              /* LCD Memory 7 */
969 
SFR_8BIT(LCDM8);                              /* LCD Memory 8 */
970 
SFR_8BIT(LCDM9);                              /* LCD Memory 9 */
971 
SFR_8BIT(LCDM10);                             /* LCD Memory 10 */
972 
SFR_8BIT(LCDM11);                             /* LCD Memory 11 */
973 
SFR_8BIT(LCDM12);                             /* LCD Memory 12 */
974 
SFR_8BIT(LCDM13);                             /* LCD Memory 13 */
975 
SFR_8BIT(LCDM14);                             /* LCD Memory 14 */
976 
SFR_8BIT(LCDM15);                             /* LCD Memory 15 */
977 
SFR_8BIT(LCDM16);                             /* LCD Memory 16 */
978 
SFR_8BIT(LCDM17);                             /* LCD Memory 17 */
979 
SFR_8BIT(LCDM18);                             /* LCD Memory 18 */
980 
SFR_8BIT(LCDM19);                             /* LCD Memory 19 */
981 
SFR_8BIT(LCDM20);                             /* LCD Memory 20 */
982 
 
983 
#define LCDMA                  (LCDM10)       /* LCD Memory A */
984 
#define LCDMB                  (LCDM11)       /* LCD Memory B */
985 
#define LCDMC                  (LCDM12)       /* LCD Memory C */
986 
#define LCDMD                  (LCDM13)       /* LCD Memory D */
987 
#define LCDME                  (LCDM14)       /* LCD Memory E */
988 
#define LCDMF                  (LCDM15)       /* LCD Memory F */
989 
 
990 
/************************************************************
991 
* HARDWARE MULTIPLIER
992 
************************************************************/
993 
#define __MSP430_HAS_MPY__                    /* Definition to show that Module is available */
994 
 
995 
SFR_16BIT(MPY);                               /* Multiply Unsigned/Operand 1 */
996 
SFR_16BIT(MPYS);                              /* Multiply Signed/Operand 1 */
997 
SFR_16BIT(MAC);                               /* Multiply Unsigned and Accumulate/Operand 1 */
998 
SFR_16BIT(MACS);                              /* Multiply Signed and Accumulate/Operand 1 */
999 
SFR_16BIT(OP2);                               /* Operand 2 */
1000 
SFR_16BIT(RESLO);                             /* Result Low Word */
1001 
SFR_16BIT(RESHI);                             /* Result High Word */
1002 
SFR_16BIT(SUMEXT);                            /* Sum Extend */
1003 
 
1004 
/************************************************************
1005 
* Operational Amplifier
1006 
************************************************************/
1007 
#define __MSP430_HAS_OA_3__                   /* Definition to show that Module is available */
1008 
 
1009 
SFR_8BIT(OA0CTL0);                            /* OA0 Control register 0 */
1010 
SFR_8BIT(OA0CTL1);                            /* OA0 Control register 1 */
1011 
SFR_8BIT(OA1CTL0);                            /* OA1 Control register 0 */
1012 
SFR_8BIT(OA1CTL1);                            /* OA1 Control register 1 */
1013 
SFR_8BIT(OA2CTL0);                            /* OA2 Control register 0 */
1014 
SFR_8BIT(OA2CTL1);                            /* OA2 Control register 1 */
1015 
 
1016 
#define OAADC0                 (0x01)         /* OAx output to ADC12 input channel select 0 */
1017 
#define OAADC1                 (0x02)         /* OAx output to ADC12 input channel select 1 */
1018 
#define OAPM0                  (0x04)         /* OAx Power mode select 0 */
1019 
#define OAPM1                  (0x08)         /* OAx Power mode select 1 */
1020 
#define OAP0                   (0x10)         /* OAx Non-inverting input select 0 */
1021 
#define OAP1                   (0x20)         /* OAx Non-inverting input select 1 */
1022 
#define OAN0                   (0x40)         /* OAx Inverting input select 0 */
1023 
#define OAN1                   (0x80)         /* OAx Inverting input select 1 */
1024 
 
1025 
#define OAPM_0                 (0x00)         /* OAx Power mode select: off */
1026 
#define OAPM_1                 (0x04)         /* OAx Power mode select: slow */
1027 
#define OAPM_2                 (0x08)         /* OAx Power mode select: meduim */
1028 
#define OAPM_3                 (0x0C)         /* OAx Power mode select: fast */
1029 
#define OAP_0                  (0x00)         /* OAx Non-inverting input select 00 */
1030 
#define OAP_1                  (0x10)         /* OAx Non-inverting input select 01 */
1031 
#define OAP_2                  (0x20)         /* OAx Non-inverting input select 10 */
1032 
#define OAP_3                  (0x30)         /* OAx Non-inverting input select 11 */
1033 
#define OAN_0                  (0x00)         /* OAx Inverting input select 00 */
1034 
#define OAN_1                  (0x40)         /* OAx Inverting input select 01 */
1035 
#define OAN_2                  (0x80)         /* OAx Inverting input select 10 */
1036 
#define OAN_3                  (0xC0)         /* OAx Inverting input select 11 */
1037 
 
1038 
#define OARRIP                 (0x01)         /* OAx Rail-to-Rail Input off */
1039 
//#define Reserved          (0x02)    /* */
1040 
#define OAFC0                  (0x04)         /* OAx Function control 0 */
1041 
#define OAFC1                  (0x08)         /* OAx Function control 1 */
1042 
#define OAFC2                  (0x10)         /* OAx Function control 2 */
1043 
#define OAFBR0                 (0x20)         /* OAx Feedback resistor select 0 */
1044 
#define OAFBR1                 (0x40)         /* OAx Feedback resistor select 1 */
1045 
#define OAFBR2                 (0x80)         /* OAx Feedback resistor select 2 */
1046 
 
1047 
#define OAFC_0                 (0x00)         /* OAx Function: Gen. Purpose */
1048 
#define OAFC_1                 (0x04)         /* OAx Function: Unity gain buffer */
1049 
#define OAFC_2                 (0x08)         /* OAx Function: Reserved */
1050 
#define OAFC_3                 (0x0C)         /* OAx Function: Comparator */
1051 
#define OAFC_4                 (0x10)         /* OAx Function: Non-Inverting PGA */
1052 
#define OAFC_5                 (0x14)         /* OAx Function: Reserved */
1053 
#define OAFC_6                 (0x18)         /* OAx Function: Inverting PGA */
1054 
#define OAFC_7                 (0x1C)         /* OAx Function: Differential PGA */
1055 
#define OAFBR_0                (0x00)         /* OAx Feedback resistor: Tap 0 */
1056 
#define OAFBR_1                (0x20)         /* OAx Feedback resistor: Tap 1 */
1057 
#define OAFBR_2                (0x40)         /* OAx Feedback resistor: Tap 2 */
1058 
#define OAFBR_3                (0x60)         /* OAx Feedback resistor: Tap 3 */
1059 
#define OAFBR_4                (0x80)         /* OAx Feedback resistor: Tap 4 */
1060 
#define OAFBR_5                (0xA0)         /* OAx Feedback resistor: Tap 5 */
1061 
#define OAFBR_6                (0xC0)         /* OAx Feedback resistor: Tap 6 */
1062 
#define OAFBR_7                (0xE0)         /* OAx Feedback resistor: Tap 7 */
1063 
 
1064 
/************************************************************
1065 
* DIGITAL I/O Port1/2
1066 
************************************************************/
1067 
#define __MSP430_HAS_PORT1__                  /* Definition to show that Module is available */
1068 
#define __MSP430_HAS_PORT2__                  /* Definition to show that Module is available */
1069 
 
1070 
SFR_8BIT(P1IN);                               /* Port 1 Input */
1071 
SFR_8BIT(P1OUT);                              /* Port 1 Output */
1072 
SFR_8BIT(P1DIR);                              /* Port 1 Direction */
1073 
SFR_8BIT(P1IFG);                              /* Port 1 Interrupt Flag */
1074 
SFR_8BIT(P1IES);                              /* Port 1 Interrupt Edge Select */
1075 
SFR_8BIT(P1IE);                               /* Port 1 Interrupt Enable */
1076 
SFR_8BIT(P1SEL);                              /* Port 1 Selection */
1077 
 
1078 
SFR_8BIT(P2IN);                               /* Port 2 Input */
1079 
SFR_8BIT(P2OUT);                              /* Port 2 Output */
1080 
SFR_8BIT(P2DIR);                              /* Port 2 Direction */
1081 
SFR_8BIT(P2IFG);                              /* Port 2 Interrupt Flag */
1082 
SFR_8BIT(P2IES);                              /* Port 2 Interrupt Edge Select */
1083 
SFR_8BIT(P2IE);                               /* Port 2 Interrupt Enable */
1084 
SFR_8BIT(P2SEL);                              /* Port 2 Selection */
1085 
 
1086 
/************************************************************
1087 
* DIGITAL I/O Port3/4
1088 
************************************************************/
1089 
#define __MSP430_HAS_PORT3__                  /* Definition to show that Module is available */
1090 
#define __MSP430_HAS_PORT4__                  /* Definition to show that Module is available */
1091 
 
1092 
SFR_8BIT(P3IN);                               /* Port 3 Input */
1093 
SFR_8BIT(P3OUT);                              /* Port 3 Output */
1094 
SFR_8BIT(P3DIR);                              /* Port 3 Direction */
1095 
SFR_8BIT(P3SEL);                              /* Port 3 Selection */
1096 
 
1097 
SFR_8BIT(P4IN);                               /* Port 4 Input */
1098 
SFR_8BIT(P4OUT);                              /* Port 4 Output */
1099 
SFR_8BIT(P4DIR);                              /* Port 4 Direction */
1100 
SFR_8BIT(P4SEL);                              /* Port 4 Selection */
1101 
 
1102 
/************************************************************
1103 
* DIGITAL I/O Port5/6
1104 
************************************************************/
1105 
#define __MSP430_HAS_PORT5__                  /* Definition to show that Module is available */
1106 
#define __MSP430_HAS_PORT6__                  /* Definition to show that Module is available */
1107 
 
1108 
SFR_8BIT(P5IN);                               /* Port 5 Input */
1109 
SFR_8BIT(P5OUT);                              /* Port 5 Output */
1110 
SFR_8BIT(P5DIR);                              /* Port 5 Direction */
1111 
SFR_8BIT(P5SEL);                              /* Port 5 Selection */
1112 
 
1113 
SFR_8BIT(P6IN);                               /* Port 6 Input */
1114 
SFR_8BIT(P6OUT);                              /* Port 6 Output */
1115 
SFR_8BIT(P6DIR);                              /* Port 6 Direction */
1116 
SFR_8BIT(P6SEL);                              /* Port 6 Selection */
1117 
 
1118 
/************************************************************
1119 
* DIGITAL I/O Port7/8
1120 
************************************************************/
1121 
#define __MSP430_HAS_PORT7__                  /* Definition to show that Module is available */
1122 
#define __MSP430_HAS_PORT8__                  /* Definition to show that Module is available */
1123 
#define __MSP430_HAS_PORTA__                  /* Definition to show that Module is available */
1124 
 
1125 
SFR_8BIT(P7IN);                               /* Port 7 Input */
1126 
SFR_8BIT(P7OUT);                              /* Port 7 Output */
1127 
SFR_8BIT(P7DIR);                              /* Port 7 Direction */
1128 
SFR_8BIT(P7SEL);                              /* Port 7 Selection */
1129 
 
1130 
SFR_8BIT(P8IN);                               /* Port 8 Input */
1131 
SFR_8BIT(P8OUT);                              /* Port 8 Output */
1132 
SFR_8BIT(P8DIR);                              /* Port 8 Direction */
1133 
SFR_8BIT(P8SEL);                              /* Port 8 Selection */
1134 
 
1135 
SFR_16BIT(PAIN);                              /* Port A Input */
1136 
SFR_16BIT(PAOUT);                             /* Port A Output */
1137 
SFR_16BIT(PADIR);                             /* Port A Direction */
1138 
SFR_16BIT(PASEL);                             /* Port A Selection */
1139 
 
1140 
/************************************************************
1141 
* DIGITAL I/O Port9/10
1142 
************************************************************/
1143 
#define __MSP430_HAS_PORT9__                  /* Definition to show that Module is available */
1144 
#define __MSP430_HAS_PORT10__                 /* Definition to show that Module is available */
1145 
#define __MSP430_HAS_PORTB__                  /* Definition to show that Module is available */
1146 
 
1147 
SFR_8BIT(P9IN);                               /* Port 9 Input */
1148 
SFR_8BIT(P9OUT);                              /* Port 9 Output */
1149 
SFR_8BIT(P9DIR);                              /* Port 9 Direction */
1150 
SFR_8BIT(P9SEL);                              /* Port 9 Selection */
1151 
 
1152 
SFR_8BIT(P10IN);                              /* Port 10 Input */
1153 
SFR_8BIT(P10OUT);                             /* Port 10 Output */
1154 
SFR_8BIT(P10DIR);                             /* Port 10 Direction */
1155 
SFR_8BIT(P10SEL);                             /* Port 10 Selection */
1156 
 
1157 
SFR_16BIT(PBIN);                              /* Port B Input */
1158 
SFR_16BIT(PBOUT);                             /* Port B Output */
1159 
SFR_16BIT(PBDIR);                             /* Port B Direction */
1160 
SFR_16BIT(PBSEL);                             /* Port B Selection */
1161 
 
1162 
/************************************************************
1163 
* Brown-Out, Supply Voltage Supervision (SVS)
1164 
************************************************************/
1165 
#define __MSP430_HAS_SVS__                    /* Definition to show that Module is available */
1166 
 
1167 
SFR_8BIT(SVSCTL);                             /* SVS Control */
1168 
#define SVSFG                  (0x01)         /* SVS Flag */
1169 
#define SVSOP                  (0x02)         /* SVS output (read only) */
1170 
#define SVSON                  (0x04)         /* Switches the SVS on/off */
1171 
#define PORON                  (0x08)         /* Enable POR Generation if Low Voltage */
1172 
#define VLD0                   (0x10)
1173 
#define VLD1                   (0x20)
1174 
#define VLD2                   (0x40)
1175 
#define VLD3                   (0x80)
1176 
 
1177 
#define VLDON                  (0x10)
1178 
#define VLDOFF                 (0x00)
1179 
#define VLD_1_8V               (0x10)
1180 
 
1181 
/************************************************************
1182 
* Timer A3
1183 
************************************************************/
1184 
#define __MSP430_HAS_TA3__                    /* Definition to show that Module is available */
1185 
 
1186 
SFR_16BIT(TAIV);                              /* Timer A Interrupt Vector Word */
1187 
SFR_16BIT(TACTL);                             /* Timer A Control */
1188 
SFR_16BIT(TACCTL0);                           /* Timer A Capture/Compare Control 0 */
1189 
SFR_16BIT(TACCTL1);                           /* Timer A Capture/Compare Control 1 */
1190 
SFR_16BIT(TACCTL2);                           /* Timer A Capture/Compare Control 2 */
1191 
SFR_16BIT(TAR);                               /* Timer A Counter Register */
1192 
SFR_16BIT(TACCR0);                            /* Timer A Capture/Compare 0 */
1193 
SFR_16BIT(TACCR1);                            /* Timer A Capture/Compare 1 */
1194 
SFR_16BIT(TACCR2);                            /* Timer A Capture/Compare 2 */
1195 
 
1196 
/* Alternate register names */
1197 
#define CCTL0                  TACCTL0        /* Timer A Capture/Compare Control 0 */
1198 
#define CCTL1                  TACCTL1        /* Timer A Capture/Compare Control 1 */
1199 
#define CCTL2                  TACCTL2        /* Timer A Capture/Compare Control 2 */
1200 
#define CCR0                   TACCR0         /* Timer A Capture/Compare 0 */
1201 
#define CCR1                   TACCR1         /* Timer A Capture/Compare 1 */
1202 
#define CCR2                   TACCR2         /* Timer A Capture/Compare 2 */
1203 
#define CCTL0_                 TACCTL0_       /* Timer A Capture/Compare Control 0 */
1204 
#define CCTL1_                 TACCTL1_       /* Timer A Capture/Compare Control 1 */
1205 
#define CCTL2_                 TACCTL2_       /* Timer A Capture/Compare Control 2 */
1206 
#define CCR0_                  TACCR0_        /* Timer A Capture/Compare 0 */
1207 
#define CCR1_                  TACCR1_        /* Timer A Capture/Compare 1 */
1208 
#define CCR2_                  TACCR2_        /* Timer A Capture/Compare 2 */
1209 
/* Alternate register names - 5xx style */
1210 
#define TA0IV                  TAIV           /* Timer A Interrupt Vector Word */
1211 
#define TA0CTL                 TACTL          /* Timer A Control */
1212 
#define TA0CCTL0               TACCTL0        /* Timer A Capture/Compare Control 0 */
1213 
#define TA0CCTL1               TACCTL1        /* Timer A Capture/Compare Control 1 */
1214 
#define TA0CCTL2               TACCTL2        /* Timer A Capture/Compare Control 2 */
1215 
#define TA0R                   TAR            /* Timer A Counter Register */
1216 
#define TA0CCR0                TACCR0         /* Timer A Capture/Compare 0 */
1217 
#define TA0CCR1                TACCR1         /* Timer A Capture/Compare 1 */
1218 
#define TA0CCR2                TACCR2         /* Timer A Capture/Compare 2 */
1219 
#define TA0IV_                 TAIV_          /* Timer A Interrupt Vector Word */
1220 
#define TA0CTL_                TACTL_         /* Timer A Control */
1221 
#define TA0CCTL0_              TACCTL0_       /* Timer A Capture/Compare Control 0 */
1222 
#define TA0CCTL1_              TACCTL1_       /* Timer A Capture/Compare Control 1 */
1223 
#define TA0CCTL2_              TACCTL2_       /* Timer A Capture/Compare Control 2 */
1224 
#define TA0R_                  TAR_           /* Timer A Counter Register */
1225 
#define TA0CCR0_               TACCR0_        /* Timer A Capture/Compare 0 */
1226 
#define TA0CCR1_               TACCR1_        /* Timer A Capture/Compare 1 */
1227 
#define TA0CCR2_               TACCR2_        /* Timer A Capture/Compare 2 */
1228 
 
1229 
#define TASSEL1                (0x0200)       /* Timer A clock source select 0 */
1230 
#define TASSEL0                (0x0100)       /* Timer A clock source select 1 */
1231 
#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
1232 
#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
1233 
#define MC1                    (0x0020)       /* Timer A mode control 1 */
1234 
#define MC0                    (0x0010)       /* Timer A mode control 0 */
1235 
#define TACLR                  (0x0004)       /* Timer A counter clear */
1236 
#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
1237 
#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
1238 
 
1239 
#define MC_0                   (0*0x10u)      /* Timer A mode control: 0 - Stop */
1240 
#define MC_1                   (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
1241 
#define MC_2                   (2*0x10u)      /* Timer A mode control: 2 - Continous up */
1242 
#define MC_3                   (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
1243 
#define ID_0                   (0*0x40u)      /* Timer A input divider: 0 - /1 */
1244 
#define ID_1                   (1*0x40u)      /* Timer A input divider: 1 - /2 */
1245 
#define ID_2                   (2*0x40u)      /* Timer A input divider: 2 - /4 */
1246 
#define ID_3                   (3*0x40u)      /* Timer A input divider: 3 - /8 */
1247 
#define TASSEL_0               (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
1248 
#define TASSEL_1               (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
1249 
#define TASSEL_2               (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
1250 
#define TASSEL_3               (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
1251 
 
1252 
#define CM1                    (0x8000)       /* Capture mode 1 */
1253 
#define CM0                    (0x4000)       /* Capture mode 0 */
1254 
#define CCIS1                  (0x2000)       /* Capture input select 1 */
1255 
#define CCIS0                  (0x1000)       /* Capture input select 0 */
1256 
#define SCS                    (0x0800)       /* Capture sychronize */
1257 
#define SCCI                   (0x0400)       /* Latched capture signal (read) */
1258 
#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
1259 
#define OUTMOD2                (0x0080)       /* Output mode 2 */
1260 
#define OUTMOD1                (0x0040)       /* Output mode 1 */
1261 
#define OUTMOD0                (0x0020)       /* Output mode 0 */
1262 
#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
1263 
#define CCI                    (0x0008)       /* Capture input signal (read) */
1264 
#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
1265 
#define COV                    (0x0002)       /* Capture/compare overflow flag */
1266 
#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
1267 
 
1268 
#define OUTMOD_0               (0*0x20u)      /* PWM output mode: 0 - output only */
1269 
#define OUTMOD_1               (1*0x20u)      /* PWM output mode: 1 - set */
1270 
#define OUTMOD_2               (2*0x20u)      /* PWM output mode: 2 - PWM toggle/reset */
1271 
#define OUTMOD_3               (3*0x20u)      /* PWM output mode: 3 - PWM set/reset */
1272 
#define OUTMOD_4               (4*0x20u)      /* PWM output mode: 4 - toggle */
1273 
#define OUTMOD_5               (5*0x20u)      /* PWM output mode: 5 - Reset */
1274 
#define OUTMOD_6               (6*0x20u)      /* PWM output mode: 6 - PWM toggle/set */
1275 
#define OUTMOD_7               (7*0x20u)      /* PWM output mode: 7 - PWM reset/set */
1276 
#define CCIS_0                 (0*0x1000u)    /* Capture input select: 0 - CCIxA */
1277 
#define CCIS_1                 (1*0x1000u)    /* Capture input select: 1 - CCIxB */
1278 
#define CCIS_2                 (2*0x1000u)    /* Capture input select: 2 - GND */
1279 
#define CCIS_3                 (3*0x1000u)    /* Capture input select: 3 - Vcc */
1280 
#define CM_0                   (0*0x4000u)    /* Capture mode: 0 - disabled */
1281 
#define CM_1                   (1*0x4000u)    /* Capture mode: 1 - pos. edge */
1282 
#define CM_2                   (2*0x4000u)    /* Capture mode: 1 - neg. edge */
1283 
#define CM_3                   (3*0x4000u)    /* Capture mode: 1 - both edges */
1284 
 
1285 
/* TA3IV Definitions */
1286 
#define TAIV_NONE              (0x0000)       /* No Interrupt pending */
1287 
#define TAIV_TACCR1            (0x0002)       /* TACCR1_CCIFG */
1288 
#define TAIV_TACCR2            (0x0004)       /* TACCR2_CCIFG */
1289 
#define TAIV_6                 (0x0006)       /* Reserved */
1290 
#define TAIV_8                 (0x0008)       /* Reserved */
1291 
#define TAIV_TAIFG             (0x000A)       /* TAIFG */
1292 
 
1293 
/************************************************************
1294 
* Timer B7
1295 
************************************************************/
1296 
#define __MSP430_HAS_TB7__                    /* Definition to show that Module is available */
1297 
 
1298 
SFR_16BIT(TBIV);                              /* Timer B Interrupt Vector Word */
1299 
SFR_16BIT(TBCTL);                             /* Timer B Control */
1300 
SFR_16BIT(TBCCTL0);                           /* Timer B Capture/Compare Control 0 */
1301 
SFR_16BIT(TBCCTL1);                           /* Timer B Capture/Compare Control 1 */
1302 
SFR_16BIT(TBCCTL2);                           /* Timer B Capture/Compare Control 2 */
1303 
SFR_16BIT(TBCCTL3);                           /* Timer B Capture/Compare Control 3 */
1304 
SFR_16BIT(TBCCTL4);                           /* Timer B Capture/Compare Control 4 */
1305 
SFR_16BIT(TBCCTL5);                           /* Timer B Capture/Compare Control 5 */
1306 
SFR_16BIT(TBCCTL6);                           /* Timer B Capture/Compare Control 6 */
1307 
SFR_16BIT(TBR);                               /* Timer B Counter Register */
1308 
SFR_16BIT(TBCCR0);                            /* Timer B Capture/Compare 0 */
1309 
SFR_16BIT(TBCCR1);                            /* Timer B Capture/Compare 1 */
1310 
SFR_16BIT(TBCCR2);                            /* Timer B Capture/Compare 2 */
1311 
SFR_16BIT(TBCCR3);                            /* Timer B Capture/Compare 3 */
1312 
SFR_16BIT(TBCCR4);                            /* Timer B Capture/Compare 4 */
1313 
SFR_16BIT(TBCCR5);                            /* Timer B Capture/Compare 5 */
1314 
SFR_16BIT(TBCCR6);                            /* Timer B Capture/Compare 6 */
1315 
 
1316 
/* Alternate register names - 5xx style */
1317 
#define TB0IV                  TBIV           /* Timer B Interrupt Vector Word */
1318 
#define TB0CTL                 TBCTL          /* Timer B Control */
1319 
#define TB0CCTL0               TBCCTL0        /* Timer B Capture/Compare Control 0 */
1320 
#define TB0CCTL1               TBCCTL1        /* Timer B Capture/Compare Control 1 */
1321 
#define TB0CCTL2               TBCCTL2        /* Timer B Capture/Compare Control 2 */
1322 
#define TB0CCTL3               TBCCTL3        /* Timer B Capture/Compare Control 3 */
1323 
#define TB0CCTL4               TBCCTL4        /* Timer B Capture/Compare Control 4 */
1324 
#define TB0CCTL5               TBCCTL5        /* Timer B Capture/Compare Control 5 */
1325 
#define TB0CCTL6               TBCCTL6        /* Timer B Capture/Compare Control 6 */
1326 
#define TB0R                   TBR            /* Timer B Counter Register */
1327 
#define TB0CCR0                TBCCR0         /* Timer B Capture/Compare 0 */
1328 
#define TB0CCR1                TBCCR1         /* Timer B Capture/Compare 1 */
1329 
#define TB0CCR2                TBCCR2         /* Timer B Capture/Compare 2 */
1330 
#define TB0CCR3                TBCCR3         /* Timer B Capture/Compare 3 */
1331 
#define TB0CCR4                TBCCR4         /* Timer B Capture/Compare 4 */
1332 
#define TB0CCR5                TBCCR5         /* Timer B Capture/Compare 5 */
1333 
#define TB0CCR6                TBCCR6         /* Timer B Capture/Compare 6 */
1334 
#define TB0IV_                 TBIV_          /* Timer B Interrupt Vector Word */
1335 
#define TB0CTL_                TBCTL_         /* Timer B Control */
1336 
#define TB0CCTL0_              TBCCTL0_       /* Timer B Capture/Compare Control 0 */
1337 
#define TB0CCTL1_              TBCCTL1_       /* Timer B Capture/Compare Control 1 */
1338 
#define TB0CCTL2_              TBCCTL2_       /* Timer B Capture/Compare Control 2 */
1339 
#define TB0CCTL3_              TBCCTL3_       /* Timer B Capture/Compare Control 3 */
1340 
#define TB0CCTL4_              TBCCTL4_       /* Timer B Capture/Compare Control 4 */
1341 
#define TB0CCTL5_              TBCCTL5_       /* Timer B Capture/Compare Control 5 */
1342 
#define TB0CCTL6_              TBCCTL6_       /* Timer B Capture/Compare Control 6 */
1343 
#define TB0R_                  TBR_           /* Timer B Counter Register */
1344 
#define TB0CCR0_               TBCCR0_        /* Timer B Capture/Compare 0 */
1345 
#define TB0CCR1_               TBCCR1_        /* Timer B Capture/Compare 1 */
1346 
#define TB0CCR2_               TBCCR2_        /* Timer B Capture/Compare 2 */
1347 
#define TB0CCR3_               TBCCR3_        /* Timer B Capture/Compare 3 */
1348 
#define TB0CCR4_               TBCCR4_        /* Timer B Capture/Compare 4 */
1349 
#define TB0CCR5_               TBCCR5_        /* Timer B Capture/Compare 5 */
1350 
#define TB0CCR6_               TBCCR6_        /* Timer B Capture/Compare 6 */
1351 
 
1352 
#define TBCLGRP1               (0x4000)       /* Timer B Compare latch load group 1 */
1353 
#define TBCLGRP0               (0x2000)       /* Timer B Compare latch load group 0 */
1354 
#define CNTL1                  (0x1000)       /* Counter lenght 1 */
1355 
#define CNTL0                  (0x0800)       /* Counter lenght 0 */
1356 
#define TBSSEL1                (0x0200)       /* Clock source 1 */
1357 
#define TBSSEL0                (0x0100)       /* Clock source 0 */
1358 
#define TBCLR                  (0x0004)       /* Timer B counter clear */
1359 
#define TBIE                   (0x0002)       /* Timer B interrupt enable */
1360 
#define TBIFG                  (0x0001)       /* Timer B interrupt flag */
1361 
 
1362 
#define SHR1                   (0x4000)       /* Timer B Compare latch load group 1 */
1363 
#define SHR0                   (0x2000)       /* Timer B Compare latch load group 0 */
1364 
 
1365 
#define TBSSEL_0               (0*0x0100u)    /* Clock Source: TBCLK */
1366 
#define TBSSEL_1               (1*0x0100u)    /* Clock Source: ACLK  */
1367 
#define TBSSEL_2               (2*0x0100u)    /* Clock Source: SMCLK */
1368 
#define TBSSEL_3               (3*0x0100u)    /* Clock Source: INCLK */
1369 
#define CNTL_0                 (0*0x0800u)    /* Counter lenght: 16 bit */
1370 
#define CNTL_1                 (1*0x0800u)    /* Counter lenght: 12 bit */
1371 
#define CNTL_2                 (2*0x0800u)    /* Counter lenght: 10 bit */
1372 
#define CNTL_3                 (3*0x0800u)    /* Counter lenght:  8 bit */
1373 
#define SHR_0                  (0*0x2000u)    /* Timer B Group: 0 - individually */
1374 
#define SHR_1                  (1*0x2000u)    /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
1375 
#define SHR_2                  (2*0x2000u)    /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
1376 
#define SHR_3                  (3*0x2000u)    /* Timer B Group: 3 - 1 group (all) */
1377 
#define TBCLGRP_0              (0*0x2000u)    /* Timer B Group: 0 - individually */
1378 
#define TBCLGRP_1              (1*0x2000u)    /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
1379 
#define TBCLGRP_2              (2*0x2000u)    /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
1380 
#define TBCLGRP_3              (3*0x2000u)    /* Timer B Group: 3 - 1 group (all) */
1381 
 
1382 
/* Additional Timer B Control Register bits are defined in Timer A */
1383 
#define CLLD1                  (0x0400)       /* Compare latch load source 1 */
1384 
#define CLLD0                  (0x0200)       /* Compare latch load source 0 */
1385 
 
1386 
#define SLSHR1                 (0x0400)       /* Compare latch load source 1 */
1387 
#define SLSHR0                 (0x0200)       /* Compare latch load source 0 */
1388 
 
1389 
#define SLSHR_0                (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
1390 
#define SLSHR_1                (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
1391 
#define SLSHR_2                (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
1392 
#define SLSHR_3                (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
1393 
 
1394 
#define CLLD_0                 (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
1395 
#define CLLD_1                 (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
1396 
#define CLLD_2                 (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
1397 
#define CLLD_3                 (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
1398 
 
1399 
/* TB7IV Definitions */
1400 
#define TBIV_NONE              (0x0000)       /* No Interrupt pending */
1401 
#define TBIV_TBCCR1            (0x0002)       /* TBCCR1_CCIFG */
1402 
#define TBIV_TBCCR2            (0x0004)       /* TBCCR2_CCIFG */
1403 
#define TBIV_TBCCR3            (0x0006)       /* TBCCR3_CCIFG */
1404 
#define TBIV_TBCCR4            (0x0008)       /* TBCCR4_CCIFG */
1405 
#define TBIV_TBCCR5            (0x000A)       /* TBCCR3_CCIFG */
1406 
#define TBIV_TBCCR6            (0x000C)       /* TBCCR4_CCIFG */
1407 
#define TBIV_TBIFG             (0x000E)       /* TBIFG */
1408 
 
1409 
/************************************************************
1410 
* USCI
1411 
************************************************************/
1412 
#define __MSP430_HAS_USCI__                   /* Definition to show that Module is available */
1413 
 
1414 
SFR_8BIT(UCA0CTL0);                           /* USCI A0 Control Register 0 */
1415 
SFR_8BIT(UCA0CTL1);                           /* USCI A0 Control Register 1 */
1416 
SFR_8BIT(UCA0BR0);                            /* USCI A0 Baud Rate 0 */
1417 
SFR_8BIT(UCA0BR1);                            /* USCI A0 Baud Rate 1 */
1418 
SFR_8BIT(UCA0MCTL);                           /* USCI A0 Modulation Control */
1419 
SFR_8BIT(UCA0STAT);                           /* USCI A0 Status Register */
1420 
SFR_8BIT(UCA0RXBUF);                          /* USCI A0 Receive Buffer */
1421 
SFR_8BIT(UCA0TXBUF);                          /* USCI A0 Transmit Buffer */
1422 
SFR_8BIT(UCA0ABCTL);                          /* USCI A0 LIN Control */
1423 
SFR_8BIT(UCA0IRTCTL);                         /* USCI A0 IrDA Transmit Control */
1424 
SFR_8BIT(UCA0IRRCTL);                         /* USCI A0 IrDA Receive Control */
1425 
 
1426 
 
1427 
 
1428 
SFR_8BIT(UCB0CTL0);                           /* USCI B0 Control Register 0 */
1429 
SFR_8BIT(UCB0CTL1);                           /* USCI B0 Control Register 1 */
1430 
SFR_8BIT(UCB0BR0);                            /* USCI B0 Baud Rate 0 */
1431 
SFR_8BIT(UCB0BR1);                            /* USCI B0 Baud Rate 1 */
1432 
SFR_8BIT(UCB0I2CIE);                          /* USCI B0 I2C Interrupt Enable Register */
1433 
SFR_8BIT(UCB0STAT);                           /* USCI B0 Status Register */
1434 
SFR_8BIT(UCB0RXBUF);                          /* USCI B0 Receive Buffer */
1435 
SFR_8BIT(UCB0TXBUF);                          /* USCI B0 Transmit Buffer */
1436 
SFR_16BIT(UCB0I2COA);                         /* USCI B0 I2C Own Address */
1437 
SFR_16BIT(UCB0I2CSA);                         /* USCI B0 I2C Slave Address */
1438 
 
1439 
// UART-Mode Bits
1440 
#define UCPEN                  (0x80)         /* Async. Mode: Parity enable */
1441 
#define UCPAR                  (0x40)         /* Async. Mode: Parity     0:odd / 1:even */
1442 
#define UCMSB                  (0x20)         /* Async. Mode: MSB first  0:LSB / 1:MSB */
1443 
#define UC7BIT                 (0x10)         /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
1444 
#define UCSPB                  (0x08)         /* Async. Mode: Stop Bits  0:one / 1: two */
1445 
#define UCMODE1                (0x04)         /* Async. Mode: USCI Mode 1 */
1446 
#define UCMODE0                (0x02)         /* Async. Mode: USCI Mode 0 */
1447 
#define UCSYNC                 (0x01)         /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
1448 
 
1449 
// SPI-Mode Bits
1450 
#define UCCKPH                 (0x80)         /* Sync. Mode: Clock Phase */
1451 
#define UCCKPL                 (0x40)         /* Sync. Mode: Clock Polarity */
1452 
#define UCMST                  (0x08)         /* Sync. Mode: Master Select */
1453 
 
1454 
// I2C-Mode Bits
1455 
#define UCA10                  (0x80)         /* 10-bit Address Mode */
1456 
#define UCSLA10                (0x40)         /* 10-bit Slave Address Mode */
1457 
#define UCMM                   (0x20)         /* Multi-Master Environment */
1458 
//#define res               (0x10)    /* reserved */
1459 
#define UCMODE_0               (0x00)         /* Sync. Mode: USCI Mode: 0 */
1460 
#define UCMODE_1               (0x02)         /* Sync. Mode: USCI Mode: 1 */
1461 
#define UCMODE_2               (0x04)         /* Sync. Mode: USCI Mode: 2 */
1462 
#define UCMODE_3               (0x06)         /* Sync. Mode: USCI Mode: 3 */
1463 
 
1464 
// UART-Mode Bits
1465 
#define UCSSEL1                (0x80)         /* USCI 0 Clock Source Select 1 */
1466 
#define UCSSEL0                (0x40)         /* USCI 0 Clock Source Select 0 */
1467 
#define UCRXEIE                (0x20)         /* RX Error interrupt enable */
1468 
#define UCBRKIE                (0x10)         /* Break interrupt enable */
1469 
#define UCDORM                 (0x08)         /* Dormant (Sleep) Mode */
1470 
#define UCTXADDR               (0x04)         /* Send next Data as Address */
1471 
#define UCTXBRK                (0x02)         /* Send next Data as Break */
1472 
#define UCSWRST                (0x01)         /* USCI Software Reset */
1473 
 
1474 
// SPI-Mode Bits
1475 
//#define res               (0x20)    /* reserved */
1476 
//#define res               (0x10)    /* reserved */
1477 
//#define res               (0x08)    /* reserved */
1478 
//#define res               (0x04)    /* reserved */
1479 
//#define res               (0x02)    /* reserved */
1480 
 
1481 
// I2C-Mode Bits
1482 
//#define res               (0x20)    /* reserved */
1483 
#define UCTR                   (0x10)         /* Transmit/Receive Select/Flag */
1484 
#define UCTXNACK               (0x08)         /* Transmit NACK */
1485 
#define UCTXSTP                (0x04)         /* Transmit STOP */
1486 
#define UCTXSTT                (0x02)         /* Transmit START */
1487 
#define UCSSEL_0               (0x00)         /* USCI 0 Clock Source: 0 */
1488 
#define UCSSEL_1               (0x40)         /* USCI 0 Clock Source: 1 */
1489 
#define UCSSEL_2               (0x80)         /* USCI 0 Clock Source: 2 */
1490 
#define UCSSEL_3               (0xC0)         /* USCI 0 Clock Source: 3 */
1491 
 
1492 
#define UCBRF3                 (0x80)         /* USCI First Stage Modulation Select 3 */
1493 
#define UCBRF2                 (0x40)         /* USCI First Stage Modulation Select 2 */
1494 
#define UCBRF1                 (0x20)         /* USCI First Stage Modulation Select 1 */
1495 
#define UCBRF0                 (0x10)         /* USCI First Stage Modulation Select 0 */
1496 
#define UCBRS2                 (0x08)         /* USCI Second Stage Modulation Select 2 */
1497 
#define UCBRS1                 (0x04)         /* USCI Second Stage Modulation Select 1 */
1498 
#define UCBRS0                 (0x02)         /* USCI Second Stage Modulation Select 0 */
1499 
#define UCOS16                 (0x01)         /* USCI 16-times Oversampling enable */
1500 
 
1501 
#define UCBRF_0                (0x00)         /* USCI First Stage Modulation: 0 */
1502 
#define UCBRF_1                (0x10)         /* USCI First Stage Modulation: 1 */
1503 
#define UCBRF_2                (0x20)         /* USCI First Stage Modulation: 2 */
1504 
#define UCBRF_3                (0x30)         /* USCI First Stage Modulation: 3 */
1505 
#define UCBRF_4                (0x40)         /* USCI First Stage Modulation: 4 */
1506 
#define UCBRF_5                (0x50)         /* USCI First Stage Modulation: 5 */
1507 
#define UCBRF_6                (0x60)         /* USCI First Stage Modulation: 6 */
1508 
#define UCBRF_7                (0x70)         /* USCI First Stage Modulation: 7 */
1509 
#define UCBRF_8                (0x80)         /* USCI First Stage Modulation: 8 */
1510 
#define UCBRF_9                (0x90)         /* USCI First Stage Modulation: 9 */
1511 
#define UCBRF_10               (0xA0)         /* USCI First Stage Modulation: A */
1512 
#define UCBRF_11               (0xB0)         /* USCI First Stage Modulation: B */
1513 
#define UCBRF_12               (0xC0)         /* USCI First Stage Modulation: C */
1514 
#define UCBRF_13               (0xD0)         /* USCI First Stage Modulation: D */
1515 
#define UCBRF_14               (0xE0)         /* USCI First Stage Modulation: E */
1516 
#define UCBRF_15               (0xF0)         /* USCI First Stage Modulation: F */
1517 
 
1518 
#define UCBRS_0                (0x00)         /* USCI Second Stage Modulation: 0 */
1519 
#define UCBRS_1                (0x02)         /* USCI Second Stage Modulation: 1 */
1520 
#define UCBRS_2                (0x04)         /* USCI Second Stage Modulation: 2 */
1521 
#define UCBRS_3                (0x06)         /* USCI Second Stage Modulation: 3 */
1522 
#define UCBRS_4                (0x08)         /* USCI Second Stage Modulation: 4 */
1523 
#define UCBRS_5                (0x0A)         /* USCI Second Stage Modulation: 5 */
1524 
#define UCBRS_6                (0x0C)         /* USCI Second Stage Modulation: 6 */
1525 
#define UCBRS_7                (0x0E)         /* USCI Second Stage Modulation: 7 */
1526 
 
1527 
#define UCLISTEN               (0x80)         /* USCI Listen mode */
1528 
#define UCFE                   (0x40)         /* USCI Frame Error Flag */
1529 
#define UCOE                   (0x20)         /* USCI Overrun Error Flag */
1530 
#define UCPE                   (0x10)         /* USCI Parity Error Flag */
1531 
#define UCBRK                  (0x08)         /* USCI Break received */
1532 
#define UCRXERR                (0x04)         /* USCI RX Error Flag */
1533 
#define UCADDR                 (0x02)         /* USCI Address received Flag */
1534 
#define UCBUSY                 (0x01)         /* USCI Busy Flag */
1535 
#define UCIDLE                 (0x02)         /* USCI Idle line detected Flag */
1536 
 
1537 
//#define res               (0x80)    /* reserved */
1538 
//#define res               (0x40)    /* reserved */
1539 
//#define res               (0x20)    /* reserved */
1540 
//#define res               (0x10)    /* reserved */
1541 
#define UCNACKIE               (0x08)         /* NACK Condition interrupt enable */
1542 
#define UCSTPIE                (0x04)         /* STOP Condition interrupt enable */
1543 
#define UCSTTIE                (0x02)         /* START Condition interrupt enable */
1544 
#define UCALIE                 (0x01)         /* Arbitration Lost interrupt enable */
1545 
 
1546 
#define UCSCLLOW               (0x40)         /* SCL low */
1547 
#define UCGC                   (0x20)         /* General Call address received Flag */
1548 
#define UCBBUSY                (0x10)         /* Bus Busy Flag */
1549 
#define UCNACKIFG              (0x08)         /* NAK Condition interrupt Flag */
1550 
#define UCSTPIFG               (0x04)         /* STOP Condition interrupt Flag */
1551 
#define UCSTTIFG               (0x02)         /* START Condition interrupt Flag */
1552 
#define UCALIFG                (0x01)         /* Arbitration Lost interrupt Flag */
1553 
 
1554 
#define UCIRTXPL5              (0x80)         /* IRDA Transmit Pulse Length 5 */
1555 
#define UCIRTXPL4              (0x40)         /* IRDA Transmit Pulse Length 4 */
1556 
#define UCIRTXPL3              (0x20)         /* IRDA Transmit Pulse Length 3 */
1557 
#define UCIRTXPL2              (0x10)         /* IRDA Transmit Pulse Length 2 */
1558 
#define UCIRTXPL1              (0x08)         /* IRDA Transmit Pulse Length 1 */
1559 
#define UCIRTXPL0              (0x04)         /* IRDA Transmit Pulse Length 0 */
1560 
#define UCIRTXCLK              (0x02)         /* IRDA Transmit Pulse Clock Select */
1561 
#define UCIREN                 (0x01)         /* IRDA Encoder/Decoder enable */
1562 
 
1563 
#define UCIRRXFL5              (0x80)         /* IRDA Receive Filter Length 5 */
1564 
#define UCIRRXFL4              (0x40)         /* IRDA Receive Filter Length 4 */
1565 
#define UCIRRXFL3              (0x20)         /* IRDA Receive Filter Length 3 */
1566 
#define UCIRRXFL2              (0x10)         /* IRDA Receive Filter Length 2 */
1567 
#define UCIRRXFL1              (0x08)         /* IRDA Receive Filter Length 1 */
1568 
#define UCIRRXFL0              (0x04)         /* IRDA Receive Filter Length 0 */
1569 
#define UCIRRXPL               (0x02)         /* IRDA Receive Input Polarity */
1570 
#define UCIRRXFE               (0x01)         /* IRDA Receive Filter enable */
1571 
 
1572 
//#define res               (0x80)    /* reserved */
1573 
//#define res               (0x40)    /* reserved */
1574 
#define UCDELIM1               (0x20)         /* Break Sync Delimiter 1 */
1575 
#define UCDELIM0               (0x10)         /* Break Sync Delimiter 0 */
1576 
#define UCSTOE                 (0x08)         /* Sync-Field Timeout error */
1577 
#define UCBTOE                 (0x04)         /* Break Timeout error */
1578 
//#define res               (0x02)    /* reserved */
1579 
#define UCABDEN                (0x01)         /* Auto Baud Rate detect enable */
1580 
 
1581 
#define UCGCEN                 (0x8000)       /* I2C General Call enable */
1582 
#define UCOA9                  (0x0200)       /* I2C Own Address 9 */
1583 
#define UCOA8                  (0x0100)       /* I2C Own Address 8 */
1584 
#define UCOA7                  (0x0080)       /* I2C Own Address 7 */
1585 
#define UCOA6                  (0x0040)       /* I2C Own Address 6 */
1586 
#define UCOA5                  (0x0020)       /* I2C Own Address 5 */
1587 
#define UCOA4                  (0x0010)       /* I2C Own Address 4 */
1588 
#define UCOA3                  (0x0008)       /* I2C Own Address 3 */
1589 
#define UCOA2                  (0x0004)       /* I2C Own Address 2 */
1590 
#define UCOA1                  (0x0002)       /* I2C Own Address 1 */
1591 
#define UCOA0                  (0x0001)       /* I2C Own Address 0 */
1592 
 
1593 
#define UCSA9                  (0x0200)       /* I2C Slave Address 9 */
1594 
#define UCSA8                  (0x0100)       /* I2C Slave Address 8 */
1595 
#define UCSA7                  (0x0080)       /* I2C Slave Address 7 */
1596 
#define UCSA6                  (0x0040)       /* I2C Slave Address 6 */
1597 
#define UCSA5                  (0x0020)       /* I2C Slave Address 5 */
1598 
#define UCSA4                  (0x0010)       /* I2C Slave Address 4 */
1599 
#define UCSA3                  (0x0008)       /* I2C Slave Address 3 */
1600 
#define UCSA2                  (0x0004)       /* I2C Slave Address 2 */
1601 
#define UCSA1                  (0x0002)       /* I2C Slave Address 1 */
1602 
#define UCSA0                  (0x0001)       /* I2C Slave Address 0 */
1603 
 
1604 
/************************************************************
1605 
* USART
1606 
************************************************************/
1607 
 
1608 
/* UxCTL */
1609 
#define PENA                   (0x80)         /* Parity enable */
1610 
#define PEV                    (0x40)         /* Parity 0:odd / 1:even */
1611 
#define SPB                    (0x20)         /* Stop Bits 0:one / 1: two */
1612 
#define CHAR                   (0x10)         /* Data 0:7-bits / 1:8-bits */
1613 
#define LISTEN                 (0x08)         /* Listen mode */
1614 
#define SYNC                   (0x04)         /* UART / SPI mode */
1615 
#define MM                     (0x02)         /* Master Mode off/on */
1616 
#define SWRST                  (0x01)         /* USART Software Reset */
1617 
 
1618 
/* UxTCTL */
1619 
#define CKPH                   (0x80)         /* SPI: Clock Phase */
1620 
#define CKPL                   (0x40)         /* Clock Polarity */
1621 
#define SSEL1                  (0x20)         /* Clock Source Select 1 */
1622 
#define SSEL0                  (0x10)         /* Clock Source Select 0 */
1623 
#define URXSE                  (0x08)         /* Receive Start edge select */
1624 
#define TXWAKE                 (0x04)         /* TX Wake up mode */
1625 
#define STC                    (0x02)         /* SPI: STC enable 0:on / 1:off */
1626 
#define TXEPT                  (0x01)         /* TX Buffer empty */
1627 
 
1628 
/* UxRCTL */
1629 
#define FE                     (0x80)         /* Frame Error */
1630 
#define PE                     (0x40)         /* Parity Error */
1631 
#define OE                     (0x20)         /* Overrun Error */
1632 
#define BRK                    (0x10)         /* Break detected */
1633 
#define URXEIE                 (0x08)         /* RX Error interrupt enable */
1634 
#define URXWIE                 (0x04)         /* RX Wake up interrupt enable */
1635 
#define RXWAKE                 (0x02)         /* RX Wake up detect */
1636 
#define RXERR                  (0x01)         /* RX Error Error */
1637 
 
1638 
/************************************************************
1639 
* USART 1
1640 
************************************************************/
1641 
#define __MSP430_HAS_UART1__                  /* Definition to show that Module is available */
1642 
 
1643 
SFR_8BIT(U1CTL);                              /* USART 1 Control */
1644 
SFR_8BIT(U1TCTL);                             /* USART 1 Transmit Control */
1645 
SFR_8BIT(U1RCTL);                             /* USART 1 Receive Control */
1646 
SFR_8BIT(U1MCTL);                             /* USART 1 Modulation Control */
1647 
SFR_8BIT(U1BR0);                              /* USART 1 Baud Rate 0 */
1648 
SFR_8BIT(U1BR1);                              /* USART 1 Baud Rate 1 */
1649 
SFR_8BIT(U1RXBUF);                            /* USART 1 Receive Buffer */
1650 
SFR_8BIT(U1TXBUF);                            /* USART 1 Transmit Buffer */
1651 
 
1652 
/* Alternate register names */
1653 
 
1654 
#define UCTL1                  U1CTL          /* USART 1 Control */
1655 
#define UTCTL1                 U1TCTL         /* USART 1 Transmit Control */
1656 
#define URCTL1                 U1RCTL         /* USART 1 Receive Control */
1657 
#define UMCTL1                 U1MCTL         /* USART 1 Modulation Control */
1658 
#define UBR01                  U1BR0          /* USART 1 Baud Rate 0 */
1659 
#define UBR11                  U1BR1          /* USART 1 Baud Rate 1 */
1660 
#define RXBUF1                 U1RXBUF        /* USART 1 Receive Buffer */
1661 
#define TXBUF1                 U1TXBUF        /* USART 1 Transmit Buffer */
1662 
#define UCTL1_                 U1CTL_         /* USART 1 Control */
1663 
#define UTCTL1_                U1TCTL_        /* USART 1 Transmit Control */
1664 
#define URCTL1_                U1RCTL_        /* USART 1 Receive Control */
1665 
#define UMCTL1_                U1MCTL_        /* USART 1 Modulation Control */
1666 
#define UBR01_                 U1BR0_         /* USART 1 Baud Rate 0 */
1667 
#define UBR11_                 U1BR1_         /* USART 1 Baud Rate 1 */
1668 
#define RXBUF1_                U1RXBUF_       /* USART 1 Receive Buffer */
1669 
#define TXBUF1_                U1TXBUF_       /* USART 1 Transmit Buffer */
1670 
#define UCTL_1                 U1CTL          /* USART 1 Control */
1671 
#define UTCTL_1                U1TCTL         /* USART 1 Transmit Control */
1672 
#define URCTL_1                U1RCTL         /* USART 1 Receive Control */
1673 
#define UMCTL_1                U1MCTL         /* USART 1 Modulation Control */
1674 
#define UBR0_1                 U1BR0          /* USART 1 Baud Rate 0 */
1675 
#define UBR1_1                 U1BR1          /* USART 1 Baud Rate 1 */
1676 
#define RXBUF_1                U1RXBUF        /* USART 1 Receive Buffer */
1677 
#define TXBUF_1                U1TXBUF        /* USART 1 Transmit Buffer */
1678 
#define UCTL_1_                U1CTL_         /* USART 1 Control */
1679 
#define UTCTL_1_               U1TCTL_        /* USART 1 Transmit Control */
1680 
#define URCTL_1_               U1RCTL_        /* USART 1 Receive Control */
1681 
#define UMCTL_1_               U1MCTL_        /* USART 1 Modulation Control */
1682 
#define UBR0_1_                U1BR0_         /* USART 1 Baud Rate 0 */
1683 
#define UBR1_1_                U1BR1_         /* USART 1 Baud Rate 1 */
1684 
#define RXBUF_1_               U1RXBUF_       /* USART 1 Receive Buffer */
1685 
#define TXBUF_1_               U1TXBUF_       /* USART 1 Transmit Buffer */
1686 
 
1687 
/************************************************************
1688 
* WATCHDOG TIMER
1689 
************************************************************/
1690 
#define __MSP430_HAS_WDT__                    /* Definition to show that Module is available */
1691 
 
1692 
SFR_16BIT(WDTCTL);                            /* Watchdog Timer Control */
1693 
/* The bit names have been prefixed with "WDT" */
1694 
#define WDTIS0                 (0x0001)
1695 
#define WDTIS1                 (0x0002)
1696 
#define WDTSSEL                (0x0004)
1697 
#define WDTCNTCL               (0x0008)
1698 
#define WDTTMSEL               (0x0010)
1699 
#define WDTNMI                 (0x0020)
1700 
#define WDTNMIES               (0x0040)
1701 
#define WDTHOLD                (0x0080)
1702 
 
1703 
#define WDTPW                  (0x5A00)
1704 
 
1705 
/* WDT-interval times [1ms] coded with Bits 0-2 */
1706 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
1707 
#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL)                         /* 32ms interval (default) */
1708 
#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0)                  /* 8ms     " */
1709 
#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1)                  /* 0.5ms   " */
1710 
#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0)           /* 0.064ms " */
1711 
/* WDT is clocked by fACLK (assumed 32KHz) */
1712 
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)                 /* 1000ms  " */
1713 
#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0)          /* 250ms   " */
1714 
#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1)          /* 16ms    " */
1715 
#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)   /* 1.9ms   " */
1716 
/* Watchdog mode -> reset after expired time */
1717 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
1718 
#define WDT_MRST_32         (WDTPW+WDTCNTCL)                                  /* 32ms interval (default) */
1719 
#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS0)                           /* 8ms     " */
1720 
#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS1)                           /* 0.5ms   " */
1721 
#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS1+WDTIS0)                    /* 0.064ms " */
1722 
/* WDT is clocked by fACLK (assumed 32KHz) */
1723 
#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL)                          /* 1000ms  " */
1724 
#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0)                   /* 250ms   " */
1725 
#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1)                   /* 16ms    " */
1726 
#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)            /* 1.9ms   " */
1727 
 
1728 
/* INTERRUPT CONTROL */
1729 
/* These two bits are defined in the Special Function Registers */
1730 
/* #define WDTIE               0x01 */
1731 
/* #define WDTIFG              0x01 */
1732 
 
1733 
/************************************************************
1734 
* Interrupt Vectors (offset from 0xFFC0)
1735 
************************************************************/
1736 
 
1737 
#pragma diag_suppress 1107
1738 
#define VECTOR_NAME(name)             name##_ptr
1739 
#define EMIT_PRAGMA(x)                _Pragma(#x)
1740 
#define CREATE_VECTOR(name)           void * const VECTOR_NAME(name) = (void *)(long)&name
1741 
#define PLACE_VECTOR(vector,section)  EMIT_PRAGMA(DATA_SECTION(vector,section))
1742 
#define PLACE_INTERRUPT(func)         EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
1743 
#define ISR_VECTOR(func,offset)       CREATE_VECTOR(func); \
1744 
                                      PLACE_VECTOR(VECTOR_NAME(func), offset) \
1745 
                                      PLACE_INTERRUPT(func)
1746 
 
1747 
 
1748 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1749 
#define DAC12_VECTOR            ".int14"                    /* 0xFFDC DAC 12 */
1750 
#else
1751 
#define DAC12_VECTOR            (14 * 1u)                    /* 0xFFDC DAC 12 */
1752 
/*#define DAC12_ISR(func)         ISR_VECTOR(func, ".int14")  */ /* 0xFFDC DAC 12 */ /* CCE V2 Style */
1753 
#endif
1754 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1755 
#define DMA_VECTOR              ".int15"                    /* 0xFFDE DMA */
1756 
#else
1757 
#define DMA_VECTOR              (15 * 1u)                    /* 0xFFDE DMA */
1758 
/*#define DMA_ISR(func)           ISR_VECTOR(func, ".int15")  */ /* 0xFFDE DMA */ /* CCE V2 Style */
1759 
#endif
1760 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1761 
#define BASICTIMER_VECTOR       ".int16"                    /* 0xFFE0 Basic Timer / RTC */
1762 
#else
1763 
#define BASICTIMER_VECTOR       (16 * 1u)                    /* 0xFFE0 Basic Timer / RTC */
1764 
/*#define BASICTIMER_ISR(func)    ISR_VECTOR(func, ".int16")  */ /* 0xFFE0 Basic Timer / RTC */ /* CCE V2 Style */
1765 
#endif
1766 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1767 
#define PORT2_VECTOR            ".int17"                    /* 0xFFE2 Port 2 */
1768 
#else
1769 
#define PORT2_VECTOR            (17 * 1u)                    /* 0xFFE2 Port 2 */
1770 
/*#define PORT2_ISR(func)         ISR_VECTOR(func, ".int17")  */ /* 0xFFE2 Port 2 */ /* CCE V2 Style */
1771 
#endif
1772 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1773 
#define USART1TX_VECTOR         ".int18"                    /* 0xFFE4 USART 1 Transmit */
1774 
#else
1775 
#define USART1TX_VECTOR         (18 * 1u)                    /* 0xFFE4 USART 1 Transmit */
1776 
/*#define USART1TX_ISR(func)      ISR_VECTOR(func, ".int18")  */ /* 0xFFE4 USART 1 Transmit */ /* CCE V2 Style */
1777 
#endif
1778 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1779 
#define USART1RX_VECTOR         ".int19"                    /* 0xFFE6 USART 1 Receive */
1780 
#else
1781 
#define USART1RX_VECTOR         (19 * 1u)                    /* 0xFFE6 USART 1 Receive */
1782 
/*#define USART1RX_ISR(func)      ISR_VECTOR(func, ".int19")  */ /* 0xFFE6 USART 1 Receive */ /* CCE V2 Style */
1783 
#endif
1784 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1785 
#define PORT1_VECTOR            ".int20"                    /* 0xFFE8 Port 1 */
1786 
#else
1787 
#define PORT1_VECTOR            (20 * 1u)                    /* 0xFFE8 Port 1 */
1788 
/*#define PORT1_ISR(func)         ISR_VECTOR(func, ".int20")  */ /* 0xFFE8 Port 1 */ /* CCE V2 Style */
1789 
#endif
1790 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1791 
#define TIMERA1_VECTOR          ".int21"                    /* 0xFFEA Timer A CC1-2, TA */
1792 
#else
1793 
#define TIMERA1_VECTOR          (21 * 1u)                    /* 0xFFEA Timer A CC1-2, TA */
1794 
/*#define TIMERA1_ISR(func)       ISR_VECTOR(func, ".int21")  */ /* 0xFFEA Timer A CC1-2, TA */ /* CCE V2 Style */
1795 
#endif
1796 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1797 
#define TIMERA0_VECTOR          ".int22"                    /* 0xFFEC Timer A CC0 */
1798 
#else
1799 
#define TIMERA0_VECTOR          (22 * 1u)                    /* 0xFFEC Timer A CC0 */
1800 
/*#define TIMERA0_ISR(func)       ISR_VECTOR(func, ".int22")  */ /* 0xFFEC Timer A CC0 */ /* CCE V2 Style */
1801 
#endif
1802 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1803 
#define ADC12_VECTOR            ".int23"                    /* 0xFFEE ADC */
1804 
#else
1805 
#define ADC12_VECTOR            (23 * 1u)                    /* 0xFFEE ADC */
1806 
/*#define ADC12_ISR(func)         ISR_VECTOR(func, ".int23")  */ /* 0xFFEE ADC */ /* CCE V2 Style */
1807 
#endif
1808 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1809 
#define USCIAB0TX_VECTOR        ".int24"                    /* 0xFFF0 USCI A0/B0 Transmit */
1810 
#else
1811 
#define USCIAB0TX_VECTOR        (24 * 1u)                    /* 0xFFF0 USCI A0/B0 Transmit */
1812 
/*#define USCIAB0TX_ISR(func)     ISR_VECTOR(func, ".int24")  */ /* 0xFFF0 USCI A0/B0 Transmit */ /* CCE V2 Style */
1813 
#endif
1814 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1815 
#define USCIAB0RX_VECTOR        ".int25"                    /* 0xFFF2 USCI A0/B0 Receive */
1816 
#else
1817 
#define USCIAB0RX_VECTOR        (25 * 1u)                    /* 0xFFF2 USCI A0/B0 Receive */
1818 
/*#define USCIAB0RX_ISR(func)     ISR_VECTOR(func, ".int25")  */ /* 0xFFF2 USCI A0/B0 Receive */ /* CCE V2 Style */
1819 
#endif
1820 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1821 
#define WDT_VECTOR              ".int26"                    /* 0xFFF4 Watchdog Timer */
1822 
#else
1823 
#define WDT_VECTOR              (26 * 1u)                    /* 0xFFF4 Watchdog Timer */
1824 
/*#define WDT_ISR(func)           ISR_VECTOR(func, ".int26")  */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
1825 
#endif
1826 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1827 
#define COMPARATORA_VECTOR      ".int27"                    /* 0xFFF6 Comparator A */
1828 
#else
1829 
#define COMPARATORA_VECTOR      (27 * 1u)                    /* 0xFFF6 Comparator A */
1830 
/*#define COMPARATORA_ISR(func)   ISR_VECTOR(func, ".int27")  */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */
1831 
#endif
1832 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1833 
#define TIMERB1_VECTOR          ".int28"                    /* 0xFFF8 Timer B CC1-2, TB */
1834 
#else
1835 
#define TIMERB1_VECTOR          (28 * 1u)                    /* 0xFFF8 Timer B CC1-2, TB */
1836 
/*#define TIMERB1_ISR(func)       ISR_VECTOR(func, ".int28")  */ /* 0xFFF8 Timer B CC1-2, TB */ /* CCE V2 Style */
1837 
#endif
1838 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1839 
#define TIMERB0_VECTOR          ".int29"                    /* 0xFFFA Timer B CC0 */
1840 
#else
1841 
#define TIMERB0_VECTOR          (29 * 1u)                    /* 0xFFFA Timer B CC0 */
1842 
/*#define TIMERB0_ISR(func)       ISR_VECTOR(func, ".int29")  */ /* 0xFFFA Timer B CC0 */ /* CCE V2 Style */
1843 
#endif
1844 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1845 
#define NMI_VECTOR              ".int30"                    /* 0xFFFC Non-maskable */
1846 
#else
1847 
#define NMI_VECTOR              (30 * 1u)                    /* 0xFFFC Non-maskable */
1848 
/*#define NMI_ISR(func)           ISR_VECTOR(func, ".int30")  */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
1849 
#endif
1850 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1851 
#define RESET_VECTOR            ".reset"                    /* 0xFFFE Reset [Highest Priority] */
1852 
#else
1853 
#define RESET_VECTOR            (31 * 1u)                    /* 0xFFFE Reset [Highest Priority] */
1854 
/*#define RESET_ISR(func)         ISR_VECTOR(func, ".int31")  */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
1855 
#endif
1856 
 
1857 
/************************************************************
1858 
* End of Modules
1859 
************************************************************/
1860 
 
1861 
#ifdef __cplusplus
1862 
}
1863 
#endif /* extern "C" */
1864 
 
1865 
#endif /* #ifndef __msp430xG46x */
1866