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/******************************************************************************/
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/* Legacy Header File */
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/* Not recommended for use in new projects. */
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/* Please use the msp430.h file or the device specific header file */
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/******************************************************************************/
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* msp430xG43x device.
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*
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* Texas Instruments, Version 2.5
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*
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* Rev. 2.0, Fixed some address of the OPAMP registers
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* Rev. 2.1, Alignment of defintions in Users Guide and of version numbers
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* Rev. 2.2, Fixed some defintions of the OPAMP registers
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* Rev. 2.21, Added DAC12OPS
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* Rev. 2.22, Removed definition of LCDLOWR (not available at 4xx devices)
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* Rev. 2.3, Fixed type in ADC12 bit definitions (replaced ADC10 with ADC12)
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* Added DMA request definitions
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* Rev. 2.3, Changed definition in OPAMP section to accord Users Guide
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* Rev. 2.1, Removed definitions for DMA channel 1 + 2
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* Rev. 2.2, Removed unused def of TASSEL2 / TBSSEL2
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* Rev. 2.3, Added VLD bits in SVS module
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* Rev. 2.4, Removed definitions for BTRESET
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* Rev. 2.5, added definitions for Interrupt Vectors xxIV
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*
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********************************************************************/
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#ifndef __msp430xG43x
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#define __msp430xG43x
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
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************************************************************/
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SFR_8BIT(IE1); /* Interrupt Enable 1 */
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#define U0IE IE1 /* UART0 Interrupt Enable Register */
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#define WDTIE (0x01)
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#define OFIE (0x02)
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#define NMIIE (0x10)
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#define ACCVIE (0x20)
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#define URXIE0 (0x40)
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#define UTXIE0 (0x80)
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SFR_8BIT(IFG1); /* Interrupt Flag 1 */
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#define U0IFG IFG1 /* UART0 Interrupt Flag Register */
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#define WDTIFG (0x01)
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#define OFIFG (0x02)
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#define NMIIFG (0x10)
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#define URXIFG0 (0x40)
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#define UTXIFG0 (0x80)
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SFR_8BIT(ME1); /* Module Enable 1 */
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#define U0ME ME1 /* UART0 Module Enable Register */
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#define URXE0 (0x40)
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#define UTXE0 (0x80)
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#define USPIE0 (0x40)
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SFR_8BIT(IE2); /* Interrupt Enable 2 */
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#define BTIE (0x80)
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SFR_8BIT(IFG2); /* Interrupt Flag 2 */
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#define BTIFG (0x80)
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/************************************************************
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* WATCHDOG TIMER
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************************************************************/
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#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
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SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
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/* The bit names have been prefixed with "WDT" */
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#define WDTIS0 (0x0001)
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#define WDTIS1 (0x0002)
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#define WDTSSEL (0x0004)
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#define WDTCNTCL (0x0008)
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#define WDTTMSEL (0x0010)
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#define WDTNMI (0x0020)
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#define WDTNMIES (0x0040)
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#define WDTHOLD (0x0080)
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#define WDTPW (0x5A00)
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/* WDT-interval times [1ms] coded with Bits 0-2 */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* Watchdog mode -> reset after expired time */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* INTERRUPT CONTROL */
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/* These two bits are defined in the Special Function Registers */
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/* #define WDTIE 0x01 */
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/* #define WDTIFG 0x01 */
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/************************************************************
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* DIGITAL I/O Port1/2
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************************************************************/
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#define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */
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#define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */
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SFR_8BIT(P1IN); /* Port 1 Input */
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SFR_8BIT(P1OUT); /* Port 1 Output */
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SFR_8BIT(P1DIR); /* Port 1 Direction */
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SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */
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SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */
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SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */
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SFR_8BIT(P1SEL); /* Port 1 Selection */
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SFR_8BIT(P2IN); /* Port 2 Input */
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SFR_8BIT(P2OUT); /* Port 2 Output */
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SFR_8BIT(P2DIR); /* Port 2 Direction */
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SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */
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SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */
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SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */
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SFR_8BIT(P2SEL); /* Port 2 Selection */
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/************************************************************
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* DIGITAL I/O Port3/4
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************************************************************/
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#define __MSP430_HAS_PORT3__ /* Definition to show that Module is available */
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#define __MSP430_HAS_PORT4__ /* Definition to show that Module is available */
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SFR_8BIT(P3IN); /* Port 3 Input */
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SFR_8BIT(P3OUT); /* Port 3 Output */
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SFR_8BIT(P3DIR); /* Port 3 Direction */
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SFR_8BIT(P3SEL); /* Port 3 Selection */
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SFR_8BIT(P4IN); /* Port 4 Input */
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SFR_8BIT(P4OUT); /* Port 4 Output */
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SFR_8BIT(P4DIR); /* Port 4 Direction */
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SFR_8BIT(P4SEL); /* Port 4 Selection */
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/************************************************************
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* DIGITAL I/O Port5/6
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************************************************************/
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#define __MSP430_HAS_PORT5__ /* Definition to show that Module is available */
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#define __MSP430_HAS_PORT6__ /* Definition to show that Module is available */
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SFR_8BIT(P5IN); /* Port 5 Input */
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SFR_8BIT(P5OUT); /* Port 5 Output */
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SFR_8BIT(P5DIR); /* Port 5 Direction */
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SFR_8BIT(P5SEL); /* Port 5 Selection */
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SFR_8BIT(P6IN); /* Port 6 Input */
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SFR_8BIT(P6OUT); /* Port 6 Output */
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SFR_8BIT(P6DIR); /* Port 6 Direction */
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SFR_8BIT(P6SEL); /* Port 6 Selection */
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/************************************************************
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* BASIC TIMER
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************************************************************/
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#define __MSP430_HAS_BT__ /* Definition to show that Module is available */
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SFR_8BIT(BTCTL); /* Basic Timer Control */
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/* The bit names have been prefixed with "BT" */
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#define BTIP0 (0x01)
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#define BTIP1 (0x02)
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#define BTIP2 (0x04)
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#define BTFRFQ0 (0x08)
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#define BTFRFQ1 (0x10)
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#define BTDIV (0x20) /* fCLK2 = ACLK:256 */
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#define BTHOLD (0x40) /* BT1 is held if this bit is set */
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#define BTSSEL (0x80) /* fBT = fMCLK (main clock) */
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SFR_8BIT(BTCNT1); /* Basic Timer Count 1 */
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SFR_8BIT(BTCNT2); /* Basic Timer Count 2 */
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/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
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#define BT_fCLK2_ACLK (0x00)
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#define BT_fCLK2_ACLK_DIV256 (BTDIV)
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#define BT_fCLK2_MCLK (BTSSEL)
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/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
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#define BT_fCLK2_DIV2 (0x00) /* fINT = fCLK2:2 (default) */
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#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */
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#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */
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#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT = fCLK2:16 */
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#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */
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#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT = fCLK2:64 */
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#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT = fCLK2:128 */
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#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 */
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/* Frequency of LCD coded with Bits 3-4 */
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#define BT_fLCD_DIV32 (0x00) /* fLCD = fACLK:32 (default) */
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#define BT_fLCD_DIV64 (BTFRFQ0) /* fLCD = fACLK:64 */
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#define BT_fLCD_DIV128 (BTFRFQ1) /* fLCD = fACLK:128 */
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#define BT_fLCD_DIV256 (BTFRFQ1+BTFRFQ0) /* fLCD = fACLK:256 */
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/* LCD frequency values with fBT=fACLK */
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#define BT_fLCD_1K (0x00) /* fACLK:32 (default) */
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#define BT_fLCD_512 (BTFRFQ0) /* fACLK:64 */
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#define BT_fLCD_256 (BTFRFQ1) /* fACLK:128 */
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#define BT_fLCD_128 (BTFRFQ1+BTFRFQ0) /* fACLK:256 */
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/* LCD frequency values with fBT=fMCLK */
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297 |
#define BT_fLCD_31K (BTSSEL) /* fMCLK:32 */
|
|
|
298 |
#define BT_fLCD_15_5K (BTSSEL+BTFRFQ0) /* fMCLK:64 */
|
|
|
299 |
#define BT_fLCD_7_8K (BTSSEL+BTFRFQ1+BTFRFQ0) /* fMCLK:256 */
|
|
|
300 |
/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
|
|
|
301 |
/* fBT=fACLK is thought for longer interval times */
|
|
|
302 |
#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */
|
|
|
303 |
#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */
|
|
|
304 |
#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */
|
|
|
305 |
#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms " */
|
|
|
306 |
#define BT_ADLY_1 (BTIP2) /* 1ms " */
|
|
|
307 |
#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms " */
|
|
|
308 |
#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms " */
|
|
|
309 |
#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms " */
|
|
|
310 |
#define BT_ADLY_16 (BTDIV) /* 16ms " */
|
|
|
311 |
#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms " */
|
|
|
312 |
#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms " */
|
|
|
313 |
#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms " */
|
|
|
314 |
#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms " */
|
|
|
315 |
#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms " */
|
|
|
316 |
#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms " */
|
|
|
317 |
#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms " */
|
|
|
318 |
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
|
|
|
319 |
/* the timing for short intervals is more precise than ACLK */
|
|
|
320 |
/* NOTE */
|
|
|
321 |
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
|
|
|
322 |
/* Too low interval time results in interrupts too frequent for the processor to handle! */
|
|
|
323 |
#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
|
|
|
324 |
#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms " *** too short for */
|
|
|
325 |
#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms " *** interrupt */
|
|
|
326 |
#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms " *** handling */
|
|
|
327 |
#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms " */
|
|
|
328 |
#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms " */
|
|
|
329 |
#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms " */
|
|
|
330 |
#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms " */
|
|
|
331 |
|
|
|
332 |
/* Reset/Hold coded with Bits 6-7 in BT(1)CTL */
|
|
|
333 |
/* this is for BT */
|
|
|
334 |
//#define BTRESET_CNT1 (BTRESET) /* BTCNT1 is reset while BTRESET is set */
|
|
|
335 |
//#define BTRESET_CNT1_2 (BTRESET+BTDIV) /* BTCNT1 .AND. BTCNT2 are reset while ~ is set */
|
|
|
336 |
/* this is for BT1 */
|
|
|
337 |
#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
|
|
|
338 |
#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
|
|
|
339 |
|
|
|
340 |
/* INTERRUPT CONTROL BITS */
|
|
|
341 |
/* #define BTIE 0x80 */
|
|
|
342 |
/* #define BTIFG 0x80 */
|
|
|
343 |
|
|
|
344 |
/************************************************************
|
|
|
345 |
* SYSTEM CLOCK, FLL+
|
|
|
346 |
************************************************************/
|
|
|
347 |
#define __MSP430_HAS_FLLPLUS__ /* Definition to show that Module is available */
|
|
|
348 |
|
|
|
349 |
SFR_8BIT(SCFI0); /* System Clock Frequency Integrator 0 */
|
|
|
350 |
#define FN_2 (0x04) /* fDCOCLK = 1.4-12MHz*/
|
|
|
351 |
#define FN_3 (0x08) /* fDCOCLK = 2.2-17Mhz*/
|
|
|
352 |
#define FN_4 (0x10) /* fDCOCLK = 3.2-25Mhz*/
|
|
|
353 |
#define FN_8 (0x20) /* fDCOCLK = 5-40Mhz*/
|
|
|
354 |
#define FLLD0 (0x40) /* Loop Divider Bit : 0 */
|
|
|
355 |
#define FLLD1 (0x80) /* Loop Divider Bit : 1 */
|
|
|
356 |
|
|
|
357 |
#define FLLD_1 (0x00) /* Multiply Selected Loop Freq. By 1 */
|
|
|
358 |
#define FLLD_2 (0x40) /* Multiply Selected Loop Freq. By 2 */
|
|
|
359 |
#define FLLD_4 (0x80) /* Multiply Selected Loop Freq. By 4 */
|
|
|
360 |
#define FLLD_8 (0xC0) /* Multiply Selected Loop Freq. By 8 */
|
|
|
361 |
|
|
|
362 |
SFR_8BIT(SCFI1); /* System Clock Frequency Integrator 1 */
|
|
|
363 |
SFR_8BIT(SCFQCTL); /* System Clock Frequency Control */
|
|
|
364 |
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
|
|
|
365 |
/* #define SCFQ_32K 0x00 fMCLK=1*fACLK only a range from */
|
|
|
366 |
#define SCFQ_64K (0x01) /* fMCLK=2*fACLK 1+1 to 127+1 is possible */
|
|
|
367 |
#define SCFQ_128K (0x03) /* fMCLK=4*fACLK */
|
|
|
368 |
#define SCFQ_256K (0x07) /* fMCLK=8*fACLK */
|
|
|
369 |
#define SCFQ_512K (0x0F) /* fMCLK=16*fACLK */
|
|
|
370 |
#define SCFQ_1M (0x1F) /* fMCLK=32*fACLK */
|
|
|
371 |
#define SCFQ_2M (0x3F) /* fMCLK=64*fACLK */
|
|
|
372 |
#define SCFQ_4M (0x7F) /* fMCLK=128*fACLK */
|
|
|
373 |
#define SCFQ_M (0x80) /* Modulation Disable */
|
|
|
374 |
|
|
|
375 |
SFR_8BIT(FLL_CTL0); /* FLL+ Control 0 */
|
|
|
376 |
#define DCOF (0x01) /* DCO Fault Flag */
|
|
|
377 |
#define LFOF (0x02) /* Low Frequency Oscillator Fault Flag */
|
|
|
378 |
#define XT1OF (0x04) /* High Frequency Oscillator 1 Fault Flag */
|
|
|
379 |
#define XT2OF (0x08) /* High Frequency Oscillator 2 Fault Flag */
|
|
|
380 |
#define OSCCAP0 (0x10) /* XIN/XOUT Cap 0 */
|
|
|
381 |
#define OSCCAP1 (0x20) /* XIN/XOUT Cap 1 */
|
|
|
382 |
#define XTS_FLL (0x40) /* 1: Selects high-freq. oscillator */
|
|
|
383 |
#define DCOPLUS (0x80) /* DCO+ Enable */
|
|
|
384 |
|
|
|
385 |
#define XCAP0PF (0x00) /* XIN Cap = XOUT Cap = 0pf */
|
|
|
386 |
#define XCAP10PF (0x10) /* XIN Cap = XOUT Cap = 10pf */
|
|
|
387 |
#define XCAP14PF (0x20) /* XIN Cap = XOUT Cap = 14pf */
|
|
|
388 |
#define XCAP18PF (0x30) /* XIN Cap = XOUT Cap = 18pf */
|
|
|
389 |
#define OSCCAP_0 (0x00) /* XIN Cap = XOUT Cap = 0pf */
|
|
|
390 |
#define OSCCAP_1 (0x10) /* XIN Cap = XOUT Cap = 10pf */
|
|
|
391 |
#define OSCCAP_2 (0x20) /* XIN Cap = XOUT Cap = 14pf */
|
|
|
392 |
#define OSCCAP_3 (0x30) /* XIN Cap = XOUT Cap = 18pf */
|
|
|
393 |
|
|
|
394 |
SFR_8BIT(FLL_CTL1); /* FLL+ Control 1 */
|
|
|
395 |
#define FLL_DIV0 (0x01) /* FLL+ Divide Px.x/ACLK 0 */
|
|
|
396 |
#define FLL_DIV1 (0x02) /* FLL+ Divide Px.x/ACLK 1 */
|
|
|
397 |
#define SELS (0x04) /* Peripheral Module Clock Source (0: DCO, 1: XT2) */
|
|
|
398 |
#define SELM0 (0x08) /* MCLK Source Select 0 */
|
|
|
399 |
#define SELM1 (0x10) /* MCLK Source Select 1 */
|
|
|
400 |
#define XT2OFF (0x20) /* High Frequency Oscillator 2 (XT2) disable */
|
|
|
401 |
#define SMCLKOFF (0x40) /* Peripheral Module Clock (SMCLK) disable */
|
|
|
402 |
|
|
|
403 |
#define FLL_DIV_1 (0x00) /* FLL+ Divide Px.x/ACLK By 1 */
|
|
|
404 |
#define FLL_DIV_2 (0x01) /* FLL+ Divide Px.x/ACLK By 2 */
|
|
|
405 |
#define FLL_DIV_4 (0x02) /* FLL+ Divide Px.x/ACLK By 4 */
|
|
|
406 |
#define FLL_DIV_8 (0x03) /* FLL+ Divide Px.x/ACLK By 8 */
|
|
|
407 |
|
|
|
408 |
#define SELM_DCO (0x00) /* Select DCO for CPU MCLK */
|
|
|
409 |
#define SELM_XT2 (0x10) /* Select XT2 for CPU MCLK */
|
|
|
410 |
#define SELM_A (0x18) /* Select A (from LFXT1) for CPU MCLK */
|
|
|
411 |
|
|
|
412 |
/* INTERRUPT CONTROL BITS */
|
|
|
413 |
/* These two bits are defined in the Special Function Registers */
|
|
|
414 |
/* #define OFIFG 0x02 */
|
|
|
415 |
/* #define OFIE 0x02 */
|
|
|
416 |
|
|
|
417 |
/************************************************************
|
|
|
418 |
* Brown-Out, Supply Voltage Supervision (SVS)
|
|
|
419 |
************************************************************/
|
|
|
420 |
#define __MSP430_HAS_SVS__ /* Definition to show that Module is available */
|
|
|
421 |
|
|
|
422 |
SFR_8BIT(SVSCTL); /* SVS Control */
|
|
|
423 |
#define SVSFG (0x01) /* SVS Flag */
|
|
|
424 |
#define SVSOP (0x02) /* SVS output (read only) */
|
|
|
425 |
#define SVSON (0x04) /* Switches the SVS on/off */
|
|
|
426 |
#define PORON (0x08) /* Enable POR Generation if Low Voltage */
|
|
|
427 |
#define VLD0 (0x10)
|
|
|
428 |
#define VLD1 (0x20)
|
|
|
429 |
#define VLD2 (0x40)
|
|
|
430 |
#define VLD3 (0x80)
|
|
|
431 |
|
|
|
432 |
#define VLDON (0x10)
|
|
|
433 |
#define VLDOFF (0x00)
|
|
|
434 |
#define VLD_1_8V (0x10)
|
|
|
435 |
|
|
|
436 |
/************************************************************
|
|
|
437 |
* LCD
|
|
|
438 |
************************************************************/
|
|
|
439 |
#define __MSP430_HAS_LCD4__ /* Definition to show that Module is available */
|
|
|
440 |
|
|
|
441 |
SFR_8BIT(LCDCTL); /* LCD Control */
|
|
|
442 |
/* the names of the mode bits are different from the spec */
|
|
|
443 |
#define LCDON (0x01)
|
|
|
444 |
//#define LCDLOWR (0x02)
|
|
|
445 |
#define LCDSON (0x04)
|
|
|
446 |
#define LCDMX0 (0x08)
|
|
|
447 |
#define LCDMX1 (0x10)
|
|
|
448 |
#define LCDP0 (0x20)
|
|
|
449 |
#define LCDP1 (0x40)
|
|
|
450 |
#define LCDP2 (0x80)
|
|
|
451 |
/* Display modes coded with Bits 2-4 */
|
|
|
452 |
#define LCDSTATIC (LCDSON)
|
|
|
453 |
#define LCD2MUX (LCDMX0+LCDSON)
|
|
|
454 |
#define LCD3MUX (LCDMX1+LCDSON)
|
|
|
455 |
#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
|
|
|
456 |
/* Group select code with Bits 5-7 Seg.lines Dig.output */
|
|
|
457 |
#define LCDSG0 (0x00) /* --------- Port Only (default) */
|
|
|
458 |
#define LCDSG0_1 (LCDP0) /* S0 - S15 see Datasheet */
|
|
|
459 |
#define LCDSG0_2 (LCDP1) /* S0 - S19 see Datasheet */
|
|
|
460 |
#define LCDSG0_3 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */
|
|
|
461 |
#define LCDSG0_4 (LCDP2) /* S0 - S27 see Datasheet */
|
|
|
462 |
#define LCDSG0_5 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */
|
|
|
463 |
#define LCDSG0_6 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */
|
|
|
464 |
#define LCDSG0_7 (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */
|
|
|
465 |
/* NOTE: YOU CAN ONLY USE THE 'S' OR 'G' DECLARATIONS FOR A COMMAND */
|
|
|
466 |
/* MOV #LCDSG0_3+LCDOG2_7,&LCDCTL ACTUALY MEANS MOV #LCDP1,&LCDCTL! */
|
|
|
467 |
#define LCDOG1_7 (0x00) /* --------- Port Only (default) */
|
|
|
468 |
#define LCDOG2_7 (LCDP0) /* S0 - S15 see Datasheet */
|
|
|
469 |
#define LCDOG3_7 (LCDP1) /* S0 - S19 see Datasheet */
|
|
|
470 |
#define LCDOG4_7 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */
|
|
|
471 |
#define LCDOG5_7 (LCDP2) /* S0 - S27 see Datasheet */
|
|
|
472 |
#define LCDOG6_7 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */
|
|
|
473 |
#define LCDOG7 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */
|
|
|
474 |
#define LCDOGOFF (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */
|
|
|
475 |
|
|
|
476 |
#define LCDMEM_ (0x0091) /* LCD Memory */
|
|
|
477 |
#ifdef __ASM_HEADER__
|
|
|
478 |
#define LCDMEM (LCDMEM_) /* LCD Memory (for assembler) */
|
|
|
479 |
#else
|
|
|
480 |
#define LCDMEM ((char*) LCDMEM_) /* LCD Memory (for C) */
|
|
|
481 |
#endif
|
|
|
482 |
SFR_8BIT(LCDM1); /* LCD Memory 1 */
|
|
|
483 |
SFR_8BIT(LCDM2); /* LCD Memory 2 */
|
|
|
484 |
SFR_8BIT(LCDM3); /* LCD Memory 3 */
|
|
|
485 |
SFR_8BIT(LCDM4); /* LCD Memory 4 */
|
|
|
486 |
SFR_8BIT(LCDM5); /* LCD Memory 5 */
|
|
|
487 |
SFR_8BIT(LCDM6); /* LCD Memory 6 */
|
|
|
488 |
SFR_8BIT(LCDM7); /* LCD Memory 7 */
|
|
|
489 |
SFR_8BIT(LCDM8); /* LCD Memory 8 */
|
|
|
490 |
SFR_8BIT(LCDM9); /* LCD Memory 9 */
|
|
|
491 |
SFR_8BIT(LCDM10); /* LCD Memory 10 */
|
|
|
492 |
SFR_8BIT(LCDM11); /* LCD Memory 11 */
|
|
|
493 |
SFR_8BIT(LCDM12); /* LCD Memory 12 */
|
|
|
494 |
SFR_8BIT(LCDM13); /* LCD Memory 13 */
|
|
|
495 |
SFR_8BIT(LCDM14); /* LCD Memory 14 */
|
|
|
496 |
SFR_8BIT(LCDM15); /* LCD Memory 15 */
|
|
|
497 |
SFR_8BIT(LCDM16); /* LCD Memory 16 */
|
|
|
498 |
SFR_8BIT(LCDM17); /* LCD Memory 17 */
|
|
|
499 |
SFR_8BIT(LCDM18); /* LCD Memory 18 */
|
|
|
500 |
SFR_8BIT(LCDM19); /* LCD Memory 19 */
|
|
|
501 |
SFR_8BIT(LCDM20); /* LCD Memory 20 */
|
|
|
502 |
|
|
|
503 |
#define LCDMA (LCDM10) /* LCD Memory A */
|
|
|
504 |
#define LCDMB (LCDM11) /* LCD Memory B */
|
|
|
505 |
#define LCDMC (LCDM12) /* LCD Memory C */
|
|
|
506 |
#define LCDMD (LCDM13) /* LCD Memory D */
|
|
|
507 |
#define LCDME (LCDM14) /* LCD Memory E */
|
|
|
508 |
#define LCDMF (LCDM15) /* LCD Memory F */
|
|
|
509 |
|
|
|
510 |
/************************************************************
|
|
|
511 |
* USART
|
|
|
512 |
************************************************************/
|
|
|
513 |
|
|
|
514 |
/* UxCTL */
|
|
|
515 |
#define PENA (0x80) /* Parity enable */
|
|
|
516 |
#define PEV (0x40) /* Parity 0:odd / 1:even */
|
|
|
517 |
#define SPB (0x20) /* Stop Bits 0:one / 1: two */
|
|
|
518 |
#define CHAR (0x10) /* Data 0:7-bits / 1:8-bits */
|
|
|
519 |
#define LISTEN (0x08) /* Listen mode */
|
|
|
520 |
#define SYNC (0x04) /* UART / SPI mode */
|
|
|
521 |
#define MM (0x02) /* Master Mode off/on */
|
|
|
522 |
#define SWRST (0x01) /* USART Software Reset */
|
|
|
523 |
|
|
|
524 |
/* UxTCTL */
|
|
|
525 |
#define CKPH (0x80) /* SPI: Clock Phase */
|
|
|
526 |
#define CKPL (0x40) /* Clock Polarity */
|
|
|
527 |
#define SSEL1 (0x20) /* Clock Source Select 1 */
|
|
|
528 |
#define SSEL0 (0x10) /* Clock Source Select 0 */
|
|
|
529 |
#define URXSE (0x08) /* Receive Start edge select */
|
|
|
530 |
#define TXWAKE (0x04) /* TX Wake up mode */
|
|
|
531 |
#define STC (0x02) /* SPI: STC enable 0:on / 1:off */
|
|
|
532 |
#define TXEPT (0x01) /* TX Buffer empty */
|
|
|
533 |
|
|
|
534 |
/* UxRCTL */
|
|
|
535 |
#define FE (0x80) /* Frame Error */
|
|
|
536 |
#define PE (0x40) /* Parity Error */
|
|
|
537 |
#define OE (0x20) /* Overrun Error */
|
|
|
538 |
#define BRK (0x10) /* Break detected */
|
|
|
539 |
#define URXEIE (0x08) /* RX Error interrupt enable */
|
|
|
540 |
#define URXWIE (0x04) /* RX Wake up interrupt enable */
|
|
|
541 |
#define RXWAKE (0x02) /* RX Wake up detect */
|
|
|
542 |
#define RXERR (0x01) /* RX Error Error */
|
|
|
543 |
|
|
|
544 |
/************************************************************
|
|
|
545 |
* USART 0
|
|
|
546 |
************************************************************/
|
|
|
547 |
#define __MSP430_HAS_UART0__ /* Definition to show that Module is available */
|
|
|
548 |
|
|
|
549 |
SFR_8BIT(U0CTL); /* USART 0 Control */
|
|
|
550 |
SFR_8BIT(U0TCTL); /* USART 0 Transmit Control */
|
|
|
551 |
SFR_8BIT(U0RCTL); /* USART 0 Receive Control */
|
|
|
552 |
SFR_8BIT(U0MCTL); /* USART 0 Modulation Control */
|
|
|
553 |
SFR_8BIT(U0BR0); /* USART 0 Baud Rate 0 */
|
|
|
554 |
SFR_8BIT(U0BR1); /* USART 0 Baud Rate 1 */
|
|
|
555 |
SFR_8BIT(U0RXBUF); /* USART 0 Receive Buffer */
|
|
|
556 |
SFR_8BIT(U0TXBUF); /* USART 0 Transmit Buffer */
|
|
|
557 |
|
|
|
558 |
/* Alternate register names */
|
|
|
559 |
|
|
|
560 |
#define UCTL0 U0CTL /* USART 0 Control */
|
|
|
561 |
#define UTCTL0 U0TCTL /* USART 0 Transmit Control */
|
|
|
562 |
#define URCTL0 U0RCTL /* USART 0 Receive Control */
|
|
|
563 |
#define UMCTL0 U0MCTL /* USART 0 Modulation Control */
|
|
|
564 |
#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */
|
|
|
565 |
#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */
|
|
|
566 |
#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */
|
|
|
567 |
#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */
|
|
|
568 |
#define UCTL0_ U0CTL_ /* USART 0 Control */
|
|
|
569 |
#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */
|
|
|
570 |
#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */
|
|
|
571 |
#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */
|
|
|
572 |
#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */
|
|
|
573 |
#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */
|
|
|
574 |
#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */
|
|
|
575 |
#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */
|
|
|
576 |
#define UCTL_0 U0CTL /* USART 0 Control */
|
|
|
577 |
#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */
|
|
|
578 |
#define URCTL_0 U0RCTL /* USART 0 Receive Control */
|
|
|
579 |
#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */
|
|
|
580 |
#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */
|
|
|
581 |
#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */
|
|
|
582 |
#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */
|
|
|
583 |
#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */
|
|
|
584 |
#define UCTL_0_ U0CTL_ /* USART 0 Control */
|
|
|
585 |
#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */
|
|
|
586 |
#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */
|
|
|
587 |
#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */
|
|
|
588 |
#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */
|
|
|
589 |
#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */
|
|
|
590 |
#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */
|
|
|
591 |
#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */
|
|
|
592 |
|
|
|
593 |
/************************************************************
|
|
|
594 |
* Timer A3
|
|
|
595 |
************************************************************/
|
|
|
596 |
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
|
|
|
597 |
|
|
|
598 |
SFR_16BIT(TAIV); /* Timer A Interrupt Vector Word */
|
|
|
599 |
SFR_16BIT(TACTL); /* Timer A Control */
|
|
|
600 |
SFR_16BIT(TACCTL0); /* Timer A Capture/Compare Control 0 */
|
|
|
601 |
SFR_16BIT(TACCTL1); /* Timer A Capture/Compare Control 1 */
|
|
|
602 |
SFR_16BIT(TACCTL2); /* Timer A Capture/Compare Control 2 */
|
|
|
603 |
SFR_16BIT(TAR); /* Timer A Counter Register */
|
|
|
604 |
SFR_16BIT(TACCR0); /* Timer A Capture/Compare 0 */
|
|
|
605 |
SFR_16BIT(TACCR1); /* Timer A Capture/Compare 1 */
|
|
|
606 |
SFR_16BIT(TACCR2); /* Timer A Capture/Compare 2 */
|
|
|
607 |
|
|
|
608 |
/* Alternate register names */
|
|
|
609 |
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
610 |
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
611 |
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
612 |
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
613 |
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
614 |
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
615 |
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
616 |
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
617 |
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
618 |
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
619 |
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
620 |
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
621 |
/* Alternate register names - 5xx style */
|
|
|
622 |
#define TA0IV TAIV /* Timer A Interrupt Vector Word */
|
|
|
623 |
#define TA0CTL TACTL /* Timer A Control */
|
|
|
624 |
#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
625 |
#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
626 |
#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
627 |
#define TA0R TAR /* Timer A Counter Register */
|
|
|
628 |
#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
629 |
#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
630 |
#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
631 |
#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */
|
|
|
632 |
#define TA0CTL_ TACTL_ /* Timer A Control */
|
|
|
633 |
#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
634 |
#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
635 |
#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
636 |
#define TA0R_ TAR_ /* Timer A Counter Register */
|
|
|
637 |
#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
638 |
#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
639 |
#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
640 |
|
|
|
641 |
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
|
|
|
642 |
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
|
|
|
643 |
#define ID1 (0x0080) /* Timer A clock input divider 1 */
|
|
|
644 |
#define ID0 (0x0040) /* Timer A clock input divider 0 */
|
|
|
645 |
#define MC1 (0x0020) /* Timer A mode control 1 */
|
|
|
646 |
#define MC0 (0x0010) /* Timer A mode control 0 */
|
|
|
647 |
#define TACLR (0x0004) /* Timer A counter clear */
|
|
|
648 |
#define TAIE (0x0002) /* Timer A counter interrupt enable */
|
|
|
649 |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
|
|
|
650 |
|
|
|
651 |
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
652 |
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
653 |
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
654 |
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
655 |
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
656 |
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
657 |
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
658 |
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
659 |
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
660 |
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
661 |
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
662 |
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
663 |
|
|
|
664 |
#define CM1 (0x8000) /* Capture mode 1 */
|
|
|
665 |
#define CM0 (0x4000) /* Capture mode 0 */
|
|
|
666 |
#define CCIS1 (0x2000) /* Capture input select 1 */
|
|
|
667 |
#define CCIS0 (0x1000) /* Capture input select 0 */
|
|
|
668 |
#define SCS (0x0800) /* Capture sychronize */
|
|
|
669 |
#define SCCI (0x0400) /* Latched capture signal (read) */
|
|
|
670 |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
|
|
|
671 |
#define OUTMOD2 (0x0080) /* Output mode 2 */
|
|
|
672 |
#define OUTMOD1 (0x0040) /* Output mode 1 */
|
|
|
673 |
#define OUTMOD0 (0x0020) /* Output mode 0 */
|
|
|
674 |
#define CCIE (0x0010) /* Capture/compare interrupt enable */
|
|
|
675 |
#define CCI (0x0008) /* Capture input signal (read) */
|
|
|
676 |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
|
|
|
677 |
#define COV (0x0002) /* Capture/compare overflow flag */
|
|
|
678 |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
|
|
|
679 |
|
|
|
680 |
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
|
|
|
681 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
|
|
|
682 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
|
|
|
683 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
|
|
|
684 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
|
|
|
685 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
|
|
|
686 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
|
|
|
687 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
|
|
|
688 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
|
|
|
689 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
|
|
|
690 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
|
|
|
691 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
|
|
|
692 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
|
|
|
693 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
|
|
|
694 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
|
|
|
695 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
|
|
|
696 |
|
|
|
697 |
/* TA3IV Definitions */
|
|
|
698 |
#define TAIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
699 |
#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */
|
|
|
700 |
#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */
|
|
|
701 |
#define TAIV_6 (0x0006) /* Reserved */
|
|
|
702 |
#define TAIV_8 (0x0008) /* Reserved */
|
|
|
703 |
#define TAIV_TAIFG (0x000A) /* TAIFG */
|
|
|
704 |
|
|
|
705 |
/************************************************************
|
|
|
706 |
* Timer B3
|
|
|
707 |
************************************************************/
|
|
|
708 |
#define __MSP430_HAS_TB3__ /* Definition to show that Module is available */
|
|
|
709 |
|
|
|
710 |
SFR_16BIT(TBIV); /* Timer B Interrupt Vector Word */
|
|
|
711 |
SFR_16BIT(TBCTL); /* Timer B Control */
|
|
|
712 |
SFR_16BIT(TBCCTL0); /* Timer B Capture/Compare Control 0 */
|
|
|
713 |
SFR_16BIT(TBCCTL1); /* Timer B Capture/Compare Control 1 */
|
|
|
714 |
SFR_16BIT(TBCCTL2); /* Timer B Capture/Compare Control 2 */
|
|
|
715 |
SFR_16BIT(TBR); /* Timer B Counter Register */
|
|
|
716 |
SFR_16BIT(TBCCR0); /* Timer B Capture/Compare 0 */
|
|
|
717 |
SFR_16BIT(TBCCR1); /* Timer B Capture/Compare 1 */
|
|
|
718 |
SFR_16BIT(TBCCR2); /* Timer B Capture/Compare 2 */
|
|
|
719 |
|
|
|
720 |
/* Alternate register names - 5xx style */
|
|
|
721 |
#define TB0IV TBIV /* Timer B Interrupt Vector Word */
|
|
|
722 |
#define TB0CTL TBCTL /* Timer B Control */
|
|
|
723 |
#define TB0CCTL0 TBCCTL0 /* Timer B Capture/Compare Control 0 */
|
|
|
724 |
#define TB0CCTL1 TBCCTL1 /* Timer B Capture/Compare Control 1 */
|
|
|
725 |
#define TB0CCTL2 TBCCTL2 /* Timer B Capture/Compare Control 2 */
|
|
|
726 |
#define TB0R TBR /* Timer B Counter Register */
|
|
|
727 |
#define TB0CCR0 TBCCR0 /* Timer B Capture/Compare 0 */
|
|
|
728 |
#define TB0CCR1 TBCCR1 /* Timer B Capture/Compare 1 */
|
|
|
729 |
#define TB0CCR2 TBCCR2 /* Timer B Capture/Compare 2 */
|
|
|
730 |
#define TB0IV_ TBIV_ /* Timer B Interrupt Vector Word */
|
|
|
731 |
#define TB0CTL_ TBCTL_ /* Timer B Control */
|
|
|
732 |
#define TB0CCTL0_ TBCCTL0_ /* Timer B Capture/Compare Control 0 */
|
|
|
733 |
#define TB0CCTL1_ TBCCTL1_ /* Timer B Capture/Compare Control 1 */
|
|
|
734 |
#define TB0CCTL2_ TBCCTL2_ /* Timer B Capture/Compare Control 2 */
|
|
|
735 |
#define TB0R_ TBR_ /* Timer B Counter Register */
|
|
|
736 |
#define TB0CCR0_ TBCCR0_ /* Timer B Capture/Compare 0 */
|
|
|
737 |
#define TB0CCR1_ TBCCR1_ /* Timer B Capture/Compare 1 */
|
|
|
738 |
#define TB0CCR2_ TBCCR2_ /* Timer B Capture/Compare 2 */
|
|
|
739 |
|
|
|
740 |
#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */
|
|
|
741 |
#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */
|
|
|
742 |
#define CNTL1 (0x1000) /* Counter lenght 1 */
|
|
|
743 |
#define CNTL0 (0x0800) /* Counter lenght 0 */
|
|
|
744 |
#define TBSSEL1 (0x0200) /* Clock source 1 */
|
|
|
745 |
#define TBSSEL0 (0x0100) /* Clock source 0 */
|
|
|
746 |
#define TBCLR (0x0004) /* Timer B counter clear */
|
|
|
747 |
#define TBIE (0x0002) /* Timer B interrupt enable */
|
|
|
748 |
#define TBIFG (0x0001) /* Timer B interrupt flag */
|
|
|
749 |
|
|
|
750 |
#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */
|
|
|
751 |
#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */
|
|
|
752 |
|
|
|
753 |
#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
|
|
|
754 |
#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
|
|
|
755 |
#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
|
|
|
756 |
#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
|
|
|
757 |
#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
|
|
|
758 |
#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
|
|
|
759 |
#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
|
|
|
760 |
#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
|
|
|
761 |
#define SHR_0 (0*0x2000u) /* Timer B Group: 0 - individually */
|
|
|
762 |
#define SHR_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
763 |
#define SHR_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
764 |
#define SHR_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
|
|
|
765 |
#define TBCLGRP_0 (0*0x2000u) /* Timer B Group: 0 - individually */
|
|
|
766 |
#define TBCLGRP_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
767 |
#define TBCLGRP_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
768 |
#define TBCLGRP_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
|
|
|
769 |
|
|
|
770 |
/* Additional Timer B Control Register bits are defined in Timer A */
|
|
|
771 |
|
|
|
772 |
#define CLLD1 (0x0400) /* Compare latch load source 1 */
|
|
|
773 |
#define CLLD0 (0x0200) /* Compare latch load source 0 */
|
|
|
774 |
|
|
|
775 |
#define SLSHR1 (0x0400) /* Compare latch load source 1 */
|
|
|
776 |
#define SLSHR0 (0x0200) /* Compare latch load source 0 */
|
|
|
777 |
|
|
|
778 |
#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
779 |
#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
|
|
|
780 |
#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
781 |
#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
|
|
|
782 |
|
|
|
783 |
#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
784 |
#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
|
|
|
785 |
#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
786 |
#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
|
|
|
787 |
|
|
|
788 |
/* TB3IV Definitions */
|
|
|
789 |
#define TBIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
790 |
#define TBIV_TBCCR1 (0x0002) /* TBCCR1_CCIFG */
|
|
|
791 |
#define TBIV_TBCCR2 (0x0004) /* TBCCR2_CCIFG */
|
|
|
792 |
#define TBIV_3 (0x0006) /* Reserved */
|
|
|
793 |
#define TBIV_4 (0x0008) /* Reserved */
|
|
|
794 |
#define TBIV_5 (0x000A) /* Reserved */
|
|
|
795 |
#define TBIV_6 (0x000C) /* Reserved */
|
|
|
796 |
#define TBIV_TBIFG (0x000E) /* TBIFG */
|
|
|
797 |
|
|
|
798 |
/*************************************************************
|
|
|
799 |
* Flash Memory
|
|
|
800 |
*************************************************************/
|
|
|
801 |
#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
|
|
|
802 |
|
|
|
803 |
SFR_16BIT(FCTL1); /* FLASH Control 1 */
|
|
|
804 |
SFR_16BIT(FCTL2); /* FLASH Control 2 */
|
|
|
805 |
SFR_16BIT(FCTL3); /* FLASH Control 3 */
|
|
|
806 |
|
|
|
807 |
#define FRKEY (0x9600) /* Flash key returned by read */
|
|
|
808 |
#define FWKEY (0xA500) /* Flash key for write */
|
|
|
809 |
#define FXKEY (0x3300) /* for use with XOR instruction */
|
|
|
810 |
|
|
|
811 |
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
|
|
|
812 |
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
|
|
|
813 |
#define WRT (0x0040) /* Enable bit for Flash write */
|
|
|
814 |
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
|
|
|
815 |
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
|
|
|
816 |
|
|
|
817 |
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
|
|
|
818 |
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
|
|
|
819 |
#ifndef FN2
|
|
|
820 |
#define FN2 (0x0004)
|
|
|
821 |
#endif
|
|
|
822 |
#ifndef FN3
|
|
|
823 |
#define FN3 (0x0008)
|
|
|
824 |
#endif
|
|
|
825 |
#ifndef FN4
|
|
|
826 |
#define FN4 (0x0010)
|
|
|
827 |
#endif
|
|
|
828 |
#define FN5 (0x0020)
|
|
|
829 |
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
|
|
|
830 |
#define FSSEL1 (0x0080) /* Flash clock select 1 */
|
|
|
831 |
|
|
|
832 |
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
|
|
|
833 |
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
|
|
|
834 |
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
|
|
|
835 |
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
|
|
|
836 |
|
|
|
837 |
#define BUSY (0x0001) /* Flash busy: 1 */
|
|
|
838 |
#define KEYV (0x0002) /* Flash Key violation flag */
|
|
|
839 |
#define ACCVIFG (0x0004) /* Flash Access violation flag */
|
|
|
840 |
#define WAIT (0x0008) /* Wait flag for segment write */
|
|
|
841 |
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
842 |
#define EMEX (0x0020) /* Flash Emergency Exit */
|
|
|
843 |
|
|
|
844 |
/************************************************************
|
|
|
845 |
* Comparator A
|
|
|
846 |
************************************************************/
|
|
|
847 |
#define __MSP430_HAS_COMPA__ /* Definition to show that Module is available */
|
|
|
848 |
|
|
|
849 |
SFR_8BIT(CACTL1); /* Comparator A Control 1 */
|
|
|
850 |
SFR_8BIT(CACTL2); /* Comparator A Control 2 */
|
|
|
851 |
SFR_8BIT(CAPD); /* Comparator A Port Disable */
|
|
|
852 |
|
|
|
853 |
#define CAIFG (0x01) /* Comp. A Interrupt Flag */
|
|
|
854 |
#define CAIE (0x02) /* Comp. A Interrupt Enable */
|
|
|
855 |
#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
|
|
|
856 |
#define CAON (0x08) /* Comp. A enable */
|
|
|
857 |
#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
|
|
|
858 |
#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
|
|
|
859 |
#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
|
|
|
860 |
#define CAEX (0x80) /* Comp. A Exchange Inputs */
|
|
|
861 |
|
|
|
862 |
#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
|
|
|
863 |
#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
|
|
|
864 |
#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
|
|
|
865 |
#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
|
|
|
866 |
|
|
|
867 |
#define CAOUT (0x01) /* Comp. A Output */
|
|
|
868 |
#define CAF (0x02) /* Comp. A Enable Output Filter */
|
|
|
869 |
#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */
|
|
|
870 |
#define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */
|
|
|
871 |
#define CACTL24 (0x10)
|
|
|
872 |
#define CACTL25 (0x20)
|
|
|
873 |
#define CACTL26 (0x40)
|
|
|
874 |
#define CACTL27 (0x80)
|
|
|
875 |
|
|
|
876 |
#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
|
|
|
877 |
#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
|
|
|
878 |
#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
|
|
|
879 |
#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
|
|
|
880 |
#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
|
|
|
881 |
#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
|
|
|
882 |
#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
|
|
|
883 |
#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
|
|
|
884 |
|
|
|
885 |
/************************************************************
|
|
|
886 |
* ADC12
|
|
|
887 |
************************************************************/
|
|
|
888 |
#define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */
|
|
|
889 |
|
|
|
890 |
SFR_16BIT(ADC12CTL0); /* ADC12 Control 0 */
|
|
|
891 |
SFR_16BIT(ADC12CTL1); /* ADC12 Control 1 */
|
|
|
892 |
SFR_16BIT(ADC12IFG); /* ADC12 Interrupt Flag */
|
|
|
893 |
SFR_16BIT(ADC12IE); /* ADC12 Interrupt Enable */
|
|
|
894 |
SFR_16BIT(ADC12IV); /* ADC12 Interrupt Vector Word */
|
|
|
895 |
|
|
|
896 |
#define ADC12MEM_ (0x0140) /* ADC12 Conversion Memory */
|
|
|
897 |
#ifdef __ASM_HEADER__
|
|
|
898 |
#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */
|
|
|
899 |
#else
|
|
|
900 |
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
|
|
|
901 |
#endif
|
|
|
902 |
SFR_16BIT(ADC12MEM0); /* ADC12 Conversion Memory 0 */
|
|
|
903 |
SFR_16BIT(ADC12MEM1); /* ADC12 Conversion Memory 1 */
|
|
|
904 |
SFR_16BIT(ADC12MEM2); /* ADC12 Conversion Memory 2 */
|
|
|
905 |
SFR_16BIT(ADC12MEM3); /* ADC12 Conversion Memory 3 */
|
|
|
906 |
SFR_16BIT(ADC12MEM4); /* ADC12 Conversion Memory 4 */
|
|
|
907 |
SFR_16BIT(ADC12MEM5); /* ADC12 Conversion Memory 5 */
|
|
|
908 |
SFR_16BIT(ADC12MEM6); /* ADC12 Conversion Memory 6 */
|
|
|
909 |
SFR_16BIT(ADC12MEM7); /* ADC12 Conversion Memory 7 */
|
|
|
910 |
SFR_16BIT(ADC12MEM8); /* ADC12 Conversion Memory 8 */
|
|
|
911 |
SFR_16BIT(ADC12MEM9); /* ADC12 Conversion Memory 9 */
|
|
|
912 |
SFR_16BIT(ADC12MEM10); /* ADC12 Conversion Memory 10 */
|
|
|
913 |
SFR_16BIT(ADC12MEM11); /* ADC12 Conversion Memory 11 */
|
|
|
914 |
SFR_16BIT(ADC12MEM12); /* ADC12 Conversion Memory 12 */
|
|
|
915 |
SFR_16BIT(ADC12MEM13); /* ADC12 Conversion Memory 13 */
|
|
|
916 |
SFR_16BIT(ADC12MEM14); /* ADC12 Conversion Memory 14 */
|
|
|
917 |
SFR_16BIT(ADC12MEM15); /* ADC12 Conversion Memory 15 */
|
|
|
918 |
|
|
|
919 |
#define ADC12MCTL_ (0x0080) /* ADC12 Memory Control */
|
|
|
920 |
#ifdef __ASM_HEADER__
|
|
|
921 |
#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */
|
|
|
922 |
#else
|
|
|
923 |
#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
|
|
|
924 |
#endif
|
|
|
925 |
SFR_8BIT(ADC12MCTL0); /* ADC12 Memory Control 0 */
|
|
|
926 |
SFR_8BIT(ADC12MCTL1); /* ADC12 Memory Control 1 */
|
|
|
927 |
SFR_8BIT(ADC12MCTL2); /* ADC12 Memory Control 2 */
|
|
|
928 |
SFR_8BIT(ADC12MCTL3); /* ADC12 Memory Control 3 */
|
|
|
929 |
SFR_8BIT(ADC12MCTL4); /* ADC12 Memory Control 4 */
|
|
|
930 |
SFR_8BIT(ADC12MCTL5); /* ADC12 Memory Control 5 */
|
|
|
931 |
SFR_8BIT(ADC12MCTL6); /* ADC12 Memory Control 6 */
|
|
|
932 |
SFR_8BIT(ADC12MCTL7); /* ADC12 Memory Control 7 */
|
|
|
933 |
SFR_8BIT(ADC12MCTL8); /* ADC12 Memory Control 8 */
|
|
|
934 |
SFR_8BIT(ADC12MCTL9); /* ADC12 Memory Control 9 */
|
|
|
935 |
SFR_8BIT(ADC12MCTL10); /* ADC12 Memory Control 10 */
|
|
|
936 |
SFR_8BIT(ADC12MCTL11); /* ADC12 Memory Control 11 */
|
|
|
937 |
SFR_8BIT(ADC12MCTL12); /* ADC12 Memory Control 12 */
|
|
|
938 |
SFR_8BIT(ADC12MCTL13); /* ADC12 Memory Control 13 */
|
|
|
939 |
SFR_8BIT(ADC12MCTL14); /* ADC12 Memory Control 14 */
|
|
|
940 |
SFR_8BIT(ADC12MCTL15); /* ADC12 Memory Control 15 */
|
|
|
941 |
|
|
|
942 |
/* ADC12CTL0 */
|
|
|
943 |
#define ADC12SC (0x001) /* ADC12 Start Conversion */
|
|
|
944 |
#define ENC (0x002) /* ADC12 Enable Conversion */
|
|
|
945 |
#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */
|
|
|
946 |
#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */
|
|
|
947 |
#define ADC12ON (0x010) /* ADC12 On/enable */
|
|
|
948 |
#define REFON (0x020) /* ADC12 Reference on */
|
|
|
949 |
#define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */
|
|
|
950 |
#define MSC (0x080) /* ADC12 Multiple SampleConversion */
|
|
|
951 |
#define SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */
|
|
|
952 |
#define SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */
|
|
|
953 |
#define SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */
|
|
|
954 |
#define SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */
|
|
|
955 |
#define SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */
|
|
|
956 |
#define SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */
|
|
|
957 |
#define SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */
|
|
|
958 |
#define SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */
|
|
|
959 |
#define MSH (0x080)
|
|
|
960 |
|
|
|
961 |
#define SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
|
|
|
962 |
#define SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */
|
|
|
963 |
#define SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */
|
|
|
964 |
#define SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */
|
|
|
965 |
#define SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */
|
|
|
966 |
#define SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */
|
|
|
967 |
#define SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */
|
|
|
968 |
#define SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */
|
|
|
969 |
#define SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */
|
|
|
970 |
#define SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */
|
|
|
971 |
#define SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */
|
|
|
972 |
#define SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */
|
|
|
973 |
#define SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */
|
|
|
974 |
#define SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */
|
|
|
975 |
#define SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */
|
|
|
976 |
#define SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */
|
|
|
977 |
|
|
|
978 |
#define SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
|
|
|
979 |
#define SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
|
|
|
980 |
#define SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
|
|
|
981 |
#define SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
|
|
|
982 |
#define SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */
|
|
|
983 |
#define SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */
|
|
|
984 |
#define SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */
|
|
|
985 |
#define SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */
|
|
|
986 |
#define SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */
|
|
|
987 |
#define SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */
|
|
|
988 |
#define SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */
|
|
|
989 |
#define SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */
|
|
|
990 |
#define SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */
|
|
|
991 |
#define SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */
|
|
|
992 |
#define SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */
|
|
|
993 |
#define SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */
|
|
|
994 |
|
|
|
995 |
/* ADC12CTL1 */
|
|
|
996 |
#define ADC12BUSY (0x0001) /* ADC12 Busy */
|
|
|
997 |
#define CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */
|
|
|
998 |
#define CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */
|
|
|
999 |
#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */
|
|
|
1000 |
#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */
|
|
|
1001 |
#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */
|
|
|
1002 |
#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */
|
|
|
1003 |
#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */
|
|
|
1004 |
#define ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
|
|
|
1005 |
#define SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
|
|
|
1006 |
#define SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */
|
|
|
1007 |
#define SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */
|
|
|
1008 |
#define CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */
|
|
|
1009 |
#define CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */
|
|
|
1010 |
#define CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */
|
|
|
1011 |
#define CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */
|
|
|
1012 |
|
|
|
1013 |
#define CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */
|
|
|
1014 |
#define CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */
|
|
|
1015 |
#define CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */
|
|
|
1016 |
#define CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */
|
|
|
1017 |
#define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */
|
|
|
1018 |
#define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */
|
|
|
1019 |
#define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */
|
|
|
1020 |
#define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */
|
|
|
1021 |
#define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */
|
|
|
1022 |
#define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */
|
|
|
1023 |
#define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */
|
|
|
1024 |
#define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */
|
|
|
1025 |
#define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */
|
|
|
1026 |
#define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */
|
|
|
1027 |
#define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */
|
|
|
1028 |
#define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */
|
|
|
1029 |
#define SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */
|
|
|
1030 |
#define SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */
|
|
|
1031 |
#define SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */
|
|
|
1032 |
#define SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */
|
|
|
1033 |
#define CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */
|
|
|
1034 |
#define CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */
|
|
|
1035 |
#define CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */
|
|
|
1036 |
#define CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */
|
|
|
1037 |
#define CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */
|
|
|
1038 |
#define CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */
|
|
|
1039 |
#define CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */
|
|
|
1040 |
#define CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */
|
|
|
1041 |
#define CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */
|
|
|
1042 |
#define CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */
|
|
|
1043 |
#define CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */
|
|
|
1044 |
#define CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */
|
|
|
1045 |
#define CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */
|
|
|
1046 |
#define CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */
|
|
|
1047 |
#define CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */
|
|
|
1048 |
#define CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */
|
|
|
1049 |
|
|
|
1050 |
/* ADC12MCTLx */
|
|
|
1051 |
#define INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */
|
|
|
1052 |
#define INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */
|
|
|
1053 |
#define INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */
|
|
|
1054 |
#define INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */
|
|
|
1055 |
#define SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */
|
|
|
1056 |
#define SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */
|
|
|
1057 |
#define SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */
|
|
|
1058 |
#define EOS (0x0080) /* ADC12 End of Sequence */
|
|
|
1059 |
|
|
|
1060 |
#define INCH_0 (0) /* ADC12 Input Channel 0 */
|
|
|
1061 |
#define INCH_1 (1) /* ADC12 Input Channel 1 */
|
|
|
1062 |
#define INCH_2 (2) /* ADC12 Input Channel 2 */
|
|
|
1063 |
#define INCH_3 (3) /* ADC12 Input Channel 3 */
|
|
|
1064 |
#define INCH_4 (4) /* ADC12 Input Channel 4 */
|
|
|
1065 |
#define INCH_5 (5) /* ADC12 Input Channel 5 */
|
|
|
1066 |
#define INCH_6 (6) /* ADC12 Input Channel 6 */
|
|
|
1067 |
#define INCH_7 (7) /* ADC12 Input Channel 7 */
|
|
|
1068 |
#define INCH_8 (8) /* ADC12 Input Channel 8 */
|
|
|
1069 |
#define INCH_9 (9) /* ADC12 Input Channel 9 */
|
|
|
1070 |
#define INCH_10 (10) /* ADC12 Input Channel 10 */
|
|
|
1071 |
#define INCH_11 (11) /* ADC12 Input Channel 11 */
|
|
|
1072 |
#define INCH_12 (12) /* ADC12 Input Channel 12 */
|
|
|
1073 |
#define INCH_13 (13) /* ADC12 Input Channel 13 */
|
|
|
1074 |
#define INCH_14 (14) /* ADC12 Input Channel 14 */
|
|
|
1075 |
#define INCH_15 (15) /* ADC12 Input Channel 15 */
|
|
|
1076 |
|
|
|
1077 |
#define SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */
|
|
|
1078 |
#define SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */
|
|
|
1079 |
#define SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */
|
|
|
1080 |
#define SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */
|
|
|
1081 |
#define SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */
|
|
|
1082 |
#define SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */
|
|
|
1083 |
#define SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */
|
|
|
1084 |
#define SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */
|
|
|
1085 |
|
|
|
1086 |
/* ADC12IV Definitions */
|
|
|
1087 |
#define ADC12IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1088 |
#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */
|
|
|
1089 |
#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */
|
|
|
1090 |
#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */
|
|
|
1091 |
#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */
|
|
|
1092 |
#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */
|
|
|
1093 |
#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */
|
|
|
1094 |
#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */
|
|
|
1095 |
#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */
|
|
|
1096 |
#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */
|
|
|
1097 |
#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */
|
|
|
1098 |
#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */
|
|
|
1099 |
#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */
|
|
|
1100 |
#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */
|
|
|
1101 |
#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */
|
|
|
1102 |
#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */
|
|
|
1103 |
#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */
|
|
|
1104 |
#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */
|
|
|
1105 |
#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */
|
|
|
1106 |
|
|
|
1107 |
/************************************************************
|
|
|
1108 |
* DAC12
|
|
|
1109 |
************************************************************/
|
|
|
1110 |
#define __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */
|
|
|
1111 |
|
|
|
1112 |
SFR_16BIT(DAC12_0CTL); /* DAC12_0 Control */
|
|
|
1113 |
SFR_16BIT(DAC12_1CTL); /* DAC12_1 Control */
|
|
|
1114 |
|
|
|
1115 |
#define DAC12GRP (0x0001) /* DAC12 group */
|
|
|
1116 |
#define DAC12ENC (0x0002) /* DAC12 enable conversion */
|
|
|
1117 |
#define DAC12IFG (0x0004) /* DAC12 interrupt flag */
|
|
|
1118 |
#define DAC12IE (0x0008) /* DAC12 interrupt enable */
|
|
|
1119 |
#define DAC12DF (0x0010) /* DAC12 data format */
|
|
|
1120 |
#define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */
|
|
|
1121 |
#define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */
|
|
|
1122 |
#define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */
|
|
|
1123 |
#define DAC12IR (0x0100) /* DAC12 input reference and output range */
|
|
|
1124 |
#define DAC12CALON (0x0200) /* DAC12 calibration */
|
|
|
1125 |
#define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */
|
|
|
1126 |
#define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */
|
|
|
1127 |
#define DAC12RES (0x1000) /* DAC12 resolution */
|
|
|
1128 |
#define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */
|
|
|
1129 |
#define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */
|
|
|
1130 |
#define DAC12OPS (0x8000) /* DAC12 Operation Amp. */
|
|
|
1131 |
|
|
|
1132 |
#define DAC12AMP_0 (0*0x0020u) /* DAC12 amplifier 0: off, 3-state */
|
|
|
1133 |
#define DAC12AMP_1 (1*0x0020u) /* DAC12 amplifier 1: off, off */
|
|
|
1134 |
#define DAC12AMP_2 (2*0x0020u) /* DAC12 amplifier 2: low, low */
|
|
|
1135 |
#define DAC12AMP_3 (3*0x0020u) /* DAC12 amplifier 3: low, medium */
|
|
|
1136 |
#define DAC12AMP_4 (4*0x0020u) /* DAC12 amplifier 4: low, high */
|
|
|
1137 |
#define DAC12AMP_5 (5*0x0020u) /* DAC12 amplifier 5: medium, medium */
|
|
|
1138 |
#define DAC12AMP_6 (6*0x0020u) /* DAC12 amplifier 6: medium, high */
|
|
|
1139 |
#define DAC12AMP_7 (7*0x0020u) /* DAC12 amplifier 7: high, high */
|
|
|
1140 |
|
|
|
1141 |
#define DAC12LSEL_0 (0*0x0400u) /* DAC12 load select 0: direct */
|
|
|
1142 |
#define DAC12LSEL_1 (1*0x0400u) /* DAC12 load select 1: latched with DAT */
|
|
|
1143 |
#define DAC12LSEL_2 (2*0x0400u) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */
|
|
|
1144 |
#define DAC12LSEL_3 (3*0x0400u) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */
|
|
|
1145 |
|
|
|
1146 |
#define DAC12SREF_0 (0*0x2000u) /* DAC12 reference 0: Vref+ */
|
|
|
1147 |
#define DAC12SREF_1 (1*0x2000u) /* DAC12 reference 1: Vref+ */
|
|
|
1148 |
#define DAC12SREF_2 (2*0x2000u) /* DAC12 reference 2: Veref+ */
|
|
|
1149 |
#define DAC12SREF_3 (3*0x2000u) /* DAC12 reference 3: Veref+ */
|
|
|
1150 |
|
|
|
1151 |
SFR_16BIT(DAC12_0DAT); /* DAC12_0 Data */
|
|
|
1152 |
SFR_16BIT(DAC12_1DAT); /* DAC12_1 Data */
|
|
|
1153 |
/************************************************************
|
|
|
1154 |
* DMA
|
|
|
1155 |
************************************************************/
|
|
|
1156 |
#define __MSP430_HAS_DMA_1__ /* Definition to show that Module is available */
|
|
|
1157 |
|
|
|
1158 |
SFR_16BIT(DMACTL0); /* DMA Module Control 0 */
|
|
|
1159 |
#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
|
|
|
1160 |
#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
|
|
|
1161 |
#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
|
|
|
1162 |
#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
|
|
|
1163 |
|
|
|
1164 |
#define DMA0TSEL_0 (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw)*/
|
|
|
1165 |
#define DMA0TSEL_1 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer_A (TACCR2.IFG) */
|
|
|
1166 |
#define DMA0TSEL_2 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer_B (TBCCR2.IFG) */
|
|
|
1167 |
#define DMA0TSEL_3 (3*0x0001u) /* DMA channel 0 transfer select 3: UART0/I2C receive */
|
|
|
1168 |
#define DMA0TSEL_4 (4*0x0001u) /* DMA channel 0 transfer select 4: UART0/I2C transmit */
|
|
|
1169 |
#define DMA0TSEL_5 (5*0x0001u) /* DMA channel 0 transfer select 5: DAC12_0CTL.DAC12IFG */
|
|
|
1170 |
#define DMA0TSEL_6 (6*0x0001u) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */
|
|
|
1171 |
#define DMA0TSEL_7 (7*0x0001u) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */
|
|
|
1172 |
#define DMA0TSEL_8 (8*0x0001u) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */
|
|
|
1173 |
#define DMA0TSEL_9 (9*0x0001u) /* DMA channel 0 transfer select 9: UART1 receive */
|
|
|
1174 |
#define DMA0TSEL_10 (10*0x0001u) /* DMA channel 0 transfer select 10: UART1 transmit */
|
|
|
1175 |
#define DMA0TSEL_11 (11*0x0001u) /* DMA channel 0 transfer select 11: Multiplier ready */
|
|
|
1176 |
#define DMA0TSEL_14 (14*0x0001u) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */
|
|
|
1177 |
#define DMA0TSEL_15 (15*0x0001u) /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */
|
|
|
1178 |
|
|
|
1179 |
SFR_16BIT(DMACTL1); /* DMA Module Control 1 */
|
|
|
1180 |
#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
|
|
|
1181 |
#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
|
|
|
1182 |
#define DMAONFETCH (0x0004) /* DMA transfer on instruction fetch */
|
|
|
1183 |
|
|
|
1184 |
SFR_16BIT(DMA0CTL); /* DMA Channel 0 Control */
|
|
|
1185 |
|
|
|
1186 |
#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
|
|
|
1187 |
#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
|
|
|
1188 |
#define DMAIE (0x0004) /* DMA interrupt enable */
|
|
|
1189 |
#define DMAIFG (0x0008) /* DMA interrupt flag */
|
|
|
1190 |
#define DMAEN (0x0010) /* DMA enable */
|
|
|
1191 |
#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
|
|
|
1192 |
#define DMASRCBYTE (0x0040) /* DMA source byte */
|
|
|
1193 |
#define DMADSTBYTE (0x0080) /* DMA destination byte */
|
|
|
1194 |
#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
|
|
|
1195 |
#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
|
|
|
1196 |
#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
|
|
|
1197 |
#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
|
|
|
1198 |
#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
|
|
|
1199 |
#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
|
|
|
1200 |
#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
|
|
|
1201 |
|
|
|
1202 |
#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
|
|
|
1203 |
#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
|
|
|
1204 |
#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
|
|
|
1205 |
#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
|
|
|
1206 |
|
|
|
1207 |
#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
|
|
|
1208 |
#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
|
|
|
1209 |
#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
|
|
|
1210 |
#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
|
|
|
1211 |
|
|
|
1212 |
#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
|
|
|
1213 |
#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
|
|
|
1214 |
#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
|
|
|
1215 |
#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
|
|
|
1216 |
|
|
|
1217 |
#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: single */
|
|
|
1218 |
#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: block */
|
|
|
1219 |
#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: interleaved */
|
|
|
1220 |
#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: interleaved */
|
|
|
1221 |
#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: single, repeat */
|
|
|
1222 |
#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: block, repeat */
|
|
|
1223 |
#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: interleaved, repeat */
|
|
|
1224 |
#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: interleaved, repeat */
|
|
|
1225 |
|
|
|
1226 |
SFR_16BIT(DMA0SA); /* DMA Channel 0 Source Address */
|
|
|
1227 |
SFR_16BIT(DMA0DA); /* DMA Channel 0 Destination Address */
|
|
|
1228 |
SFR_16BIT(DMA0SZ); /* DMA Channel 0 Transfer Size */
|
|
|
1229 |
|
|
|
1230 |
/************************************************************
|
|
|
1231 |
* Operational Amplifier
|
|
|
1232 |
************************************************************/
|
|
|
1233 |
#define __MSP430_HAS_OA_3__ /* Definition to show that Module is available */
|
|
|
1234 |
|
|
|
1235 |
SFR_8BIT(OA0CTL0); /* OA0 Control register 0 */
|
|
|
1236 |
SFR_8BIT(OA0CTL1); /* OA0 Control register 1 */
|
|
|
1237 |
SFR_8BIT(OA1CTL0); /* OA1 Control register 0 */
|
|
|
1238 |
SFR_8BIT(OA1CTL1); /* OA1 Control register 1 */
|
|
|
1239 |
SFR_8BIT(OA2CTL0); /* OA2 Control register 0 */
|
|
|
1240 |
SFR_8BIT(OA2CTL1); /* OA2 Control register 1 */
|
|
|
1241 |
|
|
|
1242 |
#define OAADC0 (0x01) /* OAx output to ADC12 input channel select 0 */
|
|
|
1243 |
#define OAADC1 (0x02) /* OAx output to ADC12 input channel select 1 */
|
|
|
1244 |
#define OAPM0 (0x04) /* OAx Power mode select 0 */
|
|
|
1245 |
#define OAPM1 (0x08) /* OAx Power mode select 1 */
|
|
|
1246 |
#define OAP0 (0x10) /* OAx Non-inverting input select 0 */
|
|
|
1247 |
#define OAP1 (0x20) /* OAx Non-inverting input select 1 */
|
|
|
1248 |
#define OAN0 (0x40) /* OAx Inverting input select 0 */
|
|
|
1249 |
#define OAN1 (0x80) /* OAx Inverting input select 1 */
|
|
|
1250 |
|
|
|
1251 |
#define OAPM_0 (0x00) /* OAx Power mode select: off */
|
|
|
1252 |
#define OAPM_1 (0x04) /* OAx Power mode select: slow */
|
|
|
1253 |
#define OAPM_2 (0x08) /* OAx Power mode select: meduim */
|
|
|
1254 |
#define OAPM_3 (0x0C) /* OAx Power mode select: fast */
|
|
|
1255 |
#define OAP_0 (0x00) /* OAx Non-inverting input select 00 */
|
|
|
1256 |
#define OAP_1 (0x10) /* OAx Non-inverting input select 01 */
|
|
|
1257 |
#define OAP_2 (0x20) /* OAx Non-inverting input select 10 */
|
|
|
1258 |
#define OAP_3 (0x30) /* OAx Non-inverting input select 11 */
|
|
|
1259 |
#define OAN_0 (0x00) /* OAx Inverting input select 00 */
|
|
|
1260 |
#define OAN_1 (0x40) /* OAx Inverting input select 01 */
|
|
|
1261 |
#define OAN_2 (0x80) /* OAx Inverting input select 10 */
|
|
|
1262 |
#define OAN_3 (0xC0) /* OAx Inverting input select 11 */
|
|
|
1263 |
|
|
|
1264 |
#define OARRIP (0x01) /* OAx Rail-to-Rail Input off */
|
|
|
1265 |
//#define Reserved (0x02) /* */
|
|
|
1266 |
#define OAFC0 (0x04) /* OAx Function control 0 */
|
|
|
1267 |
#define OAFC1 (0x08) /* OAx Function control 1 */
|
|
|
1268 |
#define OAFC2 (0x10) /* OAx Function control 2 */
|
|
|
1269 |
#define OAFBR0 (0x20) /* OAx Feedback resistor select 0 */
|
|
|
1270 |
#define OAFBR1 (0x40) /* OAx Feedback resistor select 1 */
|
|
|
1271 |
#define OAFBR2 (0x80) /* OAx Feedback resistor select 2 */
|
|
|
1272 |
|
|
|
1273 |
#define OAFC_0 (0x00) /* OAx Function: Gen. Purpose */
|
|
|
1274 |
#define OAFC_1 (0x04) /* OAx Function: Unity gain buffer */
|
|
|
1275 |
#define OAFC_2 (0x08) /* OAx Function: Reserved */
|
|
|
1276 |
#define OAFC_3 (0x0C) /* OAx Function: Comparator */
|
|
|
1277 |
#define OAFC_4 (0x10) /* OAx Function: Non-Inverting PGA */
|
|
|
1278 |
#define OAFC_5 (0x14) /* OAx Function: Reserved */
|
|
|
1279 |
#define OAFC_6 (0x18) /* OAx Function: Inverting PGA */
|
|
|
1280 |
#define OAFC_7 (0x1C) /* OAx Function: Differential PGA */
|
|
|
1281 |
#define OAFBR_0 (0x00) /* OAx Feedback resistor: Tap 0 */
|
|
|
1282 |
#define OAFBR_1 (0x20) /* OAx Feedback resistor: Tap 1 */
|
|
|
1283 |
#define OAFBR_2 (0x40) /* OAx Feedback resistor: Tap 2 */
|
|
|
1284 |
#define OAFBR_3 (0x60) /* OAx Feedback resistor: Tap 3 */
|
|
|
1285 |
#define OAFBR_4 (0x80) /* OAx Feedback resistor: Tap 4 */
|
|
|
1286 |
#define OAFBR_5 (0xA0) /* OAx Feedback resistor: Tap 5 */
|
|
|
1287 |
#define OAFBR_6 (0xC0) /* OAx Feedback resistor: Tap 6 */
|
|
|
1288 |
#define OAFBR_7 (0xE0) /* OAx Feedback resistor: Tap 7 */
|
|
|
1289 |
|
|
|
1290 |
/************************************************************
|
|
|
1291 |
* Interrupt Vectors (offset from 0xFFE0)
|
|
|
1292 |
************************************************************/
|
|
|
1293 |
|
|
|
1294 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
1295 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
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|
1296 |
#define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name
|
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|
1297 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
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|
1298 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
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|
1299 |
PLACE_VECTOR(VECTOR_NAME(func), offset)
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|
1300 |
|
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|
1301 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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|
1302 |
#define BASICTIMER_VECTOR ".int00" /* 0xFFE0 Basic Timer */
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|
1303 |
#else
|
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|
1304 |
#define BASICTIMER_VECTOR (0 * 1u) /* 0xFFE0 Basic Timer */
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|
1305 |
/*#define BASICTIMER_ISR(func) ISR_VECTOR(func, ".int00") */ /* 0xFFE0 Basic Timer */ /* CCE V2 Style */
|
|
|
1306 |
#endif
|
|
|
1307 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1308 |
#define PORT2_VECTOR ".int01" /* 0xFFE2 Port 2 */
|
|
|
1309 |
#else
|
|
|
1310 |
#define PORT2_VECTOR (1 * 1u) /* 0xFFE2 Port 2 */
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|
1311 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int01") */ /* 0xFFE2 Port 2 */ /* CCE V2 Style */
|
|
|
1312 |
#endif
|
|
|
1313 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1314 |
#define DAC12_DMA_VECTOR ".int03" /* 0xFFE6 DAC 12 */
|
|
|
1315 |
#else
|
|
|
1316 |
#define DAC12_DMA_VECTOR (3 * 1u) /* 0xFFE6 DAC 12 */
|
|
|
1317 |
/*#define DAC12_DMA_ISR(func) ISR_VECTOR(func, ".int03") */ /* 0xFFE6 DAC 12 */ /* CCE V2 Style */
|
|
|
1318 |
#endif
|
|
|
1319 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1320 |
#define PORT1_VECTOR ".int04" /* 0xFFE8 Port 1 */
|
|
|
1321 |
#else
|
|
|
1322 |
#define PORT1_VECTOR (4 * 1u) /* 0xFFE8 Port 1 */
|
|
|
1323 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int04") */ /* 0xFFE8 Port 1 */ /* CCE V2 Style */
|
|
|
1324 |
#endif
|
|
|
1325 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1326 |
#define TIMERA1_VECTOR ".int05" /* 0xFFEA Timer A CC1-2, TA */
|
|
|
1327 |
#else
|
|
|
1328 |
#define TIMERA1_VECTOR (5 * 1u) /* 0xFFEA Timer A CC1-2, TA */
|
|
|
1329 |
/*#define TIMERA1_ISR(func) ISR_VECTOR(func, ".int05") */ /* 0xFFEA Timer A CC1-2, TA */ /* CCE V2 Style */
|
|
|
1330 |
#endif
|
|
|
1331 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1332 |
#define TIMERA0_VECTOR ".int06" /* 0xFFEC Timer A CC0 */
|
|
|
1333 |
#else
|
|
|
1334 |
#define TIMERA0_VECTOR (6 * 1u) /* 0xFFEC Timer A CC0 */
|
|
|
1335 |
/*#define TIMERA0_ISR(func) ISR_VECTOR(func, ".int06") */ /* 0xFFEC Timer A CC0 */ /* CCE V2 Style */
|
|
|
1336 |
#endif
|
|
|
1337 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1338 |
#define ADC12_VECTOR ".int07" /* 0xFFEE ADC */
|
|
|
1339 |
#else
|
|
|
1340 |
#define ADC12_VECTOR (7 * 1u) /* 0xFFEE ADC */
|
|
|
1341 |
/*#define ADC12_ISR(func) ISR_VECTOR(func, ".int07") */ /* 0xFFEE ADC */ /* CCE V2 Style */
|
|
|
1342 |
#endif
|
|
|
1343 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1344 |
#define USART0TX_VECTOR ".int08" /* 0xFFF0 USART 0 Transmit */
|
|
|
1345 |
#else
|
|
|
1346 |
#define USART0TX_VECTOR (8 * 1u) /* 0xFFF0 USART 0 Transmit */
|
|
|
1347 |
/*#define USART0TX_ISR(func) ISR_VECTOR(func, ".int08") */ /* 0xFFF0 USART 0 Transmit */ /* CCE V2 Style */
|
|
|
1348 |
#endif
|
|
|
1349 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1350 |
#define USART0RX_VECTOR ".int09" /* 0xFFF2 USART 0 Receive */
|
|
|
1351 |
#else
|
|
|
1352 |
#define USART0RX_VECTOR (9 * 1u) /* 0xFFF2 USART 0 Receive */
|
|
|
1353 |
/*#define USART0RX_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 USART 0 Receive */ /* CCE V2 Style */
|
|
|
1354 |
#endif
|
|
|
1355 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1356 |
#define WDT_VECTOR ".int10" /* 0xFFF4 Watchdog Timer */
|
|
|
1357 |
#else
|
|
|
1358 |
#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */
|
|
|
1359 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
|
|
|
1360 |
#endif
|
|
|
1361 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1362 |
#define COMPARATORA_VECTOR ".int11" /* 0xFFF6 Comparator A */
|
|
|
1363 |
#else
|
|
|
1364 |
#define COMPARATORA_VECTOR (11 * 1u) /* 0xFFF6 Comparator A */
|
|
|
1365 |
/*#define COMPARATORA_ISR(func) ISR_VECTOR(func, ".int11") */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */
|
|
|
1366 |
#endif
|
|
|
1367 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1368 |
#define TIMERB1_VECTOR ".int12" /* 0xFFF8 Timer B CC1-2, TB */
|
|
|
1369 |
#else
|
|
|
1370 |
#define TIMERB1_VECTOR (12 * 1u) /* 0xFFF8 Timer B CC1-2, TB */
|
|
|
1371 |
/*#define TIMERB1_ISR(func) ISR_VECTOR(func, ".int12") */ /* 0xFFF8 Timer B CC1-2, TB */ /* CCE V2 Style */
|
|
|
1372 |
#endif
|
|
|
1373 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1374 |
#define TIMERB0_VECTOR ".int13" /* 0xFFFA Timer B CC0 */
|
|
|
1375 |
#else
|
|
|
1376 |
#define TIMERB0_VECTOR (13 * 1u) /* 0xFFFA Timer B CC0 */
|
|
|
1377 |
/*#define TIMERB0_ISR(func) ISR_VECTOR(func, ".int13") */ /* 0xFFFA Timer B CC0 */ /* CCE V2 Style */
|
|
|
1378 |
#endif
|
|
|
1379 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1380 |
#define NMI_VECTOR ".int14" /* 0xFFFC Non-maskable */
|
|
|
1381 |
#else
|
|
|
1382 |
#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */
|
|
|
1383 |
/*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
|
|
|
1384 |
#endif
|
|
|
1385 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1386 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
1387 |
#else
|
|
|
1388 |
#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
1389 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
1390 |
#endif
|
|
|
1391 |
|
|
|
1392 |
|
|
|
1393 |
/************************************************************
|
|
|
1394 |
* End of Modules
|
|
|
1395 |
************************************************************/
|
|
|
1396 |
|
|
|
1397 |
#ifdef __cplusplus
|
|
|
1398 |
}
|
|
|
1399 |
#endif /* extern "C" */
|
|
|
1400 |
|
|
|
1401 |
#endif /* #ifndef __msp430xG43x */
|
|
|
1402 |
|