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/******************************************************************************/

/* Legacy Header File                                                         */

/* Not recommended for use in new projects.                                   */

/* Please use the msp430.h file or the device specific header file            */

/******************************************************************************/

/********************************************************************

*

* Standard register and bit definitions for the Texas Instruments

* MSP430 microcontroller.

*

* This file supports assembler and C development for

* MSP430x46x devices.

*

* Texas Instruments, Version 1.0

*

* Rev. 1.0, Setup

*

*

********************************************************************/

#ifndef __msp430x46x

#define __msp430x46x

#ifdef __cplusplus

extern "C" {

#endif

/*----------------------------------------------------------------------------*/

/* PERIPHERAL FILE MAP                                                        */

/*----------------------------------------------------------------------------*/

/* External references resolved by a device-specific linker command file */

#define SFR_8BIT(address)   extern volatile unsigned char address

#define SFR_16BIT(address)  extern volatile unsigned int address

//#define SFR_20BIT(address)  extern volatile unsigned int address

typedef void (* __SFR_FARPTR)();

#define SFR_20BIT(address) extern __SFR_FARPTR address

#define SFR_32BIT(address)  extern volatile unsigned long address

/************************************************************

* STANDARD BITS

************************************************************/

#define BIT0                   (0x0001)

#define BIT1                   (0x0002)

#define BIT2                   (0x0004)

#define BIT3                   (0x0008)

#define BIT4                   (0x0010)

#define BIT5                   (0x0020)

#define BIT6                   (0x0040)

#define BIT7                   (0x0080)

#define BIT8                   (0x0100)

#define BIT9                   (0x0200)

#define BITA                   (0x0400)

#define BITB                   (0x0800)

#define BITC                   (0x1000)

#define BITD                   (0x2000)

#define BITE                   (0x4000)

#define BITF                   (0x8000)

/************************************************************

* STATUS REGISTER BITS

************************************************************/

#define C                      (0x0001)

#define Z                      (0x0002)

#define N                      (0x0004)

#define V                      (0x0100)

#define GIE                    (0x0008)

#define CPUOFF                 (0x0010)

#define OSCOFF                 (0x0020)

#define SCG0                   (0x0040)

#define SCG1                   (0x0080)

/* Low Power Modes coded with Bits 4-7 in SR */

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */

#define LPM0                   (CPUOFF)

#define LPM1                   (SCG0+CPUOFF)

#define LPM2                   (SCG1+CPUOFF)

#define LPM3                   (SCG1+SCG0+CPUOFF)

#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)

/* End #defines for assembler */

#else /* Begin #defines for C */

#define LPM0_bits              (CPUOFF)

#define LPM1_bits              (SCG0+CPUOFF)

#define LPM2_bits              (SCG1+CPUOFF)

#define LPM3_bits              (SCG1+SCG0+CPUOFF)

#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)

#include "in430.h"

#define LPM0         _bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */

#define LPM0_EXIT    _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */

#define LPM1         _bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */

#define LPM1_EXIT    _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */

#define LPM2         _bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */

#define LPM2_EXIT    _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */

#define LPM3         _bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */

#define LPM3_EXIT    _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */

#define LPM4         _bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */

#define LPM4_EXIT    _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */

#endif /* End #defines for C */

/************************************************************

* CPU

************************************************************/

#define __MSP430_HAS_MSP430X_CPU__                /* Definition to show that it has MSP430X CPU */

/************************************************************

* PERIPHERAL FILE MAP

************************************************************/

/************************************************************

* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS

************************************************************/

SFR_8BIT(IE1);                                /* Interrupt Enable 1 */

#define WDTIE                  (0x01)

#define OFIE                   (0x02)

#define NMIIE                  (0x10)

#define ACCVIE                 (0x20)

SFR_8BIT(IFG1);                               /* Interrupt Flag 1 */

#define WDTIFG                 (0x01)

#define OFIFG                  (0x02)

#define NMIIFG                 (0x10)

SFR_8BIT(IE2);                                /* Interrupt Enable 2 */

#define U1IE                   IE2            /* UART1 Interrupt Enable Register */

#define UC0IE                  IE2

#define UCA0RXIE               (0x01)

#define UCA0TXIE               (0x02)

#define UCB0RXIE               (0x04)

#define UCB0TXIE               (0x08)

#define URXIE1                 (0x10)

#define UTXIE1                 (0x20)

#define BTIE                   (0x80)

SFR_8BIT(IFG2);                               /* Interrupt Flag 2 */

#define U1IFG                  IFG2           /* UART1 Interrupt Flag Register */

#define UC0IFG                 IFG2

#define UCA0RXIFG              (0x01)

#define UCA0TXIFG              (0x02)

#define UCB0RXIFG              (0x04)

#define UCB0TXIFG              (0x08)

#define URXIFG1                (0x10)

#define UTXIFG1                (0x20)

#define BTIFG                  (0x80)

SFR_8BIT(ME2);                                /* Module Enable 2 */

#define U1ME                   ME2            /* UART1 Module Enable Register */

#define URXE1                  (0x10)

#define UTXE1                  (0x20)

#define USPIE1                 (0x10)

/************************************************************

* ADC12

************************************************************/

#define __MSP430_HAS_ADC12__                  /* Definition to show that Module is available */

SFR_16BIT(ADC12CTL0);                         /* ADC12 Control 0 */

SFR_16BIT(ADC12CTL1);                         /* ADC12 Control 1 */

SFR_16BIT(ADC12IFG);                          /* ADC12 Interrupt Flag */

SFR_16BIT(ADC12IE);                           /* ADC12 Interrupt Enable */

SFR_16BIT(ADC12IV);                           /* ADC12 Interrupt Vector Word */

#define ADC12MEM_              (0x0140)       /* ADC12 Conversion Memory */

#ifdef __ASM_HEADER__

#define ADC12MEM               (ADC12MEM_)    /* ADC12 Conversion Memory (for assembler) */

#else

#define ADC12MEM               ((int*)        ADC12MEM_) /* ADC12 Conversion Memory (for C) */

#endif

SFR_16BIT(ADC12MEM0);                         /* ADC12 Conversion Memory 0 */

SFR_16BIT(ADC12MEM1);                         /* ADC12 Conversion Memory 1 */

SFR_16BIT(ADC12MEM2);                         /* ADC12 Conversion Memory 2 */

SFR_16BIT(ADC12MEM3);                         /* ADC12 Conversion Memory 3 */

SFR_16BIT(ADC12MEM4);                         /* ADC12 Conversion Memory 4 */

SFR_16BIT(ADC12MEM5);                         /* ADC12 Conversion Memory 5 */

SFR_16BIT(ADC12MEM6);                         /* ADC12 Conversion Memory 6 */

SFR_16BIT(ADC12MEM7);                         /* ADC12 Conversion Memory 7 */

SFR_16BIT(ADC12MEM8);                         /* ADC12 Conversion Memory 8 */

SFR_16BIT(ADC12MEM9);                         /* ADC12 Conversion Memory 9 */

SFR_16BIT(ADC12MEM10);                        /* ADC12 Conversion Memory 10 */

SFR_16BIT(ADC12MEM11);                        /* ADC12 Conversion Memory 11 */

SFR_16BIT(ADC12MEM12);                        /* ADC12 Conversion Memory 12 */

SFR_16BIT(ADC12MEM13);                        /* ADC12 Conversion Memory 13 */

SFR_16BIT(ADC12MEM14);                        /* ADC12 Conversion Memory 14 */

SFR_16BIT(ADC12MEM15);                        /* ADC12 Conversion Memory 15 */

#define ADC12MCTL_             (0x0080)       /* ADC12 Memory Control */

#ifdef __ASM_HEADER__

#define ADC12MCTL              (ADC12MCTL_)   /* ADC12 Memory Control (for assembler) */

#else

#define ADC12MCTL              ((char*)       ADC12MCTL_) /* ADC12 Memory Control (for C) */

#endif

SFR_8BIT(ADC12MCTL0);                         /* ADC12 Memory Control 0 */

SFR_8BIT(ADC12MCTL1);                         /* ADC12 Memory Control 1 */

SFR_8BIT(ADC12MCTL2);                         /* ADC12 Memory Control 2 */

SFR_8BIT(ADC12MCTL3);                         /* ADC12 Memory Control 3 */

SFR_8BIT(ADC12MCTL4);                         /* ADC12 Memory Control 4 */

SFR_8BIT(ADC12MCTL5);                         /* ADC12 Memory Control 5 */

SFR_8BIT(ADC12MCTL6);                         /* ADC12 Memory Control 6 */

SFR_8BIT(ADC12MCTL7);                         /* ADC12 Memory Control 7 */

SFR_8BIT(ADC12MCTL8);                         /* ADC12 Memory Control 8 */

SFR_8BIT(ADC12MCTL9);                         /* ADC12 Memory Control 9 */

SFR_8BIT(ADC12MCTL10);                        /* ADC12 Memory Control 10 */

SFR_8BIT(ADC12MCTL11);                        /* ADC12 Memory Control 11 */

SFR_8BIT(ADC12MCTL12);                        /* ADC12 Memory Control 12 */

SFR_8BIT(ADC12MCTL13);                        /* ADC12 Memory Control 13 */

SFR_8BIT(ADC12MCTL14);                        /* ADC12 Memory Control 14 */

SFR_8BIT(ADC12MCTL15);                        /* ADC12 Memory Control 15 */

/* ADC12CTL0 */

#define ADC12SC                (0x001)        /* ADC12 Start Conversion */

#define ENC                    (0x002)        /* ADC12 Enable Conversion */

#define ADC12TOVIE             (0x004)        /* ADC12 Timer Overflow interrupt enable */

#define ADC12OVIE              (0x008)        /* ADC12 Overflow interrupt enable */

#define ADC12ON                (0x010)        /* ADC12 On/enable */

#define REFON                  (0x020)        /* ADC12 Reference on */

#define REF2_5V                (0x040)        /* ADC12 Ref 0:1.5V / 1:2.5V */

#define MSC                    (0x080)        /* ADC12 Multiple SampleConversion */

#define SHT00                  (0x0100)       /* ADC12 Sample Hold 0 Select 0 */

#define SHT01                  (0x0200)       /* ADC12 Sample Hold 0 Select 1 */

#define SHT02                  (0x0400)       /* ADC12 Sample Hold 0 Select 2 */

#define SHT03                  (0x0800)       /* ADC12 Sample Hold 0 Select 3 */

#define SHT10                  (0x1000)       /* ADC12 Sample Hold 0 Select 0 */

#define SHT11                  (0x2000)       /* ADC12 Sample Hold 1 Select 1 */

#define SHT12                  (0x4000)       /* ADC12 Sample Hold 2 Select 2 */

#define SHT13                  (0x8000)       /* ADC12 Sample Hold 3 Select 3 */

#define MSH                    (0x080)

#define SHT0_0                 (0*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 0 */

#define SHT0_1                 (1*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 1 */

#define SHT0_2                 (2*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 2 */

#define SHT0_3                 (3*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 3 */

#define SHT0_4                 (4*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 4 */

#define SHT0_5                 (5*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 5 */

#define SHT0_6                 (6*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 6 */

#define SHT0_7                 (7*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 7 */

#define SHT0_8                 (8*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 8 */

#define SHT0_9                 (9*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 9 */

#define SHT0_10                (10*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 10 */

#define SHT0_11                (11*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 11 */

#define SHT0_12                (12*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 12 */

#define SHT0_13                (13*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 13 */

#define SHT0_14                (14*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 14 */

#define SHT0_15                (15*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 15 */

#define SHT1_0                 (0*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 0 */

#define SHT1_1                 (1*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 1 */

#define SHT1_2                 (2*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 2 */

#define SHT1_3                 (3*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 3 */

#define SHT1_4                 (4*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 4 */

#define SHT1_5                 (5*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 5 */

#define SHT1_6                 (6*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 6 */

#define SHT1_7                 (7*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 7 */

#define SHT1_8                 (8*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 8 */

#define SHT1_9                 (9*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 9 */

#define SHT1_10                (10*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 10 */

#define SHT1_11                (11*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 11 */

#define SHT1_12                (12*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 12 */

#define SHT1_13                (13*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 13 */

#define SHT1_14                (14*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 14 */

#define SHT1_15                (15*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 15 */

/* ADC12CTL1 */

#define ADC12BUSY              (0x0001)       /* ADC12 Busy */

#define CONSEQ0                (0x0002)       /* ADC12 Conversion Sequence Select 0 */

#define CONSEQ1                (0x0004)       /* ADC12 Conversion Sequence Select 1 */

#define ADC12SSEL0             (0x0008)       /* ADC12 Clock Source Select 0 */

#define ADC12SSEL1             (0x0010)       /* ADC12 Clock Source Select 1 */

#define ADC12DIV0              (0x0020)       /* ADC12 Clock Divider Select 0 */

#define ADC12DIV1              (0x0040)       /* ADC12 Clock Divider Select 1 */

#define ADC12DIV2              (0x0080)       /* ADC12 Clock Divider Select 2 */

#define ISSH                   (0x0100)       /* ADC12 Invert Sample Hold Signal */

#define SHP                    (0x0200)       /* ADC12 Sample/Hold Pulse Mode */

#define SHS0                   (0x0400)       /* ADC12 Sample/Hold Source 0 */

#define SHS1                   (0x0800)       /* ADC12 Sample/Hold Source 1 */

#define CSTARTADD0             (0x1000)       /* ADC12 Conversion Start Address 0 */

#define CSTARTADD1             (0x2000)       /* ADC12 Conversion Start Address 1 */

#define CSTARTADD2             (0x4000)       /* ADC12 Conversion Start Address 2 */

#define CSTARTADD3             (0x8000)       /* ADC12 Conversion Start Address 3 */

#define CONSEQ_0               (0*2u)         /* ADC12 Conversion Sequence Select: 0 */

#define CONSEQ_1               (1*2u)         /* ADC12 Conversion Sequence Select: 1 */

#define CONSEQ_2               (2*2u)         /* ADC12 Conversion Sequence Select: 2 */

#define CONSEQ_3               (3*2u)         /* ADC12 Conversion Sequence Select: 3 */

#define ADC12SSEL_0            (0*8u)         /* ADC12 Clock Source Select: 0 */

#define ADC12SSEL_1            (1*8u)         /* ADC12 Clock Source Select: 1 */

#define ADC12SSEL_2            (2*8u)         /* ADC12 Clock Source Select: 2 */

#define ADC12SSEL_3            (3*8u)         /* ADC12 Clock Source Select: 3 */

#define ADC12DIV_0             (0*0x20u)      /* ADC12 Clock Divider Select: 0 */

#define ADC12DIV_1             (1*0x20u)      /* ADC12 Clock Divider Select: 1 */

#define ADC12DIV_2             (2*0x20u)      /* ADC12 Clock Divider Select: 2 */

#define ADC12DIV_3             (3*0x20u)      /* ADC12 Clock Divider Select: 3 */

#define ADC12DIV_4             (4*0x20u)      /* ADC12 Clock Divider Select: 4 */

#define ADC12DIV_5             (5*0x20u)      /* ADC12 Clock Divider Select: 5 */

#define ADC12DIV_6             (6*0x20u)      /* ADC12 Clock Divider Select: 6 */

#define ADC12DIV_7             (7*0x20u)      /* ADC12 Clock Divider Select: 7 */

#define SHS_0                  (0*0x400u)     /* ADC12 Sample/Hold Source: 0 */

#define SHS_1                  (1*0x400u)     /* ADC12 Sample/Hold Source: 1 */

#define SHS_2                  (2*0x400u)     /* ADC12 Sample/Hold Source: 2 */

#define SHS_3                  (3*0x400u)     /* ADC12 Sample/Hold Source: 3 */

#define CSTARTADD_0            (0*0x1000u)    /* ADC12 Conversion Start Address: 0 */

#define CSTARTADD_1            (1*0x1000u)    /* ADC12 Conversion Start Address: 1 */

#define CSTARTADD_2            (2*0x1000u)    /* ADC12 Conversion Start Address: 2 */

#define CSTARTADD_3            (3*0x1000u)    /* ADC12 Conversion Start Address: 3 */

#define CSTARTADD_4            (4*0x1000u)    /* ADC12 Conversion Start Address: 4 */

#define CSTARTADD_5            (5*0x1000u)    /* ADC12 Conversion Start Address: 5 */

#define CSTARTADD_6            (6*0x1000u)    /* ADC12 Conversion Start Address: 6 */

#define CSTARTADD_7            (7*0x1000u)    /* ADC12 Conversion Start Address: 7 */

#define CSTARTADD_8            (8*0x1000u)    /* ADC12 Conversion Start Address: 8 */

#define CSTARTADD_9            (9*0x1000u)    /* ADC12 Conversion Start Address: 9 */

#define CSTARTADD_10           (10*0x1000u)   /* ADC12 Conversion Start Address: 10 */

#define CSTARTADD_11           (11*0x1000u)   /* ADC12 Conversion Start Address: 11 */

#define CSTARTADD_12           (12*0x1000u)   /* ADC12 Conversion Start Address: 12 */

#define CSTARTADD_13           (13*0x1000u)   /* ADC12 Conversion Start Address: 13 */

#define CSTARTADD_14           (14*0x1000u)   /* ADC12 Conversion Start Address: 14 */

#define CSTARTADD_15           (15*0x1000u)   /* ADC12 Conversion Start Address: 15 */

/* ADC12MCTLx */

#define INCH0                  (0x0001)       /* ADC12 Input Channel Select Bit 0 */

#define INCH1                  (0x0002)       /* ADC12 Input Channel Select Bit 1 */

#define INCH2                  (0x0004)       /* ADC12 Input Channel Select Bit 2 */

#define INCH3                  (0x0008)       /* ADC12 Input Channel Select Bit 3 */

#define SREF0                  (0x0010)       /* ADC12 Select Reference Bit 0 */

#define SREF1                  (0x0020)       /* ADC12 Select Reference Bit 1 */

#define SREF2                  (0x0040)       /* ADC12 Select Reference Bit 2 */

#define EOS                    (0x0080)       /* ADC12 End of Sequence */

#define INCH_0                 (0)            /* ADC12 Input Channel 0 */

#define INCH_1                 (1)            /* ADC12 Input Channel 1 */

#define INCH_2                 (2)            /* ADC12 Input Channel 2 */

#define INCH_3                 (3)            /* ADC12 Input Channel 3 */

#define INCH_4                 (4)            /* ADC12 Input Channel 4 */

#define INCH_5                 (5)            /* ADC12 Input Channel 5 */

#define INCH_6                 (6)            /* ADC12 Input Channel 6 */

#define INCH_7                 (7)            /* ADC12 Input Channel 7 */

#define INCH_8                 (8)            /* ADC12 Input Channel 8 */

#define INCH_9                 (9)            /* ADC12 Input Channel 9 */

#define INCH_10                (10)           /* ADC12 Input Channel 10 */

#define INCH_11                (11)           /* ADC12 Input Channel 11 */

#define INCH_12                (12)           /* ADC12 Input Channel 12 */

#define INCH_13                (13)           /* ADC12 Input Channel 13 */

#define INCH_14                (14)           /* ADC12 Input Channel 14 */

#define INCH_15                (15)           /* ADC12 Input Channel 15 */

#define SREF_0                 (0*0x10u)      /* ADC12 Select Reference 0 */

#define SREF_1                 (1*0x10u)      /* ADC12 Select Reference 1 */

#define SREF_2                 (2*0x10u)      /* ADC12 Select Reference 2 */

#define SREF_3                 (3*0x10u)      /* ADC12 Select Reference 3 */

#define SREF_4                 (4*0x10u)      /* ADC12 Select Reference 4 */

#define SREF_5                 (5*0x10u)      /* ADC12 Select Reference 5 */

#define SREF_6                 (6*0x10u)      /* ADC12 Select Reference 6 */

#define SREF_7                 (7*0x10u)      /* ADC12 Select Reference 7 */

/* ADC12IV Definitions */

#define ADC12IV_NONE           (0x0000)       /* No Interrupt pending */

#define ADC12IV_ADC12OVIFG     (0x0002)       /* ADC12OVIFG */

#define ADC12IV_ADC12TOVIFG    (0x0004)       /* ADC12TOVIFG */

#define ADC12IV_ADC12IFG0      (0x0006)       /* ADC12IFG0 */

#define ADC12IV_ADC12IFG1      (0x0008)       /* ADC12IFG1 */

#define ADC12IV_ADC12IFG2      (0x000A)       /* ADC12IFG2 */

#define ADC12IV_ADC12IFG3      (0x000C)       /* ADC12IFG3 */

#define ADC12IV_ADC12IFG4      (0x000E)       /* ADC12IFG4 */

#define ADC12IV_ADC12IFG5      (0x0010)       /* ADC12IFG5 */

#define ADC12IV_ADC12IFG6      (0x0012)       /* ADC12IFG6 */

#define ADC12IV_ADC12IFG7      (0x0014)       /* ADC12IFG7 */

#define ADC12IV_ADC12IFG8      (0x0016)       /* ADC12IFG8 */

#define ADC12IV_ADC12IFG9      (0x0018)       /* ADC12IFG9 */

#define ADC12IV_ADC12IFG10     (0x001A)       /* ADC12IFG10 */

#define ADC12IV_ADC12IFG11     (0x001C)       /* ADC12IFG11 */

#define ADC12IV_ADC12IFG12     (0x001E)       /* ADC12IFG12 */

#define ADC12IV_ADC12IFG13     (0x0020)       /* ADC12IFG13 */

#define ADC12IV_ADC12IFG14     (0x0022)       /* ADC12IFG14 */

#define ADC12IV_ADC12IFG15     (0x0024)       /* ADC12IFG15 */

/************************************************************

* BASIC TIMER with Real Time Clock

************************************************************/

#define __MSP430_HAS_BT_RTC__                 /* Definition to show that Module is available */

SFR_8BIT(BTCTL);                              /* Basic Timer Control */

SFR_8BIT(RTCCTL);                             /* Real Time Clock Control */

SFR_8BIT(RTCNT1);                             /* Real Time Counter 1 */

SFR_8BIT(RTCNT2);                             /* Real Time Counter 2 */

SFR_8BIT(RTCNT3);                             /* Real Time Counter 3 */

SFR_8BIT(RTCNT4);                             /* Real Time Counter 4 */

SFR_8BIT(BTCNT1);                             /* Basic Timer Count 1 */

SFR_8BIT(BTCNT2);                             /* Basic Timer Count 2 */

SFR_8BIT(RTCDAY);                             /* Real Time Clock Day */

SFR_8BIT(RTCMON);                             /* Real Time Clock Month */

SFR_8BIT(RTCYEARL);                           /* Real Time Clock Year (Low Byte) */

SFR_8BIT(RTCYEARH);                           /* Real Time Clock Year (High Byte) */

#define RTCSEC                 RTCNT1

#define RTCMIN                 RTCNT2

#define RTCHOUR                RTCNT3

#define RTCDOW                 RTCNT4

SFR_16BIT(RTCTL);                             /* Basic/Real Timer Control */

SFR_16BIT(RTCTIM0);                           /* Real Time Clock Time 0 */

SFR_16BIT(RTCTIM1);                           /* Real Time Clock Time 1 */

SFR_16BIT(BTCNT12);                           /* Basic Timer Count 1/2 */

SFR_16BIT(RTCDATE);                           /* Real Time Clock Date */

SFR_16BIT(RTCYEAR);                           /* Real Time Clock Year */

#define RTCNT12                RTCTIM0

#define RTCNT34                RTCTIM1

#define BTSSEL                 (0x80)         /* fBT = fMCLK (main clock) */

#define BTHOLD                 (0x40)         /* BT1 is held if this bit is set */

#define BTDIV                  (0x20)         /* fCLK2 = ACLK:256 */

//#define res               (0x10)

//#define res               (0x08)

#define BTIP2                  (0x04)

#define BTIP1                  (0x02)

#define BTIP0                  (0x01)

#define RTCBCD                 (0x80)         /* RTC BCD Select */

#define RTCHOLD                (0x40)         /* RTC Hold */

#define RTCMODE1               (0x20)         /* RTC Mode 1 */

#define RTCMODE0               (0x10)         /* RTC Mode 0 */

#define RTCTEV1                (0x08)         /* RTC Time Event 1 */

#define RTCTEV0                (0x04)         /* RTC Time Event 0 */

#define RTCIE                  (0x02)         /* RTC Interrupt Enable */

#define RTCFG                  (0x01)         /* RTC Event Flag */

#define RTCTEV_0               (0x00)         /* RTC Time Event: 0 */

#define RTCTEV_1               (0x04)         /* RTC Time Event: 1 */

#define RTCTEV_2               (0x08)         /* RTC Time Event: 2 */

#define RTCTEV_3               (0x0C)         /* RTC Time Event: 3 */

#define RTCMODE_0              (0x00)         /* RTC Mode: 0 */

#define RTCMODE_1              (0x10)         /* RTC Mode: 1 */

#define RTCMODE_2              (0x20)         /* RTC Mode: 2 */

#define RTCMODE_3              (0x30)         /* RTC Mode: 3 */

/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */

#define BT_fCLK2_ACLK          (0x00)

#define BT_fCLK2_ACLK_DIV256   (BTDIV)

#define BT_fCLK2_MCLK          (BTSSEL)

/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */

#define BT_fCLK2_DIV2          (0x00)         /* fINT = fCLK2:2 (default) */

#define BT_fCLK2_DIV4          (BTIP0)        /* fINT = fCLK2:4 */

#define BT_fCLK2_DIV8          (BTIP1)        /* fINT = fCLK2:8 */

#define BT_fCLK2_DIV16         (BTIP1+BTIP0)  /* fINT = fCLK2:16 */

#define BT_fCLK2_DIV32         (BTIP2)        /* fINT = fCLK2:32 */

#define BT_fCLK2_DIV64         (BTIP2+BTIP0)  /* fINT = fCLK2:64 */

#define BT_fCLK2_DIV128        (BTIP2+BTIP1)  /* fINT = fCLK2:128 */

#define BT_fCLK2_DIV256     (BTIP2+BTIP1+BTIP0)       /* fINT = fCLK2:256 */

/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */

/* fBT=fACLK is thought for longer interval times */

#define BT_ADLY_0_064          (0x00)         /* 0.064ms interval (default) */

#define BT_ADLY_0_125          (BTIP0)        /* 0.125ms    " */

#define BT_ADLY_0_25           (BTIP1)        /* 0.25ms     " */

#define BT_ADLY_0_5            (BTIP1+BTIP0)  /* 0.5ms      " */

#define BT_ADLY_1              (BTIP2)        /* 1ms        " */

#define BT_ADLY_2              (BTIP2+BTIP0)  /* 2ms        " */

#define BT_ADLY_4              (BTIP2+BTIP1)  /* 4ms        " */

#define BT_ADLY_8           (BTIP2+BTIP1+BTIP0)       /* 8ms        " */

#define BT_ADLY_16             (BTDIV)        /* 16ms       " */

#define BT_ADLY_32             (BTDIV+BTIP0)  /* 32ms       " */

#define BT_ADLY_64             (BTDIV+BTIP1)  /* 64ms       " */

#define BT_ADLY_125         (BTDIV+BTIP1+BTIP0)       /* 125ms      " */

#define BT_ADLY_250            (BTDIV+BTIP2)  /* 250ms      " */

#define BT_ADLY_500         (BTDIV+BTIP2+BTIP0)       /* 500ms      " */

#define BT_ADLY_1000        (BTDIV+BTIP2+BTIP1)       /* 1000ms     " */

#define BT_ADLY_2000        (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms     " */

/* fCLK2=fMCLK (1MHz) is thought for short interval times */

/* the timing for short intervals is more precise than ACLK */

/* NOTE */

/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */

/* Too low interval time results in interrupts too frequent for the processor to handle! */

#define BT_MDLY_0_002          (BTSSEL)       /* 0.002ms interval       *** interval times */

#define BT_MDLY_0_004          (BTSSEL+BTIP0) /* 0.004ms    "           *** too short for */

#define BT_MDLY_0_008          (BTSSEL+BTIP1) /* 0.008ms    "           *** interrupt */

#define BT_MDLY_0_016       (BTSSEL+BTIP1+BTIP0)      /* 0.016ms    "           *** handling */

#define BT_MDLY_0_032          (BTSSEL+BTIP2) /* 0.032ms    " */

#define BT_MDLY_0_064       (BTSSEL+BTIP2+BTIP0)      /* 0.064ms    " */

#define BT_MDLY_0_125       (BTSSEL+BTIP2+BTIP1)      /* 0.125ms    " */

#define BT_MDLY_0_25        (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms     " */

/* Hold coded with Bits 6-7 in BT(1)CTL */

/* this is for BT */

#define BTHOLD_CNT1            (BTHOLD)       /* BTCNT1 is held while BTHOLD is set */

#define BTHOLD_CNT1_2          (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */

/* INTERRUPT CONTROL BITS */

/* #define BTIE                0x80 */

/* #define BTIFG               0x80 */

/************************************************************

* Comparator A

************************************************************/

#define __MSP430_HAS_COMPA__                  /* Definition to show that Module is available */

SFR_8BIT(CACTL1);                             /* Comparator A Control 1 */

SFR_8BIT(CACTL2);                             /* Comparator A Control 2 */

SFR_8BIT(CAPD);                               /* Comparator A Port Disable */

#define CAIFG                  (0x01)         /* Comp. A Interrupt Flag */

#define CAIE                   (0x02)         /* Comp. A Interrupt Enable */

#define CAIES                  (0x04)         /* Comp. A Int. Edge Select: 0:rising / 1:falling */

#define CAON                   (0x08)         /* Comp. A enable */

#define CAREF0                 (0x10)         /* Comp. A Internal Reference Select 0 */

#define CAREF1                 (0x20)         /* Comp. A Internal Reference Select 1 */

#define CARSEL                 (0x40)         /* Comp. A Internal Reference Enable */

#define CAEX                   (0x80)         /* Comp. A Exchange Inputs */

#define CAREF_0                (0x00)         /* Comp. A Int. Ref. Select 0 : Off */

#define CAREF_1                (0x10)         /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */

#define CAREF_2                (0x20)         /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */

#define CAREF_3                (0x30)         /* Comp. A Int. Ref. Select 3 : Vt*/

#define CAOUT                  (0x01)         /* Comp. A Output */

#define CAF                    (0x02)         /* Comp. A Enable Output Filter */

#define P2CA0                  (0x04)         /* Comp. A Connect External Signal to CA0 : 1 */

#define P2CA1                  (0x08)         /* Comp. A Connect External Signal to CA1 : 1 */

#define CACTL24                (0x10)

#define CACTL25                (0x20)

#define CACTL26                (0x40)

#define CACTL27                (0x80)

#define CAPD0                  (0x01)         /* Comp. A Disable Input Buffer of Port Register .0 */

#define CAPD1                  (0x02)         /* Comp. A Disable Input Buffer of Port Register .1 */

#define CAPD2                  (0x04)         /* Comp. A Disable Input Buffer of Port Register .2 */

#define CAPD3                  (0x08)         /* Comp. A Disable Input Buffer of Port Register .3 */

#define CAPD4                  (0x10)         /* Comp. A Disable Input Buffer of Port Register .4 */

#define CAPD5                  (0x20)         /* Comp. A Disable Input Buffer of Port Register .5 */

#define CAPD6                  (0x40)         /* Comp. A Disable Input Buffer of Port Register .6 */

#define CAPD7                  (0x80)         /* Comp. A Disable Input Buffer of Port Register .7 */

/************************************************************

* DMA_X

************************************************************/

#define __MSP430_HAS_DMAX_3__                 /* Definition to show that Module is available */

SFR_16BIT(DMACTL0);                           /* DMA Module Control 0 */

#define DMA0TSEL0              (0x0001)       /* DMA channel 0 transfer select bit 0 */

#define DMA0TSEL1              (0x0002)       /* DMA channel 0 transfer select bit 1 */

#define DMA0TSEL2              (0x0004)       /* DMA channel 0 transfer select bit 2 */

#define DMA0TSEL3              (0x0008)       /* DMA channel 0 transfer select bit 3 */

#define DMA1TSEL0              (0x0010)       /* DMA channel 1 transfer select bit 0 */

#define DMA1TSEL1              (0x0020)       /* DMA channel 1 transfer select bit 1 */

#define DMA1TSEL2              (0x0040)       /* DMA channel 1 transfer select bit 2 */

#define DMA1TSEL3              (0x0080)       /* DMA channel 1 transfer select bit 3 */

#define DMA2TSEL0              (0x0100)       /* DMA channel 2 transfer select bit 0 */

#define DMA2TSEL1              (0x0200)       /* DMA channel 2 transfer select bit 1 */

#define DMA2TSEL2              (0x0400)       /* DMA channel 2 transfer select bit 2 */

#define DMA2TSEL3              (0x0800)       /* DMA channel 2 transfer select bit 3 */

#define DMA0TSEL_0             (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw)*/

#define DMA0TSEL_1             (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer_A (TACCR2.IFG) */

#define DMA0TSEL_2             (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer_B (TBCCR2.IFG) */

#define DMA0TSEL_3             (3*0x0001u)    /* DMA channel 0 transfer select 3:  USCIA receive */

#define DMA0TSEL_4             (4*0x0001u)    /* DMA channel 0 transfer select 4:  USCIA transmit */

#define DMA0TSEL_5             (5*0x0001u)    /* DMA channel 0 transfer select 5:  DAC12_0CTL.DAC12IFG */

#define DMA0TSEL_6             (6*0x0001u)    /* DMA channel 0 transfer select 6:  ADC12 (ADC12IFG) */

#define DMA0TSEL_7             (7*0x0001u)    /* DMA channel 0 transfer select 7:  Timer_A (TACCR0.IFG) */

#define DMA0TSEL_8             (8*0x0001u)    /* DMA channel 0 transfer select 8:  Timer_B (TBCCR0.IFG) */

#define DMA0TSEL_9             (9*0x0001u)    /* DMA channel 0 transfer select 9:  UART1 receive */

#define DMA0TSEL_10            (10*0x0001u)   /* DMA channel 0 transfer select 10: UART1 transmit */

#define DMA0TSEL_11            (11*0x0001u)   /* DMA channel 0 transfer select 11: Multiplier ready */

#define DMA0TSEL_12            (12*0x0001u)   /* DMA channel 0 transfer select 12: USCIB receive */

#define DMA0TSEL_13            (13*0x0001u)   /* DMA channel 0 transfer select 13: USCIB transmit */

#define DMA0TSEL_14            (14*0x0001u)   /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */

#define DMA0TSEL_15            (15*0x0001u)   /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */

#define DMA1TSEL_0             (0*0x0010u)    /* DMA channel 1 transfer select 0:  DMA_REQ */

#define DMA1TSEL_1             (1*0x0010u)    /* DMA channel 1 transfer select 1:  Timer_A CCRIFG.2 */

#define DMA1TSEL_2             (2*0x0010u)    /* DMA channel 1 transfer select 2:  Timer_B CCRIFG.2 */

#define DMA1TSEL_3             (3*0x0010u)    /* DMA channel 1 transfer select 3:  USCIA receive */

#define DMA1TSEL_4             (4*0x0010u)    /* DMA channel 1 transfer select 4:  USCIA transmit */

#define DMA1TSEL_5             (5*0x0010u)    /* DMA channel 1 transfer select 5:  DAC12.0IFG */

#define DMA1TSEL_6             (6*0x0010u)    /* DMA channel 1 transfer select 6:  ADC12 (ADC12IFG) */

#define DMA1TSEL_7             (7*0x0010u)    /* DMA channel 1 transfer select 7:  Timer_A (TACCR0.IFG) */

#define DMA1TSEL_8             (8*0x0010u)    /* DMA channel 1 transfer select 8:  Timer_B (TBCCR0.IFG) */

#define DMA1TSEL_9             (9*0x0010u)    /* DMA channel 1 transfer select 9:  UART1 receive */

#define DMA1TSEL_10            (10*0x0010u)   /* DMA channel 1 transfer select 10: UART1 transmit */

#define DMA1TSEL_11            (11*0x0010u)   /* DMA channel 1 transfer select 11: Multiplier ready */

#define DMA1TSEL_12            (12*0x0010u)   /* DMA channel 1 transfer select 12: USCIB receive */

#define DMA1TSEL_13            (13*0x0010u)   /* DMA channel 1 transfer select 13: USCIB transmit */

#define DMA1TSEL_14            (14*0x0010u)   /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */

#define DMA1TSEL_15            (15*0x0010u)   /* DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */

#define DMA2TSEL_0             (0*0x0100u)    /* DMA channel 2 transfer select 0:  DMA_REQ */

#define DMA2TSEL_1             (1*0x0100u)    /* DMA channel 2 transfer select 1:  Timer_A CCRIFG.2 */

#define DMA2TSEL_2             (2*0x0100u)    /* DMA channel 2 transfer select 2:  Timer_B CCRIFG.2 */

#define DMA2TSEL_3             (3*0x0100u)    /* DMA channel 2 transfer select 3:  USCIA receive */

#define DMA2TSEL_4             (4*0x0100u)    /* DMA channel 2 transfer select 4:  USCIA transmit */

#define DMA2TSEL_5             (5*0x0100u)    /* DMA channel 2 transfer select 5:  DAC12.0IFG */

#define DMA2TSEL_6             (6*0x0100u)    /* DMA channel 2 transfer select 6:  ADC12 (ADC12IFG) */

#define DMA2TSEL_7             (7*0x0100u)    /* DMA channel 2 transfer select 7:  Timer_A (TACCR0.IFG) */

#define DMA2TSEL_8             (8*0x0100u)    /* DMA channel 2 transfer select 8:  Timer_B (TBCCR0.IFG) */

#define DMA2TSEL_9             (9*0x0100u)    /* DMA channel 2 transfer select 9:  UART1 receive */

#define DMA2TSEL_10            (10*0x0100u)   /* DMA channel 2 transfer select 10: UART1 transmit */

#define DMA2TSEL_11            (11*0x0100u)   /* DMA channel 2 transfer select 11: Multiplier ready */

#define DMA2TSEL_12            (12*0x0100u)   /* DMA channel 2 transfer select 12: USCIB receive */

#define DMA2TSEL_13            (13*0x0100u)   /* DMA channel 2 transfer select 13: USCIB transmit */

#define DMA2TSEL_14            (14*0x0100u)   /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */

#define DMA2TSEL_15            (15*0x0100u)   /* DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */

SFR_16BIT(DMACTL1);                           /* DMA Module Control 1 */

#define ENNMI                  (0x0001)       /* Enable NMI interruption of DMA */

#define ROUNDROBIN             (0x0002)       /* Round-Robin DMA channel priorities */

#define DMAONFETCH             (0x0004)       /* DMA transfer on instruction fetch */

SFR_16BIT(DMAIV);                             /* DMA Interrupt Vector Word */

SFR_16BIT(DMA0CTL);                           /* DMA Channel 0 Control */

SFR_16BIT(DMA1CTL);                           /* DMA Channel 1 Control */

SFR_16BIT(DMA2CTL);                           /* DMA Channel 2 Control */

#define DMAREQ                 (0x0001)       /* Initiate DMA transfer with DMATSEL */

#define DMAABORT               (0x0002)       /* DMA transfer aborted by NMI */

#define DMAIE                  (0x0004)       /* DMA interrupt enable */

#define DMAIFG                 (0x0008)       /* DMA interrupt flag */

#define DMAEN                  (0x0010)       /* DMA enable */

#define DMALEVEL               (0x0020)       /* DMA level sensitive trigger select */

#define DMASRCBYTE             (0x0040)       /* DMA source byte */

#define DMADSTBYTE             (0x0080)       /* DMA destination byte */

#define DMASRCINCR0            (0x0100)       /* DMA source increment bit 0 */

#define DMASRCINCR1            (0x0200)       /* DMA source increment bit 1 */

#define DMADSTINCR0            (0x0400)       /* DMA destination increment bit 0 */

#define DMADSTINCR1            (0x0800)       /* DMA destination increment bit 1 */

#define DMADT0                 (0x1000)       /* DMA transfer mode bit 0 */

#define DMADT1                 (0x2000)       /* DMA transfer mode bit 1 */

#define DMADT2                 (0x4000)       /* DMA transfer mode bit 2 */

#define DMASWDW                (0*0x0040u)    /* DMA transfer: source word to destination word */

#define DMASBDW                (1*0x0040u)    /* DMA transfer: source byte to destination word */

#define DMASWDB                (2*0x0040u)    /* DMA transfer: source word to destination byte */

#define DMASBDB                (3*0x0040u)    /* DMA transfer: source byte to destination byte */

#define DMASRCINCR_0           (0*0x0100u)    /* DMA source increment 0: source address unchanged */

#define DMASRCINCR_1           (1*0x0100u)    /* DMA source increment 1: source address unchanged */

#define DMASRCINCR_2           (2*0x0100u)    /* DMA source increment 2: source address decremented */

#define DMASRCINCR_3           (3*0x0100u)    /* DMA source increment 3: source address incremented */

#define DMADSTINCR_0           (0*0x0400u)    /* DMA destination increment 0: destination address unchanged */

#define DMADSTINCR_1           (1*0x0400u)    /* DMA destination increment 1: destination address unchanged */

#define DMADSTINCR_2           (2*0x0400u)    /* DMA destination increment 2: destination address decremented */

#define DMADSTINCR_3           (3*0x0400u)    /* DMA destination increment 3: destination address incremented */

#define DMADT_0                (0*0x1000u)    /* DMA transfer mode 0: single */

#define DMADT_1                (1*0x1000u)    /* DMA transfer mode 1: block */

#define DMADT_2                (2*0x1000u)    /* DMA transfer mode 2: interleaved */

#define DMADT_3                (3*0x1000u)    /* DMA transfer mode 3: interleaved */

#define DMADT_4                (4*0x1000u)    /* DMA transfer mode 4: single, repeat */

#define DMADT_5                (5*0x1000u)    /* DMA transfer mode 5: block, repeat */

#define DMADT_6                (6*0x1000u)    /* DMA transfer mode 6: interleaved, repeat */

#define DMADT_7                (7*0x1000u)    /* DMA transfer mode 7: interleaved, repeat */

SFR_20BIT(DMA0SA);                            /* DMA Channel 0 Source Address */

SFR_16BIT(DMA0SAL);                           /* DMA Channel 0 Source Address */

SFR_20BIT(DMA0DA);                            /* DMA Channel 0 Destination Address */

SFR_16BIT(DMA0DAL);                           /* DMA Channel 0 Destination Address */

SFR_16BIT(DMA0SZ);                            /* DMA Channel 0 Transfer Size */

SFR_20BIT(DMA1SA);                            /* DMA Channel 1 Source Address */

SFR_16BIT(DMA1SAL);                           /* DMA Channel 1 Source Address */

SFR_20BIT(DMA1DA);                            /* DMA Channel 1 Destination Address */

SFR_16BIT(DMA1DAL);                           /* DMA Channel 1 Destination Address */

SFR_16BIT(DMA1SZ);                            /* DMA Channel 1 Transfer Size */

SFR_20BIT(DMA2SA);                            /* DMA Channel 2 Source Address */

SFR_16BIT(DMA2SAL);                           /* DMA Channel 2 Source Address */

SFR_20BIT(DMA2DA);                            /* DMA Channel 2 Destination Address */

SFR_16BIT(DMA2DAL);                           /* DMA Channel 2 Destination Address */

SFR_16BIT(DMA2SZ);                            /* DMA Channel 2 Transfer Size */

/* DMAIV Definitions */

#define DMAIV_NONE             (0x0000)       /* No Interrupt pending */

#define DMAIV_DMA0IFG          (0x0002)       /* DMA0IFG */

#define DMAIV_DMA1IFG          (0x0004)       /* DMA1IFG */

#define DMAIV_DMA2IFG          (0x0006)       /* DMA2IFG */

/*************************************************************

* Flash Memory

*************************************************************/

#define __MSP430_HAS_FLASH__                  /* Definition to show that Module is available */

#define __MSP430_HAS_2FLASH_IP__                /* Definition to show that Module is available */

SFR_16BIT(FCTL1);                             /* FLASH Control 1 */

SFR_16BIT(FCTL2);                             /* FLASH Control 2 */

SFR_16BIT(FCTL3);                             /* FLASH Control 3 */

#define FRKEY                  (0x9600)       /* Flash key returned by read */

#define FWKEY                  (0xA500)       /* Flash key for write */

#define FXKEY                  (0x3300)       /* for use with XOR instruction */

#define ERASE                  (0x0002)       /* Enable bit for Flash segment erase */

#define MERAS                  (0x0004)       /* Enable bit for Flash mass erase */

#define GMERAS                 (0x0008)       /* Enable bit for Flash global mass erase */

#define CPUEX                  (0x0010)       /* Enable bit for CPU Execution during Flash write/erase */

#define WRT                    (0x0040)       /* Enable bit for Flash write */

#define BLKWRT                 (0x0080)       /* Enable bit for Flash segment write */

#define SEGWRT                 (0x0080)       /* old definition */ /* Enable bit for Flash segment write */

#define FN0                    (0x0001)       /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */

#define FN1                    (0x0002)       /*  32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */

#ifndef FN2

#define FN2                    (0x0004)

#endif

#ifndef FN3

#define FN3                    (0x0008)

#endif

#ifndef FN4

#define FN4                    (0x0010)

#endif

#define FN5                    (0x0020)

#define FSSEL0                 (0x0040)       /* Flash clock select 0 */        /* to distinguish from USART SSELx */

#define FSSEL1                 (0x0080)       /* Flash clock select 1 */

#define FSSEL_0                (0x0000)       /* Flash clock select: 0 - ACLK */

#define FSSEL_1                (0x0040)       /* Flash clock select: 1 - MCLK */

#define FSSEL_2                (0x0080)       /* Flash clock select: 2 - SMCLK */

#define FSSEL_3                (0x00C0)       /* Flash clock select: 3 - SMCLK */

#define BUSY                   (0x0001)       /* Flash busy: 1 */

#define KEYV                   (0x0002)       /* Flash Key violation flag */

#define ACCVIFG                (0x0004)       /* Flash Access violation flag */

#define WAIT                   (0x0008)       /* Wait flag for segment write */

#define LOCK                   (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */

#define EMEX                   (0x0020)       /* Flash Emergency Exit */

/************************************************************

* SYSTEM CLOCK, FLL+

************************************************************/

#define __MSP430_HAS_FLLPLUS__                /* Definition to show that Module is available */

SFR_8BIT(SCFI0);                              /* System Clock Frequency Integrator 0 */

#define FN_2                   (0x04)         /* fDCOCLK =   1.4-12MHz*/

#define FN_3                   (0x08)         /* fDCOCLK =   2.2-17Mhz*/

#define FN_4                   (0x10)         /* fDCOCLK =   3.2-25Mhz*/

#define FN_8                   (0x20)         /* fDCOCLK =     5-40Mhz*/

#define FLLD0                  (0x40)         /* Loop Divider Bit : 0 */

#define FLLD1                  (0x80)         /* Loop Divider Bit : 1 */

#define FLLD_1                 (0x00)         /* Multiply Selected Loop Freq. By 1 */

#define FLLD_2                 (0x40)         /* Multiply Selected Loop Freq. By 2 */

#define FLLD_4                 (0x80)         /* Multiply Selected Loop Freq. By 4 */

#define FLLD_8                 (0xC0)         /* Multiply Selected Loop Freq. By 8 */

SFR_8BIT(SCFI1);                              /* System Clock Frequency Integrator 1 */

SFR_8BIT(SCFQCTL);                            /* System Clock Frequency Control */

/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */

/* #define SCFQ_32K            0x00                        fMCLK=1*fACLK       only a range from */

#define SCFQ_64K               (0x01)         /* fMCLK=2*fACLK          1+1 to 127+1 is possible */

#define SCFQ_128K              (0x03)         /* fMCLK=4*fACLK */

#define SCFQ_256K              (0x07)         /* fMCLK=8*fACLK */

#define SCFQ_512K              (0x0F)         /* fMCLK=16*fACLK */

#define SCFQ_1M                (0x1F)         /* fMCLK=32*fACLK */

#define SCFQ_2M                (0x3F)         /* fMCLK=64*fACLK */

#define SCFQ_4M                (0x7F)         /* fMCLK=128*fACLK */

#define SCFQ_M                 (0x80)         /* Modulation Disable */

SFR_8BIT(FLL_CTL0);                           /* FLL+ Control 0 */

#define DCOF                   (0x01)         /* DCO Fault Flag */

#define LFOF                   (0x02)         /* Low Frequency Oscillator Fault Flag */

#define XT1OF                  (0x04)         /* High Frequency Oscillator 1 Fault Flag */

#define XT2OF                  (0x08)         /* High Frequency Oscillator 2 Fault Flag */

#define OSCCAP0                (0x10)         /* XIN/XOUT Cap 0 */

#define OSCCAP1                (0x20)         /* XIN/XOUT Cap 1 */

#define XTS_FLL                (0x40)         /* 1: Selects high-freq. oscillator */

#define DCOPLUS                (0x80)         /* DCO+ Enable */

#define XCAP0PF                (0x00)         /* XIN Cap = XOUT Cap = 0pf */

#define XCAP10PF               (0x10)         /* XIN Cap = XOUT Cap = 10pf */

#define XCAP14PF               (0x20)         /* XIN Cap = XOUT Cap = 14pf */

#define XCAP18PF               (0x30)         /* XIN Cap = XOUT Cap = 18pf */

#define OSCCAP_0               (0x00)         /* XIN Cap = XOUT Cap = 0pf */

#define OSCCAP_1               (0x10)         /* XIN Cap = XOUT Cap = 10pf */

#define OSCCAP_2               (0x20)         /* XIN Cap = XOUT Cap = 14pf */

#define OSCCAP_3               (0x30)         /* XIN Cap = XOUT Cap = 18pf */

SFR_8BIT(FLL_CTL1);                           /* FLL+ Control 1 */

#define FLL_DIV0               (0x01)         /* FLL+ Divide Px.x/ACLK 0 */

#define FLL_DIV1               (0x02)         /* FLL+ Divide Px.x/ACLK 1 */

#define SELS                   (0x04)         /* Peripheral Module Clock Source (0: DCO, 1: XT2) */

#define SELM0                  (0x08)         /* MCLK Source Select 0 */

#define SELM1                  (0x10)         /* MCLK Source Select 1 */

#define XT2OFF                 (0x20)         /* High Frequency Oscillator 2 (XT2) disable */

#define SMCLKOFF               (0x40)         /* Peripheral Module Clock (SMCLK) disable */

#define LFXT1DIG               (0x80)         /* Enable Digital input for LF clock */

#define FLL_DIV_1              (0x00)         /* FLL+ Divide Px.x/ACLK By 1 */

#define FLL_DIV_2              (0x01)         /* FLL+ Divide Px.x/ACLK By 2 */

#define FLL_DIV_4              (0x02)         /* FLL+ Divide Px.x/ACLK By 4 */

#define FLL_DIV_8              (0x03)         /* FLL+ Divide Px.x/ACLK By 8 */

#define SELM_DCO               (0x00)         /* Select DCO for CPU MCLK */

#define SELM_XT2               (0x10)         /* Select XT2 for CPU MCLK */

#define SELM_A                 (0x18)         /* Select A (from LFXT1) for CPU MCLK */

/* INTERRUPT CONTROL BITS */

/* These two bits are defined in the Special Function Registers */

/* #define OFIFG               0x02 */

/* #define OFIE                0x02 */

/************************************************************

* LCD_A

************************************************************/

#define __MSP430_HAS_LCD_A__                  /* Definition to show that Module is available */

SFR_8BIT(LCDACTL);                            /* LCD_A Control Register */

#define LCDON                  (0x01)

#define LCDSON                 (0x04)

#define LCDMX0                 (0x08)

#define LCDMX1                 (0x10)

#define LCDFREQ0               (0x20)

#define LCDFREQ1               (0x40)

#define LCDFREQ2               (0x80)

/* Display modes coded with Bits 2-4 */

#define LCDSTATIC              (LCDSON)

#define LCD2MUX                (LCDMX0+LCDSON)

#define LCD3MUX                (LCDMX1+LCDSON)

#define LCD4MUX                (LCDMX1+LCDMX0+LCDSON)

/* Frequency select code with Bits 5-7 */

#define LCDFREQ_32             (0x00)         /* LCD Freq: ACLK divided by 32 */

#define LCDFREQ_64             (0x20)         /* LCD Freq: ACLK divided by 64 */

#define LCDFREQ_96             (0x40)         /* LCD Freq: ACLK divided by 96 */

#define LCDFREQ_128            (0x60)         /* LCD Freq: ACLK divided by 128 */

#define LCDFREQ_192            (0x80)         /* LCD Freq: ACLK divided by 192 */

#define LCDFREQ_256            (0xA0)         /* LCD Freq: ACLK divided by 256 */

#define LCDFREQ_384            (0xC0)         /* LCD Freq: ACLK divided by 384 */

#define LCDFREQ_512            (0xE0)         /* LCD Freq: ACLK divided by 512 */

SFR_8BIT(LCDAPCTL0);                          /* LCD_A Port Control Register 0 */

#define LCDS0                  (0x01)         /* LCD Segment  0 to  3 Enable. */

#define LCDS4                  (0x02)         /* LCD Segment  4 to  7 Enable. */

#define LCDS8                  (0x04)         /* LCD Segment  8 to 11 Enable. */

#define LCDS12                 (0x08)         /* LCD Segment 12 to 15 Enable. */

#define LCDS16                 (0x10)         /* LCD Segment 16 to 19 Enable. */

#define LCDS20                 (0x20)         /* LCD Segment 20 to 23 Enable. */

#define LCDS24                 (0x40)         /* LCD Segment 24 to 27 Enable. */

#define LCDS28                 (0x80)         /* LCD Segment 28 to 31 Enable. */

SFR_8BIT(LCDAPCTL1);                          /* LCD_A Port Control Register 1 */

#define LCDS32                 (0x01)         /* LCD Segment 32 to 35 Enable. */

#define LCDS36                 (0x02)         /* LCD Segment 36 to 39 Enable. */

SFR_8BIT(LCDAVCTL0);                          /* LCD_A Voltage Control Register 0 */

#define LCD2B                  (0x01)         /* Selects 1/2 bias. */

#define VLCDREF0               (0x02)         /* Selects reference voltage for regulated charge pump: 0 */

#define VLCDREF1               (0x04)         /* Selects reference voltage for regulated charge pump: 1 */

#define LCDCPEN                (0x08)         /* LCD Voltage Charge Pump Enable. */

#define VLCDEXT                (0x10)         /* Select external source for VLCD. */

#define LCDREXT                (0x20)         /* Selects external connections for LCD mid voltages. */

#define LCDR03EXT              (0x40)         /* Selects external connection for lowest LCD voltage. */

/* Reference voltage source select for the regulated charge pump */

#define VLCDREF_0              (0<<1)         /* Internal */

#define VLCDREF_1              (1<<1)         /* External */

#define VLCDREF_2              (2<<1)         /* Reserved */

#define VLCDREF_3              (3<<1)         /* Reserved */

SFR_8BIT(LCDAVCTL1);                          /* LCD_A Voltage Control Register 1 */

#define VLCD0                  (0x02)         /* VLCD select: 0 */

#define VLCD1                  (0x04)         /* VLCD select: 1 */

#define VLCD2                  (0x08)         /* VLCD select: 2 */

#define VLCD3                  (0x10)         /* VLCD select: 3 */

/* Charge pump voltage selections */

#define VLCD_0                 (0<<1)         /* Charge pump disabled */

#define VLCD_1                 (1<<1)         /* VLCD = 2.60V */

#define VLCD_2                 (2<<1)         /* VLCD = 2.66V */

#define VLCD_3                 (3<<1)         /* VLCD = 2.72V */

#define VLCD_4                 (4<<1)         /* VLCD = 2.78V */

#define VLCD_5                 (5<<1)         /* VLCD = 2.84V */

#define VLCD_6                 (6<<1)         /* VLCD = 2.90V */

#define VLCD_7                 (7<<1)         /* VLCD = 2.96V */

#define VLCD_8                 (8<<1)         /* VLCD = 3.02V */

#define VLCD_9                 (9<<1)         /* VLCD = 3.08V */

#define VLCD_10                (10<<1)        /* VLCD = 3.14V */

#define VLCD_11                (11<<1)        /* VLCD = 3.20V */

#define VLCD_12                (12<<1)        /* VLCD = 3.26V */

#define VLCD_13                (12<<1)        /* VLCD = 3.32V */

#define VLCD_14                (13<<1)        /* VLCD = 3.38V */

#define VLCD_15                (15<<1)        /* VLCD = 3.44V */

#define VLCD_DISABLED          (0<<1)         /* Charge pump disabled */

#define VLCD_2_60              (1<<1)         /* VLCD = 2.60V */

#define VLCD_2_66              (2<<1)         /* VLCD = 2.66V */

#define VLCD_2_72              (3<<1)         /* VLCD = 2.72V */

#define VLCD_2_78              (4<<1)         /* VLCD = 2.78V */

#define VLCD_2_84              (5<<1)         /* VLCD = 2.84V */

#define VLCD_2_90              (6<<1)         /* VLCD = 2.90V */

#define VLCD_2_96              (7<<1)         /* VLCD = 2.96V */

#define VLCD_3_02              (8<<1)         /* VLCD = 3.02V */

#define VLCD_3_08              (9<<1)         /* VLCD = 3.08V */

#define VLCD_3_14              (10<<1)        /* VLCD = 3.14V */

#define VLCD_3_20              (11<<1)        /* VLCD = 3.20V */

#define VLCD_3_26              (12<<1)        /* VLCD = 3.26V */

#define VLCD_3_32              (12<<1)        /* VLCD = 3.32V */

#define VLCD_3_38              (13<<1)        /* VLCD = 3.38V */

#define VLCD_3_44              (15<<1)        /* VLCD = 3.44V */

#define LCDMEM_                (0x0091)       /* LCD Memory */

#ifdef __ASM_HEADER__

#define LCDMEM                 (LCDMEM_)      /* LCD Memory (for assembler) */

#else

#define LCDMEM                 ((char*)       LCDMEM_) /* LCD Memory (for C) */

#endif

SFR_8BIT(LCDM1);                              /* LCD Memory 1 */

SFR_8BIT(LCDM2);                              /* LCD Memory 2 */

SFR_8BIT(LCDM3);                              /* LCD Memory 3 */

SFR_8BIT(LCDM4);                              /* LCD Memory 4 */

SFR_8BIT(LCDM5);                              /* LCD Memory 5 */

SFR_8BIT(LCDM6);                              /* LCD Memory 6 */

SFR_8BIT(LCDM7);                              /* LCD Memory 7 */

SFR_8BIT(LCDM8);                              /* LCD Memory 8 */

SFR_8BIT(LCDM9);                              /* LCD Memory 9 */

SFR_8BIT(LCDM10);                             /* LCD Memory 10 */

SFR_8BIT(LCDM11);                             /* LCD Memory 11 */

SFR_8BIT(LCDM12);                             /* LCD Memory 12 */

SFR_8BIT(LCDM13);                             /* LCD Memory 13 */

SFR_8BIT(LCDM14);                             /* LCD Memory 14 */

SFR_8BIT(LCDM15);                             /* LCD Memory 15 */

SFR_8BIT(LCDM16);                             /* LCD Memory 16 */

SFR_8BIT(LCDM17);                             /* LCD Memory 17 */

SFR_8BIT(LCDM18);                             /* LCD Memory 18 */

SFR_8BIT(LCDM19);                             /* LCD Memory 19 */

SFR_8BIT(LCDM20);                             /* LCD Memory 20 */

#define LCDMA                  (LCDM10)       /* LCD Memory A */

#define LCDMB                  (LCDM11)       /* LCD Memory B */

#define LCDMC                  (LCDM12)       /* LCD Memory C */

#define LCDMD                  (LCDM13)       /* LCD Memory D */

#define LCDME                  (LCDM14)       /* LCD Memory E */

#define LCDMF                  (LCDM15)       /* LCD Memory F */

/************************************************************

* HARDWARE MULTIPLIER

************************************************************/

#define __MSP430_HAS_MPY__                    /* Definition to show that Module is available */

SFR_16BIT(MPY);                               /* Multiply Unsigned/Operand 1 */

SFR_16BIT(MPYS);                              /* Multiply Signed/Operand 1 */

SFR_16BIT(MAC);                               /* Multiply Unsigned and Accumulate/Operand 1 */

SFR_16BIT(MACS);                              /* Multiply Signed and Accumulate/Operand 1 */

SFR_16BIT(OP2);                               /* Operand 2 */

SFR_16BIT(RESLO);                             /* Result Low Word */

SFR_16BIT(RESHI);                             /* Result High Word */

SFR_16BIT(SUMEXT);                            /* Sum Extend */

/************************************************************

* DIGITAL I/O Port1/2

************************************************************/

#define __MSP430_HAS_PORT1__                  /* Definition to show that Module is available */

#define __MSP430_HAS_PORT2__                  /* Definition to show that Module is available */

SFR_8BIT(P1IN);                               /* Port 1 Input */

SFR_8BIT(P1OUT);                              /* Port 1 Output */

SFR_8BIT(P1DIR);                              /* Port 1 Direction */

SFR_8BIT(P1IFG);                              /* Port 1 Interrupt Flag */

SFR_8BIT(P1IES);                              /* Port 1 Interrupt Edge Select */

SFR_8BIT(P1IE);                               /* Port 1 Interrupt Enable */

SFR_8BIT(P1SEL);                              /* Port 1 Selection */

SFR_8BIT(P2IN);                               /* Port 2 Input */

SFR_8BIT(P2OUT);                              /* Port 2 Output */

SFR_8BIT(P2DIR);                              /* Port 2 Direction */

SFR_8BIT(P2IFG);                              /* Port 2 Interrupt Flag */

SFR_8BIT(P2IES);                              /* Port 2 Interrupt Edge Select */

SFR_8BIT(P2IE);                               /* Port 2 Interrupt Enable */

SFR_8BIT(P2SEL);                              /* Port 2 Selection */

/************************************************************

* DIGITAL I/O Port3/4

************************************************************/

#define __MSP430_HAS_PORT3__                  /* Definition to show that Module is available */

#define __MSP430_HAS_PORT4__                  /* Definition to show that Module is available */

SFR_8BIT(P3IN);                               /* Port 3 Input */

SFR_8BIT(P3OUT);                              /* Port 3 Output */

SFR_8BIT(P3DIR);                              /* Port 3 Direction */

SFR_8BIT(P3SEL);                              /* Port 3 Selection */

SFR_8BIT(P4IN);                               /* Port 4 Input */

SFR_8BIT(P4OUT);                              /* Port 4 Output */

SFR_8BIT(P4DIR);                              /* Port 4 Direction */

SFR_8BIT(P4SEL);                              /* Port 4 Selection */

/************************************************************

* DIGITAL I/O Port5/6

************************************************************/

#define __MSP430_HAS_PORT5__                  /* Definition to show that Module is available */

#define __MSP430_HAS_PORT6__                  /* Definition to show that Module is available */

SFR_8BIT(P5IN);                               /* Port 5 Input */

SFR_8BIT(P5OUT);                              /* Port 5 Output */

SFR_8BIT(P5DIR);                              /* Port 5 Direction */

SFR_8BIT(P5SEL);                              /* Port 5 Selection */

SFR_8BIT(P6IN);                               /* Port 6 Input */

SFR_8BIT(P6OUT);                              /* Port 6 Output */

SFR_8BIT(P6DIR);                              /* Port 6 Direction */