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dpurdie |
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/******************************************************************************/
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/* Legacy Header File */
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/* Not recommended for use in new projects. */
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/* Please use the msp430.h file or the device specific header file */
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/******************************************************************************/
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* MSP430x41x2 devices.
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*
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* Texas Instruments, Version 1.2
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*
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* Rev. 1.0, First Release
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* Rev. 1.1, Fixed typo in ADC10: SREF3 -> SREF2
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* Rev. 1.2, Corrected OSCCAP settings
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*
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********************************************************************/
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#ifndef __msp430x41x2
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#define __msp430x41x2
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
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************************************************************/
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SFR_8BIT(IE1); /* Interrupt Enable 1 */
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#define WDTIE (0x01) /* Watchdog Interrupt Enable */
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#define OFIE (0x02) /* Osc. Fault Interrupt Enable */
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#define NMIIE (0x10) /* NMI Interrupt Enable */
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#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */
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SFR_8BIT(IFG1); /* Interrupt Flag 1 */
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#define WDTIFG (0x01) /* Watchdog Interrupt Flag */
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#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */
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#define PORIFG (0x04) /* Power On Interrupt Flag */
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#define RSTIFG (0x08) /* Reset Interrupt Flag */
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#define NMIIFG (0x10) /* NMI Interrupt Flag */
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SFR_8BIT(IE2); /* Interrupt Enable 2 */
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#define UC0IE IE2
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#define UCA0RXIE (0x01)
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#define UCA0TXIE (0x02)
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#define UCB0RXIE (0x04)
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#define UCB0TXIE (0x08)
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#define BTIE (0x80)
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SFR_8BIT(IFG2); /* Interrupt Flag 2 */
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#define UC0IFG IFG2
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#define UCA0RXIFG (0x01)
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#define UCA0TXIFG (0x02)
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#define UCB0RXIFG (0x04)
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#define UCB0TXIFG (0x08)
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#define BTIFG (0x80)
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/************************************************************
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* ADC10
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************************************************************/
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#define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */
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SFR_8BIT(ADC10DTC0); /* ADC10 Data Transfer Control 0 */
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SFR_8BIT(ADC10DTC1); /* ADC10 Data Transfer Control 1 */
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SFR_8BIT(ADC10AE0); /* ADC10 Analog Enable 0 */
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SFR_8BIT(ADC10AE1); /* ADC10 Analog Enable 1 */
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SFR_16BIT(ADC10CTL0); /* ADC10 Control 0 */
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SFR_16BIT(ADC10CTL1); /* ADC10 Control 1 */
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SFR_16BIT(ADC10MEM); /* ADC10 Memory */
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SFR_16BIT(ADC10SA); /* ADC10 Data Transfer Start Address */
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/* ADC10CTL0 */
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#define ADC10SC (0x001) /* ADC10 Start Conversion */
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#define ENC (0x002) /* ADC10 Enable Conversion */
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#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */
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#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */
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#define ADC10ON (0x010) /* ADC10 On/Enable */
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#define REFON (0x020) /* ADC10 Reference on */
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#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */
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#define MSC (0x080) /* ADC10 Multiple SampleConversion */
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#define REFBURST (0x100) /* ADC10 Reference Burst Mode */
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#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */
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#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */
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#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */
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#define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select Bit: 1 */
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#define SREF0 (0x2000) /* ADC10 Reference Select Bit: 0 */
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#define SREF1 (0x4000) /* ADC10 Reference Select Bit: 1 */
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#define SREF2 (0x8000) /* ADC10 Reference Select Bit: 2 */
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#define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */
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#define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */
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#define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */
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#define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */
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#define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */
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#define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */
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#define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
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#define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
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#define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */
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#define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */
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#define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
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#define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
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/* ADC10CTL1 */
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#define ADC10BUSY (0x0001) /* ADC10 BUSY */
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#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */
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#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */
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#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select Bit: 0 */
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#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select Bit: 1 */
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#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select Bit: 0 */
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#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select Bit: 1 */
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#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select Bit: 2 */
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#define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */
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#define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */
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#define SHS0 (0x0400) /* ADC10 Sample/Hold Source Bit: 0 */
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#define SHS1 (0x0800) /* ADC10 Sample/Hold Source Bit: 1 */
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#define INCH0 (0x1000) /* ADC10 Input Channel Select Bit: 0 */
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#define INCH1 (0x2000) /* ADC10 Input Channel Select Bit: 1 */
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#define INCH2 (0x4000) /* ADC10 Input Channel Select Bit: 2 */
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#define INCH3 (0x8000) /* ADC10 Input Channel Select Bit: 3 */
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#define CONSEQ_0 (0*2u) /* Single channel single conversion */
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#define CONSEQ_1 (1*2u) /* Sequence of channels */
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#define CONSEQ_2 (2*2u) /* Repeat single channel */
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#define CONSEQ_3 (3*2u) /* Repeat sequence of channels */
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#define ADC10SSEL_0 (0*8u) /* ADC10OSC */
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#define ADC10SSEL_1 (1*8u) /* ACLK */
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#define ADC10SSEL_2 (2*8u) /* MCLK */
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#define ADC10SSEL_3 (3*8u) /* SMCLK */
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#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */
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#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select 1 */
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#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select 2 */
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#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select 3 */
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#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select 4 */
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#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select 5 */
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#define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select 6 */
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#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select 7 */
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#define SHS_0 (0*0x400u) /* ADC10SC */
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#define SHS_1 (1*0x400u) /* Ext. SC Trigger 1 */
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#define SHS_2 (2*0x400u) /* Ext. SC Trigger 2 */
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#define SHS_3 (3*0x400u) /* Ext. SC Trigger 3 */
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#define INCH_0 (0*0x1000u) /* Selects Channel 0 */
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#define INCH_1 (1*0x1000u) /* Selects Channel 1 */
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#define INCH_2 (2*0x1000u) /* Selects Channel 2 */
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#define INCH_3 (3*0x1000u) /* Selects Channel 3 */
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#define INCH_4 (4*0x1000u) /* Selects Channel 4 */
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#define INCH_5 (5*0x1000u) /* Selects Channel 5 */
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#define INCH_6 (6*0x1000u) /* Selects Channel 6 */
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#define INCH_7 (7*0x1000u) /* Selects Channel 7 */
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#define INCH_8 (8*0x1000u) /* Selects Channel 8 */
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#define INCH_9 (9*0x1000u) /* Selects Channel 9 */
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#define INCH_10 (10*0x1000u) /* Selects Channel 10 */
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#define INCH_11 (11*0x1000u) /* Selects Channel 11 */
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#define INCH_12 (12*0x1000u) /* Selects Channel 12 */
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#define INCH_13 (13*0x1000u) /* Selects Channel 13 */
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#define INCH_14 (14*0x1000u) /* Selects Channel 14 */
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#define INCH_15 (15*0x1000u) /* Selects Channel 15 */
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/* ADC10DTC0 */
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#define ADC10FETCH (0x001) /* This bit should normally be reset */
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#define ADC10B1 (0x002) /* ADC10 block one */
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#define ADC10CT (0x004) /* ADC10 continuous transfer */
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#define ADC10TB (0x008) /* ADC10 two-block mode */
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#define ADC10DISABLE (0x000) /* ADC10DTC1 */
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/************************************************************
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* BASIC TIMER with Real Time Clock
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************************************************************/
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#define __MSP430_HAS_BT_RTC__ /* Definition to show that Module is available */
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SFR_8BIT(BTCTL); /* Basic Timer Control */
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SFR_8BIT(RTCCTL); /* Real Time Clock Control */
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SFR_8BIT(RTCNT1); /* Real Time Counter 1 */
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SFR_8BIT(RTCNT2); /* Real Time Counter 2 */
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SFR_8BIT(RTCNT3); /* Real Time Counter 3 */
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SFR_8BIT(RTCNT4); /* Real Time Counter 4 */
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SFR_8BIT(BTCNT1); /* Basic Timer Count 1 */
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SFR_8BIT(BTCNT2); /* Basic Timer Count 2 */
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SFR_8BIT(RTCDAY); /* Real Time Clock Day */
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SFR_8BIT(RTCMON); /* Real Time Clock Month */
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SFR_8BIT(RTCYEARL); /* Real Time Clock Year (Low Byte) */
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SFR_8BIT(RTCYEARH); /* Real Time Clock Year (High Byte) */
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#define RTCSEC RTCNT1
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#define RTCMIN RTCNT2
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#define RTCHOUR RTCNT3
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#define RTCDOW RTCNT4
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SFR_16BIT(RTCTL); /* Basic/Real Timer Control */
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SFR_16BIT(RTCTIM0); /* Real Time Clock Time 0 */
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SFR_16BIT(RTCTIM1); /* Real Time Clock Time 1 */
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SFR_16BIT(BTCNT12); /* Basic Timer Count 1/2 */
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SFR_16BIT(RTCDATE); /* Real Time Clock Date */
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SFR_16BIT(RTCYEAR); /* Real Time Clock Year */
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#define RTCNT12 RTCTIM0
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#define RTCNT34 RTCTIM1
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#define BTSSEL (0x80) /* fBT = fMCLK (main clock) */
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#define BTHOLD (0x40) /* BT1 is held if this bit is set */
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#define BTDIV (0x20) /* fCLK2 = ACLK:256 */
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//#define res (0x10)
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//#define res (0x08)
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#define BTIP2 (0x04)
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292 |
#define BTIP1 (0x02)
|
|
|
293 |
#define BTIP0 (0x01)
|
|
|
294 |
|
|
|
295 |
#define RTCBCD (0x80) /* RTC BCD Select */
|
|
|
296 |
#define RTCHOLD (0x40) /* RTC Hold */
|
|
|
297 |
#define RTCMODE1 (0x20) /* RTC Mode 1 */
|
|
|
298 |
#define RTCMODE0 (0x10) /* RTC Mode 0 */
|
|
|
299 |
#define RTCTEV1 (0x08) /* RTC Time Event 1 */
|
|
|
300 |
#define RTCTEV0 (0x04) /* RTC Time Event 0 */
|
|
|
301 |
#define RTCIE (0x02) /* RTC Interrupt Enable */
|
|
|
302 |
#define RTCFG (0x01) /* RTC Event Flag */
|
|
|
303 |
|
|
|
304 |
#define RTCTEV_0 (0x00) /* RTC Time Event: 0 */
|
|
|
305 |
#define RTCTEV_1 (0x04) /* RTC Time Event: 1 */
|
|
|
306 |
#define RTCTEV_2 (0x08) /* RTC Time Event: 2 */
|
|
|
307 |
#define RTCTEV_3 (0x0C) /* RTC Time Event: 3 */
|
|
|
308 |
#define RTCMODE_0 (0x00) /* RTC Mode: 0 */
|
|
|
309 |
#define RTCMODE_1 (0x10) /* RTC Mode: 1 */
|
|
|
310 |
#define RTCMODE_2 (0x20) /* RTC Mode: 2 */
|
|
|
311 |
#define RTCMODE_3 (0x30) /* RTC Mode: 3 */
|
|
|
312 |
|
|
|
313 |
/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
|
|
|
314 |
#define BT_fCLK2_ACLK (0x00)
|
|
|
315 |
#define BT_fCLK2_ACLK_DIV256 (BTDIV)
|
|
|
316 |
#define BT_fCLK2_MCLK (BTSSEL)
|
|
|
317 |
|
|
|
318 |
/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
|
|
|
319 |
#define BT_fCLK2_DIV2 (0x00) /* fINT = fCLK2:2 (default) */
|
|
|
320 |
#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */
|
|
|
321 |
#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */
|
|
|
322 |
#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT = fCLK2:16 */
|
|
|
323 |
#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */
|
|
|
324 |
#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT = fCLK2:64 */
|
|
|
325 |
#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT = fCLK2:128 */
|
|
|
326 |
#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 */
|
|
|
327 |
|
|
|
328 |
/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
|
|
|
329 |
/* fBT=fACLK is thought for longer interval times */
|
|
|
330 |
#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */
|
|
|
331 |
#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */
|
|
|
332 |
#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */
|
|
|
333 |
#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms " */
|
|
|
334 |
#define BT_ADLY_1 (BTIP2) /* 1ms " */
|
|
|
335 |
#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms " */
|
|
|
336 |
#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms " */
|
|
|
337 |
#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms " */
|
|
|
338 |
#define BT_ADLY_16 (BTDIV) /* 16ms " */
|
|
|
339 |
#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms " */
|
|
|
340 |
#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms " */
|
|
|
341 |
#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms " */
|
|
|
342 |
#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms " */
|
|
|
343 |
#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms " */
|
|
|
344 |
#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms " */
|
|
|
345 |
#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms " */
|
|
|
346 |
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
|
|
|
347 |
/* the timing for short intervals is more precise than ACLK */
|
|
|
348 |
/* NOTE */
|
|
|
349 |
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
|
|
|
350 |
/* Too low interval time results in interrupts too frequent for the processor to handle! */
|
|
|
351 |
#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
|
|
|
352 |
#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms " *** too short for */
|
|
|
353 |
#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms " *** interrupt */
|
|
|
354 |
#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms " *** handling */
|
|
|
355 |
#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms " */
|
|
|
356 |
#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms " */
|
|
|
357 |
#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms " */
|
|
|
358 |
#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms " */
|
|
|
359 |
|
|
|
360 |
/* Hold coded with Bits 6-7 in BT(1)CTL */
|
|
|
361 |
/* this is for BT */
|
|
|
362 |
#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
|
|
|
363 |
#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
|
|
|
364 |
|
|
|
365 |
/* INTERRUPT CONTROL BITS */
|
|
|
366 |
/* #define BTIE 0x80 */
|
|
|
367 |
/* #define BTIFG 0x80 */
|
|
|
368 |
|
|
|
369 |
/************************************************************
|
|
|
370 |
* Comparator A
|
|
|
371 |
************************************************************/
|
|
|
372 |
#define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */
|
|
|
373 |
|
|
|
374 |
SFR_8BIT(CACTL1); /* Comparator A Control 1 */
|
|
|
375 |
SFR_8BIT(CACTL2); /* Comparator A Control 2 */
|
|
|
376 |
SFR_8BIT(CAPD); /* Comparator A Port Disable */
|
|
|
377 |
|
|
|
378 |
#define CAIFG (0x01) /* Comp. A Interrupt Flag */
|
|
|
379 |
#define CAIE (0x02) /* Comp. A Interrupt Enable */
|
|
|
380 |
#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
|
|
|
381 |
#define CAON (0x08) /* Comp. A enable */
|
|
|
382 |
#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
|
|
|
383 |
#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
|
|
|
384 |
#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
|
|
|
385 |
#define CAEX (0x80) /* Comp. A Exchange Inputs */
|
|
|
386 |
|
|
|
387 |
#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
|
|
|
388 |
#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
|
|
|
389 |
#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
|
|
|
390 |
#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
|
|
|
391 |
|
|
|
392 |
#define CAOUT (0x01) /* Comp. A Output */
|
|
|
393 |
#define CAF (0x02) /* Comp. A Enable Output Filter */
|
|
|
394 |
#define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */
|
|
|
395 |
#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */
|
|
|
396 |
#define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */
|
|
|
397 |
#define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */
|
|
|
398 |
#define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */
|
|
|
399 |
#define CASHORT (0x80) /* Comp. A Short + and - Terminals */
|
|
|
400 |
|
|
|
401 |
#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
|
|
|
402 |
#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
|
|
|
403 |
#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
|
|
|
404 |
#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
|
|
|
405 |
#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
|
|
|
406 |
#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
|
|
|
407 |
#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
|
|
|
408 |
#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
|
|
|
409 |
|
|
|
410 |
/*************************************************************
|
|
|
411 |
* Flash Memory
|
|
|
412 |
*************************************************************/
|
|
|
413 |
#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */
|
|
|
414 |
|
|
|
415 |
SFR_16BIT(FCTL1); /* FLASH Control 1 */
|
|
|
416 |
SFR_16BIT(FCTL2); /* FLASH Control 2 */
|
|
|
417 |
SFR_16BIT(FCTL3); /* FLASH Control 3 */
|
|
|
418 |
|
|
|
419 |
#define FRKEY (0x9600) /* Flash key returned by read */
|
|
|
420 |
#define FWKEY (0xA500) /* Flash key for write */
|
|
|
421 |
#define FXKEY (0x3300) /* for use with XOR instruction */
|
|
|
422 |
|
|
|
423 |
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
|
|
|
424 |
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
|
|
|
425 |
#define EEI (0x0008) /* Enable Erase Interrupts */
|
|
|
426 |
#define EEIEX (0x0010) /* Enable Emergency Interrupt Exit */
|
|
|
427 |
#define WRT (0x0040) /* Enable bit for Flash write */
|
|
|
428 |
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
|
|
|
429 |
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
|
|
|
430 |
|
|
|
431 |
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
|
|
|
432 |
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
|
|
|
433 |
#ifndef FN2
|
|
|
434 |
#define FN2 (0x0004)
|
|
|
435 |
#endif
|
|
|
436 |
#ifndef FN3
|
|
|
437 |
#define FN3 (0x0008)
|
|
|
438 |
#endif
|
|
|
439 |
#ifndef FN4
|
|
|
440 |
#define FN4 (0x0010)
|
|
|
441 |
#endif
|
|
|
442 |
#define FN5 (0x0020)
|
|
|
443 |
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
|
|
|
444 |
#define FSSEL1 (0x0080) /* Flash clock select 1 */
|
|
|
445 |
|
|
|
446 |
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
|
|
|
447 |
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
|
|
|
448 |
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
|
|
|
449 |
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
|
|
|
450 |
|
|
|
451 |
#define BUSY (0x0001) /* Flash busy: 1 */
|
|
|
452 |
#define KEYV (0x0002) /* Flash Key violation flag */
|
|
|
453 |
#define ACCVIFG (0x0004) /* Flash Access violation flag */
|
|
|
454 |
#define WAIT (0x0008) /* Wait flag for segment write */
|
|
|
455 |
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
456 |
#define EMEX (0x0020) /* Flash Emergency Exit */
|
|
|
457 |
#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
|
|
|
458 |
#define FAIL (0x0080) /* Last Program or Erase failed */
|
|
|
459 |
|
|
|
460 |
/************************************************************
|
|
|
461 |
* SYSTEM CLOCK, FLL+
|
|
|
462 |
************************************************************/
|
|
|
463 |
#define __MSP430_HAS_FLLPLUS__ /* Definition to show that Module is available */
|
|
|
464 |
|
|
|
465 |
SFR_8BIT(SCFI0); /* System Clock Frequency Integrator 0 */
|
|
|
466 |
#define FN_2 (0x04) /* fDCOCLK = 1.4-12MHz*/
|
|
|
467 |
#define FN_3 (0x08) /* fDCOCLK = 2.2-17Mhz*/
|
|
|
468 |
#define FN_4 (0x10) /* fDCOCLK = 3.2-25Mhz*/
|
|
|
469 |
#define FN_8 (0x20) /* fDCOCLK = 5-40Mhz*/
|
|
|
470 |
#define FLLD0 (0x40) /* Loop Divider Bit : 0 */
|
|
|
471 |
#define FLLD1 (0x80) /* Loop Divider Bit : 1 */
|
|
|
472 |
|
|
|
473 |
#define FLLD_1 (0x00) /* Multiply Selected Loop Freq. By 1 */
|
|
|
474 |
#define FLLD_2 (0x40) /* Multiply Selected Loop Freq. By 2 */
|
|
|
475 |
#define FLLD_4 (0x80) /* Multiply Selected Loop Freq. By 4 */
|
|
|
476 |
#define FLLD_8 (0xC0) /* Multiply Selected Loop Freq. By 8 */
|
|
|
477 |
|
|
|
478 |
SFR_8BIT(SCFI1); /* System Clock Frequency Integrator 1 */
|
|
|
479 |
SFR_8BIT(SCFQCTL); /* System Clock Frequency Control */
|
|
|
480 |
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
|
|
|
481 |
/* #define SCFQ_32K 0x00 fMCLK=1*fACLK only a range from */
|
|
|
482 |
#define SCFQ_64K (0x01) /* fMCLK=2*fACLK 1+1 to 127+1 is possible */
|
|
|
483 |
#define SCFQ_128K (0x03) /* fMCLK=4*fACLK */
|
|
|
484 |
#define SCFQ_256K (0x07) /* fMCLK=8*fACLK */
|
|
|
485 |
#define SCFQ_512K (0x0F) /* fMCLK=16*fACLK */
|
|
|
486 |
#define SCFQ_1M (0x1F) /* fMCLK=32*fACLK */
|
|
|
487 |
#define SCFQ_2M (0x3F) /* fMCLK=64*fACLK */
|
|
|
488 |
#define SCFQ_4M (0x7F) /* fMCLK=128*fACLK */
|
|
|
489 |
#define SCFQ_M (0x80) /* Modulation Disable */
|
|
|
490 |
|
|
|
491 |
SFR_8BIT(FLL_CTL0); /* FLL+ Control 0 */
|
|
|
492 |
#define DCOF (0x01) /* DCO Fault Flag */
|
|
|
493 |
#define LFOF (0x02) /* Low Frequency Oscillator Fault Flag */
|
|
|
494 |
#define XT1OF (0x04) /* High Frequency Oscillator 1 Fault Flag */
|
|
|
495 |
#define OSCCAP0 (0x10) /* XIN/XOUT Cap 0 */
|
|
|
496 |
#define OSCCAP1 (0x20) /* XIN/XOUT Cap 1 */
|
|
|
497 |
#define XTS_FLL (0x40) /* 1: Selects high-freq. oscillator */
|
|
|
498 |
#define DCOPLUS (0x80) /* DCO+ Enable */
|
|
|
499 |
|
|
|
500 |
#define XCAP0PF (0x00) /* XIN Cap = XOUT Cap = 0pf */
|
|
|
501 |
#define XCAP5_5F (0x10) /* XIN Cap = XOUT Cap = 5.5pf */
|
|
|
502 |
#define XCAP8_5PF (0x20) /* XIN Cap = XOUT Cap = 8.5pf */
|
|
|
503 |
#define XCAP11PF (0x30) /* XIN Cap = XOUT Cap = 11pf */
|
|
|
504 |
#define OSCCAP_0 (0x00) /* XIN Cap = XOUT Cap: 0 */
|
|
|
505 |
#define OSCCAP_1 (0x10) /* XIN Cap = XOUT Cap: 1 */
|
|
|
506 |
#define OSCCAP_2 (0x20) /* XIN Cap = XOUT Cap: 2 */
|
|
|
507 |
#define OSCCAP_3 (0x30) /* XIN Cap = XOUT Cap: 3 */
|
|
|
508 |
|
|
|
509 |
SFR_8BIT(FLL_CTL1); /* FLL+ Control 1 */
|
|
|
510 |
#define FLL_DIV0 (0x01) /* FLL+ Divide Px.x/ACLK 0 */
|
|
|
511 |
#define FLL_DIV1 (0x02) /* FLL+ Divide Px.x/ACLK 1 */
|
|
|
512 |
#define SELM0 (0x08) /* MCLK Source Select 0 */
|
|
|
513 |
#define SELM1 (0x10) /* MCLK Source Select 1 */
|
|
|
514 |
#define SMCLKOFF (0x40) /* Peripheral Module Clock (SMCLK) disable */
|
|
|
515 |
|
|
|
516 |
#define FLL_DIV_1 (0x00) /* FLL+ Divide Px.x/ACLK By 1 */
|
|
|
517 |
#define FLL_DIV_2 (0x01) /* FLL+ Divide Px.x/ACLK By 2 */
|
|
|
518 |
#define FLL_DIV_4 (0x02) /* FLL+ Divide Px.x/ACLK By 4 */
|
|
|
519 |
#define FLL_DIV_8 (0x03) /* FLL+ Divide Px.x/ACLK By 8 */
|
|
|
520 |
|
|
|
521 |
#define SELM_DCO (0x00) /* Select DCO for CPU MCLK */
|
|
|
522 |
#define SELM_A (0x18) /* Select A (from LFXT1) for CPU MCLK */
|
|
|
523 |
|
|
|
524 |
SFR_8BIT(FLL_CTL2); /* FLL+ Control 2 */
|
|
|
525 |
|
|
|
526 |
#define LF1XT1S0 (0x10) /* Mode 0 for LFXT1 */
|
|
|
527 |
#define LF1XT1S1 (0x20) /* Mode 0 for LFXT1 */
|
|
|
528 |
|
|
|
529 |
#define LF1XT1S_0 (0x00) /* Mode 0 for LF : 32kHz */
|
|
|
530 |
#define LF1XT1S_1 (0x10) /* Mode 1 for LF : reserved */
|
|
|
531 |
#define LF1XT1S_2 (0x20) /* Mode 2 for LF : VLO */
|
|
|
532 |
#define LF1XT1S_3 (0x30) /* Mode 3 for LF : Digital input signal */
|
|
|
533 |
|
|
|
534 |
/* INTERRUPT CONTROL BITS */
|
|
|
535 |
/* These two bits are defined in the Special Function Registers */
|
|
|
536 |
/* #define OFIFG 0x02 */
|
|
|
537 |
/* #define OFIE 0x02 */
|
|
|
538 |
|
|
|
539 |
/************************************************************
|
|
|
540 |
* LCD_A
|
|
|
541 |
************************************************************/
|
|
|
542 |
#define __MSP430_HAS_LCD_A__ /* Definition to show that Module is available */
|
|
|
543 |
|
|
|
544 |
SFR_8BIT(LCDACTL); /* LCD_A Control Register */
|
|
|
545 |
#define LCDON (0x01)
|
|
|
546 |
#define LCDSON (0x04)
|
|
|
547 |
#define LCDMX0 (0x08)
|
|
|
548 |
#define LCDMX1 (0x10)
|
|
|
549 |
#define LCDFREQ0 (0x20)
|
|
|
550 |
#define LCDFREQ1 (0x40)
|
|
|
551 |
#define LCDFREQ2 (0x80)
|
|
|
552 |
/* Display modes coded with Bits 2-4 */
|
|
|
553 |
#define LCDSTATIC (LCDSON)
|
|
|
554 |
#define LCD2MUX (LCDMX0+LCDSON)
|
|
|
555 |
#define LCD3MUX (LCDMX1+LCDSON)
|
|
|
556 |
#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
|
|
|
557 |
/* Frequency select code with Bits 5-7 */
|
|
|
558 |
#define LCDFREQ_32 (0x00) /* LCD Freq: ACLK divided by 32 */
|
|
|
559 |
#define LCDFREQ_64 (0x20) /* LCD Freq: ACLK divided by 64 */
|
|
|
560 |
#define LCDFREQ_96 (0x40) /* LCD Freq: ACLK divided by 96 */
|
|
|
561 |
#define LCDFREQ_128 (0x60) /* LCD Freq: ACLK divided by 128 */
|
|
|
562 |
#define LCDFREQ_192 (0x80) /* LCD Freq: ACLK divided by 192 */
|
|
|
563 |
#define LCDFREQ_256 (0xA0) /* LCD Freq: ACLK divided by 256 */
|
|
|
564 |
#define LCDFREQ_384 (0xC0) /* LCD Freq: ACLK divided by 384 */
|
|
|
565 |
#define LCDFREQ_512 (0xE0) /* LCD Freq: ACLK divided by 512 */
|
|
|
566 |
|
|
|
567 |
SFR_8BIT(LCDAPCTL0); /* LCD_A Port Control Register 0 */
|
|
|
568 |
#define LCDS0 (0x01) /* LCD Segment 0 to 3 Enable. */
|
|
|
569 |
#define LCDS4 (0x02) /* LCD Segment 4 to 7 Enable. */
|
|
|
570 |
#define LCDS8 (0x04) /* LCD Segment 8 to 11 Enable. */
|
|
|
571 |
#define LCDS12 (0x08) /* LCD Segment 12 to 15 Enable. */
|
|
|
572 |
#define LCDS16 (0x10) /* LCD Segment 16 to 19 Enable. */
|
|
|
573 |
#define LCDS20 (0x20) /* LCD Segment 20 to 23 Enable. */
|
|
|
574 |
#define LCDS24 (0x40) /* LCD Segment 24 to 27 Enable. */
|
|
|
575 |
#define LCDS28 (0x80) /* LCD Segment 28 to 31 Enable. */
|
|
|
576 |
|
|
|
577 |
SFR_8BIT(LCDAPCTL1); /* LCD_A Port Control Register 1 */
|
|
|
578 |
#define LCDS32 (0x01) /* LCD Segment 32 to 35 Enable. */
|
|
|
579 |
#define LCDS36 (0x02) /* LCD Segment 36 to 39 Enable. */
|
|
|
580 |
|
|
|
581 |
SFR_8BIT(LCDAVCTL0); /* LCD_A Voltage Control Register 0 */
|
|
|
582 |
#define LCD2B (0x01) /* Selects 1/2 bias. */
|
|
|
583 |
#define VLCDREF0 (0x02) /* Selects reference voltage for regulated charge pump: 0 */
|
|
|
584 |
#define VLCDREF1 (0x04) /* Selects reference voltage for regulated charge pump: 1 */
|
|
|
585 |
#define LCDCPEN (0x08) /* LCD Voltage Charge Pump Enable. */
|
|
|
586 |
#define VLCDEXT (0x10) /* Select external source for VLCD. */
|
|
|
587 |
#define LCDREXT (0x20) /* Selects external connections for LCD mid voltages. */
|
|
|
588 |
#define LCDR03EXT (0x40) /* Selects external connection for lowest LCD voltage. */
|
|
|
589 |
|
|
|
590 |
/* Reference voltage source select for the regulated charge pump */
|
|
|
591 |
#define VLCDREF_0 (0<<1) /* Internal */
|
|
|
592 |
#define VLCDREF_1 (1<<1) /* External */
|
|
|
593 |
#define VLCDREF_2 (2<<1) /* Reserved */
|
|
|
594 |
#define VLCDREF_3 (3<<1) /* Reserved */
|
|
|
595 |
|
|
|
596 |
SFR_8BIT(LCDAVCTL1); /* LCD_A Voltage Control Register 1 */
|
|
|
597 |
#define VLCD0 (0x02) /* VLCD select: 0 */
|
|
|
598 |
#define VLCD1 (0x04) /* VLCD select: 1 */
|
|
|
599 |
#define VLCD2 (0x08) /* VLCD select: 2 */
|
|
|
600 |
#define VLCD3 (0x10) /* VLCD select: 3 */
|
|
|
601 |
|
|
|
602 |
/* Charge pump voltage selections */
|
|
|
603 |
#define VLCD_0 (0<<1) /* Charge pump disabled */
|
|
|
604 |
#define VLCD_1 (1<<1) /* VLCD = 2.60V */
|
|
|
605 |
#define VLCD_2 (2<<1) /* VLCD = 2.66V */
|
|
|
606 |
#define VLCD_3 (3<<1) /* VLCD = 2.72V */
|
|
|
607 |
#define VLCD_4 (4<<1) /* VLCD = 2.78V */
|
|
|
608 |
#define VLCD_5 (5<<1) /* VLCD = 2.84V */
|
|
|
609 |
#define VLCD_6 (6<<1) /* VLCD = 2.90V */
|
|
|
610 |
#define VLCD_7 (7<<1) /* VLCD = 2.96V */
|
|
|
611 |
#define VLCD_8 (8<<1) /* VLCD = 3.02V */
|
|
|
612 |
#define VLCD_9 (9<<1) /* VLCD = 3.08V */
|
|
|
613 |
#define VLCD_10 (10<<1) /* VLCD = 3.14V */
|
|
|
614 |
#define VLCD_11 (11<<1) /* VLCD = 3.20V */
|
|
|
615 |
#define VLCD_12 (12<<1) /* VLCD = 3.26V */
|
|
|
616 |
#define VLCD_13 (12<<1) /* VLCD = 3.32V */
|
|
|
617 |
#define VLCD_14 (13<<1) /* VLCD = 3.38V */
|
|
|
618 |
#define VLCD_15 (15<<1) /* VLCD = 3.44V */
|
|
|
619 |
|
|
|
620 |
#define VLCD_DISABLED (0<<1) /* Charge pump disabled */
|
|
|
621 |
#define VLCD_2_60 (1<<1) /* VLCD = 2.60V */
|
|
|
622 |
#define VLCD_2_66 (2<<1) /* VLCD = 2.66V */
|
|
|
623 |
#define VLCD_2_72 (3<<1) /* VLCD = 2.72V */
|
|
|
624 |
#define VLCD_2_78 (4<<1) /* VLCD = 2.78V */
|
|
|
625 |
#define VLCD_2_84 (5<<1) /* VLCD = 2.84V */
|
|
|
626 |
#define VLCD_2_90 (6<<1) /* VLCD = 2.90V */
|
|
|
627 |
#define VLCD_2_96 (7<<1) /* VLCD = 2.96V */
|
|
|
628 |
#define VLCD_3_02 (8<<1) /* VLCD = 3.02V */
|
|
|
629 |
#define VLCD_3_08 (9<<1) /* VLCD = 3.08V */
|
|
|
630 |
#define VLCD_3_14 (10<<1) /* VLCD = 3.14V */
|
|
|
631 |
#define VLCD_3_20 (11<<1) /* VLCD = 3.20V */
|
|
|
632 |
#define VLCD_3_26 (12<<1) /* VLCD = 3.26V */
|
|
|
633 |
#define VLCD_3_32 (12<<1) /* VLCD = 3.32V */
|
|
|
634 |
#define VLCD_3_38 (13<<1) /* VLCD = 3.38V */
|
|
|
635 |
#define VLCD_3_44 (15<<1) /* VLCD = 3.44V */
|
|
|
636 |
|
|
|
637 |
#define LCDMEM_ (0x0091) /* LCD Memory */
|
|
|
638 |
#ifdef __ASM_HEADER__
|
|
|
639 |
#define LCDMEM (LCDMEM_) /* LCD Memory (for assembler) */
|
|
|
640 |
#else
|
|
|
641 |
#define LCDMEM ((char*) LCDMEM_) /* LCD Memory (for C) */
|
|
|
642 |
#endif
|
|
|
643 |
SFR_8BIT(LCDM1); /* LCD Memory 1 */
|
|
|
644 |
SFR_8BIT(LCDM2); /* LCD Memory 2 */
|
|
|
645 |
SFR_8BIT(LCDM3); /* LCD Memory 3 */
|
|
|
646 |
SFR_8BIT(LCDM4); /* LCD Memory 4 */
|
|
|
647 |
SFR_8BIT(LCDM5); /* LCD Memory 5 */
|
|
|
648 |
SFR_8BIT(LCDM6); /* LCD Memory 6 */
|
|
|
649 |
SFR_8BIT(LCDM7); /* LCD Memory 7 */
|
|
|
650 |
SFR_8BIT(LCDM8); /* LCD Memory 8 */
|
|
|
651 |
SFR_8BIT(LCDM9); /* LCD Memory 9 */
|
|
|
652 |
SFR_8BIT(LCDM10); /* LCD Memory 10 */
|
|
|
653 |
SFR_8BIT(LCDM11); /* LCD Memory 11 */
|
|
|
654 |
SFR_8BIT(LCDM12); /* LCD Memory 12 */
|
|
|
655 |
SFR_8BIT(LCDM13); /* LCD Memory 13 */
|
|
|
656 |
SFR_8BIT(LCDM14); /* LCD Memory 14 */
|
|
|
657 |
SFR_8BIT(LCDM15); /* LCD Memory 15 */
|
|
|
658 |
SFR_8BIT(LCDM16); /* LCD Memory 16 */
|
|
|
659 |
SFR_8BIT(LCDM17); /* LCD Memory 17 */
|
|
|
660 |
SFR_8BIT(LCDM18); /* LCD Memory 18 */
|
|
|
661 |
SFR_8BIT(LCDM19); /* LCD Memory 19 */
|
|
|
662 |
SFR_8BIT(LCDM20); /* LCD Memory 20 */
|
|
|
663 |
|
|
|
664 |
#define LCDMA (LCDM10) /* LCD Memory A */
|
|
|
665 |
#define LCDMB (LCDM11) /* LCD Memory B */
|
|
|
666 |
#define LCDMC (LCDM12) /* LCD Memory C */
|
|
|
667 |
#define LCDMD (LCDM13) /* LCD Memory D */
|
|
|
668 |
#define LCDME (LCDM14) /* LCD Memory E */
|
|
|
669 |
#define LCDMF (LCDM15) /* LCD Memory F */
|
|
|
670 |
|
|
|
671 |
/************************************************************
|
|
|
672 |
* DIGITAL I/O Port1/2
|
|
|
673 |
************************************************************/
|
|
|
674 |
#define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */
|
|
|
675 |
#define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */
|
|
|
676 |
|
|
|
677 |
SFR_8BIT(P1IN); /* Port 1 Input */
|
|
|
678 |
SFR_8BIT(P1OUT); /* Port 1 Output */
|
|
|
679 |
SFR_8BIT(P1DIR); /* Port 1 Direction */
|
|
|
680 |
SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */
|
|
|
681 |
SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */
|
|
|
682 |
SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */
|
|
|
683 |
SFR_8BIT(P1SEL); /* Port 1 Selection */
|
|
|
684 |
|
|
|
685 |
SFR_8BIT(P2IN); /* Port 2 Input */
|
|
|
686 |
SFR_8BIT(P2OUT); /* Port 2 Output */
|
|
|
687 |
SFR_8BIT(P2DIR); /* Port 2 Direction */
|
|
|
688 |
SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */
|
|
|
689 |
SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */
|
|
|
690 |
SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */
|
|
|
691 |
SFR_8BIT(P2SEL); /* Port 2 Selection */
|
|
|
692 |
|
|
|
693 |
/************************************************************
|
|
|
694 |
* DIGITAL I/O Port3/4
|
|
|
695 |
************************************************************/
|
|
|
696 |
#define __MSP430_HAS_PORT3__ /* Definition to show that Module is available */
|
|
|
697 |
#define __MSP430_HAS_PORT4__ /* Definition to show that Module is available */
|
|
|
698 |
|
|
|
699 |
SFR_8BIT(P3IN); /* Port 3 Input */
|
|
|
700 |
SFR_8BIT(P3OUT); /* Port 3 Output */
|
|
|
701 |
SFR_8BIT(P3DIR); /* Port 3 Direction */
|
|
|
702 |
SFR_8BIT(P3SEL); /* Port 3 Selection */
|
|
|
703 |
|
|
|
704 |
SFR_8BIT(P4IN); /* Port 4 Input */
|
|
|
705 |
SFR_8BIT(P4OUT); /* Port 4 Output */
|
|
|
706 |
SFR_8BIT(P4DIR); /* Port 4 Direction */
|
|
|
707 |
SFR_8BIT(P4SEL); /* Port 4 Selection */
|
|
|
708 |
|
|
|
709 |
/************************************************************
|
|
|
710 |
* DIGITAL I/O Port5/6
|
|
|
711 |
************************************************************/
|
|
|
712 |
#define __MSP430_HAS_PORT5__ /* Definition to show that Module is available */
|
|
|
713 |
#define __MSP430_HAS_PORT6__ /* Definition to show that Module is available */
|
|
|
714 |
|
|
|
715 |
SFR_8BIT(P5IN); /* Port 5 Input */
|
|
|
716 |
SFR_8BIT(P5OUT); /* Port 5 Output */
|
|
|
717 |
SFR_8BIT(P5DIR); /* Port 5 Direction */
|
|
|
718 |
SFR_8BIT(P5SEL); /* Port 5 Selection */
|
|
|
719 |
|
|
|
720 |
SFR_8BIT(P6IN); /* Port 6 Input */
|
|
|
721 |
SFR_8BIT(P6OUT); /* Port 6 Output */
|
|
|
722 |
SFR_8BIT(P6DIR); /* Port 6 Direction */
|
|
|
723 |
SFR_8BIT(P6SEL); /* Port 6 Selection */
|
|
|
724 |
|
|
|
725 |
/************************************************************
|
|
|
726 |
* DIGITAL I/O Port7
|
|
|
727 |
************************************************************/
|
|
|
728 |
#define __MSP430_HAS_PORT7__ /* Definition to show that Module is available */
|
|
|
729 |
|
|
|
730 |
SFR_8BIT(P7IN); /* Port 7 Input */
|
|
|
731 |
SFR_8BIT(P7OUT); /* Port 7 Output */
|
|
|
732 |
SFR_8BIT(P7DIR); /* Port 7 Direction */
|
|
|
733 |
SFR_8BIT(P7SEL); /* Port 7 Selection */
|
|
|
734 |
|
|
|
735 |
/************************************************************
|
|
|
736 |
* Brown-Out, Supply Voltage Supervision (SVS)
|
|
|
737 |
************************************************************/
|
|
|
738 |
#define __MSP430_HAS_SVS__ /* Definition to show that Module is available */
|
|
|
739 |
|
|
|
740 |
SFR_8BIT(SVSCTL); /* SVS Control */
|
|
|
741 |
#define SVSFG (0x01) /* SVS Flag */
|
|
|
742 |
#define SVSOP (0x02) /* SVS output (read only) */
|
|
|
743 |
#define SVSON (0x04) /* Switches the SVS on/off */
|
|
|
744 |
#define PORON (0x08) /* Enable POR Generation if Low Voltage */
|
|
|
745 |
#define VLD0 (0x10)
|
|
|
746 |
#define VLD1 (0x20)
|
|
|
747 |
#define VLD2 (0x40)
|
|
|
748 |
#define VLD3 (0x80)
|
|
|
749 |
|
|
|
750 |
#define VLDON (0x10)
|
|
|
751 |
#define VLDOFF (0x00)
|
|
|
752 |
#define VLD_1_8V (0x10)
|
|
|
753 |
|
|
|
754 |
/************************************************************
|
|
|
755 |
* Timer0_A3
|
|
|
756 |
************************************************************/
|
|
|
757 |
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
|
|
|
758 |
|
|
|
759 |
SFR_16BIT(TA0IV); /* Timer0_A3 Interrupt Vector Word */
|
|
|
760 |
SFR_16BIT(TA0CTL); /* Timer0_A3 Control */
|
|
|
761 |
SFR_16BIT(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */
|
|
|
762 |
SFR_16BIT(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */
|
|
|
763 |
SFR_16BIT(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */
|
|
|
764 |
SFR_16BIT(TA0R); /* Timer0_A3 */
|
|
|
765 |
SFR_16BIT(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */
|
|
|
766 |
SFR_16BIT(TA0CCR1); /* Timer0_A3 Capture/Compare 1 */
|
|
|
767 |
SFR_16BIT(TA0CCR2); /* Timer0_A3 Capture/Compare 2 */
|
|
|
768 |
|
|
|
769 |
/* Alternate register names */
|
|
|
770 |
#define TAIV TA0IV /* Timer A Interrupt Vector Word */
|
|
|
771 |
#define TACTL TA0CTL /* Timer A Control */
|
|
|
772 |
#define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
773 |
#define TACCTL1 TA0CCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
774 |
#define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
775 |
#define TAR TA0R /* Timer A */
|
|
|
776 |
#define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */
|
|
|
777 |
#define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */
|
|
|
778 |
#define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */
|
|
|
779 |
#define TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */
|
|
|
780 |
#define TACTL_ TA0CTL_ /* Timer A Control */
|
|
|
781 |
#define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
782 |
#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
783 |
#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
784 |
#define TAR_ TA0R_ /* Timer A */
|
|
|
785 |
#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */
|
|
|
786 |
#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */
|
|
|
787 |
#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */
|
|
|
788 |
|
|
|
789 |
/* Alternate register names 2 */
|
|
|
790 |
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
791 |
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
792 |
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
793 |
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
794 |
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
795 |
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
796 |
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
797 |
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
798 |
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
799 |
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
800 |
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
801 |
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
802 |
|
|
|
803 |
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
|
|
|
804 |
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
|
|
|
805 |
#define ID1 (0x0080) /* Timer A clock input divider 1 */
|
|
|
806 |
#define ID0 (0x0040) /* Timer A clock input divider 0 */
|
|
|
807 |
#define MC1 (0x0020) /* Timer A mode control 1 */
|
|
|
808 |
#define MC0 (0x0010) /* Timer A mode control 0 */
|
|
|
809 |
#define TACLR (0x0004) /* Timer A counter clear */
|
|
|
810 |
#define TAIE (0x0002) /* Timer A counter interrupt enable */
|
|
|
811 |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
|
|
|
812 |
|
|
|
813 |
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
814 |
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
815 |
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
816 |
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
817 |
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
818 |
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
819 |
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
820 |
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
821 |
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
822 |
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
823 |
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
824 |
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
825 |
|
|
|
826 |
#define CM1 (0x8000) /* Capture mode 1 */
|
|
|
827 |
#define CM0 (0x4000) /* Capture mode 0 */
|
|
|
828 |
#define CCIS1 (0x2000) /* Capture input select 1 */
|
|
|
829 |
#define CCIS0 (0x1000) /* Capture input select 0 */
|
|
|
830 |
#define SCS (0x0800) /* Capture sychronize */
|
|
|
831 |
#define SCCI (0x0400) /* Latched capture signal (read) */
|
|
|
832 |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
|
|
|
833 |
#define OUTMOD2 (0x0080) /* Output mode 2 */
|
|
|
834 |
#define OUTMOD1 (0x0040) /* Output mode 1 */
|
|
|
835 |
#define OUTMOD0 (0x0020) /* Output mode 0 */
|
|
|
836 |
#define CCIE (0x0010) /* Capture/compare interrupt enable */
|
|
|
837 |
#define CCI (0x0008) /* Capture input signal (read) */
|
|
|
838 |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
|
|
|
839 |
#define COV (0x0002) /* Capture/compare overflow flag */
|
|
|
840 |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
|
|
|
841 |
|
|
|
842 |
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
|
|
|
843 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
|
|
|
844 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
|
|
|
845 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
|
|
|
846 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
|
|
|
847 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
|
|
|
848 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
|
|
|
849 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
|
|
|
850 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
|
|
|
851 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
|
|
|
852 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
|
|
|
853 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
|
|
|
854 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
|
|
|
855 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
|
|
|
856 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
|
|
|
857 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
|
|
|
858 |
|
|
|
859 |
/* T0_A3IV Definitions */
|
|
|
860 |
#define TA0IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
861 |
#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */
|
|
|
862 |
#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */
|
|
|
863 |
#define TA0IV_6 (0x0006) /* Reserved */
|
|
|
864 |
#define TA0IV_8 (0x0008) /* Reserved */
|
|
|
865 |
#define TA0IV_TAIFG (0x000A) /* TA0IFG */
|
|
|
866 |
|
|
|
867 |
/************************************************************
|
|
|
868 |
* Timer1_A5
|
|
|
869 |
************************************************************/
|
|
|
870 |
#define __MSP430_HAS_T1A5__ /* Definition to show that Module is available */
|
|
|
871 |
|
|
|
872 |
SFR_16BIT(TA1IV); /* Timer1_A5 Interrupt Vector Word */
|
|
|
873 |
SFR_16BIT(TA1CTL); /* Timer1_A5 Control */
|
|
|
874 |
SFR_16BIT(TA1CCTL0); /* Timer1_A5 Capture/Compare Control 0 */
|
|
|
875 |
SFR_16BIT(TA1CCTL1); /* Timer1_A5 Capture/Compare Control 1 */
|
|
|
876 |
SFR_16BIT(TA1CCTL2); /* Timer1_A5 Capture/Compare Control 2 */
|
|
|
877 |
SFR_16BIT(TA1CCTL3); /* Timer1_A5 Capture/Compare Control 3 */
|
|
|
878 |
SFR_16BIT(TA1CCTL4); /* Timer1_A5 Capture/Compare Control 4 */
|
|
|
879 |
SFR_16BIT(TA1R); /* Timer1_A5 */
|
|
|
880 |
SFR_16BIT(TA1CCR0); /* Timer1_A5 Capture/Compare 0 */
|
|
|
881 |
SFR_16BIT(TA1CCR1); /* Timer1_A5 Capture/Compare 1 */
|
|
|
882 |
SFR_16BIT(TA1CCR2); /* Timer1_A5 Capture/Compare 2 */
|
|
|
883 |
SFR_16BIT(TA1CCR3); /* Timer1_A5 Capture/Compare 3 */
|
|
|
884 |
SFR_16BIT(TA1CCR4); /* Timer1_A5 Capture/Compare 4 */
|
|
|
885 |
|
|
|
886 |
/* Bits are already defined within the Timer0_Ax */
|
|
|
887 |
|
|
|
888 |
/* T1_A5IV Definitions */
|
|
|
889 |
#define TA1IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
890 |
#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */
|
|
|
891 |
#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */
|
|
|
892 |
#define TA1IV_TACCR3 (0x0006) /* TA1CCR3_CCIFG */
|
|
|
893 |
#define TA1IV_TACCR4 (0x0008) /* TA1CCR4_CCIFG */
|
|
|
894 |
#define TA1IV_TAIFG (0x000A) /* TA1IFG */
|
|
|
895 |
|
|
|
896 |
/************************************************************
|
|
|
897 |
* USCI
|
|
|
898 |
************************************************************/
|
|
|
899 |
#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */
|
|
|
900 |
|
|
|
901 |
SFR_8BIT(UCA0CTL0); /* USCI A0 Control Register 0 */
|
|
|
902 |
SFR_8BIT(UCA0CTL1); /* USCI A0 Control Register 1 */
|
|
|
903 |
SFR_8BIT(UCA0BR0); /* USCI A0 Baud Rate 0 */
|
|
|
904 |
SFR_8BIT(UCA0BR1); /* USCI A0 Baud Rate 1 */
|
|
|
905 |
SFR_8BIT(UCA0MCTL); /* USCI A0 Modulation Control */
|
|
|
906 |
SFR_8BIT(UCA0STAT); /* USCI A0 Status Register */
|
|
|
907 |
SFR_8BIT(UCA0RXBUF); /* USCI A0 Receive Buffer */
|
|
|
908 |
SFR_8BIT(UCA0TXBUF); /* USCI A0 Transmit Buffer */
|
|
|
909 |
SFR_8BIT(UCA0ABCTL); /* USCI A0 LIN Control */
|
|
|
910 |
SFR_8BIT(UCA0IRTCTL); /* USCI A0 IrDA Transmit Control */
|
|
|
911 |
SFR_8BIT(UCA0IRRCTL); /* USCI A0 IrDA Receive Control */
|
|
|
912 |
|
|
|
913 |
|
|
|
914 |
|
|
|
915 |
SFR_8BIT(UCB0CTL0); /* USCI B0 Control Register 0 */
|
|
|
916 |
SFR_8BIT(UCB0CTL1); /* USCI B0 Control Register 1 */
|
|
|
917 |
SFR_8BIT(UCB0BR0); /* USCI B0 Baud Rate 0 */
|
|
|
918 |
SFR_8BIT(UCB0BR1); /* USCI B0 Baud Rate 1 */
|
|
|
919 |
SFR_8BIT(UCB0I2CIE); /* USCI B0 I2C Interrupt Enable Register */
|
|
|
920 |
SFR_8BIT(UCB0STAT); /* USCI B0 Status Register */
|
|
|
921 |
SFR_8BIT(UCB0RXBUF); /* USCI B0 Receive Buffer */
|
|
|
922 |
SFR_8BIT(UCB0TXBUF); /* USCI B0 Transmit Buffer */
|
|
|
923 |
SFR_16BIT(UCB0I2COA); /* USCI B0 I2C Own Address */
|
|
|
924 |
SFR_16BIT(UCB0I2CSA); /* USCI B0 I2C Slave Address */
|
|
|
925 |
|
|
|
926 |
// UART-Mode Bits
|
|
|
927 |
#define UCPEN (0x80) /* Async. Mode: Parity enable */
|
|
|
928 |
#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
|
|
|
929 |
#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
|
|
|
930 |
#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
|
|
|
931 |
#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
|
|
|
932 |
#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
|
|
|
933 |
#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
|
|
|
934 |
#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
|
|
|
935 |
|
|
|
936 |
// SPI-Mode Bits
|
|
|
937 |
#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
|
|
|
938 |
#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
|
|
|
939 |
#define UCMST (0x08) /* Sync. Mode: Master Select */
|
|
|
940 |
|
|
|
941 |
// I2C-Mode Bits
|
|
|
942 |
#define UCA10 (0x80) /* 10-bit Address Mode */
|
|
|
943 |
#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
|
|
|
944 |
#define UCMM (0x20) /* Multi-Master Environment */
|
|
|
945 |
//#define res (0x10) /* reserved */
|
|
|
946 |
#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
|
|
|
947 |
#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
|
|
|
948 |
#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
|
|
|
949 |
#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
|
|
|
950 |
|
|
|
951 |
// UART-Mode Bits
|
|
|
952 |
#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
|
|
|
953 |
#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
|
|
|
954 |
#define UCRXEIE (0x20) /* RX Error interrupt enable */
|
|
|
955 |
#define UCBRKIE (0x10) /* Break interrupt enable */
|
|
|
956 |
#define UCDORM (0x08) /* Dormant (Sleep) Mode */
|
|
|
957 |
#define UCTXADDR (0x04) /* Send next Data as Address */
|
|
|
958 |
#define UCTXBRK (0x02) /* Send next Data as Break */
|
|
|
959 |
#define UCSWRST (0x01) /* USCI Software Reset */
|
|
|
960 |
|
|
|
961 |
// SPI-Mode Bits
|
|
|
962 |
//#define res (0x20) /* reserved */
|
|
|
963 |
//#define res (0x10) /* reserved */
|
|
|
964 |
//#define res (0x08) /* reserved */
|
|
|
965 |
//#define res (0x04) /* reserved */
|
|
|
966 |
//#define res (0x02) /* reserved */
|
|
|
967 |
|
|
|
968 |
// I2C-Mode Bits
|
|
|
969 |
//#define res (0x20) /* reserved */
|
|
|
970 |
#define UCTR (0x10) /* Transmit/Receive Select/Flag */
|
|
|
971 |
#define UCTXNACK (0x08) /* Transmit NACK */
|
|
|
972 |
#define UCTXSTP (0x04) /* Transmit STOP */
|
|
|
973 |
#define UCTXSTT (0x02) /* Transmit START */
|
|
|
974 |
#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
|
|
|
975 |
#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
|
|
|
976 |
#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
|
|
|
977 |
#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
|
|
|
978 |
|
|
|
979 |
#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
|
|
|
980 |
#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
|
|
|
981 |
#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
|
|
|
982 |
#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
|
|
|
983 |
#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
|
|
|
984 |
#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
|
|
|
985 |
#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
|
|
|
986 |
#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
|
|
|
987 |
|
|
|
988 |
#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
|
|
|
989 |
#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
|
|
|
990 |
#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
|
|
|
991 |
#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
|
|
|
992 |
#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
|
|
|
993 |
#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
|
|
|
994 |
#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
|
|
|
995 |
#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
|
|
|
996 |
#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
|
|
|
997 |
#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
|
|
|
998 |
#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
|
|
|
999 |
#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
|
|
|
1000 |
#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
|
|
|
1001 |
#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
|
|
|
1002 |
#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
|
|
|
1003 |
#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
|
|
|
1004 |
|
|
|
1005 |
#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
|
|
|
1006 |
#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
|
|
|
1007 |
#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
|
|
|
1008 |
#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
|
|
|
1009 |
#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
|
|
|
1010 |
#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
|
|
|
1011 |
#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
|
|
|
1012 |
#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
|
|
|
1013 |
|
|
|
1014 |
#define UCLISTEN (0x80) /* USCI Listen mode */
|
|
|
1015 |
#define UCFE (0x40) /* USCI Frame Error Flag */
|
|
|
1016 |
#define UCOE (0x20) /* USCI Overrun Error Flag */
|
|
|
1017 |
#define UCPE (0x10) /* USCI Parity Error Flag */
|
|
|
1018 |
#define UCBRK (0x08) /* USCI Break received */
|
|
|
1019 |
#define UCRXERR (0x04) /* USCI RX Error Flag */
|
|
|
1020 |
#define UCADDR (0x02) /* USCI Address received Flag */
|
|
|
1021 |
#define UCBUSY (0x01) /* USCI Busy Flag */
|
|
|
1022 |
#define UCIDLE (0x02) /* USCI Idle line detected Flag */
|
|
|
1023 |
|
|
|
1024 |
//#define res (0x80) /* reserved */
|
|
|
1025 |
//#define res (0x40) /* reserved */
|
|
|
1026 |
//#define res (0x20) /* reserved */
|
|
|
1027 |
//#define res (0x10) /* reserved */
|
|
|
1028 |
#define UCNACKIE (0x08) /* NACK Condition interrupt enable */
|
|
|
1029 |
#define UCSTPIE (0x04) /* STOP Condition interrupt enable */
|
|
|
1030 |
#define UCSTTIE (0x02) /* START Condition interrupt enable */
|
|
|
1031 |
#define UCALIE (0x01) /* Arbitration Lost interrupt enable */
|
|
|
1032 |
|
|
|
1033 |
#define UCSCLLOW (0x40) /* SCL low */
|
|
|
1034 |
#define UCGC (0x20) /* General Call address received Flag */
|
|
|
1035 |
#define UCBBUSY (0x10) /* Bus Busy Flag */
|
|
|
1036 |
#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */
|
|
|
1037 |
#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */
|
|
|
1038 |
#define UCSTTIFG (0x02) /* START Condition interrupt Flag */
|
|
|
1039 |
#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */
|
|
|
1040 |
|
|
|
1041 |
#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
|
|
|
1042 |
#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
|
|
|
1043 |
#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
|
|
|
1044 |
#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
|
|
|
1045 |
#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
|
|
|
1046 |
#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
|
|
|
1047 |
#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
|
|
|
1048 |
#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
|
|
|
1049 |
|
|
|
1050 |
#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
|
|
|
1051 |
#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
|
|
|
1052 |
#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
|
|
|
1053 |
#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
|
|
|
1054 |
#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
|
|
|
1055 |
#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
|
|
|
1056 |
#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
|
|
|
1057 |
#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
|
|
|
1058 |
|
|
|
1059 |
//#define res (0x80) /* reserved */
|
|
|
1060 |
//#define res (0x40) /* reserved */
|
|
|
1061 |
#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
|
|
|
1062 |
#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
|
|
|
1063 |
#define UCSTOE (0x08) /* Sync-Field Timeout error */
|
|
|
1064 |
#define UCBTOE (0x04) /* Break Timeout error */
|
|
|
1065 |
//#define res (0x02) /* reserved */
|
|
|
1066 |
#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
|
|
|
1067 |
|
|
|
1068 |
#define UCGCEN (0x8000) /* I2C General Call enable */
|
|
|
1069 |
#define UCOA9 (0x0200) /* I2C Own Address 9 */
|
|
|
1070 |
#define UCOA8 (0x0100) /* I2C Own Address 8 */
|
|
|
1071 |
#define UCOA7 (0x0080) /* I2C Own Address 7 */
|
|
|
1072 |
#define UCOA6 (0x0040) /* I2C Own Address 6 */
|
|
|
1073 |
#define UCOA5 (0x0020) /* I2C Own Address 5 */
|
|
|
1074 |
#define UCOA4 (0x0010) /* I2C Own Address 4 */
|
|
|
1075 |
#define UCOA3 (0x0008) /* I2C Own Address 3 */
|
|
|
1076 |
#define UCOA2 (0x0004) /* I2C Own Address 2 */
|
|
|
1077 |
#define UCOA1 (0x0002) /* I2C Own Address 1 */
|
|
|
1078 |
#define UCOA0 (0x0001) /* I2C Own Address 0 */
|
|
|
1079 |
|
|
|
1080 |
#define UCSA9 (0x0200) /* I2C Slave Address 9 */
|
|
|
1081 |
#define UCSA8 (0x0100) /* I2C Slave Address 8 */
|
|
|
1082 |
#define UCSA7 (0x0080) /* I2C Slave Address 7 */
|
|
|
1083 |
#define UCSA6 (0x0040) /* I2C Slave Address 6 */
|
|
|
1084 |
#define UCSA5 (0x0020) /* I2C Slave Address 5 */
|
|
|
1085 |
#define UCSA4 (0x0010) /* I2C Slave Address 4 */
|
|
|
1086 |
#define UCSA3 (0x0008) /* I2C Slave Address 3 */
|
|
|
1087 |
#define UCSA2 (0x0004) /* I2C Slave Address 2 */
|
|
|
1088 |
#define UCSA1 (0x0002) /* I2C Slave Address 1 */
|
|
|
1089 |
#define UCSA0 (0x0001) /* I2C Slave Address 0 */
|
|
|
1090 |
|
|
|
1091 |
/************************************************************
|
|
|
1092 |
* WATCHDOG TIMER
|
|
|
1093 |
************************************************************/
|
|
|
1094 |
#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
|
|
|
1095 |
|
|
|
1096 |
SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
|
|
|
1097 |
/* The bit names have been prefixed with "WDT" */
|
|
|
1098 |
#define WDTIS0 (0x0001)
|
|
|
1099 |
#define WDTIS1 (0x0002)
|
|
|
1100 |
#define WDTSSEL (0x0004)
|
|
|
1101 |
#define WDTCNTCL (0x0008)
|
|
|
1102 |
#define WDTTMSEL (0x0010)
|
|
|
1103 |
#define WDTNMI (0x0020)
|
|
|
1104 |
#define WDTNMIES (0x0040)
|
|
|
1105 |
#define WDTHOLD (0x0080)
|
|
|
1106 |
|
|
|
1107 |
#define WDTPW (0x5A00)
|
|
|
1108 |
|
|
|
1109 |
/* WDT-interval times [1ms] coded with Bits 0-2 */
|
|
|
1110 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
1111 |
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
|
|
|
1112 |
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
|
|
|
1113 |
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
|
|
|
1114 |
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
1115 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
1116 |
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
|
|
|
1117 |
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
|
|
|
1118 |
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
|
|
|
1119 |
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
1120 |
/* Watchdog mode -> reset after expired time */
|
|
|
1121 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
1122 |
#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
|
|
|
1123 |
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
|
|
|
1124 |
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
|
|
|
1125 |
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
1126 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
1127 |
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
|
|
|
1128 |
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
|
|
|
1129 |
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
|
|
|
1130 |
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
1131 |
|
|
|
1132 |
/* INTERRUPT CONTROL */
|
|
|
1133 |
/* These two bits are defined in the Special Function Registers */
|
|
|
1134 |
/* #define WDTIE 0x01 */
|
|
|
1135 |
/* #define WDTIFG 0x01 */
|
|
|
1136 |
|
|
|
1137 |
/************************************************************
|
|
|
1138 |
* Interrupt Vectors (offset from 0xFFE0)
|
|
|
1139 |
************************************************************/
|
|
|
1140 |
|
|
|
1141 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
1142 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
1143 |
#define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name
|
|
|
1144 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
1145 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
1146 |
PLACE_VECTOR(VECTOR_NAME(func), offset)
|
|
|
1147 |
|
|
|
1148 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1149 |
#define BASICTIMER_VECTOR ".int00" /* 0xFFE0 Basic Timer */
|
|
|
1150 |
#else
|
|
|
1151 |
#define BASICTIMER_VECTOR (0 * 1u) /* 0xFFE0 Basic Timer */
|
|
|
1152 |
/*#define BASICTIMER_ISR(func) ISR_VECTOR(func, ".int00") */ /* 0xFFE0 Basic Timer */ /* CCE V2 Style */
|
|
|
1153 |
#endif
|
|
|
1154 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1155 |
#define PORT2_VECTOR ".int01" /* 0xFFE2 Port 2 */
|
|
|
1156 |
#else
|
|
|
1157 |
#define PORT2_VECTOR (1 * 1u) /* 0xFFE2 Port 2 */
|
|
|
1158 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int01") */ /* 0xFFE2 Port 2 */ /* CCE V2 Style */
|
|
|
1159 |
#endif
|
|
|
1160 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1161 |
#define PORT1_VECTOR ".int04" /* 0xFFE8 Port 1 */
|
|
|
1162 |
#else
|
|
|
1163 |
#define PORT1_VECTOR (4 * 1u) /* 0xFFE8 Port 1 */
|
|
|
1164 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int04") */ /* 0xFFE8 Port 1 */ /* CCE V2 Style */
|
|
|
1165 |
#endif
|
|
|
1166 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1167 |
#define TIMER0_A1_VECTOR ".int05" /* 0xFFEA Timer0_A CC1-2, TA0 */
|
|
|
1168 |
#else
|
|
|
1169 |
#define TIMER0_A1_VECTOR (5 * 1u) /* 0xFFEA Timer0_A CC1-2, TA0 */
|
|
|
1170 |
/*#define TIMER0_A1_ISR(func) ISR_VECTOR(func, ".int05") */ /* 0xFFEA Timer0_A CC1-2, TA0 */ /* CCE V2 Style */
|
|
|
1171 |
#endif
|
|
|
1172 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1173 |
#define TIMER0_A0_VECTOR ".int06" /* 0xFFEC Timer0_A CC0 */
|
|
|
1174 |
#else
|
|
|
1175 |
#define TIMER0_A0_VECTOR (6 * 1u) /* 0xFFEC Timer0_A CC0 */
|
|
|
1176 |
/*#define TIMER0_A0_ISR(func) ISR_VECTOR(func, ".int06") */ /* 0xFFEC Timer0_A CC0 */ /* CCE V2 Style */
|
|
|
1177 |
#endif
|
|
|
1178 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1179 |
#define ADC10_VECTOR ".int07" /* 0xFFEE ADC10 */
|
|
|
1180 |
#else
|
|
|
1181 |
#define ADC10_VECTOR (7 * 1u) /* 0xFFEE ADC10 */
|
|
|
1182 |
/*#define ADC10_ISR(func) ISR_VECTOR(func, ".int07") */ /* 0xFFEE ADC10 */ /* CCE V2 Style */
|
|
|
1183 |
#endif
|
|
|
1184 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1185 |
#define USCIAB0TX_VECTOR ".int08" /* 0xFFF0 USCI A0/B0 Transmit */
|
|
|
1186 |
#else
|
|
|
1187 |
#define USCIAB0TX_VECTOR (8 * 1u) /* 0xFFF0 USCI A0/B0 Transmit */
|
|
|
1188 |
/*#define USCIAB0TX_ISR(func) ISR_VECTOR(func, ".int08") */ /* 0xFFF0 USCI A0/B0 Transmit */ /* CCE V2 Style */
|
|
|
1189 |
#endif
|
|
|
1190 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1191 |
#define USCIAB0RX_VECTOR ".int09" /* 0xFFF2 USCI A0/B0 Receive */
|
|
|
1192 |
#else
|
|
|
1193 |
#define USCIAB0RX_VECTOR (9 * 1u) /* 0xFFF2 USCI A0/B0 Receive */
|
|
|
1194 |
/*#define USCIAB0RX_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 USCI A0/B0 Receive */ /* CCE V2 Style */
|
|
|
1195 |
#endif
|
|
|
1196 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1197 |
#define WDT_VECTOR ".int10" /* 0xFFF4 Watchdog Timer */
|
|
|
1198 |
#else
|
|
|
1199 |
#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */
|
|
|
1200 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
|
|
|
1201 |
#endif
|
|
|
1202 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1203 |
#define COMPARATORA_VECTOR ".int11" /* 0xFFF6 Comparator A */
|
|
|
1204 |
#else
|
|
|
1205 |
#define COMPARATORA_VECTOR (11 * 1u) /* 0xFFF6 Comparator A */
|
|
|
1206 |
/*#define COMPARATORA_ISR(func) ISR_VECTOR(func, ".int11") */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */
|
|
|
1207 |
#endif
|
|
|
1208 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1209 |
#define TIMER1_A1_VECTOR ".int12" /* 0xFFF8 Timer1_A CC1-4, TA1 */
|
|
|
1210 |
#else
|
|
|
1211 |
#define TIMER1_A1_VECTOR (12 * 1u) /* 0xFFF8 Timer1_A CC1-4, TA1 */
|
|
|
1212 |
/*#define TIMER1_A1_ISR(func) ISR_VECTOR(func, ".int12") */ /* 0xFFF8 Timer1_A CC1-4, TA1 */ /* CCE V2 Style */
|
|
|
1213 |
#endif
|
|
|
1214 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1215 |
#define TIMER1_A0_VECTOR ".int13" /* 0xFFFA Timer1_A CC0 */
|
|
|
1216 |
#else
|
|
|
1217 |
#define TIMER1_A0_VECTOR (13 * 1u) /* 0xFFFA Timer1_A CC0 */
|
|
|
1218 |
/*#define TIMER1_A0_ISR(func) ISR_VECTOR(func, ".int13") */ /* 0xFFFA Timer1_A CC0 */ /* CCE V2 Style */
|
|
|
1219 |
#endif
|
|
|
1220 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1221 |
#define NMI_VECTOR ".int14" /* 0xFFFC Non-maskable */
|
|
|
1222 |
#else
|
|
|
1223 |
#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */
|
|
|
1224 |
/*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
|
|
|
1225 |
#endif
|
|
|
1226 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1227 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
1228 |
#else
|
|
|
1229 |
#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
1230 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
1231 |
#endif
|
|
|
1232 |
|
|
|
1233 |
/* Alternate Names */
|
|
|
1234 |
|
|
|
1235 |
/************************************************************
|
|
|
1236 |
* End of Modules
|
|
|
1237 |
************************************************************/
|
|
|
1238 |
|
|
|
1239 |
#ifdef __cplusplus
|
|
|
1240 |
}
|
|
|
1241 |
#endif /* extern "C" */
|
|
|
1242 |
|
|
|
1243 |
#endif /* #ifndef __msp430x41x2 */
|
|
|
1244 |
|