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/******************************************************************************/
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/* Legacy Header File */
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/* Not recommended for use in new projects. */
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/* Please use the msp430.h file or the device specific header file */
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/******************************************************************************/
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* MSP430x32x devices.
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*
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* Texas Instruments, Version 2.2
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*
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* Rev. 1.1, Changed definition of LPM4 bits (device effect not changed)
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* Corrected LPMx_EXIT to reference new intrinsic _bic_SR_register_on_exit
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* The file contents were reordered
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* Rev. 1.2, Enclose all #define statements with parentheses
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* Rev. 1.3, Added sfrb for TCDAT and TCPLD
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* Rev. 1.4, Removed incorrect label 'BTRESET'
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* Rev. 2.1, Alignment of defintions in Users Guide and of version numbers
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* Rev. 2.2, Removed definitions for BTRESET
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*
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********************************************************************/
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#ifndef __msp430x32x
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#define __msp430x32x
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
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************************************************************/
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SFR_8BIT(IE1); /* Interrupt Enable 1 */
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#define WDTIE (0x01)
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#define OFIE (0x02)
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#define P0IE_0 (0x04)
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#define P0IE_1 (0x08)
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SFR_8BIT(IFG1); /* Interrupt Flag 1 */
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#define WDTIFG (0x01)
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#define OFIFG (0x02)
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#define P0IFG_0 (0x04)
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#define P0IFG_1 (0x08)
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#define NMIIFG (0x10)
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SFR_8BIT(IE2); /* Interrupt Enable 2 */
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#define ADIE (0x04)
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#define TPIE (0x08)
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#define BTIE (0x80)
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SFR_8BIT(IFG2); /* Interrupt Flag 2 */
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#define ADIFG (0x04)
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#define BTIFG (0x80)
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/************************************************************
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* WATCHDOG TIMER
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************************************************************/
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#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
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SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
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/* The bit names have been prefixed with "WDT" */
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#define WDTIS0 (0x0001)
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#define WDTIS1 (0x0002)
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#define WDTSSEL (0x0004)
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#define WDTCNTCL (0x0008)
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#define WDTTMSEL (0x0010)
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#define WDTNMI (0x0020)
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#define WDTNMIES (0x0040)
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#define WDTHOLD (0x0080)
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#define WDTPW (0x5A00)
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/* WDT-interval times [1ms] coded with Bits 0-2 */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* Watchdog mode -> reset after expired time */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* INTERRUPT CONTROL */
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/* These two bits are defined in the Special Function Registers */
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/* #define WDTIE 0x01 */
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/* #define WDTIFG 0x01 */
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/************************************************************
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* DIGITAL I/O PORT0
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************************************************************/
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#define __MSP430_HAS_PORT0__ /* Definition to show that Module is available */
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SFR_8BIT(P0IN); /* Port 0 Input */
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#define P0IN_0 (0x01)
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#define P0IN_1 (0x02)
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#define P0IN_2 (0x04)
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#define P0IN_3 (0x08)
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#define P0IN_4 (0x10)
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#define P0IN_5 (0x20)
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#define P0IN_6 (0x40)
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#define P0IN_7 (0x80)
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SFR_8BIT(P0OUT); /* Port 0 Output */
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#define P0OUT_0 (0x01)
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#define P0OUT_1 (0x02)
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#define P0OUT_2 (0x04)
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#define P0OUT_3 (0x08)
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#define P0OUT_4 (0x10)
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#define P0OUT_5 (0x20)
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#define P0OUT_6 (0x40)
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#define P0OUT_7 (0x80)
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SFR_8BIT(P0DIR); /* Port 0 Direction */
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#define P0DIR_0 (0x01)
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#define P0DIR_1 (0x02)
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#define P0DIR_2 (0x04)
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#define P0DIR_3 (0x08)
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#define P0DIR_4 (0x10)
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#define P0DIR_5 (0x20)
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#define P0DIR_6 (0x40)
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#define P0DIR_7 (0x80)
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SFR_8BIT(P0IFG); /* Port 0 Interrupt Flag */
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/* These two bits are defined in Interrupt Flag 1 */
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/* #define P0IFG_0 0x01 */
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/* #define P0IFG_1 0x02 */
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#define P0IFG_2 (0x04)
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#define P0IFG_3 (0x08)
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#define P0IFG_4 (0x10)
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#define P0IFG_5 (0x20)
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#define P0IFG_6 (0x40)
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#define P0IFG_7 (0x80)
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SFR_8BIT(P0IES); /* Port 0 Interrupt Edge Select */
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#define P0IES_0 (0x01)
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#define P0IES_1 (0x02)
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#define P0IES_2 (0x04)
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#define P0IES_3 (0x08)
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#define P0IES_4 (0x10)
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#define P0IES_5 (0x20)
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#define P0IES_6 (0x40)
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#define P0IES_7 (0x80)
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SFR_8BIT(P0IE); /* Port 0 Interrupt Enable */
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/* These two bits are defined in Interrupt Enable 1 */
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/* #define P0IE_0 0x01 */
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/* #define P0IE_1 0x02 */
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#define P0IE_2 (0x04)
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#define P0IE_3 (0x08)
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#define P0IE_4 (0x10)
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#define P0IE_5 (0x20)
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#define P0IE_6 (0x40)
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#define P0IE_7 (0x80)
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/************************************************************
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* LCD REGISTER
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************************************************************/
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#define __MSP430_HAS_LCD__ /* Definition to show that Module is available */
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SFR_8BIT(LCDCTL); /* LCD Control */
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/* the names of the mode bits are different from the spec */
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#define LCDON (0x01)
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#define LCDLOWR (0x02)
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#define LCDSON (0x04)
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#define LCDMX0 (0x08)
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#define LCDMX1 (0x10)
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#define LCDP0 (0x20)
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#define LCDP1 (0x40)
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#define LCDP2 (0x80)
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/* Display modes coded with Bits 2-4 */
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#define LCDSTATIC (LCDSON)
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#define LCD2MUX (LCDMX0+LCDSON)
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#define LCD3MUX (LCDMX1+LCDSON)
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#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
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/* Group select code with Bits 5-7 Seg.lines Dig.output */
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#define LCDSG0 (0x00) /* S0 - S1 O2 - O29 (default) */
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#define LCDSG0_1 (LCDP0) /* S0 - S5 O6 - O29 */
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#define LCDSG0_2 (LCDP1) /* S0 - S9 O10 - O29 */
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#define LCDSG0_3 (LCDP1+LCDP0) /* S0 - S13 O14 - O29 */
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#define LCDSG0_4 (LCDP2) /* S0 - S17 O18 - O29 */
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#define LCDSG0_5 (LCDP2+LCDP0) /* S0 - S21 O22 - O29 */
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#define LCDSG0_6 (LCDP2+LCDP1) /* S0 - S25 O26 - O29 */
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#define LCDSG0_7 (LCDP2+LCDP1+LCDP0) /* S0 - S29 --------- */
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/* NOTE: YOU CAN ONLY USE THE 'S' OR 'G' DECLARATIONS FOR A COMMAND */
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/* MOV #LCDSG0_3+LCDOG2_7,&LCDCTL ACTUALY MEANS MOV #LCDP1,&LCDCTL! */
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#define LCDOG1_7 (0x00) /* S0 - S1 O2 - O29 (default) */
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#define LCDOG2_7 (LCDP0) /* S0 - S5 O6 - O29 */
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#define LCDOG3_7 (LCDP1) /* S0 - S9 O10 - O29 */
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#define LCDOG4_7 (LCDP1+LCDP0) /* S0 - S13 O14 - O29 */
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#define LCDOG5_7 (LCDP2) /* S0 - S17 O18 - O29 */
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#define LCDOG6_7 (LCDP2+LCDP0) /* S0 - S21 O22 - O29 */
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#define LCDOG7 (LCDP2+LCDP1) /* S0 - S25 O26 - O29 */
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#define LCDOGOFF (LCDP2+LCDP1+LCDP0) /* S0 - S29 --------- */
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#define LCDMEM_ (0x0031) /* LCD Memory */
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#ifdef __ASM_HEADER__
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#define LCDMEM (LCDMEM_) /* LCD Memory (for assembler) */
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#else
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#define LCDMEM ((char*) LCDMEM_) /* LCD Memory (for C) */
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#endif
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SFR_8BIT(LCDM1); /* LCD Memory 1 */
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301 |
SFR_8BIT(LCDM2); /* LCD Memory 2 */
|
|
|
302 |
SFR_8BIT(LCDM3); /* LCD Memory 3 */
|
|
|
303 |
SFR_8BIT(LCDM4); /* LCD Memory 4 */
|
|
|
304 |
SFR_8BIT(LCDM5); /* LCD Memory 5 */
|
|
|
305 |
SFR_8BIT(LCDM6); /* LCD Memory 6 */
|
|
|
306 |
SFR_8BIT(LCDM7); /* LCD Memory 7 */
|
|
|
307 |
SFR_8BIT(LCDM8); /* LCD Memory 8 */
|
|
|
308 |
SFR_8BIT(LCDM9); /* LCD Memory 9 */
|
|
|
309 |
SFR_8BIT(LCDM10); /* LCD Memory 10 */
|
|
|
310 |
SFR_8BIT(LCDM11); /* LCD Memory 11 */
|
|
|
311 |
SFR_8BIT(LCDM12); /* LCD Memory 12 */
|
|
|
312 |
SFR_8BIT(LCDM13); /* LCD Memory 13 */
|
|
|
313 |
SFR_8BIT(LCDM14); /* LCD Memory 14 */
|
|
|
314 |
SFR_8BIT(LCDM15); /* LCD Memory 15 */
|
|
|
315 |
|
|
|
316 |
#define LCDMA (LCDM10) /* LCD Memory A */
|
|
|
317 |
#define LCDMB (LCDM11) /* LCD Memory B */
|
|
|
318 |
#define LCDMC (LCDM12) /* LCD Memory C */
|
|
|
319 |
#define LCDMD (LCDM13) /* LCD Memory D */
|
|
|
320 |
#define LCDME (LCDM14) /* LCD Memory E */
|
|
|
321 |
#define LCDMF (LCDM15) /* LCD Memory F */
|
|
|
322 |
|
|
|
323 |
/************************************************************
|
|
|
324 |
* BASIC TIMER
|
|
|
325 |
************************************************************/
|
|
|
326 |
#define __MSP430_HAS_BT__ /* Definition to show that Module is available */
|
|
|
327 |
|
|
|
328 |
SFR_8BIT(BTCTL); /* Basic Timer Control */
|
|
|
329 |
/* The bit names have been prefixed with "BT" */
|
|
|
330 |
#define BTIP0 (0x01)
|
|
|
331 |
#define BTIP1 (0x02)
|
|
|
332 |
#define BTIP2 (0x04)
|
|
|
333 |
#define BTFRFQ0 (0x08)
|
|
|
334 |
#define BTFRFQ1 (0x10)
|
|
|
335 |
#define BTDIV (0x20) /* fCLK2 = ACLK:256 */
|
|
|
336 |
#define BTHOLD (0x40) /* BT1 is held if this bit is set */
|
|
|
337 |
#define BTSSEL (0x80) /* fBT = fMCLK (main clock) */
|
|
|
338 |
|
|
|
339 |
SFR_8BIT(BTCNT1); /* Basic Timer Count 1 */
|
|
|
340 |
SFR_8BIT(BTCNT2); /* Basic Timer Count 2 */
|
|
|
341 |
|
|
|
342 |
/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
|
|
|
343 |
#define BT_fCLK2_ACLK (0x00)
|
|
|
344 |
#define BT_fCLK2_ACLK_DIV256 (BTDIV)
|
|
|
345 |
#define BT_fCLK2_MCLK (BTSSEL)
|
|
|
346 |
|
|
|
347 |
/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
|
|
|
348 |
#define BT_fCLK2_DIV2 (0x00) /* fINT = fCLK2:2 (default) */
|
|
|
349 |
#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */
|
|
|
350 |
#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */
|
|
|
351 |
#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT = fCLK2:16 */
|
|
|
352 |
#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */
|
|
|
353 |
#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT = fCLK2:64 */
|
|
|
354 |
#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT = fCLK2:128 */
|
|
|
355 |
#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 */
|
|
|
356 |
/* Frequency of LCD coded with Bits 3-4 */
|
|
|
357 |
#define BT_fLCD_DIV32 (0x00) /* fLCD = fACLK:32 (default) */
|
|
|
358 |
#define BT_fLCD_DIV64 (BTFRFQ0) /* fLCD = fACLK:64 */
|
|
|
359 |
#define BT_fLCD_DIV128 (BTFRFQ1) /* fLCD = fACLK:128 */
|
|
|
360 |
#define BT_fLCD_DIV256 (BTFRFQ1+BTFRFQ0) /* fLCD = fACLK:256 */
|
|
|
361 |
/* LCD frequency values with fBT=fACLK */
|
|
|
362 |
#define BT_fLCD_1K (0x00) /* fACLK:32 (default) */
|
|
|
363 |
#define BT_fLCD_512 (BTFRFQ0) /* fACLK:64 */
|
|
|
364 |
#define BT_fLCD_256 (BTFRFQ1) /* fACLK:128 */
|
|
|
365 |
#define BT_fLCD_128 (BTFRFQ1+BTFRFQ0) /* fACLK:256 */
|
|
|
366 |
/* LCD frequency values with fBT=fMCLK */
|
|
|
367 |
#define BT_fLCD_31K (BTSSEL) /* fMCLK:32 */
|
|
|
368 |
#define BT_fLCD_15_5K (BTSSEL+BTFRFQ0) /* fMCLK:64 */
|
|
|
369 |
#define BT_fLCD_7_8K (BTSSEL+BTFRFQ1+BTFRFQ0) /* fMCLK:256 */
|
|
|
370 |
/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
|
|
|
371 |
/* fBT=fACLK is thought for longer interval times */
|
|
|
372 |
#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */
|
|
|
373 |
#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */
|
|
|
374 |
#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */
|
|
|
375 |
#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms " */
|
|
|
376 |
#define BT_ADLY_1 (BTIP2) /* 1ms " */
|
|
|
377 |
#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms " */
|
|
|
378 |
#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms " */
|
|
|
379 |
#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms " */
|
|
|
380 |
#define BT_ADLY_16 (BTDIV) /* 16ms " */
|
|
|
381 |
#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms " */
|
|
|
382 |
#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms " */
|
|
|
383 |
#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms " */
|
|
|
384 |
#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms " */
|
|
|
385 |
#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms " */
|
|
|
386 |
#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms " */
|
|
|
387 |
#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms " */
|
|
|
388 |
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
|
|
|
389 |
/* the timing for short intervals is more precise than ACLK */
|
|
|
390 |
/* NOTE */
|
|
|
391 |
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
|
|
|
392 |
/* Too low interval time results in interrupts too frequent for the processor to handle! */
|
|
|
393 |
#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
|
|
|
394 |
#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms " *** too short for */
|
|
|
395 |
#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms " *** interrupt */
|
|
|
396 |
#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms " *** handling */
|
|
|
397 |
#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms " */
|
|
|
398 |
#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms " */
|
|
|
399 |
#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms " */
|
|
|
400 |
#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms " */
|
|
|
401 |
|
|
|
402 |
/* Reset/Hold coded with Bits 6-7 in BT(1)CTL */
|
|
|
403 |
/* this is for BT */
|
|
|
404 |
//#define BTRESET_CNT1 (BTRESET) /* BTCNT1 is reset while BTRESET is set */
|
|
|
405 |
//#define BTRESET_CNT1_2 (BTRESET+BTDIV) /* BTCNT1 .AND. BTCNT2 are reset while ~ is set */
|
|
|
406 |
/* this is for BT1 */
|
|
|
407 |
#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
|
|
|
408 |
#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
|
|
|
409 |
|
|
|
410 |
/* INTERRUPT CONTROL BITS */
|
|
|
411 |
/* #define BTIE 0x80 */
|
|
|
412 |
/* #define BTIFG 0x80 */
|
|
|
413 |
|
|
|
414 |
/************************************************************
|
|
|
415 |
* SYSTEM CLOCK GENERATOR
|
|
|
416 |
************************************************************/
|
|
|
417 |
#define __MSP430_HAS_FLL__ /* Definition to show that Module is available */
|
|
|
418 |
|
|
|
419 |
SFR_8BIT(SCFI0); /* System Clock Frequency Integrator 0 */
|
|
|
420 |
#define FN_2 (0x04)
|
|
|
421 |
#define FN_3 (0x08)
|
|
|
422 |
#define FN_4 (0x10)
|
|
|
423 |
|
|
|
424 |
SFR_8BIT(SCFI1); /* System Clock Frequency Integrator 1 */
|
|
|
425 |
SFR_8BIT(SCFQCTL); /* System Clock Frequency Control */
|
|
|
426 |
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
|
|
|
427 |
/* #define SCFQ_32K 0x00 fMCLK=1*fACLK only a range from */
|
|
|
428 |
/* #define SCFQ_64K 0x01 fMCLK=2*fACLK 3+1 to 127+1 is possible */
|
|
|
429 |
#define SCFQ_128K (0x03) /* fMCLK=4*fACLK */
|
|
|
430 |
#define SCFQ_256K (0x07) /* fMCLK=8*fACLK */
|
|
|
431 |
#define SCFQ_512K (0x0F) /* fMCLK=16*fACLK */
|
|
|
432 |
#define SCFQ_1M (0x1F) /* fMCLK=32*fACLK */
|
|
|
433 |
#define SCFQ_2M (0x3F) /* fMCLK=64*fACLK */
|
|
|
434 |
#define SCFQ_4M (0x7F) /* fMCLK=128*fACLK not possible for ICE */
|
|
|
435 |
|
|
|
436 |
SFR_8BIT(CBCTL); /* Crystal Buffer Control *** WRITE-ONLY *** */
|
|
|
437 |
#define CBE (0x01)
|
|
|
438 |
#define CBSEL0 (0x02)
|
|
|
439 |
#define CBSEL1 (0x04)
|
|
|
440 |
/* Source select of frequency at output pin XBUF coded with Bits 1-2 in CBCTL */
|
|
|
441 |
#define CBSEL_ACLK (0x00) /* source is ACLK (default after POR) */
|
|
|
442 |
#define CBSEL_ACLK_DIV2 (CBSEL0) /* source is ACLK/2 */
|
|
|
443 |
#define CBSEL_ACLK_DIV4 (CBSEL1) /* source is ACLK/4 */
|
|
|
444 |
#define CBSEL_MCLK (CBSEL1+CBSEL0) /* source is MCLK */
|
|
|
445 |
|
|
|
446 |
/* INTERRUPT CONTROL BITS */
|
|
|
447 |
/* These two bits are defined in the Special Function Registers */
|
|
|
448 |
/* #define OFIFG 0x02 */
|
|
|
449 |
/* #define OFIE 0x02 */
|
|
|
450 |
|
|
|
451 |
/************************************************************
|
|
|
452 |
* 8BIT TIMER/COUNTER
|
|
|
453 |
************************************************************/
|
|
|
454 |
#define __MSP430_HAS_8BTC__ /* Definition to show that Module is available */
|
|
|
455 |
|
|
|
456 |
SFR_8BIT(TCCTL); /* Timer/Counter Control */
|
|
|
457 |
/* The bit names have been prefixed with "TC" */
|
|
|
458 |
#define TCRXD (0x01)
|
|
|
459 |
#define TCTXD (0x02)
|
|
|
460 |
#define TCRXACT (0x04)
|
|
|
461 |
#define TCENCNT (0x08)
|
|
|
462 |
#define TCTXE (0x10)
|
|
|
463 |
#define TCISCTL (0x20)
|
|
|
464 |
#define TCSSEL0 (0x40)
|
|
|
465 |
#define TCSSEL1 (0x80)
|
|
|
466 |
/* Source select of clock input coded with Bits 6-7 */
|
|
|
467 |
#define TCSSEL_P01 (0x00) /* source is signal at pin P0.1 (default) */
|
|
|
468 |
#define TCSSEL_ACLK (TCSSEL0) /* source is ACLK */
|
|
|
469 |
#define TCSSEL_MCLK (TCSSEL1) /* source is MCLK */
|
|
|
470 |
#define TCSSEL_P01_MCLK (TCSSEL1+TCSSEL0) /* source is signal pin P0.1 .AND. MCLK */
|
|
|
471 |
|
|
|
472 |
SFR_8BIT(TCPLD); /* Timer/Counter Preload */
|
|
|
473 |
SFR_8BIT(TCDAT); /* Timer/Counter Data */
|
|
|
474 |
|
|
|
475 |
/************************************************************
|
|
|
476 |
* TIMER/PORT
|
|
|
477 |
************************************************************/
|
|
|
478 |
#define __MSP430_HAS_TP__ /* Definition to show that Module is available */
|
|
|
479 |
|
|
|
480 |
SFR_8BIT(TPCTL); /* Timer/Port Control */
|
|
|
481 |
#define EN1FG (0x01)
|
|
|
482 |
#define RC1FG (0x02)
|
|
|
483 |
#define RC2FG (0x04)
|
|
|
484 |
#define EN1 (0x08)
|
|
|
485 |
#define ENA (0x10)
|
|
|
486 |
#define ENB (0x20)
|
|
|
487 |
#define TPSSEL0 (0x40)
|
|
|
488 |
#define TPSSEL1 (0x80)
|
|
|
489 |
/* The EN1 signal of TPCNT1 is coded with with Bits 3-5 in TPCTL */
|
|
|
490 |
#define TPCNT1_EN_OFF (0x00) /* TPCNT1 is disabled */
|
|
|
491 |
#define TPCNT1_EN_ON (ENA) /* " is enabled */
|
|
|
492 |
#define TPCNT1_EN_nTPIN5 (ENB) /* " is enabled with ~TPIN.5 */
|
|
|
493 |
#define TPCNT1_EN_TPIN5 (TPSSEL0+ENB) /* " is enabled with TPIN.5 */
|
|
|
494 |
#define TPCNT1_EN_nCIN (ENB+ENA) /* " is enabled with ~CIN */
|
|
|
495 |
#define TPCNT1_EN_CIN (TPSSEL0+ENB+ENA) /* " is enabled with CIN */
|
|
|
496 |
|
|
|
497 |
/* Source select of clock input coded with Bits 6-7 in TPCTL */
|
|
|
498 |
#define TPSSEL_CLK1_CIN (0x00) /* CLK1 source is signal at CIN (default) */
|
|
|
499 |
#define TPSSEL_CLK1_ACLK (TPSSEL0) /* CLK1 source is ACLK */
|
|
|
500 |
#define TPSSEL_CLK1_MCLK (TPSSEL1) /* CLK1 source is MCLK */
|
|
|
501 |
|
|
|
502 |
/* DATA REGISTER ADDRESSES */
|
|
|
503 |
SFR_8BIT(TPCNT1); /* Timer/Port Counter 1 */
|
|
|
504 |
SFR_8BIT(TPCNT2); /* Timer/Port Counter 2 */
|
|
|
505 |
|
|
|
506 |
SFR_8BIT(TPD); /* Timer/Port Data */
|
|
|
507 |
#define TPD_0 (0x01)
|
|
|
508 |
#define TPD_1 (0x02)
|
|
|
509 |
#define TPD_2 (0x04)
|
|
|
510 |
#define TPD_3 (0x08)
|
|
|
511 |
#define TPD_4 (0x10)
|
|
|
512 |
#define TPD_5 (0x20)
|
|
|
513 |
#define CPON (0x40)
|
|
|
514 |
#define B16 (0x80)
|
|
|
515 |
|
|
|
516 |
SFR_8BIT(TPE); /* Timer/Port Enable */
|
|
|
517 |
#define TPE_0 (0x01)
|
|
|
518 |
#define TPE_1 (0x02)
|
|
|
519 |
#define TPE_2 (0x04)
|
|
|
520 |
#define TPE_3 (0x08)
|
|
|
521 |
#define TPE_4 (0x10)
|
|
|
522 |
#define TPE_5 (0x20)
|
|
|
523 |
#define TPSSEL2 (0x40)
|
|
|
524 |
#define TPSSEL3 (0x80)
|
|
|
525 |
/* Source select of clock input coded with Bits 6-7 in TPE
|
|
|
526 |
NOTE: If the control bit B16 in TPD is set, TPSSEL2/3
|
|
|
527 |
are 'don't care' and the clock source of counter
|
|
|
528 |
TPCNT2 is the same as of the counter TPCNT1. */
|
|
|
529 |
#define TPSSEL_CLK2_TPIN5 (0x00) /* CLK2 source is signal TPIN.5 (default) */
|
|
|
530 |
#define TPSSEL_CLK2_ACLK (TPSSEL2) /* CLK2 source is ACLK */
|
|
|
531 |
#define TPSSEL_CLK2_MCLK (TPSSEL3) /* CLK2 source is MCLK */
|
|
|
532 |
#define TPSSEL_CLK2_OFF (TPSSEL3+TPSSEL2)/* CLK2 source is disabled */
|
|
|
533 |
|
|
|
534 |
/************************************************************
|
|
|
535 |
* A/D CONVERTER 12 + 2
|
|
|
536 |
************************************************************/
|
|
|
537 |
#define __MSP430_HAS_ADC14__ /* Definition to show that Module is available */
|
|
|
538 |
|
|
|
539 |
SFR_16BIT(AIN); /* ADC Input */
|
|
|
540 |
SFR_16BIT(AEN); /* ADC Input Enable */
|
|
|
541 |
|
|
|
542 |
SFR_16BIT(ACTL); /* ADC Control */
|
|
|
543 |
/* the names of the mode bits are different from the spec */
|
|
|
544 |
#define ADSOC (0x0001)
|
|
|
545 |
#define ADSVCC (0x0002)
|
|
|
546 |
#define ADIN0 (0x0004)
|
|
|
547 |
#define ADIN1 (0x0008)
|
|
|
548 |
#define ADIN2 (0x0010)
|
|
|
549 |
#define ADINOFF (0x0020)
|
|
|
550 |
#define ADCSRC0 (0x0040)
|
|
|
551 |
#define ADCSRC1 (0x0080)
|
|
|
552 |
#define ADCSRCOFF (0x0100)
|
|
|
553 |
#define ADRNG0 (0x0200)
|
|
|
554 |
#define ADRNG1 (0x0400)
|
|
|
555 |
#define ADAUTO (0x0800)
|
|
|
556 |
#define ADPD (0x1000)
|
|
|
557 |
/* Channel select coded with Bits 2-5 */
|
|
|
558 |
#define ADIN_A0 (0x0000) /* (default) */
|
|
|
559 |
#define ADIN_A1 (ADIN0)
|
|
|
560 |
#define ADIN_A2 (ADIN1)
|
|
|
561 |
#define ADIN_A3 (ADIN1+ADIN0)
|
|
|
562 |
#define ADIN_A4 (ADIN2)
|
|
|
563 |
#define ADIN_A5 (ADIN2+ADIN0)
|
|
|
564 |
#define ADIN_A6 (ADIN2+ADIN1)
|
|
|
565 |
#define ADIN_A7 (ADIN2+ADIN1+ADIN0)
|
|
|
566 |
/* Current source output select coded with Bits 6-8 */
|
|
|
567 |
#define ADCSRC_A0 (0x0000) /* (default) */
|
|
|
568 |
#define ADCSRC_A1 (ADCSRC0)
|
|
|
569 |
#define ADCSRC_A2 (ADCSRC1)
|
|
|
570 |
#define ADCSRC_A3 (ADCSRC1+ADCSRC0)
|
|
|
571 |
/* Range select coded with Bits 9-11 */
|
|
|
572 |
#define ADRNG_A (0x0000) /* 0<=Vin<1/4Vref (default) */
|
|
|
573 |
#define ADRNG_B (ADRNG0) /* 1/4 Vref<=Vin<1/2 Vref */
|
|
|
574 |
#define ADRNG_C (ADRNG1) /* 1/2 Vref<=Vin<3/4 Vref */
|
|
|
575 |
#define ADRNG_D (ADRNG1+ADRNG0) /* 3/4 Vref<=Vin<1 Vref */
|
|
|
576 |
#define ADRNG_AUTO (ADAUTO) /* 0<=Vin<1 Vref auto detect range */
|
|
|
577 |
|
|
|
578 |
/* DATA REGISTER ADDRESS */
|
|
|
579 |
SFR_16BIT(ADAT); /* ADC Data */
|
|
|
580 |
|
|
|
581 |
/************************************************************
|
|
|
582 |
* EPROM CONTROL
|
|
|
583 |
************************************************************/
|
|
|
584 |
#define __MSP430_HAS_EPROM__ /* Definition to show that Module is available */
|
|
|
585 |
|
|
|
586 |
SFR_8BIT(EPCTL); /* EPROM Control */
|
|
|
587 |
#define EPEXE (0x01)
|
|
|
588 |
#define EPVPPS (0x02)
|
|
|
589 |
|
|
|
590 |
/************************************************************
|
|
|
591 |
* Interrupt Vectors (offset from 0xFFE0)
|
|
|
592 |
************************************************************/
|
|
|
593 |
|
|
|
594 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
595 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
596 |
#define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name
|
|
|
597 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
598 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
599 |
PLACE_VECTOR(VECTOR_NAME(func), offset)
|
|
|
600 |
|
|
|
601 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
602 |
#define PORT0_VECTOR ".int00" /* 0xFFE0 Port 0 Bits 2-7 [Lowest Priority] */
|
|
|
603 |
#else
|
|
|
604 |
#define PORT0_VECTOR (0 * 1u) /* 0xFFE0 Port 0 Bits 2-7 [Lowest Priority] */
|
|
|
605 |
/*#define PORT0_ISR(func) ISR_VECTOR(func, ".int00") */ /* 0xFFE0 Port 0 Bits 2-7 [Lowest Priority] */ /* CCE V2 Style */
|
|
|
606 |
#endif
|
|
|
607 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
608 |
#define BASICTIMER_VECTOR ".int01" /* 0xFFE2 Basic Timer */
|
|
|
609 |
#else
|
|
|
610 |
#define BASICTIMER_VECTOR (1 * 1u) /* 0xFFE2 Basic Timer */
|
|
|
611 |
/*#define BASICTIMER_ISR(func) ISR_VECTOR(func, ".int01") */ /* 0xFFE2 Basic Timer */ /* CCE V2 Style */
|
|
|
612 |
#endif
|
|
|
613 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
614 |
#define TIMERPORT_VECTOR ".int04" /* 0xFFE8 Timer/Port */
|
|
|
615 |
#else
|
|
|
616 |
#define TIMERPORT_VECTOR (4 * 1u) /* 0xFFE8 Timer/Port */
|
|
|
617 |
/*#define TIMERPORT_ISR(func) ISR_VECTOR(func, ".int04") */ /* 0xFFE8 Timer/Port */ /* CCE V2 Style */
|
|
|
618 |
#endif
|
|
|
619 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
620 |
#define ADC_VECTOR ".int05" /* 0xFFEA ADC */
|
|
|
621 |
#else
|
|
|
622 |
#define ADC_VECTOR (5 * 1u) /* 0xFFEA ADC */
|
|
|
623 |
/*#define ADC_ISR(func) ISR_VECTOR(func, ".int05") */ /* 0xFFEA ADC */ /* CCE V2 Style */
|
|
|
624 |
#endif
|
|
|
625 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
626 |
#define WDT_VECTOR ".int10" /* 0xFFF4 Watchdog Timer */
|
|
|
627 |
#else
|
|
|
628 |
#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */
|
|
|
629 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
|
|
|
630 |
#endif
|
|
|
631 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
632 |
#define IO1_VECTOR ".int12" /* 0xFFF8 Dedicated IO (P0.1) */
|
|
|
633 |
#else
|
|
|
634 |
#define IO1_VECTOR (12 * 1u) /* 0xFFF8 Dedicated IO (P0.1) */
|
|
|
635 |
/*#define IO1_ISR(func) ISR_VECTOR(func, ".int12") */ /* 0xFFF8 Dedicated IO (P0.1) */ /* CCE V2 Style */
|
|
|
636 |
#endif
|
|
|
637 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
638 |
#define IO0_VECTOR ".int13" /* 0xFFFA Dedicated IO (P0.0) */
|
|
|
639 |
#else
|
|
|
640 |
#define IO0_VECTOR (13 * 1u) /* 0xFFFA Dedicated IO (P0.0) */
|
|
|
641 |
/*#define IO0_ISR(func) ISR_VECTOR(func, ".int13") */ /* 0xFFFA Dedicated IO (P0.0) */ /* CCE V2 Style */
|
|
|
642 |
#endif
|
|
|
643 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
644 |
#define NMI_VECTOR ".int14" /* 0xFFFC Non-maskable */
|
|
|
645 |
#else
|
|
|
646 |
#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */
|
|
|
647 |
/*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
|
|
|
648 |
#endif
|
|
|
649 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
650 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
651 |
#else
|
|
|
652 |
#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
653 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
654 |
#endif
|
|
|
655 |
|
|
|
656 |
/************************************************************
|
|
|
657 |
* End of Modules
|
|
|
658 |
************************************************************/
|
|
|
659 |
|
|
|
660 |
#ifdef __cplusplus
|
|
|
661 |
}
|
|
|
662 |
#endif /* extern "C" */
|
|
|
663 |
|
|
|
664 |
#endif /* #ifndef __msp430x32x */
|
|
|
665 |
|