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2850 dpurdie 1 
/******************************************************************************/
2 
/* Legacy Header File                                                         */
3 
/* Not recommended for use in new projects.                                   */
4 
/* Please use the msp430.h file or the device specific header file            */
5 
/******************************************************************************/
6 
 
7 
/********************************************************************
8 
*
9 
* Standard register and bit definitions for the Texas Instruments
10 
* MSP430 microcontroller.
11 
*
12 
* This file supports assembler and C development for
13 
* MSP430x26x devices.
14 
*
15 
* Texas Instruments, Version 1.5
16 
*
17 
* Rev. 1.0, Initial Version
18 
* Rev. 1.1, changed PAREN from sfrb to sfrw
19 
* Rev. 1.2  added TLV in INFO Memory
20 
* Rev. 1.3, added definitions for Interrupt Vectors xxIV
21 
* Rev. 1.4, changed 'void __data20 * volatile' definition
22 
* Rev. 1.5, fixed define: TAG_ADC12_1 to 0x08
23 
*
24 
********************************************************************/
25 
 
26 
#ifndef __msp430x26x
27 
#define __msp430x26x
28 
 
29 
#ifdef __cplusplus
30 
extern "C" {
31 
#endif
32 
 
33 
 
34 
/*----------------------------------------------------------------------------*/
35 
/* PERIPHERAL FILE MAP                                                        */
36 
/*----------------------------------------------------------------------------*/
37 
 
38 
/* External references resolved by a device-specific linker command file */
39 
#define SFR_8BIT(address)   extern volatile unsigned char address
40 
#define SFR_16BIT(address)  extern volatile unsigned int address
41 
//#define SFR_20BIT(address)  extern volatile unsigned int address
42 
typedef void (* __SFR_FARPTR)();
43 
#define SFR_20BIT(address) extern __SFR_FARPTR address
44 
#define SFR_32BIT(address)  extern volatile unsigned long address
45 
 
46 
 
47 
 
48 
/************************************************************
49 
* STANDARD BITS
50 
************************************************************/
51 
 
52 
#define BIT0                   (0x0001)
53 
#define BIT1                   (0x0002)
54 
#define BIT2                   (0x0004)
55 
#define BIT3                   (0x0008)
56 
#define BIT4                   (0x0010)
57 
#define BIT5                   (0x0020)
58 
#define BIT6                   (0x0040)
59 
#define BIT7                   (0x0080)
60 
#define BIT8                   (0x0100)
61 
#define BIT9                   (0x0200)
62 
#define BITA                   (0x0400)
63 
#define BITB                   (0x0800)
64 
#define BITC                   (0x1000)
65 
#define BITD                   (0x2000)
66 
#define BITE                   (0x4000)
67 
#define BITF                   (0x8000)
68 
 
69 
/************************************************************
70 
* STATUS REGISTER BITS
71 
************************************************************/
72 
 
73 
#define C                      (0x0001)
74 
#define Z                      (0x0002)
75 
#define N                      (0x0004)
76 
#define V                      (0x0100)
77 
#define GIE                    (0x0008)
78 
#define CPUOFF                 (0x0010)
79 
#define OSCOFF                 (0x0020)
80 
#define SCG0                   (0x0040)
81 
#define SCG1                   (0x0080)
82 
 
83 
/* Low Power Modes coded with Bits 4-7 in SR */
84 
 
85 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
86 
#define LPM0                   (CPUOFF)
87 
#define LPM1                   (SCG0+CPUOFF)
88 
#define LPM2                   (SCG1+CPUOFF)
89 
#define LPM3                   (SCG1+SCG0+CPUOFF)
90 
#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
91 
/* End #defines for assembler */
92 
 
93 
#else /* Begin #defines for C */
94 
#define LPM0_bits              (CPUOFF)
95 
#define LPM1_bits              (SCG0+CPUOFF)
96 
#define LPM2_bits              (SCG1+CPUOFF)
97 
#define LPM3_bits              (SCG1+SCG0+CPUOFF)
98 
#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
99 
 
100 
#include "in430.h"
101 
 
102 
#define LPM0         _bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
103 
#define LPM0_EXIT    _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
104 
#define LPM1         _bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
105 
#define LPM1_EXIT    _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
106 
#define LPM2         _bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
107 
#define LPM2_EXIT    _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
108 
#define LPM3         _bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
109 
#define LPM3_EXIT    _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
110 
#define LPM4         _bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
111 
#define LPM4_EXIT    _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
112 
#endif /* End #defines for C */
113 
 
114 
/************************************************************
115 
* CPU
116 
************************************************************/
117 
#define __MSP430_HAS_MSP430X_CPU__                /* Definition to show that it has MSP430X CPU */
118 
 
119 
/************************************************************
120 
* PERIPHERAL FILE MAP
121 
************************************************************/
122 
 
123 
/************************************************************
124 
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
125 
************************************************************/
126 
 
127 
SFR_8BIT(IE1);                                /* Interrupt Enable 1 */
128 
#define WDTIE                  (0x01)         /* Watchdog Interrupt Enable */
129 
#define OFIE                   (0x02)         /* Osc. Fault  Interrupt Enable */
130 
#define NMIIE                  (0x10)         /* NMI Interrupt Enable */
131 
#define ACCVIE                 (0x20)         /* Flash Access Violation Interrupt Enable */
132 
 
133 
SFR_8BIT(IFG1);                               /* Interrupt Flag 1 */
134 
#define WDTIFG                 (0x01)         /* Watchdog Interrupt Flag */
135 
#define OFIFG                  (0x02)         /* Osc. Fault Interrupt Flag */
136 
#define PORIFG                 (0x04)         /* Power On Interrupt Flag */
137 
#define RSTIFG                 (0x08)         /* Reset Interrupt Flag */
138 
#define NMIIFG                 (0x10)         /* NMI Interrupt Flag */
139 
 
140 
SFR_8BIT(IE2);                                /* Interrupt Enable 2 */
141 
#define UC0IE                  IE2
142 
#define UCA0RXIE               (0x01)
143 
#define UCA0TXIE               (0x02)
144 
#define UCB0RXIE               (0x04)
145 
#define UCB0TXIE               (0x08)
146 
 
147 
SFR_8BIT(IFG2);                               /* Interrupt Flag 2 */
148 
#define UC0IFG                 IFG2
149 
#define UCA0RXIFG              (0x01)
150 
#define UCA0TXIFG              (0x02)
151 
#define UCB0RXIFG              (0x04)
152 
#define UCB0TXIFG              (0x08)
153 
 
154 
SFR_8BIT(UC1IE);                              /* USCI 1 Interrupt Enable */
155 
#define UCA1RXIE               (0x01)
156 
#define UCA1TXIE               (0x02)
157 
#define UCB1RXIE               (0x04)
158 
#define UCB1TXIE               (0x08)
159 
 
160 
SFR_8BIT(UC1IFG);                             /* ISCI 1 Interrupt Flags */
161 
#define UCA1RXIFG              (0x01)
162 
#define UCA1TXIFG              (0x02)
163 
#define UCB1RXIFG              (0x04)
164 
#define UCB1TXIFG              (0x08)
165 
 
166 
/************************************************************
167 
* ADC12
168 
************************************************************/
169 
#define __MSP430_HAS_ADC12__                  /* Definition to show that Module is available */
170 
 
171 
SFR_16BIT(ADC12CTL0);                         /* ADC12 Control 0 */
172 
SFR_16BIT(ADC12CTL1);                         /* ADC12 Control 1 */
173 
SFR_16BIT(ADC12IFG);                          /* ADC12 Interrupt Flag */
174 
SFR_16BIT(ADC12IE);                           /* ADC12 Interrupt Enable */
175 
SFR_16BIT(ADC12IV);                           /* ADC12 Interrupt Vector Word */
176 
 
177 
#define ADC12MEM_              (0x0140)       /* ADC12 Conversion Memory */
178 
#ifdef __ASM_HEADER__
179 
#define ADC12MEM               (ADC12MEM_)    /* ADC12 Conversion Memory (for assembler) */
180 
#else
181 
#define ADC12MEM               ((int*)        ADC12MEM_) /* ADC12 Conversion Memory (for C) */
182 
#endif
183 
SFR_16BIT(ADC12MEM0);                         /* ADC12 Conversion Memory 0 */
184 
SFR_16BIT(ADC12MEM1);                         /* ADC12 Conversion Memory 1 */
185 
SFR_16BIT(ADC12MEM2);                         /* ADC12 Conversion Memory 2 */
186 
SFR_16BIT(ADC12MEM3);                         /* ADC12 Conversion Memory 3 */
187 
SFR_16BIT(ADC12MEM4);                         /* ADC12 Conversion Memory 4 */
188 
SFR_16BIT(ADC12MEM5);                         /* ADC12 Conversion Memory 5 */
189 
SFR_16BIT(ADC12MEM6);                         /* ADC12 Conversion Memory 6 */
190 
SFR_16BIT(ADC12MEM7);                         /* ADC12 Conversion Memory 7 */
191 
SFR_16BIT(ADC12MEM8);                         /* ADC12 Conversion Memory 8 */
192 
SFR_16BIT(ADC12MEM9);                         /* ADC12 Conversion Memory 9 */
193 
SFR_16BIT(ADC12MEM10);                        /* ADC12 Conversion Memory 10 */
194 
SFR_16BIT(ADC12MEM11);                        /* ADC12 Conversion Memory 11 */
195 
SFR_16BIT(ADC12MEM12);                        /* ADC12 Conversion Memory 12 */
196 
SFR_16BIT(ADC12MEM13);                        /* ADC12 Conversion Memory 13 */
197 
SFR_16BIT(ADC12MEM14);                        /* ADC12 Conversion Memory 14 */
198 
SFR_16BIT(ADC12MEM15);                        /* ADC12 Conversion Memory 15 */
199 
 
200 
#define ADC12MCTL_             (0x0080)       /* ADC12 Memory Control */
201 
#ifdef __ASM_HEADER__
202 
#define ADC12MCTL              (ADC12MCTL_)   /* ADC12 Memory Control (for assembler) */
203 
#else
204 
#define ADC12MCTL              ((char*)       ADC12MCTL_) /* ADC12 Memory Control (for C) */
205 
#endif
206 
SFR_8BIT(ADC12MCTL0);                         /* ADC12 Memory Control 0 */
207 
SFR_8BIT(ADC12MCTL1);                         /* ADC12 Memory Control 1 */
208 
SFR_8BIT(ADC12MCTL2);                         /* ADC12 Memory Control 2 */
209 
SFR_8BIT(ADC12MCTL3);                         /* ADC12 Memory Control 3 */
210 
SFR_8BIT(ADC12MCTL4);                         /* ADC12 Memory Control 4 */
211 
SFR_8BIT(ADC12MCTL5);                         /* ADC12 Memory Control 5 */
212 
SFR_8BIT(ADC12MCTL6);                         /* ADC12 Memory Control 6 */
213 
SFR_8BIT(ADC12MCTL7);                         /* ADC12 Memory Control 7 */
214 
SFR_8BIT(ADC12MCTL8);                         /* ADC12 Memory Control 8 */
215 
SFR_8BIT(ADC12MCTL9);                         /* ADC12 Memory Control 9 */
216 
SFR_8BIT(ADC12MCTL10);                        /* ADC12 Memory Control 10 */
217 
SFR_8BIT(ADC12MCTL11);                        /* ADC12 Memory Control 11 */
218 
SFR_8BIT(ADC12MCTL12);                        /* ADC12 Memory Control 12 */
219 
SFR_8BIT(ADC12MCTL13);                        /* ADC12 Memory Control 13 */
220 
SFR_8BIT(ADC12MCTL14);                        /* ADC12 Memory Control 14 */
221 
SFR_8BIT(ADC12MCTL15);                        /* ADC12 Memory Control 15 */
222 
 
223 
/* ADC12CTL0 */
224 
#define ADC12SC                (0x001)        /* ADC12 Start Conversion */
225 
#define ENC                    (0x002)        /* ADC12 Enable Conversion */
226 
#define ADC12TOVIE             (0x004)        /* ADC12 Timer Overflow interrupt enable */
227 
#define ADC12OVIE              (0x008)        /* ADC12 Overflow interrupt enable */
228 
#define ADC12ON                (0x010)        /* ADC12 On/enable */
229 
#define REFON                  (0x020)        /* ADC12 Reference on */
230 
#define REF2_5V                (0x040)        /* ADC12 Ref 0:1.5V / 1:2.5V */
231 
#define MSC                    (0x080)        /* ADC12 Multiple SampleConversion */
232 
#define SHT00                  (0x0100)       /* ADC12 Sample Hold 0 Select 0 */
233 
#define SHT01                  (0x0200)       /* ADC12 Sample Hold 0 Select 1 */
234 
#define SHT02                  (0x0400)       /* ADC12 Sample Hold 0 Select 2 */
235 
#define SHT03                  (0x0800)       /* ADC12 Sample Hold 0 Select 3 */
236 
#define SHT10                  (0x1000)       /* ADC12 Sample Hold 0 Select 0 */
237 
#define SHT11                  (0x2000)       /* ADC12 Sample Hold 1 Select 1 */
238 
#define SHT12                  (0x4000)       /* ADC12 Sample Hold 2 Select 2 */
239 
#define SHT13                  (0x8000)       /* ADC12 Sample Hold 3 Select 3 */
240 
#define MSH                    (0x080)
241 
 
242 
#define SHT0_0                 (0*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 0 */
243 
#define SHT0_1                 (1*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 1 */
244 
#define SHT0_2                 (2*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 2 */
245 
#define SHT0_3                 (3*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 3 */
246 
#define SHT0_4                 (4*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 4 */
247 
#define SHT0_5                 (5*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 5 */
248 
#define SHT0_6                 (6*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 6 */
249 
#define SHT0_7                 (7*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 7 */
250 
#define SHT0_8                 (8*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 8 */
251 
#define SHT0_9                 (9*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 9 */
252 
#define SHT0_10                (10*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 10 */
253 
#define SHT0_11                (11*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 11 */
254 
#define SHT0_12                (12*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 12 */
255 
#define SHT0_13                (13*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 13 */
256 
#define SHT0_14                (14*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 14 */
257 
#define SHT0_15                (15*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 15 */
258 
 
259 
#define SHT1_0                 (0*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 0 */
260 
#define SHT1_1                 (1*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 1 */
261 
#define SHT1_2                 (2*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 2 */
262 
#define SHT1_3                 (3*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 3 */
263 
#define SHT1_4                 (4*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 4 */
264 
#define SHT1_5                 (5*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 5 */
265 
#define SHT1_6                 (6*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 6 */
266 
#define SHT1_7                 (7*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 7 */
267 
#define SHT1_8                 (8*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 8 */
268 
#define SHT1_9                 (9*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 9 */
269 
#define SHT1_10                (10*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 10 */
270 
#define SHT1_11                (11*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 11 */
271 
#define SHT1_12                (12*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 12 */
272 
#define SHT1_13                (13*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 13 */
273 
#define SHT1_14                (14*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 14 */
274 
#define SHT1_15                (15*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 15 */
275 
 
276 
/* ADC12CTL1 */
277 
#define ADC12BUSY              (0x0001)       /* ADC12 Busy */
278 
#define CONSEQ0                (0x0002)       /* ADC12 Conversion Sequence Select 0 */
279 
#define CONSEQ1                (0x0004)       /* ADC12 Conversion Sequence Select 1 */
280 
#define ADC12SSEL0             (0x0008)       /* ADC12 Clock Source Select 0 */
281 
#define ADC12SSEL1             (0x0010)       /* ADC12 Clock Source Select 1 */
282 
#define ADC12DIV0              (0x0020)       /* ADC12 Clock Divider Select 0 */
283 
#define ADC12DIV1              (0x0040)       /* ADC12 Clock Divider Select 1 */
284 
#define ADC12DIV2              (0x0080)       /* ADC12 Clock Divider Select 2 */
285 
#define ISSH                   (0x0100)       /* ADC12 Invert Sample Hold Signal */
286 
#define SHP                    (0x0200)       /* ADC12 Sample/Hold Pulse Mode */
287 
#define SHS0                   (0x0400)       /* ADC12 Sample/Hold Source 0 */
288 
#define SHS1                   (0x0800)       /* ADC12 Sample/Hold Source 1 */
289 
#define CSTARTADD0             (0x1000)       /* ADC12 Conversion Start Address 0 */
290 
#define CSTARTADD1             (0x2000)       /* ADC12 Conversion Start Address 1 */
291 
#define CSTARTADD2             (0x4000)       /* ADC12 Conversion Start Address 2 */
292 
#define CSTARTADD3             (0x8000)       /* ADC12 Conversion Start Address 3 */
293 
 
294 
#define CONSEQ_0               (0*2u)         /* ADC12 Conversion Sequence Select: 0 */
295 
#define CONSEQ_1               (1*2u)         /* ADC12 Conversion Sequence Select: 1 */
296 
#define CONSEQ_2               (2*2u)         /* ADC12 Conversion Sequence Select: 2 */
297 
#define CONSEQ_3               (3*2u)         /* ADC12 Conversion Sequence Select: 3 */
298 
#define ADC12SSEL_0            (0*8u)         /* ADC12 Clock Source Select: 0 */
299 
#define ADC12SSEL_1            (1*8u)         /* ADC12 Clock Source Select: 1 */
300 
#define ADC12SSEL_2            (2*8u)         /* ADC12 Clock Source Select: 2 */
301 
#define ADC12SSEL_3            (3*8u)         /* ADC12 Clock Source Select: 3 */
302 
#define ADC12DIV_0             (0*0x20u)      /* ADC12 Clock Divider Select: 0 */
303 
#define ADC12DIV_1             (1*0x20u)      /* ADC12 Clock Divider Select: 1 */
304 
#define ADC12DIV_2             (2*0x20u)      /* ADC12 Clock Divider Select: 2 */
305 
#define ADC12DIV_3             (3*0x20u)      /* ADC12 Clock Divider Select: 3 */
306 
#define ADC12DIV_4             (4*0x20u)      /* ADC12 Clock Divider Select: 4 */
307 
#define ADC12DIV_5             (5*0x20u)      /* ADC12 Clock Divider Select: 5 */
308 
#define ADC12DIV_6             (6*0x20u)      /* ADC12 Clock Divider Select: 6 */
309 
#define ADC12DIV_7             (7*0x20u)      /* ADC12 Clock Divider Select: 7 */
310 
#define SHS_0                  (0*0x400u)     /* ADC12 Sample/Hold Source: 0 */
311 
#define SHS_1                  (1*0x400u)     /* ADC12 Sample/Hold Source: 1 */
312 
#define SHS_2                  (2*0x400u)     /* ADC12 Sample/Hold Source: 2 */
313 
#define SHS_3                  (3*0x400u)     /* ADC12 Sample/Hold Source: 3 */
314 
#define CSTARTADD_0            (0*0x1000u)    /* ADC12 Conversion Start Address: 0 */
315 
#define CSTARTADD_1            (1*0x1000u)    /* ADC12 Conversion Start Address: 1 */
316 
#define CSTARTADD_2            (2*0x1000u)    /* ADC12 Conversion Start Address: 2 */
317 
#define CSTARTADD_3            (3*0x1000u)    /* ADC12 Conversion Start Address: 3 */
318 
#define CSTARTADD_4            (4*0x1000u)    /* ADC12 Conversion Start Address: 4 */
319 
#define CSTARTADD_5            (5*0x1000u)    /* ADC12 Conversion Start Address: 5 */
320 
#define CSTARTADD_6            (6*0x1000u)    /* ADC12 Conversion Start Address: 6 */
321 
#define CSTARTADD_7            (7*0x1000u)    /* ADC12 Conversion Start Address: 7 */
322 
#define CSTARTADD_8            (8*0x1000u)    /* ADC12 Conversion Start Address: 8 */
323 
#define CSTARTADD_9            (9*0x1000u)    /* ADC12 Conversion Start Address: 9 */
324 
#define CSTARTADD_10           (10*0x1000u)   /* ADC12 Conversion Start Address: 10 */
325 
#define CSTARTADD_11           (11*0x1000u)   /* ADC12 Conversion Start Address: 11 */
326 
#define CSTARTADD_12           (12*0x1000u)   /* ADC12 Conversion Start Address: 12 */
327 
#define CSTARTADD_13           (13*0x1000u)   /* ADC12 Conversion Start Address: 13 */
328 
#define CSTARTADD_14           (14*0x1000u)   /* ADC12 Conversion Start Address: 14 */
329 
#define CSTARTADD_15           (15*0x1000u)   /* ADC12 Conversion Start Address: 15 */
330 
 
331 
/* ADC12MCTLx */
332 
#define INCH0                  (0x0001)       /* ADC12 Input Channel Select Bit 0 */
333 
#define INCH1                  (0x0002)       /* ADC12 Input Channel Select Bit 1 */
334 
#define INCH2                  (0x0004)       /* ADC12 Input Channel Select Bit 2 */
335 
#define INCH3                  (0x0008)       /* ADC12 Input Channel Select Bit 3 */
336 
#define SREF0                  (0x0010)       /* ADC12 Select Reference Bit 0 */
337 
#define SREF1                  (0x0020)       /* ADC12 Select Reference Bit 1 */
338 
#define SREF2                  (0x0040)       /* ADC12 Select Reference Bit 2 */
339 
#define EOS                    (0x0080)       /* ADC12 End of Sequence */
340 
 
341 
#define INCH_0                 (0)            /* ADC12 Input Channel 0 */
342 
#define INCH_1                 (1)            /* ADC12 Input Channel 1 */
343 
#define INCH_2                 (2)            /* ADC12 Input Channel 2 */
344 
#define INCH_3                 (3)            /* ADC12 Input Channel 3 */
345 
#define INCH_4                 (4)            /* ADC12 Input Channel 4 */
346 
#define INCH_5                 (5)            /* ADC12 Input Channel 5 */
347 
#define INCH_6                 (6)            /* ADC12 Input Channel 6 */
348 
#define INCH_7                 (7)            /* ADC12 Input Channel 7 */
349 
#define INCH_8                 (8)            /* ADC12 Input Channel 8 */
350 
#define INCH_9                 (9)            /* ADC12 Input Channel 9 */
351 
#define INCH_10                (10)           /* ADC12 Input Channel 10 */
352 
#define INCH_11                (11)           /* ADC12 Input Channel 11 */
353 
#define INCH_12                (12)           /* ADC12 Input Channel 12 */
354 
#define INCH_13                (13)           /* ADC12 Input Channel 13 */
355 
#define INCH_14                (14)           /* ADC12 Input Channel 14 */
356 
#define INCH_15                (15)           /* ADC12 Input Channel 15 */
357 
 
358 
#define SREF_0                 (0*0x10u)      /* ADC12 Select Reference 0 */
359 
#define SREF_1                 (1*0x10u)      /* ADC12 Select Reference 1 */
360 
#define SREF_2                 (2*0x10u)      /* ADC12 Select Reference 2 */
361 
#define SREF_3                 (3*0x10u)      /* ADC12 Select Reference 3 */
362 
#define SREF_4                 (4*0x10u)      /* ADC12 Select Reference 4 */
363 
#define SREF_5                 (5*0x10u)      /* ADC12 Select Reference 5 */
364 
#define SREF_6                 (6*0x10u)      /* ADC12 Select Reference 6 */
365 
#define SREF_7                 (7*0x10u)      /* ADC12 Select Reference 7 */
366 
 
367 
/* ADC12IV Definitions */
368 
#define ADC12IV_NONE           (0x0000)       /* No Interrupt pending */
369 
#define ADC12IV_ADC12OVIFG     (0x0002)       /* ADC12OVIFG */
370 
#define ADC12IV_ADC12TOVIFG    (0x0004)       /* ADC12TOVIFG */
371 
#define ADC12IV_ADC12IFG0      (0x0006)       /* ADC12IFG0 */
372 
#define ADC12IV_ADC12IFG1      (0x0008)       /* ADC12IFG1 */
373 
#define ADC12IV_ADC12IFG2      (0x000A)       /* ADC12IFG2 */
374 
#define ADC12IV_ADC12IFG3      (0x000C)       /* ADC12IFG3 */
375 
#define ADC12IV_ADC12IFG4      (0x000E)       /* ADC12IFG4 */
376 
#define ADC12IV_ADC12IFG5      (0x0010)       /* ADC12IFG5 */
377 
#define ADC12IV_ADC12IFG6      (0x0012)       /* ADC12IFG6 */
378 
#define ADC12IV_ADC12IFG7      (0x0014)       /* ADC12IFG7 */
379 
#define ADC12IV_ADC12IFG8      (0x0016)       /* ADC12IFG8 */
380 
#define ADC12IV_ADC12IFG9      (0x0018)       /* ADC12IFG9 */
381 
#define ADC12IV_ADC12IFG10     (0x001A)       /* ADC12IFG10 */
382 
#define ADC12IV_ADC12IFG11     (0x001C)       /* ADC12IFG11 */
383 
#define ADC12IV_ADC12IFG12     (0x001E)       /* ADC12IFG12 */
384 
#define ADC12IV_ADC12IFG13     (0x0020)       /* ADC12IFG13 */
385 
#define ADC12IV_ADC12IFG14     (0x0022)       /* ADC12IFG14 */
386 
#define ADC12IV_ADC12IFG15     (0x0024)       /* ADC12IFG15 */
387 
 
388 
/************************************************************
389 
* Basic Clock Module
390 
************************************************************/
391 
#define __MSP430_HAS_BC2__                    /* Definition to show that Module is available */
392 
 
393 
SFR_8BIT(DCOCTL);                             /* DCO Clock Frequency Control */
394 
SFR_8BIT(BCSCTL1);                            /* Basic Clock System Control 1 */
395 
SFR_8BIT(BCSCTL2);                            /* Basic Clock System Control 2 */
396 
SFR_8BIT(BCSCTL3);                            /* Basic Clock System Control 3 */
397 
 
398 
#define MOD0                   (0x01)         /* Modulation Bit 0 */
399 
#define MOD1                   (0x02)         /* Modulation Bit 1 */
400 
#define MOD2                   (0x04)         /* Modulation Bit 2 */
401 
#define MOD3                   (0x08)         /* Modulation Bit 3 */
402 
#define MOD4                   (0x10)         /* Modulation Bit 4 */
403 
#define DCO0                   (0x20)         /* DCO Select Bit 0 */
404 
#define DCO1                   (0x40)         /* DCO Select Bit 1 */
405 
#define DCO2                   (0x80)         /* DCO Select Bit 2 */
406 
 
407 
#define RSEL0                  (0x01)         /* Range Select Bit 0 */
408 
#define RSEL1                  (0x02)         /* Range Select Bit 1 */
409 
#define RSEL2                  (0x04)         /* Range Select Bit 2 */
410 
#define RSEL3                  (0x08)         /* Range Select Bit 3 */
411 
#define DIVA0                  (0x10)         /* ACLK Divider 0 */
412 
#define DIVA1                  (0x20)         /* ACLK Divider 1 */
413 
#define XTS                    (0x40)         /* LFXTCLK 0:Low Freq. / 1: High Freq. */
414 
#define XT2OFF                 (0x80)         /* Enable XT2CLK */
415 
 
416 
#define DIVA_0                 (0x00)         /* ACLK Divider 0: /1 */
417 
#define DIVA_1                 (0x10)         /* ACLK Divider 1: /2 */
418 
#define DIVA_2                 (0x20)         /* ACLK Divider 2: /4 */
419 
#define DIVA_3                 (0x30)         /* ACLK Divider 3: /8 */
420 
 
421 
#define DCOR                   (0x01)         /* Enable External Resistor : 1 */
422 
#define DIVS0                  (0x02)         /* SMCLK Divider 0 */
423 
#define DIVS1                  (0x04)         /* SMCLK Divider 1 */
424 
#define SELS                   (0x08)         /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
425 
#define DIVM0                  (0x10)         /* MCLK Divider 0 */
426 
#define DIVM1                  (0x20)         /* MCLK Divider 1 */
427 
#define SELM0                  (0x40)         /* MCLK Source Select 0 */
428 
#define SELM1                  (0x80)         /* MCLK Source Select 1 */
429 
 
430 
#define DIVS_0                 (0x00)         /* SMCLK Divider 0: /1 */
431 
#define DIVS_1                 (0x02)         /* SMCLK Divider 1: /2 */
432 
#define DIVS_2                 (0x04)         /* SMCLK Divider 2: /4 */
433 
#define DIVS_3                 (0x06)         /* SMCLK Divider 3: /8 */
434 
 
435 
#define DIVM_0                 (0x00)         /* MCLK Divider 0: /1 */
436 
#define DIVM_1                 (0x10)         /* MCLK Divider 1: /2 */
437 
#define DIVM_2                 (0x20)         /* MCLK Divider 2: /4 */
438 
#define DIVM_3                 (0x30)         /* MCLK Divider 3: /8 */
439 
 
440 
#define SELM_0                 (0x00)         /* MCLK Source Select 0: DCOCLK */
441 
#define SELM_1                 (0x40)         /* MCLK Source Select 1: DCOCLK */
442 
#define SELM_2                 (0x80)         /* MCLK Source Select 2: XT2CLK/LFXTCLK */
443 
#define SELM_3                 (0xC0)         /* MCLK Source Select 3: LFXTCLK */
444 
 
445 
#define LFXT1OF                (0x01)         /* Low/high Frequency Oscillator Fault Flag */
446 
#define XT2OF                  (0x02)         /* High frequency oscillator 2 fault flag */
447 
#define XCAP0                  (0x04)         /* XIN/XOUT Cap 0 */
448 
#define XCAP1                  (0x08)         /* XIN/XOUT Cap 1 */
449 
#define LFXT1S0                (0x10)         /* Mode 0 for LFXT1 (XTS = 0) */
450 
#define LFXT1S1                (0x20)         /* Mode 1 for LFXT1 (XTS = 0) */
451 
#define XT2S0                  (0x40)         /* Mode 0 for XT2 */
452 
#define XT2S1                  (0x80)         /* Mode 1 for XT2 */
453 
 
454 
#define XCAP_0                 (0x00)         /* XIN/XOUT Cap : 0 pF */
455 
#define XCAP_1                 (0x04)         /* XIN/XOUT Cap : 6 pF */
456 
#define XCAP_2                 (0x08)         /* XIN/XOUT Cap : 10 pF */
457 
#define XCAP_3                 (0x0C)         /* XIN/XOUT Cap : 12.5 pF */
458 
 
459 
#define LFXT1S_0               (0x00)         /* Mode 0 for LFXT1 : Normal operation */
460 
#define LFXT1S_1               (0x10)         /* Mode 1 for LFXT1 : Reserved */
461 
#define LFXT1S_2               (0x20)         /* Mode 2 for LFXT1 : VLO */
462 
#define LFXT1S_3               (0x30)         /* Mode 3 for LFXT1 : Digital input signal */
463 
 
464 
#define XT2S_0                 (0x00)         /* Mode 0 for XT2 : 0.4 - 1 MHz */
465 
#define XT2S_1                 (0x40)         /* Mode 1 for XT2 : 1 - 4 MHz */
466 
#define XT2S_2                 (0x80)         /* Mode 2 for XT2 : 2 - 16 MHz */
467 
#define XT2S_3                 (0xC0)         /* Mode 3 for XT2 : Digital input signal */
468 
 
469 
/************************************************************
470 
* Comparator A
471 
************************************************************/
472 
#define __MSP430_HAS_CAPLUS__                 /* Definition to show that Module is available */
473 
 
474 
SFR_8BIT(CACTL1);                             /* Comparator A Control 1 */
475 
SFR_8BIT(CACTL2);                             /* Comparator A Control 2 */
476 
SFR_8BIT(CAPD);                               /* Comparator A Port Disable */
477 
 
478 
#define CAIFG                  (0x01)         /* Comp. A Interrupt Flag */
479 
#define CAIE                   (0x02)         /* Comp. A Interrupt Enable */
480 
#define CAIES                  (0x04)         /* Comp. A Int. Edge Select: 0:rising / 1:falling */
481 
#define CAON                   (0x08)         /* Comp. A enable */
482 
#define CAREF0                 (0x10)         /* Comp. A Internal Reference Select 0 */
483 
#define CAREF1                 (0x20)         /* Comp. A Internal Reference Select 1 */
484 
#define CARSEL                 (0x40)         /* Comp. A Internal Reference Enable */
485 
#define CAEX                   (0x80)         /* Comp. A Exchange Inputs */
486 
 
487 
#define CAREF_0                (0x00)         /* Comp. A Int. Ref. Select 0 : Off */
488 
#define CAREF_1                (0x10)         /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
489 
#define CAREF_2                (0x20)         /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
490 
#define CAREF_3                (0x30)         /* Comp. A Int. Ref. Select 3 : Vt*/
491 
 
492 
#define CAOUT                  (0x01)         /* Comp. A Output */
493 
#define CAF                    (0x02)         /* Comp. A Enable Output Filter */
494 
#define P2CA0                  (0x04)         /* Comp. A +Terminal Multiplexer */
495 
#define P2CA1                  (0x08)         /* Comp. A -Terminal Multiplexer */
496 
#define P2CA2                  (0x10)         /* Comp. A -Terminal Multiplexer */
497 
#define P2CA3                  (0x20)         /* Comp. A -Terminal Multiplexer */
498 
#define P2CA4                  (0x40)         /* Comp. A +Terminal Multiplexer */
499 
#define CASHORT                (0x80)         /* Comp. A Short + and - Terminals */
500 
 
501 
#define CAPD0                  (0x01)         /* Comp. A Disable Input Buffer of Port Register .0 */
502 
#define CAPD1                  (0x02)         /* Comp. A Disable Input Buffer of Port Register .1 */
503 
#define CAPD2                  (0x04)         /* Comp. A Disable Input Buffer of Port Register .2 */
504 
#define CAPD3                  (0x08)         /* Comp. A Disable Input Buffer of Port Register .3 */
505 
#define CAPD4                  (0x10)         /* Comp. A Disable Input Buffer of Port Register .4 */
506 
#define CAPD5                  (0x20)         /* Comp. A Disable Input Buffer of Port Register .5 */
507 
#define CAPD6                  (0x40)         /* Comp. A Disable Input Buffer of Port Register .6 */
508 
#define CAPD7                  (0x80)         /* Comp. A Disable Input Buffer of Port Register .7 */
509 
 
510 
/************************************************************
511 
* DAC12
512 
************************************************************/
513 
#define __MSP430_HAS_DAC12_2__                /* Definition to show that Module is available */
514 
 
515 
SFR_16BIT(DAC12_0CTL);                        /* DAC12_0 Control */
516 
SFR_16BIT(DAC12_1CTL);                        /* DAC12_1 Control */
517 
 
518 
#define DAC12GRP               (0x0001)       /* DAC12 group */
519 
#define DAC12ENC               (0x0002)       /* DAC12 enable conversion */
520 
#define DAC12IFG               (0x0004)       /* DAC12 interrupt flag */
521 
#define DAC12IE                (0x0008)       /* DAC12 interrupt enable */
522 
#define DAC12DF                (0x0010)       /* DAC12 data format */
523 
#define DAC12AMP0              (0x0020)       /* DAC12 amplifier bit 0 */
524 
#define DAC12AMP1              (0x0040)       /* DAC12 amplifier bit 1 */
525 
#define DAC12AMP2              (0x0080)       /* DAC12 amplifier bit 2 */
526 
#define DAC12IR                (0x0100)       /* DAC12 input reference and output range */
527 
#define DAC12CALON             (0x0200)       /* DAC12 calibration */
528 
#define DAC12LSEL0             (0x0400)       /* DAC12 load select bit 0 */
529 
#define DAC12LSEL1             (0x0800)       /* DAC12 load select bit 1 */
530 
#define DAC12RES               (0x1000)       /* DAC12 resolution */
531 
#define DAC12SREF0             (0x2000)       /* DAC12 reference bit 0 */
532 
#define DAC12SREF1             (0x4000)       /* DAC12 reference bit 1 */
533 
#define DAC12OPS               (0x8000)       /* DAC12 Operation Amp. */
534 
 
535 
#define DAC12AMP_0             (0*0x0020u)    /* DAC12 amplifier 0: off,    3-state */
536 
#define DAC12AMP_1             (1*0x0020u)    /* DAC12 amplifier 1: off,    off */
537 
#define DAC12AMP_2             (2*0x0020u)    /* DAC12 amplifier 2: low,    low */
538 
#define DAC12AMP_3             (3*0x0020u)    /* DAC12 amplifier 3: low,    medium */
539 
#define DAC12AMP_4             (4*0x0020u)    /* DAC12 amplifier 4: low,    high */
540 
#define DAC12AMP_5             (5*0x0020u)    /* DAC12 amplifier 5: medium, medium */
541 
#define DAC12AMP_6             (6*0x0020u)    /* DAC12 amplifier 6: medium, high */
542 
#define DAC12AMP_7             (7*0x0020u)    /* DAC12 amplifier 7: high,   high */
543 
 
544 
#define DAC12LSEL_0            (0*0x0400u)    /* DAC12 load select 0: direct */
545 
#define DAC12LSEL_1            (1*0x0400u)    /* DAC12 load select 1: latched with DAT */
546 
#define DAC12LSEL_2            (2*0x0400u)    /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */
547 
#define DAC12LSEL_3            (3*0x0400u)    /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */
548 
 
549 
#define DAC12SREF_0            (0*0x2000u)    /* DAC12 reference 0: Vref+ */
550 
#define DAC12SREF_1            (1*0x2000u)    /* DAC12 reference 1: Vref+ */
551 
#define DAC12SREF_2            (2*0x2000u)    /* DAC12 reference 2: Veref+ */
552 
#define DAC12SREF_3            (3*0x2000u)    /* DAC12 reference 3: Veref+ */
553 
 
554 
SFR_16BIT(DAC12_0DAT);                        /* DAC12_0 Data */
555 
SFR_16BIT(DAC12_1DAT);                        /* DAC12_1 Data */
556 
/************************************************************
557 
* DMA_X
558 
************************************************************/
559 
#define __MSP430_HAS_DMAX_3__                 /* Definition to show that Module is available */
560 
 
561 
SFR_16BIT(DMACTL0);                           /* DMA Module Control 0 */
562 
#define DMA0TSEL0              (0x0001)       /* DMA channel 0 transfer select bit 0 */
563 
#define DMA0TSEL1              (0x0002)       /* DMA channel 0 transfer select bit 1 */
564 
#define DMA0TSEL2              (0x0004)       /* DMA channel 0 transfer select bit 2 */
565 
#define DMA0TSEL3              (0x0008)       /* DMA channel 0 transfer select bit 3 */
566 
#define DMA1TSEL0              (0x0010)       /* DMA channel 1 transfer select bit 0 */
567 
#define DMA1TSEL1              (0x0020)       /* DMA channel 1 transfer select bit 1 */
568 
#define DMA1TSEL2              (0x0040)       /* DMA channel 1 transfer select bit 2 */
569 
#define DMA1TSEL3              (0x0080)       /* DMA channel 1 transfer select bit 3 */
570 
#define DMA2TSEL0              (0x0100)       /* DMA channel 2 transfer select bit 0 */
571 
#define DMA2TSEL1              (0x0200)       /* DMA channel 2 transfer select bit 1 */
572 
#define DMA2TSEL2              (0x0400)       /* DMA channel 2 transfer select bit 2 */
573 
#define DMA2TSEL3              (0x0800)       /* DMA channel 2 transfer select bit 3 */
574 
 
575 
#define DMA0TSEL_0             (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw)*/
576 
#define DMA0TSEL_1             (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer_A (TACCR2.IFG) */
577 
#define DMA0TSEL_2             (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer_B (TBCCR2.IFG) */
578 
#define DMA0TSEL_3             (3*0x0001u)    /* DMA channel 0 transfer select 3:  USCIA0 receive */
579 
#define DMA0TSEL_4             (4*0x0001u)    /* DMA channel 0 transfer select 4:  USCIA0 transmit */
580 
#define DMA0TSEL_5             (5*0x0001u)    /* DMA channel 0 transfer select 5:  DAC12_0CTL.DAC12IFG */
581 
#define DMA0TSEL_6             (6*0x0001u)    /* DMA channel 0 transfer select 6:  ADC12 (ADC12IFG) */
582 
#define DMA0TSEL_7             (7*0x0001u)    /* DMA channel 0 transfer select 7:  Timer_A (TACCR0.IFG) */
583 
#define DMA0TSEL_8             (8*0x0001u)    /* DMA channel 0 transfer select 8:  Timer_B (TBCCR0.IFG) */
584 
#define DMA0TSEL_9             (9*0x0001u)    /* DMA channel 0 transfer select 9:  USCIA1 receive */
585 
#define DMA0TSEL_10            (10*0x0001u)   /* DMA channel 0 transfer select 10: USCIA1 transmit */
586 
#define DMA0TSEL_11            (11*0x0001u)   /* DMA channel 0 transfer select 11: Multiplier ready */
587 
#define DMA0TSEL_12            (12*0x0001u)   /* DMA channel 0 transfer select 12: USCIB0 receive */
588 
#define DMA0TSEL_13            (13*0x0001u)   /* DMA channel 0 transfer select 13: USCIB0 transmit */
589 
#define DMA0TSEL_14            (14*0x0001u)   /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */
590 
#define DMA0TSEL_15            (15*0x0001u)   /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */
591 
 
592 
#define DMA1TSEL_0             (0*0x0010u)    /* DMA channel 1 transfer select 0:  DMA_REQ */
593 
#define DMA1TSEL_1             (1*0x0010u)    /* DMA channel 1 transfer select 1:  Timer_A CCRIFG.2 */
594 
#define DMA1TSEL_2             (2*0x0010u)    /* DMA channel 1 transfer select 2:  Timer_B CCRIFG.2 */
595 
#define DMA1TSEL_3             (3*0x0010u)    /* DMA channel 1 transfer select 3:  USCIA0 receive */
596 
#define DMA1TSEL_4             (4*0x0010u)    /* DMA channel 1 transfer select 4:  USCIA0 transmit */
597 
#define DMA1TSEL_5             (5*0x0010u)    /* DMA channel 1 transfer select 5:  DAC12.0IFG */
598 
#define DMA1TSEL_6             (6*0x0010u)    /* DMA channel 1 transfer select 6:  ADC12 (ADC12IFG) */
599 
#define DMA1TSEL_7             (7*0x0010u)    /* DMA channel 1 transfer select 7:  Timer_A (TACCR0.IFG) */
600 
#define DMA1TSEL_8             (8*0x0010u)    /* DMA channel 1 transfer select 8:  Timer_B (TBCCR0.IFG) */
601 
#define DMA1TSEL_9             (9*0x0010u)    /* DMA channel 1 transfer select 9:  USCIA1 receive */
602 
#define DMA1TSEL_10            (10*0x0010u)   /* DMA channel 1 transfer select 10: USCIA1 transmit */
603 
#define DMA1TSEL_11            (11*0x0010u)   /* DMA channel 1 transfer select 11: Multiplier ready */
604 
#define DMA1TSEL_12            (12*0x0010u)   /* DMA channel 1 transfer select 12: USCIB0 receive */
605 
#define DMA1TSEL_13            (13*0x0010u)   /* DMA channel 1 transfer select 13: USCIB0 transmit */
606 
#define DMA1TSEL_14            (14*0x0010u)   /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */
607 
#define DMA1TSEL_15            (15*0x0010u)   /* DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */
608 
 
609 
#define DMA2TSEL_0             (0*0x0100u)    /* DMA channel 2 transfer select 0:  DMA_REQ */
610 
#define DMA2TSEL_1             (1*0x0100u)    /* DMA channel 2 transfer select 1:  Timer_A CCRIFG.2 */
611 
#define DMA2TSEL_2             (2*0x0100u)    /* DMA channel 2 transfer select 2:  Timer_B CCRIFG.2 */
612 
#define DMA2TSEL_3             (3*0x0100u)    /* DMA channel 2 transfer select 3:  USCIA0 receive */
613 
#define DMA2TSEL_4             (4*0x0100u)    /* DMA channel 2 transfer select 4:  USCIA0 transmit */
614 
#define DMA2TSEL_5             (5*0x0100u)    /* DMA channel 2 transfer select 5:  DAC12.0IFG */
615 
#define DMA2TSEL_6             (6*0x0100u)    /* DMA channel 2 transfer select 6:  ADC12 (ADC12IFG) */
616 
#define DMA2TSEL_7             (7*0x0100u)    /* DMA channel 2 transfer select 7:  Timer_A (TACCR0.IFG) */
617 
#define DMA2TSEL_8             (8*0x0100u)    /* DMA channel 2 transfer select 8:  Timer_B (TBCCR0.IFG) */
618 
#define DMA2TSEL_9             (9*0x0100u)    /* DMA channel 2 transfer select 9:  USCIA1 receive */
619 
#define DMA2TSEL_10            (10*0x0100u)   /* DMA channel 2 transfer select 10: USCIA1 transmit */
620 
#define DMA2TSEL_11            (11*0x0100u)   /* DMA channel 2 transfer select 11: Multiplier ready */
621 
#define DMA2TSEL_12            (12*0x0100u)   /* DMA channel 2 transfer select 12: USCIB0 receive */
622 
#define DMA2TSEL_13            (13*0x0100u)   /* DMA channel 2 transfer select 13: USCIB0 transmit */
623 
#define DMA2TSEL_14            (14*0x0100u)   /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */
624 
#define DMA2TSEL_15            (15*0x0100u)   /* DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */
625 
 
626 
SFR_16BIT(DMACTL1);                           /* DMA Module Control 1 */
627 
#define ENNMI                  (0x0001)       /* Enable NMI interruption of DMA */
628 
#define ROUNDROBIN             (0x0002)       /* Round-Robin DMA channel priorities */
629 
#define DMAONFETCH             (0x0004)       /* DMA transfer on instruction fetch */
630 
 
631 
SFR_16BIT(DMAIV);                             /* DMA Interrupt Vector Word */
632 
SFR_16BIT(DMA0CTL);                           /* DMA Channel 0 Control */
633 
SFR_16BIT(DMA1CTL);                           /* DMA Channel 1 Control */
634 
SFR_16BIT(DMA2CTL);                           /* DMA Channel 2 Control */
635 
 
636 
#define DMAREQ                 (0x0001)       /* Initiate DMA transfer with DMATSEL */
637 
#define DMAABORT               (0x0002)       /* DMA transfer aborted by NMI */
638 
#define DMAIE                  (0x0004)       /* DMA interrupt enable */
639 
#define DMAIFG                 (0x0008)       /* DMA interrupt flag */
640 
#define DMAEN                  (0x0010)       /* DMA enable */
641 
#define DMALEVEL               (0x0020)       /* DMA level sensitive trigger select */
642 
#define DMASRCBYTE             (0x0040)       /* DMA source byte */
643 
#define DMADSTBYTE             (0x0080)       /* DMA destination byte */
644 
#define DMASRCINCR0            (0x0100)       /* DMA source increment bit 0 */
645 
#define DMASRCINCR1            (0x0200)       /* DMA source increment bit 1 */
646 
#define DMADSTINCR0            (0x0400)       /* DMA destination increment bit 0 */
647 
#define DMADSTINCR1            (0x0800)       /* DMA destination increment bit 1 */
648 
#define DMADT0                 (0x1000)       /* DMA transfer mode bit 0 */
649 
#define DMADT1                 (0x2000)       /* DMA transfer mode bit 1 */
650 
#define DMADT2                 (0x4000)       /* DMA transfer mode bit 2 */
651 
 
652 
#define DMASWDW                (0*0x0040u)    /* DMA transfer: source word to destination word */
653 
#define DMASBDW                (1*0x0040u)    /* DMA transfer: source byte to destination word */
654 
#define DMASWDB                (2*0x0040u)    /* DMA transfer: source word to destination byte */
655 
#define DMASBDB                (3*0x0040u)    /* DMA transfer: source byte to destination byte */
656 
 
657 
#define DMASRCINCR_0           (0*0x0100u)    /* DMA source increment 0: source address unchanged */
658 
#define DMASRCINCR_1           (1*0x0100u)    /* DMA source increment 1: source address unchanged */
659 
#define DMASRCINCR_2           (2*0x0100u)    /* DMA source increment 2: source address decremented */
660 
#define DMASRCINCR_3           (3*0x0100u)    /* DMA source increment 3: source address incremented */
661 
 
662 
#define DMADSTINCR_0           (0*0x0400u)    /* DMA destination increment 0: destination address unchanged */
663 
#define DMADSTINCR_1           (1*0x0400u)    /* DMA destination increment 1: destination address unchanged */
664 
#define DMADSTINCR_2           (2*0x0400u)    /* DMA destination increment 2: destination address decremented */
665 
#define DMADSTINCR_3           (3*0x0400u)    /* DMA destination increment 3: destination address incremented */
666 
 
667 
#define DMADT_0                (0*0x1000u)    /* DMA transfer mode 0: single */
668 
#define DMADT_1                (1*0x1000u)    /* DMA transfer mode 1: block */
669 
#define DMADT_2                (2*0x1000u)    /* DMA transfer mode 2: interleaved */
670 
#define DMADT_3                (3*0x1000u)    /* DMA transfer mode 3: interleaved */
671 
#define DMADT_4                (4*0x1000u)    /* DMA transfer mode 4: single, repeat */
672 
#define DMADT_5                (5*0x1000u)    /* DMA transfer mode 5: block, repeat */
673 
#define DMADT_6                (6*0x1000u)    /* DMA transfer mode 6: interleaved, repeat */
674 
#define DMADT_7                (7*0x1000u)    /* DMA transfer mode 7: interleaved, repeat */
675 
 
676 
SFR_20BIT(DMA0SA);                            /* DMA Channel 0 Source Address */
677 
SFR_16BIT(DMA0SAL);                           /* DMA Channel 0 Source Address */
678 
SFR_20BIT(DMA0DA);                            /* DMA Channel 0 Destination Address */
679 
SFR_16BIT(DMA0DAL);                           /* DMA Channel 0 Destination Address */
680 
SFR_16BIT(DMA0SZ);                            /* DMA Channel 0 Transfer Size */
681 
SFR_20BIT(DMA1SA);                            /* DMA Channel 1 Source Address */
682 
SFR_16BIT(DMA1SAL);                           /* DMA Channel 1 Source Address */
683 
SFR_20BIT(DMA1DA);                            /* DMA Channel 1 Destination Address */
684 
SFR_16BIT(DMA1DAL);                           /* DMA Channel 1 Destination Address */
685 
SFR_16BIT(DMA1SZ);                            /* DMA Channel 1 Transfer Size */
686 
SFR_20BIT(DMA2SA);                            /* DMA Channel 2 Source Address */
687 
SFR_16BIT(DMA2SAL);                           /* DMA Channel 2 Source Address */
688 
SFR_20BIT(DMA2DA);                            /* DMA Channel 2 Destination Address */
689 
SFR_16BIT(DMA2DAL);                           /* DMA Channel 2 Destination Address */
690 
SFR_16BIT(DMA2SZ);                            /* DMA Channel 2 Transfer Size */
691 
 
692 
/* DMAIV Definitions */
693 
#define DMAIV_NONE             (0x0000)       /* No Interrupt pending */
694 
#define DMAIV_DMA0IFG          (0x0002)       /* DMA0IFG */
695 
#define DMAIV_DMA1IFG          (0x0004)       /* DMA1IFG */
696 
#define DMAIV_DMA2IFG          (0x0006)       /* DMA2IFG */
697 
 
698 
/*************************************************************
699 
* Flash Memory
700 
*************************************************************/
701 
#define __MSP430_HAS_FLASH2__                 /* Definition to show that Module is available */
702 
 
703 
SFR_16BIT(FCTL1);                             /* FLASH Control 1 */
704 
SFR_16BIT(FCTL2);                             /* FLASH Control 2 */
705 
SFR_16BIT(FCTL3);                             /* FLASH Control 3 */
706 
SFR_16BIT(FCTL4);                             /* FLASH Control 4 */
707 
 
708 
#define FRKEY                  (0x9600)       /* Flash key returned by read */
709 
#define FWKEY                  (0xA500)       /* Flash key for write */
710 
#define FXKEY                  (0x3300)       /* for use with XOR instruction */
711 
 
712 
#define ERASE                  (0x0002)       /* Enable bit for Flash segment erase */
713 
#define MERAS                  (0x0004)       /* Enable bit for Flash mass erase */
714 
#define EEI                    (0x0008)       /* Enable Erase Interrupts */
715 
#define EEIEX                  (0x0010)       /* Enable Emergency Interrupt Exit */
716 
#define WRT                    (0x0040)       /* Enable bit for Flash write */
717 
#define BLKWRT                 (0x0080)       /* Enable bit for Flash segment write */
718 
#define SEGWRT                 (0x0080)       /* old definition */ /* Enable bit for Flash segment write */
719 
 
720 
#define FN0                    (0x0001)       /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
721 
#define FN1                    (0x0002)       /*  32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
722 
#ifndef FN2
723 
#define FN2                    (0x0004)
724 
#endif
725 
#ifndef FN3
726 
#define FN3                    (0x0008)
727 
#endif
728 
#ifndef FN4
729 
#define FN4                    (0x0010)
730 
#endif
731 
#define FN5                    (0x0020)
732 
#define FSSEL0                 (0x0040)       /* Flash clock select 0 */        /* to distinguish from USART SSELx */
733 
#define FSSEL1                 (0x0080)       /* Flash clock select 1 */
734 
 
735 
#define FSSEL_0                (0x0000)       /* Flash clock select: 0 - ACLK */
736 
#define FSSEL_1                (0x0040)       /* Flash clock select: 1 - MCLK */
737 
#define FSSEL_2                (0x0080)       /* Flash clock select: 2 - SMCLK */
738 
#define FSSEL_3                (0x00C0)       /* Flash clock select: 3 - SMCLK */
739 
 
740 
#define BUSY                   (0x0001)       /* Flash busy: 1 */
741 
#define KEYV                   (0x0002)       /* Flash Key violation flag */
742 
#define ACCVIFG                (0x0004)       /* Flash Access violation flag */
743 
#define WAIT                   (0x0008)       /* Wait flag for segment write */
744 
#define LOCK                   (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
745 
#define EMEX                   (0x0020)       /* Flash Emergency Exit */
746 
#define LOCKA                  (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
747 
#define FAIL                   (0x0080)       /* Last Program or Erase failed */
748 
 
749 
#define MGR0                   (0x0010)       /* Marginal read 0 mode. */
750 
#define MGR1                   (0x0020)       /* Marginal read 1 mode. */
751 
 
752 
/************************************************************
753 
* HARDWARE MULTIPLIER
754 
************************************************************/
755 
#define __MSP430_HAS_MPY__                    /* Definition to show that Module is available */
756 
 
757 
SFR_16BIT(MPY);                               /* Multiply Unsigned/Operand 1 */
758 
SFR_16BIT(MPYS);                              /* Multiply Signed/Operand 1 */
759 
SFR_16BIT(MAC);                               /* Multiply Unsigned and Accumulate/Operand 1 */
760 
SFR_16BIT(MACS);                              /* Multiply Signed and Accumulate/Operand 1 */
761 
SFR_16BIT(OP2);                               /* Operand 2 */
762 
SFR_16BIT(RESLO);                             /* Result Low Word */
763 
SFR_16BIT(RESHI);                             /* Result High Word */
764 
SFR_16BIT(SUMEXT);                            /* Sum Extend */
765 
 
766 
/************************************************************
767 
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
768 
************************************************************/
769 
#define __MSP430_HAS_PORT1_R__                /* Definition to show that Module is available */
770 
#define __MSP430_HAS_PORT2_R__                /* Definition to show that Module is available */
771 
 
772 
SFR_8BIT(P1IN);                               /* Port 1 Input */
773 
SFR_8BIT(P1OUT);                              /* Port 1 Output */
774 
SFR_8BIT(P1DIR);                              /* Port 1 Direction */
775 
SFR_8BIT(P1IFG);                              /* Port 1 Interrupt Flag */
776 
SFR_8BIT(P1IES);                              /* Port 1 Interrupt Edge Select */
777 
SFR_8BIT(P1IE);                               /* Port 1 Interrupt Enable */
778 
SFR_8BIT(P1SEL);                              /* Port 1 Selection */
779 
SFR_8BIT(P1REN);                              /* Port 1 Resistor Enable */
780 
 
781 
SFR_8BIT(P2IN);                               /* Port 2 Input */
782 
SFR_8BIT(P2OUT);                              /* Port 2 Output */
783 
SFR_8BIT(P2DIR);                              /* Port 2 Direction */
784 
SFR_8BIT(P2IFG);                              /* Port 2 Interrupt Flag */
785 
SFR_8BIT(P2IES);                              /* Port 2 Interrupt Edge Select */
786 
SFR_8BIT(P2IE);                               /* Port 2 Interrupt Enable */
787 
SFR_8BIT(P2SEL);                              /* Port 2 Selection */
788 
SFR_8BIT(P2REN);                              /* Port 2 Resistor Enable */
789 
 
790 
/************************************************************
791 
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
792 
************************************************************/
793 
#define __MSP430_HAS_PORT3_R__                /* Definition to show that Module is available */
794 
#define __MSP430_HAS_PORT4_R__                /* Definition to show that Module is available */
795 
 
796 
SFR_8BIT(P3IN);                               /* Port 3 Input */
797 
SFR_8BIT(P3OUT);                              /* Port 3 Output */
798 
SFR_8BIT(P3DIR);                              /* Port 3 Direction */
799 
SFR_8BIT(P3SEL);                              /* Port 3 Selection */
800 
SFR_8BIT(P3REN);                              /* Port 3 Resistor Enable */
801 
 
802 
SFR_8BIT(P4IN);                               /* Port 4 Input */
803 
SFR_8BIT(P4OUT);                              /* Port 4 Output */
804 
SFR_8BIT(P4DIR);                              /* Port 4 Direction */
805 
SFR_8BIT(P4SEL);                              /* Port 4 Selection */
806 
SFR_8BIT(P4REN);                              /* Port 4 Resistor Enable */
807 
 
808 
/************************************************************
809 
* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
810 
************************************************************/
811 
#define __MSP430_HAS_PORT5_R__                /* Definition to show that Module is available */
812 
#define __MSP430_HAS_PORT6_R__                /* Definition to show that Module is available */
813 
 
814 
SFR_8BIT(P5IN);                               /* Port 5 Input */
815 
SFR_8BIT(P5OUT);                              /* Port 5 Output */
816 
SFR_8BIT(P5DIR);                              /* Port 5 Direction */
817 
SFR_8BIT(P5SEL);                              /* Port 5 Selection */
818 
SFR_8BIT(P5REN);                              /* Port 5 Resistor Enable */
819 
 
820 
SFR_8BIT(P6IN);                               /* Port 6 Input */
821 
SFR_8BIT(P6OUT);                              /* Port 6 Output */
822 
SFR_8BIT(P6DIR);                              /* Port 6 Direction */
823 
SFR_8BIT(P6SEL);                              /* Port 6 Selection */
824 
SFR_8BIT(P6REN);                              /* Port 6 Resistor Enable */
825 
 
826 
/************************************************************
827 
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
828 
************************************************************/
829 
#define __MSP430_HAS_PORT7_R__                /* Definition to show that Module is available */
830 
#define __MSP430_HAS_PORT8_R__                /* Definition to show that Module is available */
831 
#define __MSP430_HAS_PORTA_R__                /* Definition to show that Module is available */
832 
 
833 
SFR_8BIT(P7IN);                               /* Port 7 Input */
834 
SFR_8BIT(P7OUT);                              /* Port 7 Output */
835 
SFR_8BIT(P7DIR);                              /* Port 7 Direction */
836 
SFR_8BIT(P7SEL);                              /* Port 7 Selection */
837 
SFR_8BIT(P7REN);                              /* Port 7 Resistor Enable */
838 
 
839 
SFR_8BIT(P8IN);                               /* Port 8 Input */
840 
SFR_8BIT(P8OUT);                              /* Port 8 Output */
841 
SFR_8BIT(P8DIR);                              /* Port 8 Direction */
842 
SFR_8BIT(P8SEL);                              /* Port 8 Selection */
843 
SFR_8BIT(P8REN);                              /* Port 8 Resistor Enable */
844 
 
845 
SFR_16BIT(PAIN);                              /* Port A Input */
846 
SFR_16BIT(PAOUT);                             /* Port A Output */
847 
SFR_16BIT(PADIR);                             /* Port A Direction */
848 
SFR_16BIT(PASEL);                             /* Port A Selection */
849 
SFR_16BIT(PAREN);                             /* Port A Resistor Enable */
850 
 
851 
/************************************************************
852 
* Brown-Out, Supply Voltage Supervision (SVS)
853 
************************************************************/
854 
#define __MSP430_HAS_SVS__                    /* Definition to show that Module is available */
855 
 
856 
SFR_8BIT(SVSCTL);                             /* SVS Control */
857 
#define SVSFG                  (0x01)         /* SVS Flag */
858 
#define SVSOP                  (0x02)         /* SVS output (read only) */
859 
#define SVSON                  (0x04)         /* Switches the SVS on/off */
860 
#define PORON                  (0x08)         /* Enable POR Generation if Low Voltage */
861 
#define VLD0                   (0x10)
862 
#define VLD1                   (0x20)
863 
#define VLD2                   (0x40)
864 
#define VLD3                   (0x80)
865 
 
866 
#define VLDON                  (0x10)
867 
#define VLDOFF                 (0x00)
868 
#define VLD_1_8V               (0x10)
869 
 
870 
/************************************************************
871 
* Timer A3
872 
************************************************************/
873 
#define __MSP430_HAS_TA3__                    /* Definition to show that Module is available */
874 
 
875 
SFR_16BIT(TAIV);                              /* Timer A Interrupt Vector Word */
876 
SFR_16BIT(TACTL);                             /* Timer A Control */
877 
SFR_16BIT(TACCTL0);                           /* Timer A Capture/Compare Control 0 */
878 
SFR_16BIT(TACCTL1);                           /* Timer A Capture/Compare Control 1 */
879 
SFR_16BIT(TACCTL2);                           /* Timer A Capture/Compare Control 2 */
880 
SFR_16BIT(TAR);                               /* Timer A Counter Register */
881 
SFR_16BIT(TACCR0);                            /* Timer A Capture/Compare 0 */
882 
SFR_16BIT(TACCR1);                            /* Timer A Capture/Compare 1 */
883 
SFR_16BIT(TACCR2);                            /* Timer A Capture/Compare 2 */
884 
 
885 
/* Alternate register names */
886 
#define CCTL0                  TACCTL0        /* Timer A Capture/Compare Control 0 */
887 
#define CCTL1                  TACCTL1        /* Timer A Capture/Compare Control 1 */
888 
#define CCTL2                  TACCTL2        /* Timer A Capture/Compare Control 2 */
889 
#define CCR0                   TACCR0         /* Timer A Capture/Compare 0 */
890 
#define CCR1                   TACCR1         /* Timer A Capture/Compare 1 */
891 
#define CCR2                   TACCR2         /* Timer A Capture/Compare 2 */
892 
#define CCTL0_                 TACCTL0_       /* Timer A Capture/Compare Control 0 */
893 
#define CCTL1_                 TACCTL1_       /* Timer A Capture/Compare Control 1 */
894 
#define CCTL2_                 TACCTL2_       /* Timer A Capture/Compare Control 2 */
895 
#define CCR0_                  TACCR0_        /* Timer A Capture/Compare 0 */
896 
#define CCR1_                  TACCR1_        /* Timer A Capture/Compare 1 */
897 
#define CCR2_                  TACCR2_        /* Timer A Capture/Compare 2 */
898 
/* Alternate register names - 5xx style */
899 
#define TA0IV                  TAIV           /* Timer A Interrupt Vector Word */
900 
#define TA0CTL                 TACTL          /* Timer A Control */
901 
#define TA0CCTL0               TACCTL0        /* Timer A Capture/Compare Control 0 */
902 
#define TA0CCTL1               TACCTL1        /* Timer A Capture/Compare Control 1 */
903 
#define TA0CCTL2               TACCTL2        /* Timer A Capture/Compare Control 2 */
904 
#define TA0R                   TAR            /* Timer A Counter Register */
905 
#define TA0CCR0                TACCR0         /* Timer A Capture/Compare 0 */
906 
#define TA0CCR1                TACCR1         /* Timer A Capture/Compare 1 */
907 
#define TA0CCR2                TACCR2         /* Timer A Capture/Compare 2 */
908 
#define TA0IV_                 TAIV_          /* Timer A Interrupt Vector Word */
909 
#define TA0CTL_                TACTL_         /* Timer A Control */
910 
#define TA0CCTL0_              TACCTL0_       /* Timer A Capture/Compare Control 0 */
911 
#define TA0CCTL1_              TACCTL1_       /* Timer A Capture/Compare Control 1 */
912 
#define TA0CCTL2_              TACCTL2_       /* Timer A Capture/Compare Control 2 */
913 
#define TA0R_                  TAR_           /* Timer A Counter Register */
914 
#define TA0CCR0_               TACCR0_        /* Timer A Capture/Compare 0 */
915 
#define TA0CCR1_               TACCR1_        /* Timer A Capture/Compare 1 */
916 
#define TA0CCR2_               TACCR2_        /* Timer A Capture/Compare 2 */
917 
 
918 
#define TASSEL1                (0x0200)       /* Timer A clock source select 0 */
919 
#define TASSEL0                (0x0100)       /* Timer A clock source select 1 */
920 
#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
921 
#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
922 
#define MC1                    (0x0020)       /* Timer A mode control 1 */
923 
#define MC0                    (0x0010)       /* Timer A mode control 0 */
924 
#define TACLR                  (0x0004)       /* Timer A counter clear */
925 
#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
926 
#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
927 
 
928 
#define MC_0                   (0*0x10u)      /* Timer A mode control: 0 - Stop */
929 
#define MC_1                   (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
930 
#define MC_2                   (2*0x10u)      /* Timer A mode control: 2 - Continous up */
931 
#define MC_3                   (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
932 
#define ID_0                   (0*0x40u)      /* Timer A input divider: 0 - /1 */
933 
#define ID_1                   (1*0x40u)      /* Timer A input divider: 1 - /2 */
934 
#define ID_2                   (2*0x40u)      /* Timer A input divider: 2 - /4 */
935 
#define ID_3                   (3*0x40u)      /* Timer A input divider: 3 - /8 */
936 
#define TASSEL_0               (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
937 
#define TASSEL_1               (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
938 
#define TASSEL_2               (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
939 
#define TASSEL_3               (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
940 
 
941 
#define CM1                    (0x8000)       /* Capture mode 1 */
942 
#define CM0                    (0x4000)       /* Capture mode 0 */
943 
#define CCIS1                  (0x2000)       /* Capture input select 1 */
944 
#define CCIS0                  (0x1000)       /* Capture input select 0 */
945 
#define SCS                    (0x0800)       /* Capture sychronize */
946 
#define SCCI                   (0x0400)       /* Latched capture signal (read) */
947 
#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
948 
#define OUTMOD2                (0x0080)       /* Output mode 2 */
949 
#define OUTMOD1                (0x0040)       /* Output mode 1 */
950 
#define OUTMOD0                (0x0020)       /* Output mode 0 */
951 
#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
952 
#define CCI                    (0x0008)       /* Capture input signal (read) */
953 
#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
954 
#define COV                    (0x0002)       /* Capture/compare overflow flag */
955 
#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
956 
 
957 
#define OUTMOD_0               (0*0x20u)      /* PWM output mode: 0 - output only */
958 
#define OUTMOD_1               (1*0x20u)      /* PWM output mode: 1 - set */
959 
#define OUTMOD_2               (2*0x20u)      /* PWM output mode: 2 - PWM toggle/reset */
960 
#define OUTMOD_3               (3*0x20u)      /* PWM output mode: 3 - PWM set/reset */
961 
#define OUTMOD_4               (4*0x20u)      /* PWM output mode: 4 - toggle */
962 
#define OUTMOD_5               (5*0x20u)      /* PWM output mode: 5 - Reset */
963 
#define OUTMOD_6               (6*0x20u)      /* PWM output mode: 6 - PWM toggle/set */
964 
#define OUTMOD_7               (7*0x20u)      /* PWM output mode: 7 - PWM reset/set */
965 
#define CCIS_0                 (0*0x1000u)    /* Capture input select: 0 - CCIxA */
966 
#define CCIS_1                 (1*0x1000u)    /* Capture input select: 1 - CCIxB */
967 
#define CCIS_2                 (2*0x1000u)    /* Capture input select: 2 - GND */
968 
#define CCIS_3                 (3*0x1000u)    /* Capture input select: 3 - Vcc */
969 
#define CM_0                   (0*0x4000u)    /* Capture mode: 0 - disabled */
970 
#define CM_1                   (1*0x4000u)    /* Capture mode: 1 - pos. edge */
971 
#define CM_2                   (2*0x4000u)    /* Capture mode: 1 - neg. edge */
972 
#define CM_3                   (3*0x4000u)    /* Capture mode: 1 - both edges */
973 
 
974 
/* TA3IV Definitions */
975 
#define TAIV_NONE              (0x0000)       /* No Interrupt pending */
976 
#define TAIV_TACCR1            (0x0002)       /* TACCR1_CCIFG */
977 
#define TAIV_TACCR2            (0x0004)       /* TACCR2_CCIFG */
978 
#define TAIV_6                 (0x0006)       /* Reserved */
979 
#define TAIV_8                 (0x0008)       /* Reserved */
980 
#define TAIV_TAIFG             (0x000A)       /* TAIFG */
981 
 
982 
/************************************************************
983 
* Timer B7
984 
************************************************************/
985 
#define __MSP430_HAS_TB7__                    /* Definition to show that Module is available */
986 
 
987 
SFR_16BIT(TBIV);                              /* Timer B Interrupt Vector Word */
988 
SFR_16BIT(TBCTL);                             /* Timer B Control */
989 
SFR_16BIT(TBCCTL0);                           /* Timer B Capture/Compare Control 0 */
990 
SFR_16BIT(TBCCTL1);                           /* Timer B Capture/Compare Control 1 */
991 
SFR_16BIT(TBCCTL2);                           /* Timer B Capture/Compare Control 2 */
992 
SFR_16BIT(TBCCTL3);                           /* Timer B Capture/Compare Control 3 */
993 
SFR_16BIT(TBCCTL4);                           /* Timer B Capture/Compare Control 4 */
994 
SFR_16BIT(TBCCTL5);                           /* Timer B Capture/Compare Control 5 */
995 
SFR_16BIT(TBCCTL6);                           /* Timer B Capture/Compare Control 6 */
996 
SFR_16BIT(TBR);                               /* Timer B Counter Register */
997 
SFR_16BIT(TBCCR0);                            /* Timer B Capture/Compare 0 */
998 
SFR_16BIT(TBCCR1);                            /* Timer B Capture/Compare 1 */
999 
SFR_16BIT(TBCCR2);                            /* Timer B Capture/Compare 2 */
1000 
SFR_16BIT(TBCCR3);                            /* Timer B Capture/Compare 3 */
1001 
SFR_16BIT(TBCCR4);                            /* Timer B Capture/Compare 4 */
1002 
SFR_16BIT(TBCCR5);                            /* Timer B Capture/Compare 5 */
1003 
SFR_16BIT(TBCCR6);                            /* Timer B Capture/Compare 6 */
1004 
 
1005 
/* Alternate register names - 5xx style */
1006 
#define TB0IV                  TBIV           /* Timer B Interrupt Vector Word */
1007 
#define TB0CTL                 TBCTL          /* Timer B Control */
1008 
#define TB0CCTL0               TBCCTL0        /* Timer B Capture/Compare Control 0 */
1009 
#define TB0CCTL1               TBCCTL1        /* Timer B Capture/Compare Control 1 */
1010 
#define TB0CCTL2               TBCCTL2        /* Timer B Capture/Compare Control 2 */
1011 
#define TB0CCTL3               TBCCTL3        /* Timer B Capture/Compare Control 3 */
1012 
#define TB0CCTL4               TBCCTL4        /* Timer B Capture/Compare Control 4 */
1013 
#define TB0CCTL5               TBCCTL5        /* Timer B Capture/Compare Control 5 */
1014 
#define TB0CCTL6               TBCCTL6        /* Timer B Capture/Compare Control 6 */
1015 
#define TB0R                   TBR            /* Timer B Counter Register */
1016 
#define TB0CCR0                TBCCR0         /* Timer B Capture/Compare 0 */
1017 
#define TB0CCR1                TBCCR1         /* Timer B Capture/Compare 1 */
1018 
#define TB0CCR2                TBCCR2         /* Timer B Capture/Compare 2 */
1019 
#define TB0CCR3                TBCCR3         /* Timer B Capture/Compare 3 */
1020 
#define TB0CCR4                TBCCR4         /* Timer B Capture/Compare 4 */
1021 
#define TB0CCR5                TBCCR5         /* Timer B Capture/Compare 5 */
1022 
#define TB0CCR6                TBCCR6         /* Timer B Capture/Compare 6 */
1023 
#define TB0IV_                 TBIV_          /* Timer B Interrupt Vector Word */
1024 
#define TB0CTL_                TBCTL_         /* Timer B Control */
1025 
#define TB0CCTL0_              TBCCTL0_       /* Timer B Capture/Compare Control 0 */
1026 
#define TB0CCTL1_              TBCCTL1_       /* Timer B Capture/Compare Control 1 */
1027 
#define TB0CCTL2_              TBCCTL2_       /* Timer B Capture/Compare Control 2 */
1028 
#define TB0CCTL3_              TBCCTL3_       /* Timer B Capture/Compare Control 3 */
1029 
#define TB0CCTL4_              TBCCTL4_       /* Timer B Capture/Compare Control 4 */
1030 
#define TB0CCTL5_              TBCCTL5_       /* Timer B Capture/Compare Control 5 */
1031 
#define TB0CCTL6_              TBCCTL6_       /* Timer B Capture/Compare Control 6 */
1032 
#define TB0R_                  TBR_           /* Timer B Counter Register */
1033 
#define TB0CCR0_               TBCCR0_        /* Timer B Capture/Compare 0 */
1034 
#define TB0CCR1_               TBCCR1_        /* Timer B Capture/Compare 1 */
1035 
#define TB0CCR2_               TBCCR2_        /* Timer B Capture/Compare 2 */
1036 
#define TB0CCR3_               TBCCR3_        /* Timer B Capture/Compare 3 */
1037 
#define TB0CCR4_               TBCCR4_        /* Timer B Capture/Compare 4 */
1038 
#define TB0CCR5_               TBCCR5_        /* Timer B Capture/Compare 5 */
1039 
#define TB0CCR6_               TBCCR6_        /* Timer B Capture/Compare 6 */
1040 
 
1041 
#define TBCLGRP1               (0x4000)       /* Timer B Compare latch load group 1 */
1042 
#define TBCLGRP0               (0x2000)       /* Timer B Compare latch load group 0 */
1043 
#define CNTL1                  (0x1000)       /* Counter lenght 1 */
1044 
#define CNTL0                  (0x0800)       /* Counter lenght 0 */
1045 
#define TBSSEL1                (0x0200)       /* Clock source 1 */
1046 
#define TBSSEL0                (0x0100)       /* Clock source 0 */
1047 
#define TBCLR                  (0x0004)       /* Timer B counter clear */
1048 
#define TBIE                   (0x0002)       /* Timer B interrupt enable */
1049 
#define TBIFG                  (0x0001)       /* Timer B interrupt flag */
1050 
 
1051 
#define SHR1                   (0x4000)       /* Timer B Compare latch load group 1 */
1052 
#define SHR0                   (0x2000)       /* Timer B Compare latch load group 0 */
1053 
 
1054 
#define TBSSEL_0               (0*0x0100u)    /* Clock Source: TBCLK */
1055 
#define TBSSEL_1               (1*0x0100u)    /* Clock Source: ACLK  */
1056 
#define TBSSEL_2               (2*0x0100u)    /* Clock Source: SMCLK */
1057 
#define TBSSEL_3               (3*0x0100u)    /* Clock Source: INCLK */
1058 
#define CNTL_0                 (0*0x0800u)    /* Counter lenght: 16 bit */
1059 
#define CNTL_1                 (1*0x0800u)    /* Counter lenght: 12 bit */
1060 
#define CNTL_2                 (2*0x0800u)    /* Counter lenght: 10 bit */
1061 
#define CNTL_3                 (3*0x0800u)    /* Counter lenght:  8 bit */
1062 
#define SHR_0                  (0*0x2000u)    /* Timer B Group: 0 - individually */
1063 
#define SHR_1                  (1*0x2000u)    /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
1064 
#define SHR_2                  (2*0x2000u)    /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
1065 
#define SHR_3                  (3*0x2000u)    /* Timer B Group: 3 - 1 group (all) */
1066 
#define TBCLGRP_0              (0*0x2000u)    /* Timer B Group: 0 - individually */
1067 
#define TBCLGRP_1              (1*0x2000u)    /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
1068 
#define TBCLGRP_2              (2*0x2000u)    /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
1069 
#define TBCLGRP_3              (3*0x2000u)    /* Timer B Group: 3 - 1 group (all) */
1070 
 
1071 
/* Additional Timer B Control Register bits are defined in Timer A */
1072 
#define CLLD1                  (0x0400)       /* Compare latch load source 1 */
1073 
#define CLLD0                  (0x0200)       /* Compare latch load source 0 */
1074 
 
1075 
#define SLSHR1                 (0x0400)       /* Compare latch load source 1 */
1076 
#define SLSHR0                 (0x0200)       /* Compare latch load source 0 */
1077 
 
1078 
#define SLSHR_0                (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
1079 
#define SLSHR_1                (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
1080 
#define SLSHR_2                (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
1081 
#define SLSHR_3                (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
1082 
 
1083 
#define CLLD_0                 (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
1084 
#define CLLD_1                 (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
1085 
#define CLLD_2                 (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
1086 
#define CLLD_3                 (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
1087 
 
1088 
/* TB7IV Definitions */
1089 
#define TBIV_NONE              (0x0000)       /* No Interrupt pending */
1090 
#define TBIV_TBCCR1            (0x0002)       /* TBCCR1_CCIFG */
1091 
#define TBIV_TBCCR2            (0x0004)       /* TBCCR2_CCIFG */
1092 
#define TBIV_TBCCR3            (0x0006)       /* TBCCR3_CCIFG */
1093 
#define TBIV_TBCCR4            (0x0008)       /* TBCCR4_CCIFG */
1094 
#define TBIV_TBCCR5            (0x000A)       /* TBCCR3_CCIFG */
1095 
#define TBIV_TBCCR6            (0x000C)       /* TBCCR4_CCIFG */
1096 
#define TBIV_TBIFG             (0x000E)       /* TBIFG */
1097 
 
1098 
/************************************************************
1099 
* USCI
1100 
************************************************************/
1101 
#define __MSP430_HAS_USCI__                   /* Definition to show that Module is available */
1102 
#define __MSP430_HAS_USCI_AB0__                /* Definition to show that Module is available */
1103 
#define __MSP430_HAS_USCI_AB1__                /* Definition to show that Module is available */
1104 
 
1105 
SFR_8BIT(UCA0CTL0);                           /* USCI A0 Control Register 0 */
1106 
SFR_8BIT(UCA0CTL1);                           /* USCI A0 Control Register 1 */
1107 
SFR_8BIT(UCA0BR0);                            /* USCI A0 Baud Rate 0 */
1108 
SFR_8BIT(UCA0BR1);                            /* USCI A0 Baud Rate 1 */
1109 
SFR_8BIT(UCA0MCTL);                           /* USCI A0 Modulation Control */
1110 
SFR_8BIT(UCA0STAT);                           /* USCI A0 Status Register */
1111 
SFR_8BIT(UCA0RXBUF);                          /* USCI A0 Receive Buffer */
1112 
SFR_8BIT(UCA0TXBUF);                          /* USCI A0 Transmit Buffer */
1113 
SFR_8BIT(UCA0ABCTL);                          /* USCI A0 LIN Control */
1114 
SFR_8BIT(UCA0IRTCTL);                         /* USCI A0 IrDA Transmit Control */
1115 
SFR_8BIT(UCA0IRRCTL);                         /* USCI A0 IrDA Receive Control */
1116 
 
1117 
 
1118 
 
1119 
SFR_8BIT(UCB0CTL0);                           /* USCI B0 Control Register 0 */
1120 
SFR_8BIT(UCB0CTL1);                           /* USCI B0 Control Register 1 */
1121 
SFR_8BIT(UCB0BR0);                            /* USCI B0 Baud Rate 0 */
1122 
SFR_8BIT(UCB0BR1);                            /* USCI B0 Baud Rate 1 */
1123 
SFR_8BIT(UCB0I2CIE);                          /* USCI B0 I2C Interrupt Enable Register */
1124 
SFR_8BIT(UCB0STAT);                           /* USCI B0 Status Register */
1125 
SFR_8BIT(UCB0RXBUF);                          /* USCI B0 Receive Buffer */
1126 
SFR_8BIT(UCB0TXBUF);                          /* USCI B0 Transmit Buffer */
1127 
SFR_16BIT(UCB0I2COA);                         /* USCI B0 I2C Own Address */
1128 
SFR_16BIT(UCB0I2CSA);                         /* USCI B0 I2C Slave Address */
1129 
 
1130 
SFR_8BIT(UCA1CTL0);                           /* USCI A1 Control Register 0 */
1131 
SFR_8BIT(UCA1CTL1);                           /* USCI A1 Control Register 1 */
1132 
SFR_8BIT(UCA1BR0);                            /* USCI A1 Baud Rate 0 */
1133 
SFR_8BIT(UCA1BR1);                            /* USCI A1 Baud Rate 1 */
1134 
SFR_8BIT(UCA1MCTL);                           /* USCI A1 Modulation Control */
1135 
SFR_8BIT(UCA1STAT);                           /* USCI A1 Status Register */
1136 
SFR_8BIT(UCA1RXBUF);                          /* USCI A1 Receive Buffer */
1137 
SFR_8BIT(UCA1TXBUF);                          /* USCI A1 Transmit Buffer */
1138 
SFR_8BIT(UCA1ABCTL);                          /* USCI A1 LIN Control */
1139 
SFR_8BIT(UCA1IRTCTL);                         /* USCI A1 IrDA Transmit Control */
1140 
SFR_8BIT(UCA1IRRCTL);                         /* USCI A1 IrDA Receive Control */
1141 
 
1142 
 
1143 
 
1144 
SFR_8BIT(UCB1CTL0);                           /* USCI B1 Control Register 0 */
1145 
SFR_8BIT(UCB1CTL1);                           /* USCI B1 Control Register 1 */
1146 
SFR_8BIT(UCB1BR0);                            /* USCI B1 Baud Rate 0 */
1147 
SFR_8BIT(UCB1BR1);                            /* USCI B1 Baud Rate 1 */
1148 
SFR_8BIT(UCB1I2CIE);                          /* USCI B1 I2C Interrupt Enable Register */
1149 
SFR_8BIT(UCB1STAT);                           /* USCI B1 Status Register */
1150 
SFR_8BIT(UCB1RXBUF);                          /* USCI B1 Receive Buffer */
1151 
SFR_8BIT(UCB1TXBUF);                          /* USCI B1 Transmit Buffer */
1152 
SFR_16BIT(UCB1I2COA);                         /* USCI B1 I2C Own Address */
1153 
SFR_16BIT(UCB1I2CSA);                         /* USCI B1 I2C Slave Address */
1154 
 
1155 
// UART-Mode Bits
1156 
#define UCPEN                  (0x80)         /* Async. Mode: Parity enable */
1157 
#define UCPAR                  (0x40)         /* Async. Mode: Parity     0:odd / 1:even */
1158 
#define UCMSB                  (0x20)         /* Async. Mode: MSB first  0:LSB / 1:MSB */
1159 
#define UC7BIT                 (0x10)         /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
1160 
#define UCSPB                  (0x08)         /* Async. Mode: Stop Bits  0:one / 1: two */
1161 
#define UCMODE1                (0x04)         /* Async. Mode: USCI Mode 1 */
1162 
#define UCMODE0                (0x02)         /* Async. Mode: USCI Mode 0 */
1163 
#define UCSYNC                 (0x01)         /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
1164 
 
1165 
// SPI-Mode Bits
1166 
#define UCCKPH                 (0x80)         /* Sync. Mode: Clock Phase */
1167 
#define UCCKPL                 (0x40)         /* Sync. Mode: Clock Polarity */
1168 
#define UCMST                  (0x08)         /* Sync. Mode: Master Select */
1169 
 
1170 
// I2C-Mode Bits
1171 
#define UCA10                  (0x80)         /* 10-bit Address Mode */
1172 
#define UCSLA10                (0x40)         /* 10-bit Slave Address Mode */
1173 
#define UCMM                   (0x20)         /* Multi-Master Environment */
1174 
//#define res               (0x10)    /* reserved */
1175 
#define UCMODE_0               (0x00)         /* Sync. Mode: USCI Mode: 0 */
1176 
#define UCMODE_1               (0x02)         /* Sync. Mode: USCI Mode: 1 */
1177 
#define UCMODE_2               (0x04)         /* Sync. Mode: USCI Mode: 2 */
1178 
#define UCMODE_3               (0x06)         /* Sync. Mode: USCI Mode: 3 */
1179 
 
1180 
// UART-Mode Bits
1181 
#define UCSSEL1                (0x80)         /* USCI 0 Clock Source Select 1 */
1182 
#define UCSSEL0                (0x40)         /* USCI 0 Clock Source Select 0 */
1183 
#define UCRXEIE                (0x20)         /* RX Error interrupt enable */
1184 
#define UCBRKIE                (0x10)         /* Break interrupt enable */
1185 
#define UCDORM                 (0x08)         /* Dormant (Sleep) Mode */
1186 
#define UCTXADDR               (0x04)         /* Send next Data as Address */
1187 
#define UCTXBRK                (0x02)         /* Send next Data as Break */
1188 
#define UCSWRST                (0x01)         /* USCI Software Reset */
1189 
 
1190 
// SPI-Mode Bits
1191 
//#define res               (0x20)    /* reserved */
1192 
//#define res               (0x10)    /* reserved */
1193 
//#define res               (0x08)    /* reserved */
1194 
//#define res               (0x04)    /* reserved */
1195 
//#define res               (0x02)    /* reserved */
1196 
 
1197 
// I2C-Mode Bits
1198 
//#define res               (0x20)    /* reserved */
1199 
#define UCTR                   (0x10)         /* Transmit/Receive Select/Flag */
1200 
#define UCTXNACK               (0x08)         /* Transmit NACK */
1201 
#define UCTXSTP                (0x04)         /* Transmit STOP */
1202 
#define UCTXSTT                (0x02)         /* Transmit START */
1203 
#define UCSSEL_0               (0x00)         /* USCI 0 Clock Source: 0 */
1204 
#define UCSSEL_1               (0x40)         /* USCI 0 Clock Source: 1 */
1205 
#define UCSSEL_2               (0x80)         /* USCI 0 Clock Source: 2 */
1206 
#define UCSSEL_3               (0xC0)         /* USCI 0 Clock Source: 3 */
1207 
 
1208 
#define UCBRF3                 (0x80)         /* USCI First Stage Modulation Select 3 */
1209 
#define UCBRF2                 (0x40)         /* USCI First Stage Modulation Select 2 */
1210 
#define UCBRF1                 (0x20)         /* USCI First Stage Modulation Select 1 */
1211 
#define UCBRF0                 (0x10)         /* USCI First Stage Modulation Select 0 */
1212 
#define UCBRS2                 (0x08)         /* USCI Second Stage Modulation Select 2 */
1213 
#define UCBRS1                 (0x04)         /* USCI Second Stage Modulation Select 1 */
1214 
#define UCBRS0                 (0x02)         /* USCI Second Stage Modulation Select 0 */
1215 
#define UCOS16                 (0x01)         /* USCI 16-times Oversampling enable */
1216 
 
1217 
#define UCBRF_0                (0x00)         /* USCI First Stage Modulation: 0 */
1218 
#define UCBRF_1                (0x10)         /* USCI First Stage Modulation: 1 */
1219 
#define UCBRF_2                (0x20)         /* USCI First Stage Modulation: 2 */
1220 
#define UCBRF_3                (0x30)         /* USCI First Stage Modulation: 3 */
1221 
#define UCBRF_4                (0x40)         /* USCI First Stage Modulation: 4 */
1222 
#define UCBRF_5                (0x50)         /* USCI First Stage Modulation: 5 */
1223 
#define UCBRF_6                (0x60)         /* USCI First Stage Modulation: 6 */
1224 
#define UCBRF_7                (0x70)         /* USCI First Stage Modulation: 7 */
1225 
#define UCBRF_8                (0x80)         /* USCI First Stage Modulation: 8 */
1226 
#define UCBRF_9                (0x90)         /* USCI First Stage Modulation: 9 */
1227 
#define UCBRF_10               (0xA0)         /* USCI First Stage Modulation: A */
1228 
#define UCBRF_11               (0xB0)         /* USCI First Stage Modulation: B */
1229 
#define UCBRF_12               (0xC0)         /* USCI First Stage Modulation: C */
1230 
#define UCBRF_13               (0xD0)         /* USCI First Stage Modulation: D */
1231 
#define UCBRF_14               (0xE0)         /* USCI First Stage Modulation: E */
1232 
#define UCBRF_15               (0xF0)         /* USCI First Stage Modulation: F */
1233 
 
1234 
#define UCBRS_0                (0x00)         /* USCI Second Stage Modulation: 0 */
1235 
#define UCBRS_1                (0x02)         /* USCI Second Stage Modulation: 1 */
1236 
#define UCBRS_2                (0x04)         /* USCI Second Stage Modulation: 2 */
1237 
#define UCBRS_3                (0x06)         /* USCI Second Stage Modulation: 3 */
1238 
#define UCBRS_4                (0x08)         /* USCI Second Stage Modulation: 4 */
1239 
#define UCBRS_5                (0x0A)         /* USCI Second Stage Modulation: 5 */
1240 
#define UCBRS_6                (0x0C)         /* USCI Second Stage Modulation: 6 */
1241 
#define UCBRS_7                (0x0E)         /* USCI Second Stage Modulation: 7 */
1242 
 
1243 
#define UCLISTEN               (0x80)         /* USCI Listen mode */
1244 
#define UCFE                   (0x40)         /* USCI Frame Error Flag */
1245 
#define UCOE                   (0x20)         /* USCI Overrun Error Flag */
1246 
#define UCPE                   (0x10)         /* USCI Parity Error Flag */
1247 
#define UCBRK                  (0x08)         /* USCI Break received */
1248 
#define UCRXERR                (0x04)         /* USCI RX Error Flag */
1249 
#define UCADDR                 (0x02)         /* USCI Address received Flag */
1250 
#define UCBUSY                 (0x01)         /* USCI Busy Flag */
1251 
#define UCIDLE                 (0x02)         /* USCI Idle line detected Flag */
1252 
 
1253 
//#define res               (0x80)    /* reserved */
1254 
//#define res               (0x40)    /* reserved */
1255 
//#define res               (0x20)    /* reserved */
1256 
//#define res               (0x10)    /* reserved */
1257 
#define UCNACKIE               (0x08)         /* NACK Condition interrupt enable */
1258 
#define UCSTPIE                (0x04)         /* STOP Condition interrupt enable */
1259 
#define UCSTTIE                (0x02)         /* START Condition interrupt enable */
1260 
#define UCALIE                 (0x01)         /* Arbitration Lost interrupt enable */
1261 
 
1262 
#define UCSCLLOW               (0x40)         /* SCL low */
1263 
#define UCGC                   (0x20)         /* General Call address received Flag */
1264 
#define UCBBUSY                (0x10)         /* Bus Busy Flag */
1265 
#define UCNACKIFG              (0x08)         /* NAK Condition interrupt Flag */
1266 
#define UCSTPIFG               (0x04)         /* STOP Condition interrupt Flag */
1267 
#define UCSTTIFG               (0x02)         /* START Condition interrupt Flag */
1268 
#define UCALIFG                (0x01)         /* Arbitration Lost interrupt Flag */
1269 
 
1270 
#define UCIRTXPL5              (0x80)         /* IRDA Transmit Pulse Length 5 */
1271 
#define UCIRTXPL4              (0x40)         /* IRDA Transmit Pulse Length 4 */
1272 
#define UCIRTXPL3              (0x20)         /* IRDA Transmit Pulse Length 3 */
1273 
#define UCIRTXPL2              (0x10)         /* IRDA Transmit Pulse Length 2 */
1274 
#define UCIRTXPL1              (0x08)         /* IRDA Transmit Pulse Length 1 */
1275 
#define UCIRTXPL0              (0x04)         /* IRDA Transmit Pulse Length 0 */
1276 
#define UCIRTXCLK              (0x02)         /* IRDA Transmit Pulse Clock Select */
1277 
#define UCIREN                 (0x01)         /* IRDA Encoder/Decoder enable */
1278 
 
1279 
#define UCIRRXFL5              (0x80)         /* IRDA Receive Filter Length 5 */
1280 
#define UCIRRXFL4              (0x40)         /* IRDA Receive Filter Length 4 */
1281 
#define UCIRRXFL3              (0x20)         /* IRDA Receive Filter Length 3 */
1282 
#define UCIRRXFL2              (0x10)         /* IRDA Receive Filter Length 2 */
1283 
#define UCIRRXFL1              (0x08)         /* IRDA Receive Filter Length 1 */
1284 
#define UCIRRXFL0              (0x04)         /* IRDA Receive Filter Length 0 */
1285 
#define UCIRRXPL               (0x02)         /* IRDA Receive Input Polarity */
1286 
#define UCIRRXFE               (0x01)         /* IRDA Receive Filter enable */
1287 
 
1288 
//#define res               (0x80)    /* reserved */
1289 
//#define res               (0x40)    /* reserved */
1290 
#define UCDELIM1               (0x20)         /* Break Sync Delimiter 1 */
1291 
#define UCDELIM0               (0x10)         /* Break Sync Delimiter 0 */
1292 
#define UCSTOE                 (0x08)         /* Sync-Field Timeout error */
1293 
#define UCBTOE                 (0x04)         /* Break Timeout error */
1294 
//#define res               (0x02)    /* reserved */
1295 
#define UCABDEN                (0x01)         /* Auto Baud Rate detect enable */
1296 
 
1297 
#define UCGCEN                 (0x8000)       /* I2C General Call enable */
1298 
#define UCOA9                  (0x0200)       /* I2C Own Address 9 */
1299 
#define UCOA8                  (0x0100)       /* I2C Own Address 8 */
1300 
#define UCOA7                  (0x0080)       /* I2C Own Address 7 */
1301 
#define UCOA6                  (0x0040)       /* I2C Own Address 6 */
1302 
#define UCOA5                  (0x0020)       /* I2C Own Address 5 */
1303 
#define UCOA4                  (0x0010)       /* I2C Own Address 4 */
1304 
#define UCOA3                  (0x0008)       /* I2C Own Address 3 */
1305 
#define UCOA2                  (0x0004)       /* I2C Own Address 2 */
1306 
#define UCOA1                  (0x0002)       /* I2C Own Address 1 */
1307 
#define UCOA0                  (0x0001)       /* I2C Own Address 0 */
1308 
 
1309 
#define UCSA9                  (0x0200)       /* I2C Slave Address 9 */
1310 
#define UCSA8                  (0x0100)       /* I2C Slave Address 8 */
1311 
#define UCSA7                  (0x0080)       /* I2C Slave Address 7 */
1312 
#define UCSA6                  (0x0040)       /* I2C Slave Address 6 */
1313 
#define UCSA5                  (0x0020)       /* I2C Slave Address 5 */
1314 
#define UCSA4                  (0x0010)       /* I2C Slave Address 4 */
1315 
#define UCSA3                  (0x0008)       /* I2C Slave Address 3 */
1316 
#define UCSA2                  (0x0004)       /* I2C Slave Address 2 */
1317 
#define UCSA1                  (0x0002)       /* I2C Slave Address 1 */
1318 
#define UCSA0                  (0x0001)       /* I2C Slave Address 0 */
1319 
 
1320 
/************************************************************
1321 
* WATCHDOG TIMER
1322 
************************************************************/
1323 
#define __MSP430_HAS_WDT__                    /* Definition to show that Module is available */
1324 
 
1325 
SFR_16BIT(WDTCTL);                            /* Watchdog Timer Control */
1326 
/* The bit names have been prefixed with "WDT" */
1327 
#define WDTIS0                 (0x0001)
1328 
#define WDTIS1                 (0x0002)
1329 
#define WDTSSEL                (0x0004)
1330 
#define WDTCNTCL               (0x0008)
1331 
#define WDTTMSEL               (0x0010)
1332 
#define WDTNMI                 (0x0020)
1333 
#define WDTNMIES               (0x0040)
1334 
#define WDTHOLD                (0x0080)
1335 
 
1336 
#define WDTPW                  (0x5A00)
1337 
 
1338 
/* WDT-interval times [1ms] coded with Bits 0-2 */
1339 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
1340 
#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL)                         /* 32ms interval (default) */
1341 
#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0)                  /* 8ms     " */
1342 
#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1)                  /* 0.5ms   " */
1343 
#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0)           /* 0.064ms " */
1344 
/* WDT is clocked by fACLK (assumed 32KHz) */
1345 
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)                 /* 1000ms  " */
1346 
#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0)          /* 250ms   " */
1347 
#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1)          /* 16ms    " */
1348 
#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)   /* 1.9ms   " */
1349 
/* Watchdog mode -> reset after expired time */
1350 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
1351 
#define WDT_MRST_32         (WDTPW+WDTCNTCL)                                  /* 32ms interval (default) */
1352 
#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS0)                           /* 8ms     " */
1353 
#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS1)                           /* 0.5ms   " */
1354 
#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS1+WDTIS0)                    /* 0.064ms " */
1355 
/* WDT is clocked by fACLK (assumed 32KHz) */
1356 
#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL)                          /* 1000ms  " */
1357 
#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0)                   /* 250ms   " */
1358 
#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1)                   /* 16ms    " */
1359 
#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)            /* 1.9ms   " */
1360 
 
1361 
/* INTERRUPT CONTROL */
1362 
/* These two bits are defined in the Special Function Registers */
1363 
/* #define WDTIE               0x01 */
1364 
/* #define WDTIFG              0x01 */
1365 
 
1366 
/************************************************************
1367 
* Calibration Data in Info Mem
1368 
************************************************************/
1369 
 
1370 
/* TLV Calibration Data Structure */
1371 
#define TAG_DCO_30             (0x01)         /* Tag for DCO30  Calibration Data */
1372 
#define TAG_ADC12_1            (0x08)         /* Tag for ADC12_1 Calibration Data */
1373 
#define TAG_EMPTY              (0xFE)         /* Tag for Empty Data Field in Calibration Data */
1374 
 
1375 
#ifndef __DisableCalData
1376 
SFR_16BIT(TLV_CHECKSUM);                      /* TLV CHECK SUM */
1377 
SFR_8BIT(TLV_DCO_30_TAG);                     /* TLV TAG_DCO30 TAG */
1378 
SFR_8BIT(TLV_DCO_30_LEN);                     /* TLV TAG_DCO30 LEN */
1379 
SFR_8BIT(TLV_ADC12_1_TAG);                    /* TLV ADC12_1 TAG */
1380 
SFR_8BIT(TLV_ADC12_1_LEN);                    /* TLV ADC12_1 LEN */
1381 
#endif
1382 
 
1383 
#define CAL_ADC_25T85          (0x0007)       /* Index for 2.5V/85Deg Cal. Value */
1384 
#define CAL_ADC_25T30          (0x0006)       /* Index for 2.5V/30Deg Cal. Value */
1385 
#define CAL_ADC_25VREF_FACTOR  (0x0005)       /* Index for 2.5V Ref. Factor */
1386 
#define CAL_ADC_15T85          (0x0004)       /* Index for 1.5V/85Deg Cal. Value */
1387 
#define CAL_ADC_15T30          (0x0003)       /* Index for 1.5V/30Deg Cal. Value */
1388 
#define CAL_ADC_15VREF_FACTOR  (0x0002)       /* Index for ADC 1.5V Ref. Factor */
1389 
#define CAL_ADC_OFFSET         (0x0001)       /* Index for ADC Offset */
1390 
#define CAL_ADC_GAIN_FACTOR    (0x0000)       /* Index for ADC Gain Factor */
1391 
 
1392 
#define CAL_DCO_16MHZ          (0x0000)       /* Index for DCOCTL  Calibration Data for 16MHz */
1393 
#define CAL_BC1_16MHZ          (0x0001)       /* Index for BCSCTL1 Calibration Data for 16MHz */
1394 
#define CAL_DCO_12MHZ          (0x0002)       /* Index for DCOCTL  Calibration Data for 12MHz */
1395 
#define CAL_BC1_12MHZ          (0x0003)       /* Index for BCSCTL1 Calibration Data for 12MHz */
1396 
#define CAL_DCO_8MHZ           (0x0004)       /* Index for DCOCTL  Calibration Data for 8MHz */
1397 
#define CAL_BC1_8MHZ           (0x0005)       /* Index for BCSCTL1 Calibration Data for 8MHz */
1398 
#define CAL_DCO_1MHZ           (0x0006)       /* Index for DCOCTL  Calibration Data for 1MHz */
1399 
#define CAL_BC1_1MHZ           (0x0007)       /* Index for BCSCTL1 Calibration Data for 1MHz */
1400 
 
1401 
 
1402 
/************************************************************
1403 
* Calibration Data in Info Mem
1404 
************************************************************/
1405 
 
1406 
#ifndef __DisableCalData
1407 
 
1408 
SFR_8BIT(CALDCO_16MHZ);                       /* DCOCTL  Calibration Data for 16MHz */
1409 
SFR_8BIT(CALBC1_16MHZ);                       /* BCSCTL1 Calibration Data for 16MHz */
1410 
SFR_8BIT(CALDCO_12MHZ);                       /* DCOCTL  Calibration Data for 12MHz */
1411 
SFR_8BIT(CALBC1_12MHZ);                       /* BCSCTL1 Calibration Data for 12MHz */
1412 
SFR_8BIT(CALDCO_8MHZ);                        /* DCOCTL  Calibration Data for 8MHz */
1413 
SFR_8BIT(CALBC1_8MHZ);                        /* BCSCTL1 Calibration Data for 8MHz */
1414 
SFR_8BIT(CALDCO_1MHZ);                        /* DCOCTL  Calibration Data for 1MHz */
1415 
SFR_8BIT(CALBC1_1MHZ);                        /* BCSCTL1 Calibration Data for 1MHz */
1416 
 
1417 
#endif /* #ifndef __DisableCalData */
1418 
 
1419 
/************************************************************
1420 
* Interrupt Vectors (offset from 0xFFC0)
1421 
************************************************************/
1422 
 
1423 
#pragma diag_suppress 1107
1424 
#define VECTOR_NAME(name)             name##_ptr
1425 
#define EMIT_PRAGMA(x)                _Pragma(#x)
1426 
#define CREATE_VECTOR(name)           void * const VECTOR_NAME(name) = (void *)(long)&name
1427 
#define PLACE_VECTOR(vector,section)  EMIT_PRAGMA(DATA_SECTION(vector,section))
1428 
#define PLACE_INTERRUPT(func)         EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
1429 
#define ISR_VECTOR(func,offset)       CREATE_VECTOR(func); \
1430 
                                      PLACE_VECTOR(VECTOR_NAME(func), offset) \
1431 
                                      PLACE_INTERRUPT(func)
1432 
 
1433 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1434 
#define RESERVED0_VECTOR        ".int00"                    /* 0xFFC0 Reserved Int. Vector 0 */
1435 
#else
1436 
#define RESERVED0_VECTOR        (0 * 1u)                     /* 0xFFC0 Reserved Int. Vector 0 */
1437 
/*#define RESERVED0_ISR(func)     ISR_VECTOR(func, ".int00")  */ /* 0xFFC0 Reserved Int. Vector 0 */ /* CCE V2 Style */
1438 
#endif
1439 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1440 
#define RESERVED1_VECTOR        ".int01"                    /* 0xFFC2 Reserved Int. Vector 1 */
1441 
#else
1442 
#define RESERVED1_VECTOR        (1 * 1u)                     /* 0xFFC2 Reserved Int. Vector 1 */
1443 
/*#define RESERVED1_ISR(func)     ISR_VECTOR(func, ".int01")  */ /* 0xFFC2 Reserved Int. Vector 1 */ /* CCE V2 Style */
1444 
#endif
1445 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1446 
#define RESERVED2_VECTOR        ".int02"                    /* 0xFFC4 Reserved Int. Vector 2 */
1447 
#else
1448 
#define RESERVED2_VECTOR        (2 * 1u)                     /* 0xFFC4 Reserved Int. Vector 2 */
1449 
/*#define RESERVED2_ISR(func)     ISR_VECTOR(func, ".int02")  */ /* 0xFFC4 Reserved Int. Vector 2 */ /* CCE V2 Style */
1450 
#endif
1451 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1452 
#define RESERVED3_VECTOR        ".int03"                    /* 0xFFC6 Reserved Int. Vector 3 */
1453 
#else
1454 
#define RESERVED3_VECTOR        (3 * 1u)                     /* 0xFFC6 Reserved Int. Vector 3 */
1455 
/*#define RESERVED3_ISR(func)     ISR_VECTOR(func, ".int03")  */ /* 0xFFC6 Reserved Int. Vector 3 */ /* CCE V2 Style */
1456 
#endif
1457 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1458 
#define RESERVED4_VECTOR        ".int04"                    /* 0xFFC8 Reserved Int. Vector 4 */
1459 
#else
1460 
#define RESERVED4_VECTOR        (4 * 1u)                     /* 0xFFC8 Reserved Int. Vector 4 */
1461 
/*#define RESERVED4_ISR(func)     ISR_VECTOR(func, ".int04")  */ /* 0xFFC8 Reserved Int. Vector 4 */ /* CCE V2 Style */
1462 
#endif
1463 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1464 
#define RESERVED5_VECTOR        ".int05"                    /* 0xFFCA Reserved Int. Vector 5 */
1465 
#else
1466 
#define RESERVED5_VECTOR        (5 * 1u)                     /* 0xFFCA Reserved Int. Vector 5 */
1467 
/*#define RESERVED5_ISR(func)     ISR_VECTOR(func, ".int05")  */ /* 0xFFCA Reserved Int. Vector 5 */ /* CCE V2 Style */
1468 
#endif
1469 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1470 
#define RESERVED6_VECTOR        ".int06"                    /* 0xFFCC Reserved Int. Vector 6 */
1471 
#else
1472 
#define RESERVED6_VECTOR        (6 * 1u)                     /* 0xFFCC Reserved Int. Vector 6 */
1473 
/*#define RESERVED6_ISR(func)     ISR_VECTOR(func, ".int06")  */ /* 0xFFCC Reserved Int. Vector 6 */ /* CCE V2 Style */
1474 
#endif
1475 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1476 
#define RESERVED7_VECTOR        ".int07"                    /* 0xFFCE Reserved Int. Vector 7 */
1477 
#else
1478 
#define RESERVED7_VECTOR        (7 * 1u)                     /* 0xFFCE Reserved Int. Vector 7 */
1479 
/*#define RESERVED7_ISR(func)     ISR_VECTOR(func, ".int07")  */ /* 0xFFCE Reserved Int. Vector 7 */ /* CCE V2 Style */
1480 
#endif
1481 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1482 
#define RESERVED8_VECTOR        ".int08"                    /* 0xFFD0 Reserved Int. Vector 8 */
1483 
#else
1484 
#define RESERVED8_VECTOR        (8 * 1u)                     /* 0xFFD0 Reserved Int. Vector 8 */
1485 
/*#define RESERVED8_ISR(func)     ISR_VECTOR(func, ".int08")  */ /* 0xFFD0 Reserved Int. Vector 8 */ /* CCE V2 Style */
1486 
#endif
1487 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1488 
#define RESERVED9_VECTOR        ".int09"                    /* 0xFFD2 Reserved Int. Vector 9 */
1489 
#else
1490 
#define RESERVED9_VECTOR        (9 * 1u)                     /* 0xFFD2 Reserved Int. Vector 9 */
1491 
/*#define RESERVED9_ISR(func)     ISR_VECTOR(func, ".int09")  */ /* 0xFFD2 Reserved Int. Vector 9 */ /* CCE V2 Style */
1492 
#endif
1493 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1494 
#define RESERVED10_VECTOR       ".int10"                    /* 0xFFD4 Reserved Int. Vector 10 */
1495 
#else
1496 
#define RESERVED10_VECTOR       (10 * 1u)                    /* 0xFFD4 Reserved Int. Vector 10 */
1497 
/*#define RESERVED10_ISR(func)    ISR_VECTOR(func, ".int10")  */ /* 0xFFD4 Reserved Int. Vector 10 */ /* CCE V2 Style */
1498 
#endif
1499 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1500 
#define RESERVED11_VECTOR       ".int11"                    /* 0xFFD6 Reserved Int. Vector 11 */
1501 
#else
1502 
#define RESERVED11_VECTOR       (11 * 1u)                    /* 0xFFD6 Reserved Int. Vector 11 */
1503 
/*#define RESERVED11_ISR(func)    ISR_VECTOR(func, ".int11")  */ /* 0xFFD6 Reserved Int. Vector 11 */ /* CCE V2 Style */
1504 
#endif
1505 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1506 
#define RESERVED12_VECTOR       ".int12"                    /* 0xFFD8 Reserved Int. Vector 12 */
1507 
#else
1508 
#define RESERVED12_VECTOR       (12 * 1u)                    /* 0xFFD8 Reserved Int. Vector 12 */
1509 
/*#define RESERVED12_ISR(func)    ISR_VECTOR(func, ".int12")  */ /* 0xFFD8 Reserved Int. Vector 12 */ /* CCE V2 Style */
1510 
#endif
1511 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1512 
#define RESERVED13_VECTOR       ".int13"                    /* 0xFFDA Reserved Int. Vector 13 */
1513 
#else
1514 
#define RESERVED13_VECTOR       (13 * 1u)                    /* 0xFFDA Reserved Int. Vector 13 */
1515 
/*#define RESERVED13_ISR(func)    ISR_VECTOR(func, ".int13")  */ /* 0xFFDA Reserved Int. Vector 13 */ /* CCE V2 Style */
1516 
#endif
1517 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1518 
#define DAC12_VECTOR            ".int14"                    /* 0xFFDC DAC12 */
1519 
#else
1520 
#define DAC12_VECTOR            (14 * 1u)                    /* 0xFFDC DAC12 */
1521 
/*#define DAC12_ISR(func)         ISR_VECTOR(func, ".int14")  */ /* 0xFFDC DAC12 */ /* CCE V2 Style */
1522 
#endif
1523 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1524 
#define DMA_VECTOR              ".int15"                    /* 0xFFDE DMA */
1525 
#else
1526 
#define DMA_VECTOR              (15 * 1u)                    /* 0xFFDE DMA */
1527 
/*#define DMA_ISR(func)           ISR_VECTOR(func, ".int15")  */ /* 0xFFDE DMA */ /* CCE V2 Style */
1528 
#endif
1529 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1530 
#define USCIAB1TX_VECTOR        ".int16"                    /* 0xFFE0 USCI A1/B1 Transmit */
1531 
#else
1532 
#define USCIAB1TX_VECTOR        (16 * 1u)                    /* 0xFFE0 USCI A1/B1 Transmit */
1533 
/*#define USCIAB1TX_ISR(func)     ISR_VECTOR(func, ".int16")  */ /* 0xFFE0 USCI A1/B1 Transmit */ /* CCE V2 Style */
1534 
#endif
1535 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1536 
#define USCIAB1RX_VECTOR        ".int17"                    /* 0xFFE2 USCI A1/B1 Receive */
1537 
#else
1538 
#define USCIAB1RX_VECTOR        (17 * 1u)                    /* 0xFFE2 USCI A1/B1 Receive */
1539 
/*#define USCIAB1RX_ISR(func)     ISR_VECTOR(func, ".int17")  */ /* 0xFFE2 USCI A1/B1 Receive */ /* CCE V2 Style */
1540 
#endif
1541 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1542 
#define PORT1_VECTOR            ".int18"                    /* 0xFFE4 Port 1 */
1543 
#else
1544 
#define PORT1_VECTOR            (18 * 1u)                    /* 0xFFE4 Port 1 */
1545 
/*#define PORT1_ISR(func)         ISR_VECTOR(func, ".int18")  */ /* 0xFFE4 Port 1 */ /* CCE V2 Style */
1546 
#endif
1547 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1548 
#define PORT2_VECTOR            ".int19"                    /* 0xFFE6 Port 2 */
1549 
#else
1550 
#define PORT2_VECTOR            (19 * 1u)                    /* 0xFFE6 Port 2 */
1551 
/*#define PORT2_ISR(func)         ISR_VECTOR(func, ".int19")  */ /* 0xFFE6 Port 2 */ /* CCE V2 Style */
1552 
#endif
1553 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1554 
#define RESERVED20_VECTOR       ".int20"                    /* 0xFFE8 Reserved Int. Vector 20 */
1555 
#else
1556 
#define RESERVED20_VECTOR       (20 * 1u)                    /* 0xFFE8 Reserved Int. Vector 20 */
1557 
/*#define RESERVED20_ISR(func)    ISR_VECTOR(func, ".int20")  */ /* 0xFFE8 Reserved Int. Vector 20 */ /* CCE V2 Style */
1558 
#endif
1559 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1560 
#define ADC12_VECTOR            ".int21"                    /* 0xFFEA ADC */
1561 
#else
1562 
#define ADC12_VECTOR            (21 * 1u)                    /* 0xFFEA ADC */
1563 
/*#define ADC12_ISR(func)         ISR_VECTOR(func, ".int21")  */ /* 0xFFEA ADC */ /* CCE V2 Style */
1564 
#endif
1565 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1566 
#define USCIAB0TX_VECTOR        ".int22"                    /* 0xFFEC USCI A0/B0 Transmit */
1567 
#else
1568 
#define USCIAB0TX_VECTOR        (22 * 1u)                    /* 0xFFEC USCI A0/B0 Transmit */
1569 
/*#define USCIAB0TX_ISR(func)     ISR_VECTOR(func, ".int22")  */ /* 0xFFEC USCI A0/B0 Transmit */ /* CCE V2 Style */
1570 
#endif
1571 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1572 
#define USCIAB0RX_VECTOR        ".int23"                    /* 0xFFEE USCI A0/B0 Receive */
1573 
#else
1574 
#define USCIAB0RX_VECTOR        (23 * 1u)                    /* 0xFFEE USCI A0/B0 Receive */
1575 
/*#define USCIAB0RX_ISR(func)     ISR_VECTOR(func, ".int23")  */ /* 0xFFEE USCI A0/B0 Receive */ /* CCE V2 Style */
1576 
#endif
1577 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1578 
#define TIMERA1_VECTOR          ".int24"                    /* 0xFFF0 Timer A CC1-2, TA */
1579 
#else
1580 
#define TIMERA1_VECTOR          (24 * 1u)                    /* 0xFFF0 Timer A CC1-2, TA */
1581 
/*#define TIMERA1_ISR(func)       ISR_VECTOR(func, ".int24")  */ /* 0xFFF0 Timer A CC1-2, TA */ /* CCE V2 Style */
1582 
#endif
1583 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1584 
#define TIMERA0_VECTOR          ".int25"                    /* 0xFFF2 Timer A CC0 */
1585 
#else
1586 
#define TIMERA0_VECTOR          (25 * 1u)                    /* 0xFFF2 Timer A CC0 */
1587 
/*#define TIMERA0_ISR(func)       ISR_VECTOR(func, ".int25")  */ /* 0xFFF2 Timer A CC0 */ /* CCE V2 Style */
1588 
#endif
1589 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1590 
#define WDT_VECTOR              ".int26"                    /* 0xFFF4 Watchdog Timer */
1591 
#else
1592 
#define WDT_VECTOR              (26 * 1u)                    /* 0xFFF4 Watchdog Timer */
1593 
/*#define WDT_ISR(func)           ISR_VECTOR(func, ".int26")  */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
1594 
#endif
1595 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1596 
#define COMPARATORA_VECTOR      ".int27"                    /* 0xFFF6 Comparator A */
1597 
#else
1598 
#define COMPARATORA_VECTOR      (27 * 1u)                    /* 0xFFF6 Comparator A */
1599 
/*#define COMPARATORA_ISR(func)   ISR_VECTOR(func, ".int27")  */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */
1600 
#endif
1601 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1602 
#define TIMERB1_VECTOR          ".int28"                    /* 0xFFF8 Timer B CC1-6, TB */
1603 
#else
1604 
#define TIMERB1_VECTOR          (28 * 1u)                    /* 0xFFF8 Timer B CC1-6, TB */
1605 
/*#define TIMERB1_ISR(func)       ISR_VECTOR(func, ".int28")  */ /* 0xFFF8 Timer B CC1-6, TB */ /* CCE V2 Style */
1606 
#endif
1607 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1608 
#define TIMERB0_VECTOR          ".int29"                    /* 0xFFFA Timer B CC0 */
1609 
#else
1610 
#define TIMERB0_VECTOR          (29 * 1u)                    /* 0xFFFA Timer B CC0 */
1611 
/*#define TIMERB0_ISR(func)       ISR_VECTOR(func, ".int29")  */ /* 0xFFFA Timer B CC0 */ /* CCE V2 Style */
1612 
#endif
1613 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1614 
#define NMI_VECTOR              ".int30"                    /* 0xFFFC Non-maskable */
1615 
#else
1616 
#define NMI_VECTOR              (30 * 1u)                    /* 0xFFFC Non-maskable */
1617 
/*#define NMI_ISR(func)           ISR_VECTOR(func, ".int30")  */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
1618 
#endif
1619 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1620 
#define RESET_VECTOR            ".reset"                    /* 0xFFFE Reset [Highest Priority] */
1621 
#else
1622 
#define RESET_VECTOR            (31 * 1u)                    /* 0xFFFE Reset [Highest Priority] */
1623 
/*#define RESET_ISR(func)         ISR_VECTOR(func, ".int31")  */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
1624 
#endif
1625 
 
1626 
/************************************************************
1627 
* End of Modules
1628 
************************************************************/
1629 
 
1630 
#ifdef __cplusplus
1631 
}
1632 
#endif /* extern "C" */
1633 
 
1634 
#endif /* #ifndef __msp430x26x */
1635