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2850 dpurdie 1 
/******************************************************************************/
2 
/* Legacy Header File                                                         */
3 
/* Not recommended for use in new projects.                                   */
4 
/* Please use the msp430.h file or the device specific header file            */
5 
/******************************************************************************/
6 
 
7 
/********************************************************************
8 
*
9 
* Standard register and bit definitions for the Texas Instruments
10 
* MSP430 microcontroller.
11 
*
12 
* This file supports assembler and C development for
13 
* MSP430x23x devices.
14 
*
15 
* Texas Instruments, Version 1.4
16 
*
17 
* Rev. 1.0, Initial Version
18 
* Rev. 1.1  added TLV in INFO Memory
19 
* Rev. 1.2  added missing SVS Register
20 
* Rev. 1.3, added definitions for Interrupt Vectors xxIV
21 
* Rev. 1.4, fixed define: TAG_ADC12_1 to 0x08
22 
*
23 
********************************************************************/
24 
 
25 
#ifndef __msp430x23x
26 
#define __msp430x23x
27 
 
28 
#ifdef __cplusplus
29 
extern "C" {
30 
#endif
31 
 
32 
 
33 
/*----------------------------------------------------------------------------*/
34 
/* PERIPHERAL FILE MAP                                                        */
35 
/*----------------------------------------------------------------------------*/
36 
 
37 
/* External references resolved by a device-specific linker command file */
38 
#define SFR_8BIT(address)   extern volatile unsigned char address
39 
#define SFR_16BIT(address)  extern volatile unsigned int address
40 
 
41 
 
42 
/************************************************************
43 
* STANDARD BITS
44 
************************************************************/
45 
 
46 
#define BIT0                   (0x0001)
47 
#define BIT1                   (0x0002)
48 
#define BIT2                   (0x0004)
49 
#define BIT3                   (0x0008)
50 
#define BIT4                   (0x0010)
51 
#define BIT5                   (0x0020)
52 
#define BIT6                   (0x0040)
53 
#define BIT7                   (0x0080)
54 
#define BIT8                   (0x0100)
55 
#define BIT9                   (0x0200)
56 
#define BITA                   (0x0400)
57 
#define BITB                   (0x0800)
58 
#define BITC                   (0x1000)
59 
#define BITD                   (0x2000)
60 
#define BITE                   (0x4000)
61 
#define BITF                   (0x8000)
62 
 
63 
/************************************************************
64 
* STATUS REGISTER BITS
65 
************************************************************/
66 
 
67 
#define C                      (0x0001)
68 
#define Z                      (0x0002)
69 
#define N                      (0x0004)
70 
#define V                      (0x0100)
71 
#define GIE                    (0x0008)
72 
#define CPUOFF                 (0x0010)
73 
#define OSCOFF                 (0x0020)
74 
#define SCG0                   (0x0040)
75 
#define SCG1                   (0x0080)
76 
 
77 
/* Low Power Modes coded with Bits 4-7 in SR */
78 
 
79 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
80 
#define LPM0                   (CPUOFF)
81 
#define LPM1                   (SCG0+CPUOFF)
82 
#define LPM2                   (SCG1+CPUOFF)
83 
#define LPM3                   (SCG1+SCG0+CPUOFF)
84 
#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
85 
/* End #defines for assembler */
86 
 
87 
#else /* Begin #defines for C */
88 
#define LPM0_bits              (CPUOFF)
89 
#define LPM1_bits              (SCG0+CPUOFF)
90 
#define LPM2_bits              (SCG1+CPUOFF)
91 
#define LPM3_bits              (SCG1+SCG0+CPUOFF)
92 
#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
93 
 
94 
#include "in430.h"
95 
 
96 
#define LPM0         _bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
97 
#define LPM0_EXIT    _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
98 
#define LPM1         _bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
99 
#define LPM1_EXIT    _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
100 
#define LPM2         _bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
101 
#define LPM2_EXIT    _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
102 
#define LPM3         _bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
103 
#define LPM3_EXIT    _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
104 
#define LPM4         _bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
105 
#define LPM4_EXIT    _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
106 
#endif /* End #defines for C */
107 
 
108 
/************************************************************
109 
* PERIPHERAL FILE MAP
110 
************************************************************/
111 
 
112 
/************************************************************
113 
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
114 
************************************************************/
115 
 
116 
SFR_8BIT(IE1);                                /* Interrupt Enable 1 */
117 
#define WDTIE                  (0x01)         /* Watchdog Interrupt Enable */
118 
#define OFIE                   (0x02)         /* Osc. Fault  Interrupt Enable */
119 
#define NMIIE                  (0x10)         /* NMI Interrupt Enable */
120 
#define ACCVIE                 (0x20)         /* Flash Access Violation Interrupt Enable */
121 
 
122 
SFR_8BIT(IFG1);                               /* Interrupt Flag 1 */
123 
#define WDTIFG                 (0x01)         /* Watchdog Interrupt Flag */
124 
#define OFIFG                  (0x02)         /* Osc. Fault Interrupt Flag */
125 
#define PORIFG                 (0x04)         /* Power On Interrupt Flag */
126 
#define RSTIFG                 (0x08)         /* Reset Interrupt Flag */
127 
#define NMIIFG                 (0x10)         /* NMI Interrupt Flag */
128 
 
129 
SFR_8BIT(IE2);                                /* Interrupt Enable 2 */
130 
#define UC0IE                  IE2
131 
#define UCA0RXIE               (0x01)
132 
#define UCA0TXIE               (0x02)
133 
#define UCB0RXIE               (0x04)
134 
#define UCB0TXIE               (0x08)
135 
 
136 
SFR_8BIT(IFG2);                               /* Interrupt Flag 2 */
137 
#define UC0IFG                 IFG2
138 
#define UCA0RXIFG              (0x01)
139 
#define UCA0TXIFG              (0x02)
140 
#define UCB0RXIFG              (0x04)
141 
#define UCB0TXIFG              (0x08)
142 
 
143 
/************************************************************
144 
* ADC12
145 
************************************************************/
146 
#define __MSP430_HAS_ADC12__                  /* Definition to show that Module is available */
147 
 
148 
SFR_16BIT(ADC12CTL0);                         /* ADC12 Control 0 */
149 
SFR_16BIT(ADC12CTL1);                         /* ADC12 Control 1 */
150 
SFR_16BIT(ADC12IFG);                          /* ADC12 Interrupt Flag */
151 
SFR_16BIT(ADC12IE);                           /* ADC12 Interrupt Enable */
152 
SFR_16BIT(ADC12IV);                           /* ADC12 Interrupt Vector Word */
153 
 
154 
#define ADC12MEM_              (0x0140)       /* ADC12 Conversion Memory */
155 
#ifdef __ASM_HEADER__
156 
#define ADC12MEM               (ADC12MEM_)    /* ADC12 Conversion Memory (for assembler) */
157 
#else
158 
#define ADC12MEM               ((int*)        ADC12MEM_) /* ADC12 Conversion Memory (for C) */
159 
#endif
160 
SFR_16BIT(ADC12MEM0);                         /* ADC12 Conversion Memory 0 */
161 
SFR_16BIT(ADC12MEM1);                         /* ADC12 Conversion Memory 1 */
162 
SFR_16BIT(ADC12MEM2);                         /* ADC12 Conversion Memory 2 */
163 
SFR_16BIT(ADC12MEM3);                         /* ADC12 Conversion Memory 3 */
164 
SFR_16BIT(ADC12MEM4);                         /* ADC12 Conversion Memory 4 */
165 
SFR_16BIT(ADC12MEM5);                         /* ADC12 Conversion Memory 5 */
166 
SFR_16BIT(ADC12MEM6);                         /* ADC12 Conversion Memory 6 */
167 
SFR_16BIT(ADC12MEM7);                         /* ADC12 Conversion Memory 7 */
168 
SFR_16BIT(ADC12MEM8);                         /* ADC12 Conversion Memory 8 */
169 
SFR_16BIT(ADC12MEM9);                         /* ADC12 Conversion Memory 9 */
170 
SFR_16BIT(ADC12MEM10);                        /* ADC12 Conversion Memory 10 */
171 
SFR_16BIT(ADC12MEM11);                        /* ADC12 Conversion Memory 11 */
172 
SFR_16BIT(ADC12MEM12);                        /* ADC12 Conversion Memory 12 */
173 
SFR_16BIT(ADC12MEM13);                        /* ADC12 Conversion Memory 13 */
174 
SFR_16BIT(ADC12MEM14);                        /* ADC12 Conversion Memory 14 */
175 
SFR_16BIT(ADC12MEM15);                        /* ADC12 Conversion Memory 15 */
176 
 
177 
#define ADC12MCTL_             (0x0080)       /* ADC12 Memory Control */
178 
#ifdef __ASM_HEADER__
179 
#define ADC12MCTL              (ADC12MCTL_)   /* ADC12 Memory Control (for assembler) */
180 
#else
181 
#define ADC12MCTL              ((char*)       ADC12MCTL_) /* ADC12 Memory Control (for C) */
182 
#endif
183 
SFR_8BIT(ADC12MCTL0);                         /* ADC12 Memory Control 0 */
184 
SFR_8BIT(ADC12MCTL1);                         /* ADC12 Memory Control 1 */
185 
SFR_8BIT(ADC12MCTL2);                         /* ADC12 Memory Control 2 */
186 
SFR_8BIT(ADC12MCTL3);                         /* ADC12 Memory Control 3 */
187 
SFR_8BIT(ADC12MCTL4);                         /* ADC12 Memory Control 4 */
188 
SFR_8BIT(ADC12MCTL5);                         /* ADC12 Memory Control 5 */
189 
SFR_8BIT(ADC12MCTL6);                         /* ADC12 Memory Control 6 */
190 
SFR_8BIT(ADC12MCTL7);                         /* ADC12 Memory Control 7 */
191 
SFR_8BIT(ADC12MCTL8);                         /* ADC12 Memory Control 8 */
192 
SFR_8BIT(ADC12MCTL9);                         /* ADC12 Memory Control 9 */
193 
SFR_8BIT(ADC12MCTL10);                        /* ADC12 Memory Control 10 */
194 
SFR_8BIT(ADC12MCTL11);                        /* ADC12 Memory Control 11 */
195 
SFR_8BIT(ADC12MCTL12);                        /* ADC12 Memory Control 12 */
196 
SFR_8BIT(ADC12MCTL13);                        /* ADC12 Memory Control 13 */
197 
SFR_8BIT(ADC12MCTL14);                        /* ADC12 Memory Control 14 */
198 
SFR_8BIT(ADC12MCTL15);                        /* ADC12 Memory Control 15 */
199 
 
200 
/* ADC12CTL0 */
201 
#define ADC12SC                (0x001)        /* ADC12 Start Conversion */
202 
#define ENC                    (0x002)        /* ADC12 Enable Conversion */
203 
#define ADC12TOVIE             (0x004)        /* ADC12 Timer Overflow interrupt enable */
204 
#define ADC12OVIE              (0x008)        /* ADC12 Overflow interrupt enable */
205 
#define ADC12ON                (0x010)        /* ADC12 On/enable */
206 
#define REFON                  (0x020)        /* ADC12 Reference on */
207 
#define REF2_5V                (0x040)        /* ADC12 Ref 0:1.5V / 1:2.5V */
208 
#define MSC                    (0x080)        /* ADC12 Multiple SampleConversion */
209 
#define SHT00                  (0x0100)       /* ADC12 Sample Hold 0 Select 0 */
210 
#define SHT01                  (0x0200)       /* ADC12 Sample Hold 0 Select 1 */
211 
#define SHT02                  (0x0400)       /* ADC12 Sample Hold 0 Select 2 */
212 
#define SHT03                  (0x0800)       /* ADC12 Sample Hold 0 Select 3 */
213 
#define SHT10                  (0x1000)       /* ADC12 Sample Hold 0 Select 0 */
214 
#define SHT11                  (0x2000)       /* ADC12 Sample Hold 1 Select 1 */
215 
#define SHT12                  (0x4000)       /* ADC12 Sample Hold 2 Select 2 */
216 
#define SHT13                  (0x8000)       /* ADC12 Sample Hold 3 Select 3 */
217 
#define MSH                    (0x080)
218 
 
219 
#define SHT0_0                 (0*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 0 */
220 
#define SHT0_1                 (1*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 1 */
221 
#define SHT0_2                 (2*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 2 */
222 
#define SHT0_3                 (3*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 3 */
223 
#define SHT0_4                 (4*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 4 */
224 
#define SHT0_5                 (5*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 5 */
225 
#define SHT0_6                 (6*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 6 */
226 
#define SHT0_7                 (7*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 7 */
227 
#define SHT0_8                 (8*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 8 */
228 
#define SHT0_9                 (9*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 9 */
229 
#define SHT0_10                (10*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 10 */
230 
#define SHT0_11                (11*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 11 */
231 
#define SHT0_12                (12*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 12 */
232 
#define SHT0_13                (13*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 13 */
233 
#define SHT0_14                (14*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 14 */
234 
#define SHT0_15                (15*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 15 */
235 
 
236 
#define SHT1_0                 (0*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 0 */
237 
#define SHT1_1                 (1*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 1 */
238 
#define SHT1_2                 (2*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 2 */
239 
#define SHT1_3                 (3*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 3 */
240 
#define SHT1_4                 (4*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 4 */
241 
#define SHT1_5                 (5*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 5 */
242 
#define SHT1_6                 (6*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 6 */
243 
#define SHT1_7                 (7*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 7 */
244 
#define SHT1_8                 (8*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 8 */
245 
#define SHT1_9                 (9*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 9 */
246 
#define SHT1_10                (10*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 10 */
247 
#define SHT1_11                (11*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 11 */
248 
#define SHT1_12                (12*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 12 */
249 
#define SHT1_13                (13*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 13 */
250 
#define SHT1_14                (14*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 14 */
251 
#define SHT1_15                (15*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 15 */
252 
 
253 
/* ADC12CTL1 */
254 
#define ADC12BUSY              (0x0001)       /* ADC12 Busy */
255 
#define CONSEQ0                (0x0002)       /* ADC12 Conversion Sequence Select 0 */
256 
#define CONSEQ1                (0x0004)       /* ADC12 Conversion Sequence Select 1 */
257 
#define ADC12SSEL0             (0x0008)       /* ADC12 Clock Source Select 0 */
258 
#define ADC12SSEL1             (0x0010)       /* ADC12 Clock Source Select 1 */
259 
#define ADC12DIV0              (0x0020)       /* ADC12 Clock Divider Select 0 */
260 
#define ADC12DIV1              (0x0040)       /* ADC12 Clock Divider Select 1 */
261 
#define ADC12DIV2              (0x0080)       /* ADC12 Clock Divider Select 2 */
262 
#define ISSH                   (0x0100)       /* ADC12 Invert Sample Hold Signal */
263 
#define SHP                    (0x0200)       /* ADC12 Sample/Hold Pulse Mode */
264 
#define SHS0                   (0x0400)       /* ADC12 Sample/Hold Source 0 */
265 
#define SHS1                   (0x0800)       /* ADC12 Sample/Hold Source 1 */
266 
#define CSTARTADD0             (0x1000)       /* ADC12 Conversion Start Address 0 */
267 
#define CSTARTADD1             (0x2000)       /* ADC12 Conversion Start Address 1 */
268 
#define CSTARTADD2             (0x4000)       /* ADC12 Conversion Start Address 2 */
269 
#define CSTARTADD3             (0x8000)       /* ADC12 Conversion Start Address 3 */
270 
 
271 
#define CONSEQ_0               (0*2u)         /* ADC12 Conversion Sequence Select: 0 */
272 
#define CONSEQ_1               (1*2u)         /* ADC12 Conversion Sequence Select: 1 */
273 
#define CONSEQ_2               (2*2u)         /* ADC12 Conversion Sequence Select: 2 */
274 
#define CONSEQ_3               (3*2u)         /* ADC12 Conversion Sequence Select: 3 */
275 
#define ADC12SSEL_0            (0*8u)         /* ADC12 Clock Source Select: 0 */
276 
#define ADC12SSEL_1            (1*8u)         /* ADC12 Clock Source Select: 1 */
277 
#define ADC12SSEL_2            (2*8u)         /* ADC12 Clock Source Select: 2 */
278 
#define ADC12SSEL_3            (3*8u)         /* ADC12 Clock Source Select: 3 */
279 
#define ADC12DIV_0             (0*0x20u)      /* ADC12 Clock Divider Select: 0 */
280 
#define ADC12DIV_1             (1*0x20u)      /* ADC12 Clock Divider Select: 1 */
281 
#define ADC12DIV_2             (2*0x20u)      /* ADC12 Clock Divider Select: 2 */
282 
#define ADC12DIV_3             (3*0x20u)      /* ADC12 Clock Divider Select: 3 */
283 
#define ADC12DIV_4             (4*0x20u)      /* ADC12 Clock Divider Select: 4 */
284 
#define ADC12DIV_5             (5*0x20u)      /* ADC12 Clock Divider Select: 5 */
285 
#define ADC12DIV_6             (6*0x20u)      /* ADC12 Clock Divider Select: 6 */
286 
#define ADC12DIV_7             (7*0x20u)      /* ADC12 Clock Divider Select: 7 */
287 
#define SHS_0                  (0*0x400u)     /* ADC12 Sample/Hold Source: 0 */
288 
#define SHS_1                  (1*0x400u)     /* ADC12 Sample/Hold Source: 1 */
289 
#define SHS_2                  (2*0x400u)     /* ADC12 Sample/Hold Source: 2 */
290 
#define SHS_3                  (3*0x400u)     /* ADC12 Sample/Hold Source: 3 */
291 
#define CSTARTADD_0            (0*0x1000u)    /* ADC12 Conversion Start Address: 0 */
292 
#define CSTARTADD_1            (1*0x1000u)    /* ADC12 Conversion Start Address: 1 */
293 
#define CSTARTADD_2            (2*0x1000u)    /* ADC12 Conversion Start Address: 2 */
294 
#define CSTARTADD_3            (3*0x1000u)    /* ADC12 Conversion Start Address: 3 */
295 
#define CSTARTADD_4            (4*0x1000u)    /* ADC12 Conversion Start Address: 4 */
296 
#define CSTARTADD_5            (5*0x1000u)    /* ADC12 Conversion Start Address: 5 */
297 
#define CSTARTADD_6            (6*0x1000u)    /* ADC12 Conversion Start Address: 6 */
298 
#define CSTARTADD_7            (7*0x1000u)    /* ADC12 Conversion Start Address: 7 */
299 
#define CSTARTADD_8            (8*0x1000u)    /* ADC12 Conversion Start Address: 8 */
300 
#define CSTARTADD_9            (9*0x1000u)    /* ADC12 Conversion Start Address: 9 */
301 
#define CSTARTADD_10           (10*0x1000u)   /* ADC12 Conversion Start Address: 10 */
302 
#define CSTARTADD_11           (11*0x1000u)   /* ADC12 Conversion Start Address: 11 */
303 
#define CSTARTADD_12           (12*0x1000u)   /* ADC12 Conversion Start Address: 12 */
304 
#define CSTARTADD_13           (13*0x1000u)   /* ADC12 Conversion Start Address: 13 */
305 
#define CSTARTADD_14           (14*0x1000u)   /* ADC12 Conversion Start Address: 14 */
306 
#define CSTARTADD_15           (15*0x1000u)   /* ADC12 Conversion Start Address: 15 */
307 
 
308 
/* ADC12MCTLx */
309 
#define INCH0                  (0x0001)       /* ADC12 Input Channel Select Bit 0 */
310 
#define INCH1                  (0x0002)       /* ADC12 Input Channel Select Bit 1 */
311 
#define INCH2                  (0x0004)       /* ADC12 Input Channel Select Bit 2 */
312 
#define INCH3                  (0x0008)       /* ADC12 Input Channel Select Bit 3 */
313 
#define SREF0                  (0x0010)       /* ADC12 Select Reference Bit 0 */
314 
#define SREF1                  (0x0020)       /* ADC12 Select Reference Bit 1 */
315 
#define SREF2                  (0x0040)       /* ADC12 Select Reference Bit 2 */
316 
#define EOS                    (0x0080)       /* ADC12 End of Sequence */
317 
 
318 
#define INCH_0                 (0)            /* ADC12 Input Channel 0 */
319 
#define INCH_1                 (1)            /* ADC12 Input Channel 1 */
320 
#define INCH_2                 (2)            /* ADC12 Input Channel 2 */
321 
#define INCH_3                 (3)            /* ADC12 Input Channel 3 */
322 
#define INCH_4                 (4)            /* ADC12 Input Channel 4 */
323 
#define INCH_5                 (5)            /* ADC12 Input Channel 5 */
324 
#define INCH_6                 (6)            /* ADC12 Input Channel 6 */
325 
#define INCH_7                 (7)            /* ADC12 Input Channel 7 */
326 
#define INCH_8                 (8)            /* ADC12 Input Channel 8 */
327 
#define INCH_9                 (9)            /* ADC12 Input Channel 9 */
328 
#define INCH_10                (10)           /* ADC12 Input Channel 10 */
329 
#define INCH_11                (11)           /* ADC12 Input Channel 11 */
330 
#define INCH_12                (12)           /* ADC12 Input Channel 12 */
331 
#define INCH_13                (13)           /* ADC12 Input Channel 13 */
332 
#define INCH_14                (14)           /* ADC12 Input Channel 14 */
333 
#define INCH_15                (15)           /* ADC12 Input Channel 15 */
334 
 
335 
#define SREF_0                 (0*0x10u)      /* ADC12 Select Reference 0 */
336 
#define SREF_1                 (1*0x10u)      /* ADC12 Select Reference 1 */
337 
#define SREF_2                 (2*0x10u)      /* ADC12 Select Reference 2 */
338 
#define SREF_3                 (3*0x10u)      /* ADC12 Select Reference 3 */
339 
#define SREF_4                 (4*0x10u)      /* ADC12 Select Reference 4 */
340 
#define SREF_5                 (5*0x10u)      /* ADC12 Select Reference 5 */
341 
#define SREF_6                 (6*0x10u)      /* ADC12 Select Reference 6 */
342 
#define SREF_7                 (7*0x10u)      /* ADC12 Select Reference 7 */
343 
 
344 
/* ADC12IV Definitions */
345 
#define ADC12IV_NONE           (0x0000)       /* No Interrupt pending */
346 
#define ADC12IV_ADC12OVIFG     (0x0002)       /* ADC12OVIFG */
347 
#define ADC12IV_ADC12TOVIFG    (0x0004)       /* ADC12TOVIFG */
348 
#define ADC12IV_ADC12IFG0      (0x0006)       /* ADC12IFG0 */
349 
#define ADC12IV_ADC12IFG1      (0x0008)       /* ADC12IFG1 */
350 
#define ADC12IV_ADC12IFG2      (0x000A)       /* ADC12IFG2 */
351 
#define ADC12IV_ADC12IFG3      (0x000C)       /* ADC12IFG3 */
352 
#define ADC12IV_ADC12IFG4      (0x000E)       /* ADC12IFG4 */
353 
#define ADC12IV_ADC12IFG5      (0x0010)       /* ADC12IFG5 */
354 
#define ADC12IV_ADC12IFG6      (0x0012)       /* ADC12IFG6 */
355 
#define ADC12IV_ADC12IFG7      (0x0014)       /* ADC12IFG7 */
356 
#define ADC12IV_ADC12IFG8      (0x0016)       /* ADC12IFG8 */
357 
#define ADC12IV_ADC12IFG9      (0x0018)       /* ADC12IFG9 */
358 
#define ADC12IV_ADC12IFG10     (0x001A)       /* ADC12IFG10 */
359 
#define ADC12IV_ADC12IFG11     (0x001C)       /* ADC12IFG11 */
360 
#define ADC12IV_ADC12IFG12     (0x001E)       /* ADC12IFG12 */
361 
#define ADC12IV_ADC12IFG13     (0x0020)       /* ADC12IFG13 */
362 
#define ADC12IV_ADC12IFG14     (0x0022)       /* ADC12IFG14 */
363 
#define ADC12IV_ADC12IFG15     (0x0024)       /* ADC12IFG15 */
364 
 
365 
/************************************************************
366 
* Basic Clock Module
367 
************************************************************/
368 
#define __MSP430_HAS_BC2__                    /* Definition to show that Module is available */
369 
 
370 
SFR_8BIT(DCOCTL);                             /* DCO Clock Frequency Control */
371 
SFR_8BIT(BCSCTL1);                            /* Basic Clock System Control 1 */
372 
SFR_8BIT(BCSCTL2);                            /* Basic Clock System Control 2 */
373 
SFR_8BIT(BCSCTL3);                            /* Basic Clock System Control 3 */
374 
 
375 
#define MOD0                   (0x01)         /* Modulation Bit 0 */
376 
#define MOD1                   (0x02)         /* Modulation Bit 1 */
377 
#define MOD2                   (0x04)         /* Modulation Bit 2 */
378 
#define MOD3                   (0x08)         /* Modulation Bit 3 */
379 
#define MOD4                   (0x10)         /* Modulation Bit 4 */
380 
#define DCO0                   (0x20)         /* DCO Select Bit 0 */
381 
#define DCO1                   (0x40)         /* DCO Select Bit 1 */
382 
#define DCO2                   (0x80)         /* DCO Select Bit 2 */
383 
 
384 
#define RSEL0                  (0x01)         /* Range Select Bit 0 */
385 
#define RSEL1                  (0x02)         /* Range Select Bit 1 */
386 
#define RSEL2                  (0x04)         /* Range Select Bit 2 */
387 
#define RSEL3                  (0x08)         /* Range Select Bit 3 */
388 
#define DIVA0                  (0x10)         /* ACLK Divider 0 */
389 
#define DIVA1                  (0x20)         /* ACLK Divider 1 */
390 
#define XTS                    (0x40)         /* LFXTCLK 0:Low Freq. / 1: High Freq. */
391 
#define XT2OFF                 (0x80)         /* Enable XT2CLK */
392 
 
393 
#define DIVA_0                 (0x00)         /* ACLK Divider 0: /1 */
394 
#define DIVA_1                 (0x10)         /* ACLK Divider 1: /2 */
395 
#define DIVA_2                 (0x20)         /* ACLK Divider 2: /4 */
396 
#define DIVA_3                 (0x30)         /* ACLK Divider 3: /8 */
397 
 
398 
#define DCOR                   (0x01)         /* Enable External Resistor : 1 */
399 
#define DIVS0                  (0x02)         /* SMCLK Divider 0 */
400 
#define DIVS1                  (0x04)         /* SMCLK Divider 1 */
401 
#define SELS                   (0x08)         /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
402 
#define DIVM0                  (0x10)         /* MCLK Divider 0 */
403 
#define DIVM1                  (0x20)         /* MCLK Divider 1 */
404 
#define SELM0                  (0x40)         /* MCLK Source Select 0 */
405 
#define SELM1                  (0x80)         /* MCLK Source Select 1 */
406 
 
407 
#define DIVS_0                 (0x00)         /* SMCLK Divider 0: /1 */
408 
#define DIVS_1                 (0x02)         /* SMCLK Divider 1: /2 */
409 
#define DIVS_2                 (0x04)         /* SMCLK Divider 2: /4 */
410 
#define DIVS_3                 (0x06)         /* SMCLK Divider 3: /8 */
411 
 
412 
#define DIVM_0                 (0x00)         /* MCLK Divider 0: /1 */
413 
#define DIVM_1                 (0x10)         /* MCLK Divider 1: /2 */
414 
#define DIVM_2                 (0x20)         /* MCLK Divider 2: /4 */
415 
#define DIVM_3                 (0x30)         /* MCLK Divider 3: /8 */
416 
 
417 
#define SELM_0                 (0x00)         /* MCLK Source Select 0: DCOCLK */
418 
#define SELM_1                 (0x40)         /* MCLK Source Select 1: DCOCLK */
419 
#define SELM_2                 (0x80)         /* MCLK Source Select 2: XT2CLK/LFXTCLK */
420 
#define SELM_3                 (0xC0)         /* MCLK Source Select 3: LFXTCLK */
421 
 
422 
#define LFXT1OF                (0x01)         /* Low/high Frequency Oscillator Fault Flag */
423 
#define XT2OF                  (0x02)         /* High frequency oscillator 2 fault flag */
424 
#define XCAP0                  (0x04)         /* XIN/XOUT Cap 0 */
425 
#define XCAP1                  (0x08)         /* XIN/XOUT Cap 1 */
426 
#define LFXT1S0                (0x10)         /* Mode 0 for LFXT1 (XTS = 0) */
427 
#define LFXT1S1                (0x20)         /* Mode 1 for LFXT1 (XTS = 0) */
428 
#define XT2S0                  (0x40)         /* Mode 0 for XT2 */
429 
#define XT2S1                  (0x80)         /* Mode 1 for XT2 */
430 
 
431 
#define XCAP_0                 (0x00)         /* XIN/XOUT Cap : 0 pF */
432 
#define XCAP_1                 (0x04)         /* XIN/XOUT Cap : 6 pF */
433 
#define XCAP_2                 (0x08)         /* XIN/XOUT Cap : 10 pF */
434 
#define XCAP_3                 (0x0C)         /* XIN/XOUT Cap : 12.5 pF */
435 
 
436 
#define LFXT1S_0               (0x00)         /* Mode 0 for LFXT1 : Normal operation */
437 
#define LFXT1S_1               (0x10)         /* Mode 1 for LFXT1 : Reserved */
438 
#define LFXT1S_2               (0x20)         /* Mode 2 for LFXT1 : VLO */
439 
#define LFXT1S_3               (0x30)         /* Mode 3 for LFXT1 : Digital input signal */
440 
 
441 
#define XT2S_0                 (0x00)         /* Mode 0 for XT2 : 0.4 - 1 MHz */
442 
#define XT2S_1                 (0x40)         /* Mode 1 for XT2 : 1 - 4 MHz */
443 
#define XT2S_2                 (0x80)         /* Mode 2 for XT2 : 2 - 16 MHz */
444 
#define XT2S_3                 (0xC0)         /* Mode 3 for XT2 : Digital input signal */
445 
 
446 
/************************************************************
447 
* Comparator A
448 
************************************************************/
449 
#define __MSP430_HAS_CAPLUS__                 /* Definition to show that Module is available */
450 
 
451 
SFR_8BIT(CACTL1);                             /* Comparator A Control 1 */
452 
SFR_8BIT(CACTL2);                             /* Comparator A Control 2 */
453 
SFR_8BIT(CAPD);                               /* Comparator A Port Disable */
454 
 
455 
#define CAIFG                  (0x01)         /* Comp. A Interrupt Flag */
456 
#define CAIE                   (0x02)         /* Comp. A Interrupt Enable */
457 
#define CAIES                  (0x04)         /* Comp. A Int. Edge Select: 0:rising / 1:falling */
458 
#define CAON                   (0x08)         /* Comp. A enable */
459 
#define CAREF0                 (0x10)         /* Comp. A Internal Reference Select 0 */
460 
#define CAREF1                 (0x20)         /* Comp. A Internal Reference Select 1 */
461 
#define CARSEL                 (0x40)         /* Comp. A Internal Reference Enable */
462 
#define CAEX                   (0x80)         /* Comp. A Exchange Inputs */
463 
 
464 
#define CAREF_0                (0x00)         /* Comp. A Int. Ref. Select 0 : Off */
465 
#define CAREF_1                (0x10)         /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
466 
#define CAREF_2                (0x20)         /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
467 
#define CAREF_3                (0x30)         /* Comp. A Int. Ref. Select 3 : Vt*/
468 
 
469 
#define CAOUT                  (0x01)         /* Comp. A Output */
470 
#define CAF                    (0x02)         /* Comp. A Enable Output Filter */
471 
#define P2CA0                  (0x04)         /* Comp. A +Terminal Multiplexer */
472 
#define P2CA1                  (0x08)         /* Comp. A -Terminal Multiplexer */
473 
#define P2CA2                  (0x10)         /* Comp. A -Terminal Multiplexer */
474 
#define P2CA3                  (0x20)         /* Comp. A -Terminal Multiplexer */
475 
#define P2CA4                  (0x40)         /* Comp. A +Terminal Multiplexer */
476 
#define CASHORT                (0x80)         /* Comp. A Short + and - Terminals */
477 
 
478 
#define CAPD0                  (0x01)         /* Comp. A Disable Input Buffer of Port Register .0 */
479 
#define CAPD1                  (0x02)         /* Comp. A Disable Input Buffer of Port Register .1 */
480 
#define CAPD2                  (0x04)         /* Comp. A Disable Input Buffer of Port Register .2 */
481 
#define CAPD3                  (0x08)         /* Comp. A Disable Input Buffer of Port Register .3 */
482 
#define CAPD4                  (0x10)         /* Comp. A Disable Input Buffer of Port Register .4 */
483 
#define CAPD5                  (0x20)         /* Comp. A Disable Input Buffer of Port Register .5 */
484 
#define CAPD6                  (0x40)         /* Comp. A Disable Input Buffer of Port Register .6 */
485 
#define CAPD7                  (0x80)         /* Comp. A Disable Input Buffer of Port Register .7 */
486 
 
487 
/*************************************************************
488 
* Flash Memory
489 
*************************************************************/
490 
#define __MSP430_HAS_FLASH2__                 /* Definition to show that Module is available */
491 
 
492 
SFR_16BIT(FCTL1);                             /* FLASH Control 1 */
493 
SFR_16BIT(FCTL2);                             /* FLASH Control 2 */
494 
SFR_16BIT(FCTL3);                             /* FLASH Control 3 */
495 
SFR_16BIT(FCTL4);                             /* FLASH Control 4 */
496 
 
497 
#define FRKEY                  (0x9600)       /* Flash key returned by read */
498 
#define FWKEY                  (0xA500)       /* Flash key for write */
499 
#define FXKEY                  (0x3300)       /* for use with XOR instruction */
500 
 
501 
#define ERASE                  (0x0002)       /* Enable bit for Flash segment erase */
502 
#define MERAS                  (0x0004)       /* Enable bit for Flash mass erase */
503 
#define EEI                    (0x0008)       /* Enable Erase Interrupts */
504 
#define EEIEX                  (0x0010)       /* Enable Emergency Interrupt Exit */
505 
#define WRT                    (0x0040)       /* Enable bit for Flash write */
506 
#define BLKWRT                 (0x0080)       /* Enable bit for Flash segment write */
507 
#define SEGWRT                 (0x0080)       /* old definition */ /* Enable bit for Flash segment write */
508 
 
509 
#define FN0                    (0x0001)       /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
510 
#define FN1                    (0x0002)       /*  32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
511 
#ifndef FN2
512 
#define FN2                    (0x0004)
513 
#endif
514 
#ifndef FN3
515 
#define FN3                    (0x0008)
516 
#endif
517 
#ifndef FN4
518 
#define FN4                    (0x0010)
519 
#endif
520 
#define FN5                    (0x0020)
521 
#define FSSEL0                 (0x0040)       /* Flash clock select 0 */        /* to distinguish from USART SSELx */
522 
#define FSSEL1                 (0x0080)       /* Flash clock select 1 */
523 
 
524 
#define FSSEL_0                (0x0000)       /* Flash clock select: 0 - ACLK */
525 
#define FSSEL_1                (0x0040)       /* Flash clock select: 1 - MCLK */
526 
#define FSSEL_2                (0x0080)       /* Flash clock select: 2 - SMCLK */
527 
#define FSSEL_3                (0x00C0)       /* Flash clock select: 3 - SMCLK */
528 
 
529 
#define BUSY                   (0x0001)       /* Flash busy: 1 */
530 
#define KEYV                   (0x0002)       /* Flash Key violation flag */
531 
#define ACCVIFG                (0x0004)       /* Flash Access violation flag */
532 
#define WAIT                   (0x0008)       /* Wait flag for segment write */
533 
#define LOCK                   (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
534 
#define EMEX                   (0x0020)       /* Flash Emergency Exit */
535 
#define LOCKA                  (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
536 
#define FAIL                   (0x0080)       /* Last Program or Erase failed */
537 
 
538 
#define MGR0                   (0x0010)       /* Marginal read 0 mode. */
539 
#define MGR1                   (0x0020)       /* Marginal read 1 mode. */
540 
 
541 
/************************************************************
542 
* HARDWARE MULTIPLIER
543 
************************************************************/
544 
#define __MSP430_HAS_MPY__                    /* Definition to show that Module is available */
545 
 
546 
SFR_16BIT(MPY);                               /* Multiply Unsigned/Operand 1 */
547 
SFR_16BIT(MPYS);                              /* Multiply Signed/Operand 1 */
548 
SFR_16BIT(MAC);                               /* Multiply Unsigned and Accumulate/Operand 1 */
549 
SFR_16BIT(MACS);                              /* Multiply Signed and Accumulate/Operand 1 */
550 
SFR_16BIT(OP2);                               /* Operand 2 */
551 
SFR_16BIT(RESLO);                             /* Result Low Word */
552 
SFR_16BIT(RESHI);                             /* Result High Word */
553 
SFR_16BIT(SUMEXT);                            /* Sum Extend */
554 
 
555 
/************************************************************
556 
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
557 
************************************************************/
558 
#define __MSP430_HAS_PORT1_R__                /* Definition to show that Module is available */
559 
#define __MSP430_HAS_PORT2_R__                /* Definition to show that Module is available */
560 
 
561 
SFR_8BIT(P1IN);                               /* Port 1 Input */
562 
SFR_8BIT(P1OUT);                              /* Port 1 Output */
563 
SFR_8BIT(P1DIR);                              /* Port 1 Direction */
564 
SFR_8BIT(P1IFG);                              /* Port 1 Interrupt Flag */
565 
SFR_8BIT(P1IES);                              /* Port 1 Interrupt Edge Select */
566 
SFR_8BIT(P1IE);                               /* Port 1 Interrupt Enable */
567 
SFR_8BIT(P1SEL);                              /* Port 1 Selection */
568 
SFR_8BIT(P1REN);                              /* Port 1 Resistor Enable */
569 
 
570 
SFR_8BIT(P2IN);                               /* Port 2 Input */
571 
SFR_8BIT(P2OUT);                              /* Port 2 Output */
572 
SFR_8BIT(P2DIR);                              /* Port 2 Direction */
573 
SFR_8BIT(P2IFG);                              /* Port 2 Interrupt Flag */
574 
SFR_8BIT(P2IES);                              /* Port 2 Interrupt Edge Select */
575 
SFR_8BIT(P2IE);                               /* Port 2 Interrupt Enable */
576 
SFR_8BIT(P2SEL);                              /* Port 2 Selection */
577 
SFR_8BIT(P2REN);                              /* Port 2 Resistor Enable */
578 
 
579 
/************************************************************
580 
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
581 
************************************************************/
582 
#define __MSP430_HAS_PORT3_R__                /* Definition to show that Module is available */
583 
#define __MSP430_HAS_PORT4_R__                /* Definition to show that Module is available */
584 
 
585 
SFR_8BIT(P3IN);                               /* Port 3 Input */
586 
SFR_8BIT(P3OUT);                              /* Port 3 Output */
587 
SFR_8BIT(P3DIR);                              /* Port 3 Direction */
588 
SFR_8BIT(P3SEL);                              /* Port 3 Selection */
589 
SFR_8BIT(P3REN);                              /* Port 3 Resistor Enable */
590 
 
591 
SFR_8BIT(P4IN);                               /* Port 4 Input */
592 
SFR_8BIT(P4OUT);                              /* Port 4 Output */
593 
SFR_8BIT(P4DIR);                              /* Port 4 Direction */
594 
SFR_8BIT(P4SEL);                              /* Port 4 Selection */
595 
SFR_8BIT(P4REN);                              /* Port 4 Resistor Enable */
596 
 
597 
/************************************************************
598 
* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
599 
************************************************************/
600 
#define __MSP430_HAS_PORT5_R__                /* Definition to show that Module is available */
601 
#define __MSP430_HAS_PORT6_R__                /* Definition to show that Module is available */
602 
 
603 
SFR_8BIT(P5IN);                               /* Port 5 Input */
604 
SFR_8BIT(P5OUT);                              /* Port 5 Output */
605 
SFR_8BIT(P5DIR);                              /* Port 5 Direction */
606 
SFR_8BIT(P5SEL);                              /* Port 5 Selection */
607 
SFR_8BIT(P5REN);                              /* Port 5 Resistor Enable */
608 
 
609 
SFR_8BIT(P6IN);                               /* Port 6 Input */
610 
SFR_8BIT(P6OUT);                              /* Port 6 Output */
611 
SFR_8BIT(P6DIR);                              /* Port 6 Direction */
612 
SFR_8BIT(P6SEL);                              /* Port 6 Selection */
613 
SFR_8BIT(P6REN);                              /* Port 6 Resistor Enable */
614 
 
615 
/************************************************************
616 
* Brown-Out, Supply Voltage Supervision (SVS)
617 
************************************************************/
618 
#define __MSP430_HAS_SVS__                    /* Definition to show that Module is available */
619 
 
620 
SFR_8BIT(SVSCTL);                             /* SVS Control */
621 
#define SVSFG                  (0x01)         /* SVS Flag */
622 
#define SVSOP                  (0x02)         /* SVS output (read only) */
623 
#define SVSON                  (0x04)         /* Switches the SVS on/off */
624 
#define PORON                  (0x08)         /* Enable POR Generation if Low Voltage */
625 
#define VLD0                   (0x10)
626 
#define VLD1                   (0x20)
627 
#define VLD2                   (0x40)
628 
#define VLD3                   (0x80)
629 
 
630 
#define VLDON                  (0x10)
631 
#define VLDOFF                 (0x00)
632 
#define VLD_1_8V               (0x10)
633 
 
634 
/************************************************************
635 
* Timer A3
636 
************************************************************/
637 
#define __MSP430_HAS_TA3__                    /* Definition to show that Module is available */
638 
 
639 
SFR_16BIT(TAIV);                              /* Timer A Interrupt Vector Word */
640 
SFR_16BIT(TACTL);                             /* Timer A Control */
641 
SFR_16BIT(TACCTL0);                           /* Timer A Capture/Compare Control 0 */
642 
SFR_16BIT(TACCTL1);                           /* Timer A Capture/Compare Control 1 */
643 
SFR_16BIT(TACCTL2);                           /* Timer A Capture/Compare Control 2 */
644 
SFR_16BIT(TAR);                               /* Timer A Counter Register */
645 
SFR_16BIT(TACCR0);                            /* Timer A Capture/Compare 0 */
646 
SFR_16BIT(TACCR1);                            /* Timer A Capture/Compare 1 */
647 
SFR_16BIT(TACCR2);                            /* Timer A Capture/Compare 2 */
648 
 
649 
/* Alternate register names */
650 
#define CCTL0                  TACCTL0        /* Timer A Capture/Compare Control 0 */
651 
#define CCTL1                  TACCTL1        /* Timer A Capture/Compare Control 1 */
652 
#define CCTL2                  TACCTL2        /* Timer A Capture/Compare Control 2 */
653 
#define CCR0                   TACCR0         /* Timer A Capture/Compare 0 */
654 
#define CCR1                   TACCR1         /* Timer A Capture/Compare 1 */
655 
#define CCR2                   TACCR2         /* Timer A Capture/Compare 2 */
656 
#define CCTL0_                 TACCTL0_       /* Timer A Capture/Compare Control 0 */
657 
#define CCTL1_                 TACCTL1_       /* Timer A Capture/Compare Control 1 */
658 
#define CCTL2_                 TACCTL2_       /* Timer A Capture/Compare Control 2 */
659 
#define CCR0_                  TACCR0_        /* Timer A Capture/Compare 0 */
660 
#define CCR1_                  TACCR1_        /* Timer A Capture/Compare 1 */
661 
#define CCR2_                  TACCR2_        /* Timer A Capture/Compare 2 */
662 
/* Alternate register names - 5xx style */
663 
#define TA0IV                  TAIV           /* Timer A Interrupt Vector Word */
664 
#define TA0CTL                 TACTL          /* Timer A Control */
665 
#define TA0CCTL0               TACCTL0        /* Timer A Capture/Compare Control 0 */
666 
#define TA0CCTL1               TACCTL1        /* Timer A Capture/Compare Control 1 */
667 
#define TA0CCTL2               TACCTL2        /* Timer A Capture/Compare Control 2 */
668 
#define TA0R                   TAR            /* Timer A Counter Register */
669 
#define TA0CCR0                TACCR0         /* Timer A Capture/Compare 0 */
670 
#define TA0CCR1                TACCR1         /* Timer A Capture/Compare 1 */
671 
#define TA0CCR2                TACCR2         /* Timer A Capture/Compare 2 */
672 
#define TA0IV_                 TAIV_          /* Timer A Interrupt Vector Word */
673 
#define TA0CTL_                TACTL_         /* Timer A Control */
674 
#define TA0CCTL0_              TACCTL0_       /* Timer A Capture/Compare Control 0 */
675 
#define TA0CCTL1_              TACCTL1_       /* Timer A Capture/Compare Control 1 */
676 
#define TA0CCTL2_              TACCTL2_       /* Timer A Capture/Compare Control 2 */
677 
#define TA0R_                  TAR_           /* Timer A Counter Register */
678 
#define TA0CCR0_               TACCR0_        /* Timer A Capture/Compare 0 */
679 
#define TA0CCR1_               TACCR1_        /* Timer A Capture/Compare 1 */
680 
#define TA0CCR2_               TACCR2_        /* Timer A Capture/Compare 2 */
681 
 
682 
#define TASSEL1                (0x0200)       /* Timer A clock source select 0 */
683 
#define TASSEL0                (0x0100)       /* Timer A clock source select 1 */
684 
#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
685 
#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
686 
#define MC1                    (0x0020)       /* Timer A mode control 1 */
687 
#define MC0                    (0x0010)       /* Timer A mode control 0 */
688 
#define TACLR                  (0x0004)       /* Timer A counter clear */
689 
#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
690 
#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
691 
 
692 
#define MC_0                   (0*0x10u)      /* Timer A mode control: 0 - Stop */
693 
#define MC_1                   (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
694 
#define MC_2                   (2*0x10u)      /* Timer A mode control: 2 - Continous up */
695 
#define MC_3                   (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
696 
#define ID_0                   (0*0x40u)      /* Timer A input divider: 0 - /1 */
697 
#define ID_1                   (1*0x40u)      /* Timer A input divider: 1 - /2 */
698 
#define ID_2                   (2*0x40u)      /* Timer A input divider: 2 - /4 */
699 
#define ID_3                   (3*0x40u)      /* Timer A input divider: 3 - /8 */
700 
#define TASSEL_0               (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
701 
#define TASSEL_1               (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
702 
#define TASSEL_2               (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
703 
#define TASSEL_3               (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
704 
 
705 
#define CM1                    (0x8000)       /* Capture mode 1 */
706 
#define CM0                    (0x4000)       /* Capture mode 0 */
707 
#define CCIS1                  (0x2000)       /* Capture input select 1 */
708 
#define CCIS0                  (0x1000)       /* Capture input select 0 */
709 
#define SCS                    (0x0800)       /* Capture sychronize */
710 
#define SCCI                   (0x0400)       /* Latched capture signal (read) */
711 
#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
712 
#define OUTMOD2                (0x0080)       /* Output mode 2 */
713 
#define OUTMOD1                (0x0040)       /* Output mode 1 */
714 
#define OUTMOD0                (0x0020)       /* Output mode 0 */
715 
#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
716 
#define CCI                    (0x0008)       /* Capture input signal (read) */
717 
#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
718 
#define COV                    (0x0002)       /* Capture/compare overflow flag */
719 
#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
720 
 
721 
#define OUTMOD_0               (0*0x20u)      /* PWM output mode: 0 - output only */
722 
#define OUTMOD_1               (1*0x20u)      /* PWM output mode: 1 - set */
723 
#define OUTMOD_2               (2*0x20u)      /* PWM output mode: 2 - PWM toggle/reset */
724 
#define OUTMOD_3               (3*0x20u)      /* PWM output mode: 3 - PWM set/reset */
725 
#define OUTMOD_4               (4*0x20u)      /* PWM output mode: 4 - toggle */
726 
#define OUTMOD_5               (5*0x20u)      /* PWM output mode: 5 - Reset */
727 
#define OUTMOD_6               (6*0x20u)      /* PWM output mode: 6 - PWM toggle/set */
728 
#define OUTMOD_7               (7*0x20u)      /* PWM output mode: 7 - PWM reset/set */
729 
#define CCIS_0                 (0*0x1000u)    /* Capture input select: 0 - CCIxA */
730 
#define CCIS_1                 (1*0x1000u)    /* Capture input select: 1 - CCIxB */
731 
#define CCIS_2                 (2*0x1000u)    /* Capture input select: 2 - GND */
732 
#define CCIS_3                 (3*0x1000u)    /* Capture input select: 3 - Vcc */
733 
#define CM_0                   (0*0x4000u)    /* Capture mode: 0 - disabled */
734 
#define CM_1                   (1*0x4000u)    /* Capture mode: 1 - pos. edge */
735 
#define CM_2                   (2*0x4000u)    /* Capture mode: 1 - neg. edge */
736 
#define CM_3                   (3*0x4000u)    /* Capture mode: 1 - both edges */
737 
 
738 
/* TA3IV Definitions */
739 
#define TAIV_NONE              (0x0000)       /* No Interrupt pending */
740 
#define TAIV_TACCR1            (0x0002)       /* TACCR1_CCIFG */
741 
#define TAIV_TACCR2            (0x0004)       /* TACCR2_CCIFG */
742 
#define TAIV_6                 (0x0006)       /* Reserved */
743 
#define TAIV_8                 (0x0008)       /* Reserved */
744 
#define TAIV_TAIFG             (0x000A)       /* TAIFG */
745 
 
746 
/************************************************************
747 
* Timer B3
748 
************************************************************/
749 
#define __MSP430_HAS_TB3__                    /* Definition to show that Module is available */
750 
 
751 
SFR_16BIT(TBIV);                              /* Timer B Interrupt Vector Word */
752 
SFR_16BIT(TBCTL);                             /* Timer B Control */
753 
SFR_16BIT(TBCCTL0);                           /* Timer B Capture/Compare Control 0 */
754 
SFR_16BIT(TBCCTL1);                           /* Timer B Capture/Compare Control 1 */
755 
SFR_16BIT(TBCCTL2);                           /* Timer B Capture/Compare Control 2 */
756 
SFR_16BIT(TBR);                               /* Timer B Counter Register */
757 
SFR_16BIT(TBCCR0);                            /* Timer B Capture/Compare 0 */
758 
SFR_16BIT(TBCCR1);                            /* Timer B Capture/Compare 1 */
759 
SFR_16BIT(TBCCR2);                            /* Timer B Capture/Compare 2 */
760 
 
761 
/* Alternate register names - 5xx style */
762 
#define TB0IV                  TBIV           /* Timer B Interrupt Vector Word */
763 
#define TB0CTL                 TBCTL          /* Timer B Control */
764 
#define TB0CCTL0               TBCCTL0        /* Timer B Capture/Compare Control 0 */
765 
#define TB0CCTL1               TBCCTL1        /* Timer B Capture/Compare Control 1 */
766 
#define TB0CCTL2               TBCCTL2        /* Timer B Capture/Compare Control 2 */
767 
#define TB0R                   TBR            /* Timer B Counter Register */
768 
#define TB0CCR0                TBCCR0         /* Timer B Capture/Compare 0 */
769 
#define TB0CCR1                TBCCR1         /* Timer B Capture/Compare 1 */
770 
#define TB0CCR2                TBCCR2         /* Timer B Capture/Compare 2 */
771 
#define TB0IV_                 TBIV_          /* Timer B Interrupt Vector Word */
772 
#define TB0CTL_                TBCTL_         /* Timer B Control */
773 
#define TB0CCTL0_              TBCCTL0_       /* Timer B Capture/Compare Control 0 */
774 
#define TB0CCTL1_              TBCCTL1_       /* Timer B Capture/Compare Control 1 */
775 
#define TB0CCTL2_              TBCCTL2_       /* Timer B Capture/Compare Control 2 */
776 
#define TB0R_                  TBR_           /* Timer B Counter Register */
777 
#define TB0CCR0_               TBCCR0_        /* Timer B Capture/Compare 0 */
778 
#define TB0CCR1_               TBCCR1_        /* Timer B Capture/Compare 1 */
779 
#define TB0CCR2_               TBCCR2_        /* Timer B Capture/Compare 2 */
780 
 
781 
#define TBCLGRP1               (0x4000)       /* Timer B Compare latch load group 1 */
782 
#define TBCLGRP0               (0x2000)       /* Timer B Compare latch load group 0 */
783 
#define CNTL1                  (0x1000)       /* Counter lenght 1 */
784 
#define CNTL0                  (0x0800)       /* Counter lenght 0 */
785 
#define TBSSEL1                (0x0200)       /* Clock source 1 */
786 
#define TBSSEL0                (0x0100)       /* Clock source 0 */
787 
#define TBCLR                  (0x0004)       /* Timer B counter clear */
788 
#define TBIE                   (0x0002)       /* Timer B interrupt enable */
789 
#define TBIFG                  (0x0001)       /* Timer B interrupt flag */
790 
 
791 
#define SHR1                   (0x4000)       /* Timer B Compare latch load group 1 */
792 
#define SHR0                   (0x2000)       /* Timer B Compare latch load group 0 */
793 
 
794 
#define TBSSEL_0               (0*0x0100u)    /* Clock Source: TBCLK */
795 
#define TBSSEL_1               (1*0x0100u)    /* Clock Source: ACLK  */
796 
#define TBSSEL_2               (2*0x0100u)    /* Clock Source: SMCLK */
797 
#define TBSSEL_3               (3*0x0100u)    /* Clock Source: INCLK */
798 
#define CNTL_0                 (0*0x0800u)    /* Counter lenght: 16 bit */
799 
#define CNTL_1                 (1*0x0800u)    /* Counter lenght: 12 bit */
800 
#define CNTL_2                 (2*0x0800u)    /* Counter lenght: 10 bit */
801 
#define CNTL_3                 (3*0x0800u)    /* Counter lenght:  8 bit */
802 
#define SHR_0                  (0*0x2000u)    /* Timer B Group: 0 - individually */
803 
#define SHR_1                  (1*0x2000u)    /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
804 
#define SHR_2                  (2*0x2000u)    /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
805 
#define SHR_3                  (3*0x2000u)    /* Timer B Group: 3 - 1 group (all) */
806 
#define TBCLGRP_0              (0*0x2000u)    /* Timer B Group: 0 - individually */
807 
#define TBCLGRP_1              (1*0x2000u)    /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
808 
#define TBCLGRP_2              (2*0x2000u)    /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
809 
#define TBCLGRP_3              (3*0x2000u)    /* Timer B Group: 3 - 1 group (all) */
810 
 
811 
/* Additional Timer B Control Register bits are defined in Timer A */
812 
 
813 
#define CLLD1                  (0x0400)       /* Compare latch load source 1 */
814 
#define CLLD0                  (0x0200)       /* Compare latch load source 0 */
815 
 
816 
#define SLSHR1                 (0x0400)       /* Compare latch load source 1 */
817 
#define SLSHR0                 (0x0200)       /* Compare latch load source 0 */
818 
 
819 
#define SLSHR_0                (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
820 
#define SLSHR_1                (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
821 
#define SLSHR_2                (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
822 
#define SLSHR_3                (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
823 
 
824 
#define CLLD_0                 (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
825 
#define CLLD_1                 (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
826 
#define CLLD_2                 (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
827 
#define CLLD_3                 (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
828 
 
829 
/* TB3IV Definitions */
830 
#define TBIV_NONE              (0x0000)       /* No Interrupt pending */
831 
#define TBIV_TBCCR1            (0x0002)       /* TBCCR1_CCIFG */
832 
#define TBIV_TBCCR2            (0x0004)       /* TBCCR2_CCIFG */
833 
#define TBIV_3                 (0x0006)       /* Reserved */
834 
#define TBIV_4                 (0x0008)       /* Reserved */
835 
#define TBIV_5                 (0x000A)       /* Reserved */
836 
#define TBIV_6                 (0x000C)       /* Reserved */
837 
#define TBIV_TBIFG             (0x000E)       /* TBIFG */
838 
 
839 
/************************************************************
840 
* USCI
841 
************************************************************/
842 
#define __MSP430_HAS_USCI__                   /* Definition to show that Module is available */
843 
 
844 
SFR_8BIT(UCA0CTL0);                           /* USCI A0 Control Register 0 */
845 
SFR_8BIT(UCA0CTL1);                           /* USCI A0 Control Register 1 */
846 
SFR_8BIT(UCA0BR0);                            /* USCI A0 Baud Rate 0 */
847 
SFR_8BIT(UCA0BR1);                            /* USCI A0 Baud Rate 1 */
848 
SFR_8BIT(UCA0MCTL);                           /* USCI A0 Modulation Control */
849 
SFR_8BIT(UCA0STAT);                           /* USCI A0 Status Register */
850 
SFR_8BIT(UCA0RXBUF);                          /* USCI A0 Receive Buffer */
851 
SFR_8BIT(UCA0TXBUF);                          /* USCI A0 Transmit Buffer */
852 
SFR_8BIT(UCA0ABCTL);                          /* USCI A0 LIN Control */
853 
SFR_8BIT(UCA0IRTCTL);                         /* USCI A0 IrDA Transmit Control */
854 
SFR_8BIT(UCA0IRRCTL);                         /* USCI A0 IrDA Receive Control */
855 
 
856 
 
857 
 
858 
SFR_8BIT(UCB0CTL0);                           /* USCI B0 Control Register 0 */
859 
SFR_8BIT(UCB0CTL1);                           /* USCI B0 Control Register 1 */
860 
SFR_8BIT(UCB0BR0);                            /* USCI B0 Baud Rate 0 */
861 
SFR_8BIT(UCB0BR1);                            /* USCI B0 Baud Rate 1 */
862 
SFR_8BIT(UCB0I2CIE);                          /* USCI B0 I2C Interrupt Enable Register */
863 
SFR_8BIT(UCB0STAT);                           /* USCI B0 Status Register */
864 
SFR_8BIT(UCB0RXBUF);                          /* USCI B0 Receive Buffer */
865 
SFR_8BIT(UCB0TXBUF);                          /* USCI B0 Transmit Buffer */
866 
SFR_16BIT(UCB0I2COA);                         /* USCI B0 I2C Own Address */
867 
SFR_16BIT(UCB0I2CSA);                         /* USCI B0 I2C Slave Address */
868 
 
869 
// UART-Mode Bits
870 
#define UCPEN                  (0x80)         /* Async. Mode: Parity enable */
871 
#define UCPAR                  (0x40)         /* Async. Mode: Parity     0:odd / 1:even */
872 
#define UCMSB                  (0x20)         /* Async. Mode: MSB first  0:LSB / 1:MSB */
873 
#define UC7BIT                 (0x10)         /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
874 
#define UCSPB                  (0x08)         /* Async. Mode: Stop Bits  0:one / 1: two */
875 
#define UCMODE1                (0x04)         /* Async. Mode: USCI Mode 1 */
876 
#define UCMODE0                (0x02)         /* Async. Mode: USCI Mode 0 */
877 
#define UCSYNC                 (0x01)         /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
878 
 
879 
// SPI-Mode Bits
880 
#define UCCKPH                 (0x80)         /* Sync. Mode: Clock Phase */
881 
#define UCCKPL                 (0x40)         /* Sync. Mode: Clock Polarity */
882 
#define UCMST                  (0x08)         /* Sync. Mode: Master Select */
883 
 
884 
// I2C-Mode Bits
885 
#define UCA10                  (0x80)         /* 10-bit Address Mode */
886 
#define UCSLA10                (0x40)         /* 10-bit Slave Address Mode */
887 
#define UCMM                   (0x20)         /* Multi-Master Environment */
888 
//#define res               (0x10)    /* reserved */
889 
#define UCMODE_0               (0x00)         /* Sync. Mode: USCI Mode: 0 */
890 
#define UCMODE_1               (0x02)         /* Sync. Mode: USCI Mode: 1 */
891 
#define UCMODE_2               (0x04)         /* Sync. Mode: USCI Mode: 2 */
892 
#define UCMODE_3               (0x06)         /* Sync. Mode: USCI Mode: 3 */
893 
 
894 
// UART-Mode Bits
895 
#define UCSSEL1                (0x80)         /* USCI 0 Clock Source Select 1 */
896 
#define UCSSEL0                (0x40)         /* USCI 0 Clock Source Select 0 */
897 
#define UCRXEIE                (0x20)         /* RX Error interrupt enable */
898 
#define UCBRKIE                (0x10)         /* Break interrupt enable */
899 
#define UCDORM                 (0x08)         /* Dormant (Sleep) Mode */
900 
#define UCTXADDR               (0x04)         /* Send next Data as Address */
901 
#define UCTXBRK                (0x02)         /* Send next Data as Break */
902 
#define UCSWRST                (0x01)         /* USCI Software Reset */
903 
 
904 
// SPI-Mode Bits
905 
//#define res               (0x20)    /* reserved */
906 
//#define res               (0x10)    /* reserved */
907 
//#define res               (0x08)    /* reserved */
908 
//#define res               (0x04)    /* reserved */
909 
//#define res               (0x02)    /* reserved */
910 
 
911 
// I2C-Mode Bits
912 
//#define res               (0x20)    /* reserved */
913 
#define UCTR                   (0x10)         /* Transmit/Receive Select/Flag */
914 
#define UCTXNACK               (0x08)         /* Transmit NACK */
915 
#define UCTXSTP                (0x04)         /* Transmit STOP */
916 
#define UCTXSTT                (0x02)         /* Transmit START */
917 
#define UCSSEL_0               (0x00)         /* USCI 0 Clock Source: 0 */
918 
#define UCSSEL_1               (0x40)         /* USCI 0 Clock Source: 1 */
919 
#define UCSSEL_2               (0x80)         /* USCI 0 Clock Source: 2 */
920 
#define UCSSEL_3               (0xC0)         /* USCI 0 Clock Source: 3 */
921 
 
922 
#define UCBRF3                 (0x80)         /* USCI First Stage Modulation Select 3 */
923 
#define UCBRF2                 (0x40)         /* USCI First Stage Modulation Select 2 */
924 
#define UCBRF1                 (0x20)         /* USCI First Stage Modulation Select 1 */
925 
#define UCBRF0                 (0x10)         /* USCI First Stage Modulation Select 0 */
926 
#define UCBRS2                 (0x08)         /* USCI Second Stage Modulation Select 2 */
927 
#define UCBRS1                 (0x04)         /* USCI Second Stage Modulation Select 1 */
928 
#define UCBRS0                 (0x02)         /* USCI Second Stage Modulation Select 0 */
929 
#define UCOS16                 (0x01)         /* USCI 16-times Oversampling enable */
930 
 
931 
#define UCBRF_0                (0x00)         /* USCI First Stage Modulation: 0 */
932 
#define UCBRF_1                (0x10)         /* USCI First Stage Modulation: 1 */
933 
#define UCBRF_2                (0x20)         /* USCI First Stage Modulation: 2 */
934 
#define UCBRF_3                (0x30)         /* USCI First Stage Modulation: 3 */
935 
#define UCBRF_4                (0x40)         /* USCI First Stage Modulation: 4 */
936 
#define UCBRF_5                (0x50)         /* USCI First Stage Modulation: 5 */
937 
#define UCBRF_6                (0x60)         /* USCI First Stage Modulation: 6 */
938 
#define UCBRF_7                (0x70)         /* USCI First Stage Modulation: 7 */
939 
#define UCBRF_8                (0x80)         /* USCI First Stage Modulation: 8 */
940 
#define UCBRF_9                (0x90)         /* USCI First Stage Modulation: 9 */
941 
#define UCBRF_10               (0xA0)         /* USCI First Stage Modulation: A */
942 
#define UCBRF_11               (0xB0)         /* USCI First Stage Modulation: B */
943 
#define UCBRF_12               (0xC0)         /* USCI First Stage Modulation: C */
944 
#define UCBRF_13               (0xD0)         /* USCI First Stage Modulation: D */
945 
#define UCBRF_14               (0xE0)         /* USCI First Stage Modulation: E */
946 
#define UCBRF_15               (0xF0)         /* USCI First Stage Modulation: F */
947 
 
948 
#define UCBRS_0                (0x00)         /* USCI Second Stage Modulation: 0 */
949 
#define UCBRS_1                (0x02)         /* USCI Second Stage Modulation: 1 */
950 
#define UCBRS_2                (0x04)         /* USCI Second Stage Modulation: 2 */
951 
#define UCBRS_3                (0x06)         /* USCI Second Stage Modulation: 3 */
952 
#define UCBRS_4                (0x08)         /* USCI Second Stage Modulation: 4 */
953 
#define UCBRS_5                (0x0A)         /* USCI Second Stage Modulation: 5 */
954 
#define UCBRS_6                (0x0C)         /* USCI Second Stage Modulation: 6 */
955 
#define UCBRS_7                (0x0E)         /* USCI Second Stage Modulation: 7 */
956 
 
957 
#define UCLISTEN               (0x80)         /* USCI Listen mode */
958 
#define UCFE                   (0x40)         /* USCI Frame Error Flag */
959 
#define UCOE                   (0x20)         /* USCI Overrun Error Flag */
960 
#define UCPE                   (0x10)         /* USCI Parity Error Flag */
961 
#define UCBRK                  (0x08)         /* USCI Break received */
962 
#define UCRXERR                (0x04)         /* USCI RX Error Flag */
963 
#define UCADDR                 (0x02)         /* USCI Address received Flag */
964 
#define UCBUSY                 (0x01)         /* USCI Busy Flag */
965 
#define UCIDLE                 (0x02)         /* USCI Idle line detected Flag */
966 
 
967 
//#define res               (0x80)    /* reserved */
968 
//#define res               (0x40)    /* reserved */
969 
//#define res               (0x20)    /* reserved */
970 
//#define res               (0x10)    /* reserved */
971 
#define UCNACKIE               (0x08)         /* NACK Condition interrupt enable */
972 
#define UCSTPIE                (0x04)         /* STOP Condition interrupt enable */
973 
#define UCSTTIE                (0x02)         /* START Condition interrupt enable */
974 
#define UCALIE                 (0x01)         /* Arbitration Lost interrupt enable */
975 
 
976 
#define UCSCLLOW               (0x40)         /* SCL low */
977 
#define UCGC                   (0x20)         /* General Call address received Flag */
978 
#define UCBBUSY                (0x10)         /* Bus Busy Flag */
979 
#define UCNACKIFG              (0x08)         /* NAK Condition interrupt Flag */
980 
#define UCSTPIFG               (0x04)         /* STOP Condition interrupt Flag */
981 
#define UCSTTIFG               (0x02)         /* START Condition interrupt Flag */
982 
#define UCALIFG                (0x01)         /* Arbitration Lost interrupt Flag */
983 
 
984 
#define UCIRTXPL5              (0x80)         /* IRDA Transmit Pulse Length 5 */
985 
#define UCIRTXPL4              (0x40)         /* IRDA Transmit Pulse Length 4 */
986 
#define UCIRTXPL3              (0x20)         /* IRDA Transmit Pulse Length 3 */
987 
#define UCIRTXPL2              (0x10)         /* IRDA Transmit Pulse Length 2 */
988 
#define UCIRTXPL1              (0x08)         /* IRDA Transmit Pulse Length 1 */
989 
#define UCIRTXPL0              (0x04)         /* IRDA Transmit Pulse Length 0 */
990 
#define UCIRTXCLK              (0x02)         /* IRDA Transmit Pulse Clock Select */
991 
#define UCIREN                 (0x01)         /* IRDA Encoder/Decoder enable */
992 
 
993 
#define UCIRRXFL5              (0x80)         /* IRDA Receive Filter Length 5 */
994 
#define UCIRRXFL4              (0x40)         /* IRDA Receive Filter Length 4 */
995 
#define UCIRRXFL3              (0x20)         /* IRDA Receive Filter Length 3 */
996 
#define UCIRRXFL2              (0x10)         /* IRDA Receive Filter Length 2 */
997 
#define UCIRRXFL1              (0x08)         /* IRDA Receive Filter Length 1 */
998 
#define UCIRRXFL0              (0x04)         /* IRDA Receive Filter Length 0 */
999 
#define UCIRRXPL               (0x02)         /* IRDA Receive Input Polarity */
1000 
#define UCIRRXFE               (0x01)         /* IRDA Receive Filter enable */
1001 
 
1002 
//#define res               (0x80)    /* reserved */
1003 
//#define res               (0x40)    /* reserved */
1004 
#define UCDELIM1               (0x20)         /* Break Sync Delimiter 1 */
1005 
#define UCDELIM0               (0x10)         /* Break Sync Delimiter 0 */
1006 
#define UCSTOE                 (0x08)         /* Sync-Field Timeout error */
1007 
#define UCBTOE                 (0x04)         /* Break Timeout error */
1008 
//#define res               (0x02)    /* reserved */
1009 
#define UCABDEN                (0x01)         /* Auto Baud Rate detect enable */
1010 
 
1011 
#define UCGCEN                 (0x8000)       /* I2C General Call enable */
1012 
#define UCOA9                  (0x0200)       /* I2C Own Address 9 */
1013 
#define UCOA8                  (0x0100)       /* I2C Own Address 8 */
1014 
#define UCOA7                  (0x0080)       /* I2C Own Address 7 */
1015 
#define UCOA6                  (0x0040)       /* I2C Own Address 6 */
1016 
#define UCOA5                  (0x0020)       /* I2C Own Address 5 */
1017 
#define UCOA4                  (0x0010)       /* I2C Own Address 4 */
1018 
#define UCOA3                  (0x0008)       /* I2C Own Address 3 */
1019 
#define UCOA2                  (0x0004)       /* I2C Own Address 2 */
1020 
#define UCOA1                  (0x0002)       /* I2C Own Address 1 */
1021 
#define UCOA0                  (0x0001)       /* I2C Own Address 0 */
1022 
 
1023 
#define UCSA9                  (0x0200)       /* I2C Slave Address 9 */
1024 
#define UCSA8                  (0x0100)       /* I2C Slave Address 8 */
1025 
#define UCSA7                  (0x0080)       /* I2C Slave Address 7 */
1026 
#define UCSA6                  (0x0040)       /* I2C Slave Address 6 */
1027 
#define UCSA5                  (0x0020)       /* I2C Slave Address 5 */
1028 
#define UCSA4                  (0x0010)       /* I2C Slave Address 4 */
1029 
#define UCSA3                  (0x0008)       /* I2C Slave Address 3 */
1030 
#define UCSA2                  (0x0004)       /* I2C Slave Address 2 */
1031 
#define UCSA1                  (0x0002)       /* I2C Slave Address 1 */
1032 
#define UCSA0                  (0x0001)       /* I2C Slave Address 0 */
1033 
 
1034 
/************************************************************
1035 
* WATCHDOG TIMER
1036 
************************************************************/
1037 
#define __MSP430_HAS_WDT__                    /* Definition to show that Module is available */
1038 
 
1039 
SFR_16BIT(WDTCTL);                            /* Watchdog Timer Control */
1040 
/* The bit names have been prefixed with "WDT" */
1041 
#define WDTIS0                 (0x0001)
1042 
#define WDTIS1                 (0x0002)
1043 
#define WDTSSEL                (0x0004)
1044 
#define WDTCNTCL               (0x0008)
1045 
#define WDTTMSEL               (0x0010)
1046 
#define WDTNMI                 (0x0020)
1047 
#define WDTNMIES               (0x0040)
1048 
#define WDTHOLD                (0x0080)
1049 
 
1050 
#define WDTPW                  (0x5A00)
1051 
 
1052 
/* WDT-interval times [1ms] coded with Bits 0-2 */
1053 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
1054 
#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL)                         /* 32ms interval (default) */
1055 
#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0)                  /* 8ms     " */
1056 
#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1)                  /* 0.5ms   " */
1057 
#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0)           /* 0.064ms " */
1058 
/* WDT is clocked by fACLK (assumed 32KHz) */
1059 
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)                 /* 1000ms  " */
1060 
#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0)          /* 250ms   " */
1061 
#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1)          /* 16ms    " */
1062 
#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)   /* 1.9ms   " */
1063 
/* Watchdog mode -> reset after expired time */
1064 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
1065 
#define WDT_MRST_32         (WDTPW+WDTCNTCL)                                  /* 32ms interval (default) */
1066 
#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS0)                           /* 8ms     " */
1067 
#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS1)                           /* 0.5ms   " */
1068 
#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS1+WDTIS0)                    /* 0.064ms " */
1069 
/* WDT is clocked by fACLK (assumed 32KHz) */
1070 
#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL)                          /* 1000ms  " */
1071 
#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0)                   /* 250ms   " */
1072 
#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1)                   /* 16ms    " */
1073 
#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)            /* 1.9ms   " */
1074 
 
1075 
/* INTERRUPT CONTROL */
1076 
/* These two bits are defined in the Special Function Registers */
1077 
/* #define WDTIE               0x01 */
1078 
/* #define WDTIFG              0x01 */
1079 
 
1080 
/************************************************************
1081 
* Calibration Data in Info Mem
1082 
************************************************************/
1083 
 
1084 
/* TLV Calibration Data Structure */
1085 
#define TAG_DCO_30             (0x01)         /* Tag for DCO30  Calibration Data */
1086 
#define TAG_ADC12_1            (0x08)         /* Tag for ADC12_1 Calibration Data */
1087 
#define TAG_EMPTY              (0xFE)         /* Tag for Empty Data Field in Calibration Data */
1088 
 
1089 
#ifndef __DisableCalData
1090 
SFR_16BIT(TLV_CHECKSUM);                      /* TLV CHECK SUM */
1091 
SFR_8BIT(TLV_DCO_30_TAG);                     /* TLV TAG_DCO30 TAG */
1092 
SFR_8BIT(TLV_DCO_30_LEN);                     /* TLV TAG_DCO30 LEN */
1093 
SFR_8BIT(TLV_ADC12_1_TAG);                    /* TLV ADC12_1 TAG */
1094 
SFR_8BIT(TLV_ADC12_1_LEN);                    /* TLV ADC12_1 LEN */
1095 
#endif
1096 
 
1097 
#define CAL_ADC_25T85          (0x0007)       /* Index for 2.5V/85Deg Cal. Value */
1098 
#define CAL_ADC_25T30          (0x0006)       /* Index for 2.5V/30Deg Cal. Value */
1099 
#define CAL_ADC_25VREF_FACTOR  (0x0005)       /* Index for 2.5V Ref. Factor */
1100 
#define CAL_ADC_15T85          (0x0004)       /* Index for 1.5V/85Deg Cal. Value */
1101 
#define CAL_ADC_15T30          (0x0003)       /* Index for 1.5V/30Deg Cal. Value */
1102 
#define CAL_ADC_15VREF_FACTOR  (0x0002)       /* Index for ADC 1.5V Ref. Factor */
1103 
#define CAL_ADC_OFFSET         (0x0001)       /* Index for ADC Offset */
1104 
#define CAL_ADC_GAIN_FACTOR    (0x0000)       /* Index for ADC Gain Factor */
1105 
 
1106 
#define CAL_DCO_16MHZ          (0x0000)       /* Index for DCOCTL  Calibration Data for 16MHz */
1107 
#define CAL_BC1_16MHZ          (0x0001)       /* Index for BCSCTL1 Calibration Data for 16MHz */
1108 
#define CAL_DCO_12MHZ          (0x0002)       /* Index for DCOCTL  Calibration Data for 12MHz */
1109 
#define CAL_BC1_12MHZ          (0x0003)       /* Index for BCSCTL1 Calibration Data for 12MHz */
1110 
#define CAL_DCO_8MHZ           (0x0004)       /* Index for DCOCTL  Calibration Data for 8MHz */
1111 
#define CAL_BC1_8MHZ           (0x0005)       /* Index for BCSCTL1 Calibration Data for 8MHz */
1112 
#define CAL_DCO_1MHZ           (0x0006)       /* Index for DCOCTL  Calibration Data for 1MHz */
1113 
#define CAL_BC1_1MHZ           (0x0007)       /* Index for BCSCTL1 Calibration Data for 1MHz */
1114 
 
1115 
 
1116 
/************************************************************
1117 
* Calibration Data in Info Mem
1118 
************************************************************/
1119 
 
1120 
#ifndef __DisableCalData
1121 
 
1122 
SFR_8BIT(CALDCO_16MHZ);                       /* DCOCTL  Calibration Data for 16MHz */
1123 
SFR_8BIT(CALBC1_16MHZ);                       /* BCSCTL1 Calibration Data for 16MHz */
1124 
SFR_8BIT(CALDCO_12MHZ);                       /* DCOCTL  Calibration Data for 12MHz */
1125 
SFR_8BIT(CALBC1_12MHZ);                       /* BCSCTL1 Calibration Data for 12MHz */
1126 
SFR_8BIT(CALDCO_8MHZ);                        /* DCOCTL  Calibration Data for 8MHz */
1127 
SFR_8BIT(CALBC1_8MHZ);                        /* BCSCTL1 Calibration Data for 8MHz */
1128 
SFR_8BIT(CALDCO_1MHZ);                        /* DCOCTL  Calibration Data for 1MHz */
1129 
SFR_8BIT(CALBC1_1MHZ);                        /* BCSCTL1 Calibration Data for 1MHz */
1130 
 
1131 
#endif /* #ifndef __DisableCalData */
1132 
 
1133 
/************************************************************
1134 
* Interrupt Vectors (offset from 0xFFE0)
1135 
************************************************************/
1136 
 
1137 
#define VECTOR_NAME(name)       name##_ptr
1138 
#define EMIT_PRAGMA(x)          _Pragma(#x)
1139 
#define CREATE_VECTOR(name)     void (* const VECTOR_NAME(name))(void) = &name
1140 
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
1141 
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
1142 
                                PLACE_VECTOR(VECTOR_NAME(func), offset)
1143 
 
1144 
 
1145 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1146 
#define PORT1_VECTOR            ".int02"                    /* 0xFFE4 Port 1 */
1147 
#else
1148 
#define PORT1_VECTOR            (2 * 1u)                     /* 0xFFE4 Port 1 */
1149 
/*#define PORT1_ISR(func)         ISR_VECTOR(func, ".int02")  */ /* 0xFFE4 Port 1 */ /* CCE V2 Style */
1150 
#endif
1151 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1152 
#define PORT2_VECTOR            ".int03"                    /* 0xFFE6 Port 2 */
1153 
#else
1154 
#define PORT2_VECTOR            (3 * 1u)                     /* 0xFFE6 Port 2 */
1155 
/*#define PORT2_ISR(func)         ISR_VECTOR(func, ".int03")  */ /* 0xFFE6 Port 2 */ /* CCE V2 Style */
1156 
#endif
1157 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1158 
#define ADC12_VECTOR            ".int05"                    /* 0xFFEA ADC */
1159 
#else
1160 
#define ADC12_VECTOR            (5 * 1u)                     /* 0xFFEA ADC */
1161 
/*#define ADC12_ISR(func)         ISR_VECTOR(func, ".int05")  */ /* 0xFFEA ADC */ /* CCE V2 Style */
1162 
#endif
1163 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1164 
#define USCIAB0TX_VECTOR        ".int06"                    /* 0xFFEC USCI A0/B0 Transmit */
1165 
#else
1166 
#define USCIAB0TX_VECTOR        (6 * 1u)                     /* 0xFFEC USCI A0/B0 Transmit */
1167 
/*#define USCIAB0TX_ISR(func)     ISR_VECTOR(func, ".int06")  */ /* 0xFFEC USCI A0/B0 Transmit */ /* CCE V2 Style */
1168 
#endif
1169 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1170 
#define USCIAB0RX_VECTOR        ".int07"                    /* 0xFFEE USCI A0/B0 Receive */
1171 
#else
1172 
#define USCIAB0RX_VECTOR        (7 * 1u)                     /* 0xFFEE USCI A0/B0 Receive */
1173 
/*#define USCIAB0RX_ISR(func)     ISR_VECTOR(func, ".int07")  */ /* 0xFFEE USCI A0/B0 Receive */ /* CCE V2 Style */
1174 
#endif
1175 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1176 
#define TIMERA1_VECTOR          ".int08"                    /* 0xFFF0 Timer A CC1-2, TA */
1177 
#else
1178 
#define TIMERA1_VECTOR          (8 * 1u)                     /* 0xFFF0 Timer A CC1-2, TA */
1179 
/*#define TIMERA1_ISR(func)       ISR_VECTOR(func, ".int08")  */ /* 0xFFF0 Timer A CC1-2, TA */ /* CCE V2 Style */
1180 
#endif
1181 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1182 
#define TIMERA0_VECTOR          ".int09"                    /* 0xFFF2 Timer A CC0 */
1183 
#else
1184 
#define TIMERA0_VECTOR          (9 * 1u)                     /* 0xFFF2 Timer A CC0 */
1185 
/*#define TIMERA0_ISR(func)       ISR_VECTOR(func, ".int09")  */ /* 0xFFF2 Timer A CC0 */ /* CCE V2 Style */
1186 
#endif
1187 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1188 
#define WDT_VECTOR              ".int10"                    /* 0xFFF4 Watchdog Timer */
1189 
#else
1190 
#define WDT_VECTOR              (10 * 1u)                    /* 0xFFF4 Watchdog Timer */
1191 
/*#define WDT_ISR(func)           ISR_VECTOR(func, ".int10")  */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
1192 
#endif
1193 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1194 
#define COMPARATORA_VECTOR      ".int11"                    /* 0xFFF6 Comparator A */
1195 
#else
1196 
#define COMPARATORA_VECTOR      (11 * 1u)                    /* 0xFFF6 Comparator A */
1197 
/*#define COMPARATORA_ISR(func)   ISR_VECTOR(func, ".int11")  */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */
1198 
#endif
1199 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1200 
#define TIMERB1_VECTOR          ".int12"                    /* 0xFFF8 Timer B CC1-6, TB */
1201 
#else
1202 
#define TIMERB1_VECTOR          (12 * 1u)                    /* 0xFFF8 Timer B CC1-6, TB */
1203 
/*#define TIMERB1_ISR(func)       ISR_VECTOR(func, ".int12")  */ /* 0xFFF8 Timer B CC1-6, TB */ /* CCE V2 Style */
1204 
#endif
1205 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1206 
#define TIMERB0_VECTOR          ".int13"                    /* 0xFFFA Timer B CC0 */
1207 
#else
1208 
#define TIMERB0_VECTOR          (13 * 1u)                    /* 0xFFFA Timer B CC0 */
1209 
/*#define TIMERB0_ISR(func)       ISR_VECTOR(func, ".int13")  */ /* 0xFFFA Timer B CC0 */ /* CCE V2 Style */
1210 
#endif
1211 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1212 
#define NMI_VECTOR              ".int14"                    /* 0xFFFC Non-maskable */
1213 
#else
1214 
#define NMI_VECTOR              (14 * 1u)                    /* 0xFFFC Non-maskable */
1215 
/*#define NMI_ISR(func)           ISR_VECTOR(func, ".int14")  */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
1216 
#endif
1217 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1218 
#define RESET_VECTOR            ".reset"                    /* 0xFFFE Reset [Highest Priority] */
1219 
#else
1220 
#define RESET_VECTOR            (15 * 1u)                    /* 0xFFFE Reset [Highest Priority] */
1221 
/*#define RESET_ISR(func)         ISR_VECTOR(func, ".int15")  */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
1222 
#endif
1223 
 
1224 
/************************************************************
1225 
* End of Modules
1226 
************************************************************/
1227 
 
1228 
#ifdef __cplusplus
1229 
}
1230 
#endif /* extern "C" */
1231 
 
1232 
#endif /* #ifndef __msp430x23x */
1233