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/******************************************************************************/
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/* Legacy Header File */
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/* Not recommended for use in new projects. */
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/* Please use the msp430.h file or the device specific header file */
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/******************************************************************************/
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* MSP430x22x4 devices.
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*
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* Texas Instruments, Version 1.5
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*
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* Rev. 1.0, Setup
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* Rev. 1.1, Updated names for USCI
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* Rev. 1.2, Added missing definitions in OA and ADC10
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* Rev. 1.3 Removed bit definitions for ADC10AEx as this are in conflict with ADC10AEx Register
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* Removed not existing SWCTL register definition
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* Rev. 1.4, added definitions for Interrupt Vectors xxIV
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* Rev. 1.5, Fixed typo in ADC10: SREF3 -> SREF2
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*
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********************************************************************/
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#ifndef __msp430x22x4
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#define __msp430x22x4
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
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************************************************************/
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SFR_8BIT(IE1); /* Interrupt Enable 1 */
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#define WDTIE (0x01) /* Watchdog Interrupt Enable */
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#define OFIE (0x02) /* Osc. Fault Interrupt Enable */
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#define NMIIE (0x10) /* NMI Interrupt Enable */
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#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */
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SFR_8BIT(IFG1); /* Interrupt Flag 1 */
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#define WDTIFG (0x01) /* Watchdog Interrupt Flag */
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#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */
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#define PORIFG (0x04) /* Power On Interrupt Flag */
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#define RSTIFG (0x08) /* Reset Interrupt Flag */
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#define NMIIFG (0x10) /* NMI Interrupt Flag */
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SFR_8BIT(IE2); /* Interrupt Enable 2 */
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#define UC0IE IE2
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#define UCA0RXIE (0x01)
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#define UCA0TXIE (0x02)
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#define UCB0RXIE (0x04)
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#define UCB0TXIE (0x08)
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SFR_8BIT(IFG2); /* Interrupt Flag 2 */
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#define UC0IFG IFG2
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#define UCA0RXIFG (0x01)
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#define UCA0TXIFG (0x02)
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#define UCB0RXIFG (0x04)
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#define UCB0TXIFG (0x08)
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/************************************************************
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* ADC10
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************************************************************/
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#define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */
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SFR_8BIT(ADC10DTC0); /* ADC10 Data Transfer Control 0 */
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SFR_8BIT(ADC10DTC1); /* ADC10 Data Transfer Control 1 */
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SFR_8BIT(ADC10AE0); /* ADC10 Analog Enable 0 */
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SFR_8BIT(ADC10AE1); /* ADC10 Analog Enable 1 */
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SFR_16BIT(ADC10CTL0); /* ADC10 Control 0 */
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SFR_16BIT(ADC10CTL1); /* ADC10 Control 1 */
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SFR_16BIT(ADC10MEM); /* ADC10 Memory */
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SFR_16BIT(ADC10SA); /* ADC10 Data Transfer Start Address */
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/* ADC10CTL0 */
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#define ADC10SC (0x001) /* ADC10 Start Conversion */
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#define ENC (0x002) /* ADC10 Enable Conversion */
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#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */
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#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */
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#define ADC10ON (0x010) /* ADC10 On/Enable */
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#define REFON (0x020) /* ADC10 Reference on */
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#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */
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#define MSC (0x080) /* ADC10 Multiple SampleConversion */
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#define REFBURST (0x100) /* ADC10 Reference Burst Mode */
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#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */
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#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */
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#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */
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#define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select Bit: 1 */
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#define SREF0 (0x2000) /* ADC10 Reference Select Bit: 0 */
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#define SREF1 (0x4000) /* ADC10 Reference Select Bit: 1 */
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#define SREF2 (0x8000) /* ADC10 Reference Select Bit: 2 */
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#define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */
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#define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */
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#define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */
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#define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */
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#define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */
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#define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */
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#define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
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#define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
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#define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */
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#define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */
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#define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
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#define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
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/* ADC10CTL1 */
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#define ADC10BUSY (0x0001) /* ADC10 BUSY */
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#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */
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#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */
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#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select Bit: 0 */
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#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select Bit: 1 */
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#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select Bit: 0 */
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#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select Bit: 1 */
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#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select Bit: 2 */
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#define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */
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#define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */
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#define SHS0 (0x0400) /* ADC10 Sample/Hold Source Bit: 0 */
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#define SHS1 (0x0800) /* ADC10 Sample/Hold Source Bit: 1 */
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#define INCH0 (0x1000) /* ADC10 Input Channel Select Bit: 0 */
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#define INCH1 (0x2000) /* ADC10 Input Channel Select Bit: 1 */
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#define INCH2 (0x4000) /* ADC10 Input Channel Select Bit: 2 */
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#define INCH3 (0x8000) /* ADC10 Input Channel Select Bit: 3 */
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#define CONSEQ_0 (0*2u) /* Single channel single conversion */
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#define CONSEQ_1 (1*2u) /* Sequence of channels */
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#define CONSEQ_2 (2*2u) /* Repeat single channel */
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#define CONSEQ_3 (3*2u) /* Repeat sequence of channels */
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#define ADC10SSEL_0 (0*8u) /* ADC10OSC */
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#define ADC10SSEL_1 (1*8u) /* ACLK */
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#define ADC10SSEL_2 (2*8u) /* MCLK */
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#define ADC10SSEL_3 (3*8u) /* SMCLK */
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#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */
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#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select 1 */
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#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select 2 */
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#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select 3 */
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#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select 4 */
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#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select 5 */
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#define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select 6 */
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#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select 7 */
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#define SHS_0 (0*0x400u) /* ADC10SC */
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#define SHS_1 (1*0x400u) /* TA3 OUT1 */
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#define SHS_2 (2*0x400u) /* TA3 OUT0 */
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#define SHS_3 (3*0x400u) /* TA3 OUT2 */
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#define INCH_0 (0*0x1000u) /* Selects Channel 0 */
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#define INCH_1 (1*0x1000u) /* Selects Channel 1 */
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#define INCH_2 (2*0x1000u) /* Selects Channel 2 */
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#define INCH_3 (3*0x1000u) /* Selects Channel 3 */
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#define INCH_4 (4*0x1000u) /* Selects Channel 4 */
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#define INCH_5 (5*0x1000u) /* Selects Channel 5 */
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#define INCH_6 (6*0x1000u) /* Selects Channel 6 */
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#define INCH_7 (7*0x1000u) /* Selects Channel 7 */
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#define INCH_8 (8*0x1000u) /* Selects Channel 8 */
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#define INCH_9 (9*0x1000u) /* Selects Channel 9 */
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#define INCH_10 (10*0x1000u) /* Selects Channel 10 */
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#define INCH_11 (11*0x1000u) /* Selects Channel 11 */
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#define INCH_12 (12*0x1000u) /* Selects Channel 12 */
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#define INCH_13 (13*0x1000u) /* Selects Channel 13 */
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#define INCH_14 (14*0x1000u) /* Selects Channel 14 */
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#define INCH_15 (15*0x1000u) /* Selects Channel 15 */
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/* ADC10DTC0 */
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#define ADC10FETCH (0x001) /* This bit should normally be reset */
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#define ADC10B1 (0x002) /* ADC10 block one */
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#define ADC10CT (0x004) /* ADC10 continuous transfer */
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#define ADC10TB (0x008) /* ADC10 two-block mode */
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#define ADC10DISABLE (0x000) /* ADC10DTC1 */
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/************************************************************
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* Basic Clock Module
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************************************************************/
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#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */
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SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */
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SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */
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SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */
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SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */
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#define MOD0 (0x01) /* Modulation Bit 0 */
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#define MOD1 (0x02) /* Modulation Bit 1 */
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#define MOD2 (0x04) /* Modulation Bit 2 */
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#define MOD3 (0x08) /* Modulation Bit 3 */
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#define MOD4 (0x10) /* Modulation Bit 4 */
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#define DCO0 (0x20) /* DCO Select Bit 0 */
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#define DCO1 (0x40) /* DCO Select Bit 1 */
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#define DCO2 (0x80) /* DCO Select Bit 2 */
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#define RSEL0 (0x01) /* Range Select Bit 0 */
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#define RSEL1 (0x02) /* Range Select Bit 1 */
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#define RSEL2 (0x04) /* Range Select Bit 2 */
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#define RSEL3 (0x08) /* Range Select Bit 3 */
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#define DIVA0 (0x10) /* ACLK Divider 0 */
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#define DIVA1 (0x20) /* ACLK Divider 1 */
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#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */
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#define XT2OFF (0x80) /* Enable XT2CLK */
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#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */
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#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */
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#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */
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#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */
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#define DCOR (0x01) /* Enable External Resistor : 1 */
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291 |
#define DIVS0 (0x02) /* SMCLK Divider 0 */
|
|
|
292 |
#define DIVS1 (0x04) /* SMCLK Divider 1 */
|
|
|
293 |
#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
|
|
|
294 |
#define DIVM0 (0x10) /* MCLK Divider 0 */
|
|
|
295 |
#define DIVM1 (0x20) /* MCLK Divider 1 */
|
|
|
296 |
#define SELM0 (0x40) /* MCLK Source Select 0 */
|
|
|
297 |
#define SELM1 (0x80) /* MCLK Source Select 1 */
|
|
|
298 |
|
|
|
299 |
#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */
|
|
|
300 |
#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */
|
|
|
301 |
#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */
|
|
|
302 |
#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */
|
|
|
303 |
|
|
|
304 |
#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */
|
|
|
305 |
#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */
|
|
|
306 |
#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */
|
|
|
307 |
#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */
|
|
|
308 |
|
|
|
309 |
#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */
|
|
|
310 |
#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */
|
|
|
311 |
#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
|
|
|
312 |
#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */
|
|
|
313 |
|
|
|
314 |
#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */
|
|
|
315 |
#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */
|
|
|
316 |
#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */
|
|
|
317 |
#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */
|
|
|
318 |
#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */
|
|
|
319 |
#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */
|
|
|
320 |
#define XT2S0 (0x40) /* Mode 0 for XT2 */
|
|
|
321 |
#define XT2S1 (0x80) /* Mode 1 for XT2 */
|
|
|
322 |
|
|
|
323 |
#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */
|
|
|
324 |
#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */
|
|
|
325 |
#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */
|
|
|
326 |
#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */
|
|
|
327 |
|
|
|
328 |
#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */
|
|
|
329 |
#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */
|
|
|
330 |
#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */
|
|
|
331 |
#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */
|
|
|
332 |
|
|
|
333 |
#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */
|
|
|
334 |
#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */
|
|
|
335 |
#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */
|
|
|
336 |
#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */
|
|
|
337 |
|
|
|
338 |
/*************************************************************
|
|
|
339 |
* Flash Memory
|
|
|
340 |
*************************************************************/
|
|
|
341 |
#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */
|
|
|
342 |
|
|
|
343 |
SFR_16BIT(FCTL1); /* FLASH Control 1 */
|
|
|
344 |
SFR_16BIT(FCTL2); /* FLASH Control 2 */
|
|
|
345 |
SFR_16BIT(FCTL3); /* FLASH Control 3 */
|
|
|
346 |
|
|
|
347 |
#define FRKEY (0x9600) /* Flash key returned by read */
|
|
|
348 |
#define FWKEY (0xA500) /* Flash key for write */
|
|
|
349 |
#define FXKEY (0x3300) /* for use with XOR instruction */
|
|
|
350 |
|
|
|
351 |
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
|
|
|
352 |
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
|
|
|
353 |
#define EEI (0x0008) /* Enable Erase Interrupts */
|
|
|
354 |
#define EEIEX (0x0010) /* Enable Emergency Interrupt Exit */
|
|
|
355 |
#define WRT (0x0040) /* Enable bit for Flash write */
|
|
|
356 |
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
|
|
|
357 |
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
|
|
|
358 |
|
|
|
359 |
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
|
|
|
360 |
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
|
|
|
361 |
#ifndef FN2
|
|
|
362 |
#define FN2 (0x0004)
|
|
|
363 |
#endif
|
|
|
364 |
#ifndef FN3
|
|
|
365 |
#define FN3 (0x0008)
|
|
|
366 |
#endif
|
|
|
367 |
#ifndef FN4
|
|
|
368 |
#define FN4 (0x0010)
|
|
|
369 |
#endif
|
|
|
370 |
#define FN5 (0x0020)
|
|
|
371 |
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
|
|
|
372 |
#define FSSEL1 (0x0080) /* Flash clock select 1 */
|
|
|
373 |
|
|
|
374 |
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
|
|
|
375 |
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
|
|
|
376 |
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
|
|
|
377 |
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
|
|
|
378 |
|
|
|
379 |
#define BUSY (0x0001) /* Flash busy: 1 */
|
|
|
380 |
#define KEYV (0x0002) /* Flash Key violation flag */
|
|
|
381 |
#define ACCVIFG (0x0004) /* Flash Access violation flag */
|
|
|
382 |
#define WAIT (0x0008) /* Wait flag for segment write */
|
|
|
383 |
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
384 |
#define EMEX (0x0020) /* Flash Emergency Exit */
|
|
|
385 |
#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
|
|
|
386 |
#define FAIL (0x0080) /* Last Program or Erase failed */
|
|
|
387 |
|
|
|
388 |
/************************************************************
|
|
|
389 |
* Operational Amplifier
|
|
|
390 |
************************************************************/
|
|
|
391 |
#define __MSP430_HAS_OA_2__ /* Definition to show that Module is available */
|
|
|
392 |
|
|
|
393 |
SFR_8BIT(OA0CTL0); /* OA0 Control register 0 */
|
|
|
394 |
SFR_8BIT(OA0CTL1); /* OA0 Control register 1 */
|
|
|
395 |
SFR_8BIT(OA1CTL0); /* OA1 Control register 0 */
|
|
|
396 |
SFR_8BIT(OA1CTL1); /* OA1 Control register 1 */
|
|
|
397 |
|
|
|
398 |
#define OAADC0 (0x01) /* OAx output to ADC12 input channel select 0 */
|
|
|
399 |
#define OAADC1 (0x02) /* OAx output to ADC12 input channel select 1 */
|
|
|
400 |
#define OAPM0 (0x04) /* OAx Power mode select 0 */
|
|
|
401 |
#define OAPM1 (0x08) /* OAx Power mode select 1 */
|
|
|
402 |
#define OAP0 (0x10) /* OAx Non-inverting input select 0 */
|
|
|
403 |
#define OAP1 (0x20) /* OAx Non-inverting input select 1 */
|
|
|
404 |
#define OAN0 (0x40) /* OAx Inverting input select 0 */
|
|
|
405 |
#define OAN1 (0x80) /* OAx Inverting input select 1 */
|
|
|
406 |
|
|
|
407 |
#define OAPM_0 (0x00) /* OAx Power mode select: off */
|
|
|
408 |
#define OAPM_1 (0x04) /* OAx Power mode select: slow */
|
|
|
409 |
#define OAPM_2 (0x08) /* OAx Power mode select: meduim */
|
|
|
410 |
#define OAPM_3 (0x0C) /* OAx Power mode select: fast */
|
|
|
411 |
#define OAP_0 (0x00) /* OAx Non-inverting input select 00 */
|
|
|
412 |
#define OAP_1 (0x10) /* OAx Non-inverting input select 01 */
|
|
|
413 |
#define OAP_2 (0x20) /* OAx Non-inverting input select 10 */
|
|
|
414 |
#define OAP_3 (0x30) /* OAx Non-inverting input select 11 */
|
|
|
415 |
#define OAN_0 (0x00) /* OAx Inverting input select 00 */
|
|
|
416 |
#define OAN_1 (0x40) /* OAx Inverting input select 01 */
|
|
|
417 |
#define OAN_2 (0x80) /* OAx Inverting input select 10 */
|
|
|
418 |
#define OAN_3 (0xC0) /* OAx Inverting input select 11 */
|
|
|
419 |
|
|
|
420 |
#define OARRIP (0x01) /* OAx Rail-to-Rail Input off */
|
|
|
421 |
#define OANEXT (0x02) /* OAx Inverting input external */
|
|
|
422 |
//#define OACAL (0x02) /* OAx Offset Calibration */
|
|
|
423 |
#define OAFC0 (0x04) /* OAx Function control 0 */
|
|
|
424 |
#define OAFC1 (0x08) /* OAx Function control 1 */
|
|
|
425 |
#define OAFC2 (0x10) /* OAx Function control 2 */
|
|
|
426 |
#define OAFBR0 (0x20) /* OAx Feedback resistor select 0 */
|
|
|
427 |
#define OAFBR1 (0x40) /* OAx Feedback resistor select 1 */
|
|
|
428 |
#define OAFBR2 (0x80) /* OAx Feedback resistor select 2 */
|
|
|
429 |
|
|
|
430 |
#define OAFC_0 (0x00) /* OAx Function: Gen. Purpose */
|
|
|
431 |
#define OAFC_1 (0x04) /* OAx Function: Unity gain buffer */
|
|
|
432 |
#define OAFC_2 (0x08) /* OAx Function: Reserved */
|
|
|
433 |
#define OAFC_3 (0x0C) /* OAx Function: Comparator */
|
|
|
434 |
#define OAFC_4 (0x10) /* OAx Function: Non-inverting PGA */
|
|
|
435 |
#define OAFC_5 (0x14) /* OAx Function: Cascaded non-inverting PGA */
|
|
|
436 |
#define OAFC_6 (0x18) /* OAx Function: Inverting PGA */
|
|
|
437 |
#define OAFC_7 (0x1C) /* OAx Function: Differential amplifier */
|
|
|
438 |
#define OAFBR_0 (0x00) /* OAx Feedback resistor: Tap 0 */
|
|
|
439 |
#define OAFBR_1 (0x20) /* OAx Feedback resistor: Tap 1 */
|
|
|
440 |
#define OAFBR_2 (0x40) /* OAx Feedback resistor: Tap 2 */
|
|
|
441 |
#define OAFBR_3 (0x60) /* OAx Feedback resistor: Tap 3 */
|
|
|
442 |
#define OAFBR_4 (0x80) /* OAx Feedback resistor: Tap 4 */
|
|
|
443 |
#define OAFBR_5 (0xA0) /* OAx Feedback resistor: Tap 5 */
|
|
|
444 |
#define OAFBR_6 (0xC0) /* OAx Feedback resistor: Tap 6 */
|
|
|
445 |
#define OAFBR_7 (0xE0) /* OAx Feedback resistor: Tap 7 */
|
|
|
446 |
|
|
|
447 |
/************************************************************
|
|
|
448 |
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
|
|
|
449 |
************************************************************/
|
|
|
450 |
#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
|
|
|
451 |
#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
|
|
|
452 |
|
|
|
453 |
SFR_8BIT(P1IN); /* Port 1 Input */
|
|
|
454 |
SFR_8BIT(P1OUT); /* Port 1 Output */
|
|
|
455 |
SFR_8BIT(P1DIR); /* Port 1 Direction */
|
|
|
456 |
SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */
|
|
|
457 |
SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */
|
|
|
458 |
SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */
|
|
|
459 |
SFR_8BIT(P1SEL); /* Port 1 Selection */
|
|
|
460 |
SFR_8BIT(P1REN); /* Port 1 Resistor Enable */
|
|
|
461 |
|
|
|
462 |
SFR_8BIT(P2IN); /* Port 2 Input */
|
|
|
463 |
SFR_8BIT(P2OUT); /* Port 2 Output */
|
|
|
464 |
SFR_8BIT(P2DIR); /* Port 2 Direction */
|
|
|
465 |
SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */
|
|
|
466 |
SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */
|
|
|
467 |
SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */
|
|
|
468 |
SFR_8BIT(P2SEL); /* Port 2 Selection */
|
|
|
469 |
SFR_8BIT(P2REN); /* Port 2 Resistor Enable */
|
|
|
470 |
|
|
|
471 |
/************************************************************
|
|
|
472 |
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
|
|
|
473 |
************************************************************/
|
|
|
474 |
#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
|
|
|
475 |
#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
|
|
|
476 |
|
|
|
477 |
SFR_8BIT(P3IN); /* Port 3 Input */
|
|
|
478 |
SFR_8BIT(P3OUT); /* Port 3 Output */
|
|
|
479 |
SFR_8BIT(P3DIR); /* Port 3 Direction */
|
|
|
480 |
SFR_8BIT(P3SEL); /* Port 3 Selection */
|
|
|
481 |
SFR_8BIT(P3REN); /* Port 3 Resistor Enable */
|
|
|
482 |
|
|
|
483 |
SFR_8BIT(P4IN); /* Port 4 Input */
|
|
|
484 |
SFR_8BIT(P4OUT); /* Port 4 Output */
|
|
|
485 |
SFR_8BIT(P4DIR); /* Port 4 Direction */
|
|
|
486 |
SFR_8BIT(P4SEL); /* Port 4 Selection */
|
|
|
487 |
SFR_8BIT(P4REN); /* Port 4 Resistor Enable */
|
|
|
488 |
|
|
|
489 |
/************************************************************
|
|
|
490 |
* Timer A3
|
|
|
491 |
************************************************************/
|
|
|
492 |
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
|
|
|
493 |
|
|
|
494 |
SFR_16BIT(TAIV); /* Timer A Interrupt Vector Word */
|
|
|
495 |
SFR_16BIT(TACTL); /* Timer A Control */
|
|
|
496 |
SFR_16BIT(TACCTL0); /* Timer A Capture/Compare Control 0 */
|
|
|
497 |
SFR_16BIT(TACCTL1); /* Timer A Capture/Compare Control 1 */
|
|
|
498 |
SFR_16BIT(TACCTL2); /* Timer A Capture/Compare Control 2 */
|
|
|
499 |
SFR_16BIT(TAR); /* Timer A Counter Register */
|
|
|
500 |
SFR_16BIT(TACCR0); /* Timer A Capture/Compare 0 */
|
|
|
501 |
SFR_16BIT(TACCR1); /* Timer A Capture/Compare 1 */
|
|
|
502 |
SFR_16BIT(TACCR2); /* Timer A Capture/Compare 2 */
|
|
|
503 |
|
|
|
504 |
/* Alternate register names */
|
|
|
505 |
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
506 |
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
507 |
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
508 |
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
509 |
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
510 |
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
511 |
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
512 |
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
513 |
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
514 |
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
515 |
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
516 |
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
517 |
/* Alternate register names - 5xx style */
|
|
|
518 |
#define TA0IV TAIV /* Timer A Interrupt Vector Word */
|
|
|
519 |
#define TA0CTL TACTL /* Timer A Control */
|
|
|
520 |
#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
521 |
#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
522 |
#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
523 |
#define TA0R TAR /* Timer A Counter Register */
|
|
|
524 |
#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
525 |
#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
526 |
#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
527 |
#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */
|
|
|
528 |
#define TA0CTL_ TACTL_ /* Timer A Control */
|
|
|
529 |
#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
530 |
#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
531 |
#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
532 |
#define TA0R_ TAR_ /* Timer A Counter Register */
|
|
|
533 |
#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
534 |
#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
535 |
#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
536 |
|
|
|
537 |
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
|
|
|
538 |
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
|
|
|
539 |
#define ID1 (0x0080) /* Timer A clock input divider 1 */
|
|
|
540 |
#define ID0 (0x0040) /* Timer A clock input divider 0 */
|
|
|
541 |
#define MC1 (0x0020) /* Timer A mode control 1 */
|
|
|
542 |
#define MC0 (0x0010) /* Timer A mode control 0 */
|
|
|
543 |
#define TACLR (0x0004) /* Timer A counter clear */
|
|
|
544 |
#define TAIE (0x0002) /* Timer A counter interrupt enable */
|
|
|
545 |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
|
|
|
546 |
|
|
|
547 |
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
548 |
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
549 |
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
550 |
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
551 |
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
552 |
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
553 |
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
554 |
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
555 |
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
556 |
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
557 |
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
558 |
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
559 |
|
|
|
560 |
#define CM1 (0x8000) /* Capture mode 1 */
|
|
|
561 |
#define CM0 (0x4000) /* Capture mode 0 */
|
|
|
562 |
#define CCIS1 (0x2000) /* Capture input select 1 */
|
|
|
563 |
#define CCIS0 (0x1000) /* Capture input select 0 */
|
|
|
564 |
#define SCS (0x0800) /* Capture sychronize */
|
|
|
565 |
#define SCCI (0x0400) /* Latched capture signal (read) */
|
|
|
566 |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
|
|
|
567 |
#define OUTMOD2 (0x0080) /* Output mode 2 */
|
|
|
568 |
#define OUTMOD1 (0x0040) /* Output mode 1 */
|
|
|
569 |
#define OUTMOD0 (0x0020) /* Output mode 0 */
|
|
|
570 |
#define CCIE (0x0010) /* Capture/compare interrupt enable */
|
|
|
571 |
#define CCI (0x0008) /* Capture input signal (read) */
|
|
|
572 |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
|
|
|
573 |
#define COV (0x0002) /* Capture/compare overflow flag */
|
|
|
574 |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
|
|
|
575 |
|
|
|
576 |
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
|
|
|
577 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
|
|
|
578 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
|
|
|
579 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
|
|
|
580 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
|
|
|
581 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
|
|
|
582 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
|
|
|
583 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
|
|
|
584 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
|
|
|
585 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
|
|
|
586 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
|
|
|
587 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
|
|
|
588 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
|
|
|
589 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
|
|
|
590 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
|
|
|
591 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
|
|
|
592 |
|
|
|
593 |
/* TA3IV Definitions */
|
|
|
594 |
#define TAIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
595 |
#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */
|
|
|
596 |
#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */
|
|
|
597 |
#define TAIV_6 (0x0006) /* Reserved */
|
|
|
598 |
#define TAIV_8 (0x0008) /* Reserved */
|
|
|
599 |
#define TAIV_TAIFG (0x000A) /* TAIFG */
|
|
|
600 |
|
|
|
601 |
/************************************************************
|
|
|
602 |
* Timer B3
|
|
|
603 |
************************************************************/
|
|
|
604 |
#define __MSP430_HAS_TB3__ /* Definition to show that Module is available */
|
|
|
605 |
|
|
|
606 |
SFR_16BIT(TBIV); /* Timer B Interrupt Vector Word */
|
|
|
607 |
SFR_16BIT(TBCTL); /* Timer B Control */
|
|
|
608 |
SFR_16BIT(TBCCTL0); /* Timer B Capture/Compare Control 0 */
|
|
|
609 |
SFR_16BIT(TBCCTL1); /* Timer B Capture/Compare Control 1 */
|
|
|
610 |
SFR_16BIT(TBCCTL2); /* Timer B Capture/Compare Control 2 */
|
|
|
611 |
SFR_16BIT(TBR); /* Timer B Counter Register */
|
|
|
612 |
SFR_16BIT(TBCCR0); /* Timer B Capture/Compare 0 */
|
|
|
613 |
SFR_16BIT(TBCCR1); /* Timer B Capture/Compare 1 */
|
|
|
614 |
SFR_16BIT(TBCCR2); /* Timer B Capture/Compare 2 */
|
|
|
615 |
|
|
|
616 |
/* Alternate register names - 5xx style */
|
|
|
617 |
#define TB0IV TBIV /* Timer B Interrupt Vector Word */
|
|
|
618 |
#define TB0CTL TBCTL /* Timer B Control */
|
|
|
619 |
#define TB0CCTL0 TBCCTL0 /* Timer B Capture/Compare Control 0 */
|
|
|
620 |
#define TB0CCTL1 TBCCTL1 /* Timer B Capture/Compare Control 1 */
|
|
|
621 |
#define TB0CCTL2 TBCCTL2 /* Timer B Capture/Compare Control 2 */
|
|
|
622 |
#define TB0R TBR /* Timer B Counter Register */
|
|
|
623 |
#define TB0CCR0 TBCCR0 /* Timer B Capture/Compare 0 */
|
|
|
624 |
#define TB0CCR1 TBCCR1 /* Timer B Capture/Compare 1 */
|
|
|
625 |
#define TB0CCR2 TBCCR2 /* Timer B Capture/Compare 2 */
|
|
|
626 |
#define TB0IV_ TBIV_ /* Timer B Interrupt Vector Word */
|
|
|
627 |
#define TB0CTL_ TBCTL_ /* Timer B Control */
|
|
|
628 |
#define TB0CCTL0_ TBCCTL0_ /* Timer B Capture/Compare Control 0 */
|
|
|
629 |
#define TB0CCTL1_ TBCCTL1_ /* Timer B Capture/Compare Control 1 */
|
|
|
630 |
#define TB0CCTL2_ TBCCTL2_ /* Timer B Capture/Compare Control 2 */
|
|
|
631 |
#define TB0R_ TBR_ /* Timer B Counter Register */
|
|
|
632 |
#define TB0CCR0_ TBCCR0_ /* Timer B Capture/Compare 0 */
|
|
|
633 |
#define TB0CCR1_ TBCCR1_ /* Timer B Capture/Compare 1 */
|
|
|
634 |
#define TB0CCR2_ TBCCR2_ /* Timer B Capture/Compare 2 */
|
|
|
635 |
|
|
|
636 |
#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */
|
|
|
637 |
#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */
|
|
|
638 |
#define CNTL1 (0x1000) /* Counter lenght 1 */
|
|
|
639 |
#define CNTL0 (0x0800) /* Counter lenght 0 */
|
|
|
640 |
#define TBSSEL1 (0x0200) /* Clock source 1 */
|
|
|
641 |
#define TBSSEL0 (0x0100) /* Clock source 0 */
|
|
|
642 |
#define TBCLR (0x0004) /* Timer B counter clear */
|
|
|
643 |
#define TBIE (0x0002) /* Timer B interrupt enable */
|
|
|
644 |
#define TBIFG (0x0001) /* Timer B interrupt flag */
|
|
|
645 |
|
|
|
646 |
#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */
|
|
|
647 |
#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */
|
|
|
648 |
|
|
|
649 |
#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
|
|
|
650 |
#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
|
|
|
651 |
#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
|
|
|
652 |
#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
|
|
|
653 |
#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
|
|
|
654 |
#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
|
|
|
655 |
#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
|
|
|
656 |
#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
|
|
|
657 |
#define SHR_0 (0*0x2000u) /* Timer B Group: 0 - individually */
|
|
|
658 |
#define SHR_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
659 |
#define SHR_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
660 |
#define SHR_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
|
|
|
661 |
#define TBCLGRP_0 (0*0x2000u) /* Timer B Group: 0 - individually */
|
|
|
662 |
#define TBCLGRP_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
663 |
#define TBCLGRP_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
664 |
#define TBCLGRP_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
|
|
|
665 |
|
|
|
666 |
/* Additional Timer B Control Register bits are defined in Timer A */
|
|
|
667 |
|
|
|
668 |
#define CLLD1 (0x0400) /* Compare latch load source 1 */
|
|
|
669 |
#define CLLD0 (0x0200) /* Compare latch load source 0 */
|
|
|
670 |
|
|
|
671 |
#define SLSHR1 (0x0400) /* Compare latch load source 1 */
|
|
|
672 |
#define SLSHR0 (0x0200) /* Compare latch load source 0 */
|
|
|
673 |
|
|
|
674 |
#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
675 |
#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
|
|
|
676 |
#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
677 |
#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
|
|
|
678 |
|
|
|
679 |
#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
680 |
#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
|
|
|
681 |
#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
682 |
#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
|
|
|
683 |
|
|
|
684 |
/* TB3IV Definitions */
|
|
|
685 |
#define TBIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
686 |
#define TBIV_TBCCR1 (0x0002) /* TBCCR1_CCIFG */
|
|
|
687 |
#define TBIV_TBCCR2 (0x0004) /* TBCCR2_CCIFG */
|
|
|
688 |
#define TBIV_3 (0x0006) /* Reserved */
|
|
|
689 |
#define TBIV_4 (0x0008) /* Reserved */
|
|
|
690 |
#define TBIV_5 (0x000A) /* Reserved */
|
|
|
691 |
#define TBIV_6 (0x000C) /* Reserved */
|
|
|
692 |
#define TBIV_TBIFG (0x000E) /* TBIFG */
|
|
|
693 |
|
|
|
694 |
/************************************************************
|
|
|
695 |
* USCI
|
|
|
696 |
************************************************************/
|
|
|
697 |
#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */
|
|
|
698 |
|
|
|
699 |
SFR_8BIT(UCA0CTL0); /* USCI A0 Control Register 0 */
|
|
|
700 |
SFR_8BIT(UCA0CTL1); /* USCI A0 Control Register 1 */
|
|
|
701 |
SFR_8BIT(UCA0BR0); /* USCI A0 Baud Rate 0 */
|
|
|
702 |
SFR_8BIT(UCA0BR1); /* USCI A0 Baud Rate 1 */
|
|
|
703 |
SFR_8BIT(UCA0MCTL); /* USCI A0 Modulation Control */
|
|
|
704 |
SFR_8BIT(UCA0STAT); /* USCI A0 Status Register */
|
|
|
705 |
SFR_8BIT(UCA0RXBUF); /* USCI A0 Receive Buffer */
|
|
|
706 |
SFR_8BIT(UCA0TXBUF); /* USCI A0 Transmit Buffer */
|
|
|
707 |
SFR_8BIT(UCA0ABCTL); /* USCI A0 LIN Control */
|
|
|
708 |
SFR_8BIT(UCA0IRTCTL); /* USCI A0 IrDA Transmit Control */
|
|
|
709 |
SFR_8BIT(UCA0IRRCTL); /* USCI A0 IrDA Receive Control */
|
|
|
710 |
|
|
|
711 |
|
|
|
712 |
|
|
|
713 |
SFR_8BIT(UCB0CTL0); /* USCI B0 Control Register 0 */
|
|
|
714 |
SFR_8BIT(UCB0CTL1); /* USCI B0 Control Register 1 */
|
|
|
715 |
SFR_8BIT(UCB0BR0); /* USCI B0 Baud Rate 0 */
|
|
|
716 |
SFR_8BIT(UCB0BR1); /* USCI B0 Baud Rate 1 */
|
|
|
717 |
SFR_8BIT(UCB0I2CIE); /* USCI B0 I2C Interrupt Enable Register */
|
|
|
718 |
SFR_8BIT(UCB0STAT); /* USCI B0 Status Register */
|
|
|
719 |
SFR_8BIT(UCB0RXBUF); /* USCI B0 Receive Buffer */
|
|
|
720 |
SFR_8BIT(UCB0TXBUF); /* USCI B0 Transmit Buffer */
|
|
|
721 |
SFR_16BIT(UCB0I2COA); /* USCI B0 I2C Own Address */
|
|
|
722 |
SFR_16BIT(UCB0I2CSA); /* USCI B0 I2C Slave Address */
|
|
|
723 |
|
|
|
724 |
// UART-Mode Bits
|
|
|
725 |
#define UCPEN (0x80) /* Async. Mode: Parity enable */
|
|
|
726 |
#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
|
|
|
727 |
#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
|
|
|
728 |
#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
|
|
|
729 |
#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
|
|
|
730 |
#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
|
|
|
731 |
#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
|
|
|
732 |
#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
|
|
|
733 |
|
|
|
734 |
// SPI-Mode Bits
|
|
|
735 |
#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
|
|
|
736 |
#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
|
|
|
737 |
#define UCMST (0x08) /* Sync. Mode: Master Select */
|
|
|
738 |
|
|
|
739 |
// I2C-Mode Bits
|
|
|
740 |
#define UCA10 (0x80) /* 10-bit Address Mode */
|
|
|
741 |
#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
|
|
|
742 |
#define UCMM (0x20) /* Multi-Master Environment */
|
|
|
743 |
//#define res (0x10) /* reserved */
|
|
|
744 |
#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
|
|
|
745 |
#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
|
|
|
746 |
#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
|
|
|
747 |
#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
|
|
|
748 |
|
|
|
749 |
// UART-Mode Bits
|
|
|
750 |
#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
|
|
|
751 |
#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
|
|
|
752 |
#define UCRXEIE (0x20) /* RX Error interrupt enable */
|
|
|
753 |
#define UCBRKIE (0x10) /* Break interrupt enable */
|
|
|
754 |
#define UCDORM (0x08) /* Dormant (Sleep) Mode */
|
|
|
755 |
#define UCTXADDR (0x04) /* Send next Data as Address */
|
|
|
756 |
#define UCTXBRK (0x02) /* Send next Data as Break */
|
|
|
757 |
#define UCSWRST (0x01) /* USCI Software Reset */
|
|
|
758 |
|
|
|
759 |
// SPI-Mode Bits
|
|
|
760 |
//#define res (0x20) /* reserved */
|
|
|
761 |
//#define res (0x10) /* reserved */
|
|
|
762 |
//#define res (0x08) /* reserved */
|
|
|
763 |
//#define res (0x04) /* reserved */
|
|
|
764 |
//#define res (0x02) /* reserved */
|
|
|
765 |
|
|
|
766 |
// I2C-Mode Bits
|
|
|
767 |
//#define res (0x20) /* reserved */
|
|
|
768 |
#define UCTR (0x10) /* Transmit/Receive Select/Flag */
|
|
|
769 |
#define UCTXNACK (0x08) /* Transmit NACK */
|
|
|
770 |
#define UCTXSTP (0x04) /* Transmit STOP */
|
|
|
771 |
#define UCTXSTT (0x02) /* Transmit START */
|
|
|
772 |
#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
|
|
|
773 |
#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
|
|
|
774 |
#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
|
|
|
775 |
#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
|
|
|
776 |
|
|
|
777 |
#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
|
|
|
778 |
#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
|
|
|
779 |
#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
|
|
|
780 |
#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
|
|
|
781 |
#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
|
|
|
782 |
#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
|
|
|
783 |
#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
|
|
|
784 |
#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
|
|
|
785 |
|
|
|
786 |
#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
|
|
|
787 |
#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
|
|
|
788 |
#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
|
|
|
789 |
#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
|
|
|
790 |
#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
|
|
|
791 |
#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
|
|
|
792 |
#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
|
|
|
793 |
#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
|
|
|
794 |
#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
|
|
|
795 |
#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
|
|
|
796 |
#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
|
|
|
797 |
#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
|
|
|
798 |
#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
|
|
|
799 |
#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
|
|
|
800 |
#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
|
|
|
801 |
#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
|
|
|
802 |
|
|
|
803 |
#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
|
|
|
804 |
#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
|
|
|
805 |
#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
|
|
|
806 |
#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
|
|
|
807 |
#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
|
|
|
808 |
#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
|
|
|
809 |
#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
|
|
|
810 |
#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
|
|
|
811 |
|
|
|
812 |
#define UCLISTEN (0x80) /* USCI Listen mode */
|
|
|
813 |
#define UCFE (0x40) /* USCI Frame Error Flag */
|
|
|
814 |
#define UCOE (0x20) /* USCI Overrun Error Flag */
|
|
|
815 |
#define UCPE (0x10) /* USCI Parity Error Flag */
|
|
|
816 |
#define UCBRK (0x08) /* USCI Break received */
|
|
|
817 |
#define UCRXERR (0x04) /* USCI RX Error Flag */
|
|
|
818 |
#define UCADDR (0x02) /* USCI Address received Flag */
|
|
|
819 |
#define UCBUSY (0x01) /* USCI Busy Flag */
|
|
|
820 |
#define UCIDLE (0x02) /* USCI Idle line detected Flag */
|
|
|
821 |
|
|
|
822 |
//#define res (0x80) /* reserved */
|
|
|
823 |
//#define res (0x40) /* reserved */
|
|
|
824 |
//#define res (0x20) /* reserved */
|
|
|
825 |
//#define res (0x10) /* reserved */
|
|
|
826 |
#define UCNACKIE (0x08) /* NACK Condition interrupt enable */
|
|
|
827 |
#define UCSTPIE (0x04) /* STOP Condition interrupt enable */
|
|
|
828 |
#define UCSTTIE (0x02) /* START Condition interrupt enable */
|
|
|
829 |
#define UCALIE (0x01) /* Arbitration Lost interrupt enable */
|
|
|
830 |
|
|
|
831 |
#define UCSCLLOW (0x40) /* SCL low */
|
|
|
832 |
#define UCGC (0x20) /* General Call address received Flag */
|
|
|
833 |
#define UCBBUSY (0x10) /* Bus Busy Flag */
|
|
|
834 |
#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */
|
|
|
835 |
#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */
|
|
|
836 |
#define UCSTTIFG (0x02) /* START Condition interrupt Flag */
|
|
|
837 |
#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */
|
|
|
838 |
|
|
|
839 |
#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
|
|
|
840 |
#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
|
|
|
841 |
#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
|
|
|
842 |
#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
|
|
|
843 |
#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
|
|
|
844 |
#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
|
|
|
845 |
#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
|
|
|
846 |
#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
|
|
|
847 |
|
|
|
848 |
#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
|
|
|
849 |
#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
|
|
|
850 |
#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
|
|
|
851 |
#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
|
|
|
852 |
#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
|
|
|
853 |
#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
|
|
|
854 |
#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
|
|
|
855 |
#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
|
|
|
856 |
|
|
|
857 |
//#define res (0x80) /* reserved */
|
|
|
858 |
//#define res (0x40) /* reserved */
|
|
|
859 |
#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
|
|
|
860 |
#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
|
|
|
861 |
#define UCSTOE (0x08) /* Sync-Field Timeout error */
|
|
|
862 |
#define UCBTOE (0x04) /* Break Timeout error */
|
|
|
863 |
//#define res (0x02) /* reserved */
|
|
|
864 |
#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
|
|
|
865 |
|
|
|
866 |
#define UCGCEN (0x8000) /* I2C General Call enable */
|
|
|
867 |
#define UCOA9 (0x0200) /* I2C Own Address 9 */
|
|
|
868 |
#define UCOA8 (0x0100) /* I2C Own Address 8 */
|
|
|
869 |
#define UCOA7 (0x0080) /* I2C Own Address 7 */
|
|
|
870 |
#define UCOA6 (0x0040) /* I2C Own Address 6 */
|
|
|
871 |
#define UCOA5 (0x0020) /* I2C Own Address 5 */
|
|
|
872 |
#define UCOA4 (0x0010) /* I2C Own Address 4 */
|
|
|
873 |
#define UCOA3 (0x0008) /* I2C Own Address 3 */
|
|
|
874 |
#define UCOA2 (0x0004) /* I2C Own Address 2 */
|
|
|
875 |
#define UCOA1 (0x0002) /* I2C Own Address 1 */
|
|
|
876 |
#define UCOA0 (0x0001) /* I2C Own Address 0 */
|
|
|
877 |
|
|
|
878 |
#define UCSA9 (0x0200) /* I2C Slave Address 9 */
|
|
|
879 |
#define UCSA8 (0x0100) /* I2C Slave Address 8 */
|
|
|
880 |
#define UCSA7 (0x0080) /* I2C Slave Address 7 */
|
|
|
881 |
#define UCSA6 (0x0040) /* I2C Slave Address 6 */
|
|
|
882 |
#define UCSA5 (0x0020) /* I2C Slave Address 5 */
|
|
|
883 |
#define UCSA4 (0x0010) /* I2C Slave Address 4 */
|
|
|
884 |
#define UCSA3 (0x0008) /* I2C Slave Address 3 */
|
|
|
885 |
#define UCSA2 (0x0004) /* I2C Slave Address 2 */
|
|
|
886 |
#define UCSA1 (0x0002) /* I2C Slave Address 1 */
|
|
|
887 |
#define UCSA0 (0x0001) /* I2C Slave Address 0 */
|
|
|
888 |
|
|
|
889 |
/************************************************************
|
|
|
890 |
* WATCHDOG TIMER
|
|
|
891 |
************************************************************/
|
|
|
892 |
#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
|
|
|
893 |
|
|
|
894 |
SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
|
|
|
895 |
/* The bit names have been prefixed with "WDT" */
|
|
|
896 |
#define WDTIS0 (0x0001)
|
|
|
897 |
#define WDTIS1 (0x0002)
|
|
|
898 |
#define WDTSSEL (0x0004)
|
|
|
899 |
#define WDTCNTCL (0x0008)
|
|
|
900 |
#define WDTTMSEL (0x0010)
|
|
|
901 |
#define WDTNMI (0x0020)
|
|
|
902 |
#define WDTNMIES (0x0040)
|
|
|
903 |
#define WDTHOLD (0x0080)
|
|
|
904 |
|
|
|
905 |
#define WDTPW (0x5A00)
|
|
|
906 |
|
|
|
907 |
/* WDT-interval times [1ms] coded with Bits 0-2 */
|
|
|
908 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
909 |
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
|
|
|
910 |
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
|
|
|
911 |
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
|
|
|
912 |
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
913 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
914 |
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
|
|
|
915 |
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
|
|
|
916 |
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
|
|
|
917 |
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
918 |
/* Watchdog mode -> reset after expired time */
|
|
|
919 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
920 |
#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
|
|
|
921 |
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
|
|
|
922 |
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
|
|
|
923 |
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
924 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
925 |
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
|
|
|
926 |
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
|
|
|
927 |
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
|
|
|
928 |
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
929 |
|
|
|
930 |
/* INTERRUPT CONTROL */
|
|
|
931 |
/* These two bits are defined in the Special Function Registers */
|
|
|
932 |
/* #define WDTIE 0x01 */
|
|
|
933 |
/* #define WDTIFG 0x01 */
|
|
|
934 |
|
|
|
935 |
/************************************************************
|
|
|
936 |
* Calibration Data in Info Mem
|
|
|
937 |
************************************************************/
|
|
|
938 |
|
|
|
939 |
#ifndef __DisableCalData
|
|
|
940 |
|
|
|
941 |
SFR_8BIT(CALDCO_16MHZ); /* DCOCTL Calibration Data for 16MHz */
|
|
|
942 |
SFR_8BIT(CALBC1_16MHZ); /* BCSCTL1 Calibration Data for 16MHz */
|
|
|
943 |
SFR_8BIT(CALDCO_12MHZ); /* DCOCTL Calibration Data for 12MHz */
|
|
|
944 |
SFR_8BIT(CALBC1_12MHZ); /* BCSCTL1 Calibration Data for 12MHz */
|
|
|
945 |
SFR_8BIT(CALDCO_8MHZ); /* DCOCTL Calibration Data for 8MHz */
|
|
|
946 |
SFR_8BIT(CALBC1_8MHZ); /* BCSCTL1 Calibration Data for 8MHz */
|
|
|
947 |
SFR_8BIT(CALDCO_1MHZ); /* DCOCTL Calibration Data for 1MHz */
|
|
|
948 |
SFR_8BIT(CALBC1_1MHZ); /* BCSCTL1 Calibration Data for 1MHz */
|
|
|
949 |
|
|
|
950 |
#endif /* #ifndef __DisableCalData */
|
|
|
951 |
|
|
|
952 |
/************************************************************
|
|
|
953 |
* Interrupt Vectors (offset from 0xFFE0)
|
|
|
954 |
************************************************************/
|
|
|
955 |
|
|
|
956 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
957 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
958 |
#define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name
|
|
|
959 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
960 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
961 |
PLACE_VECTOR(VECTOR_NAME(func), offset)
|
|
|
962 |
|
|
|
963 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
964 |
#define PORT1_VECTOR ".int02" /* 0xFFE4 Port 1 */
|
|
|
965 |
#else
|
|
|
966 |
#define PORT1_VECTOR (2 * 1u) /* 0xFFE4 Port 1 */
|
|
|
967 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int02") */ /* 0xFFE4 Port 1 */ /* CCE V2 Style */
|
|
|
968 |
#endif
|
|
|
969 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
970 |
#define PORT2_VECTOR ".int03" /* 0xFFE6 Port 2 */
|
|
|
971 |
#else
|
|
|
972 |
#define PORT2_VECTOR (3 * 1u) /* 0xFFE6 Port 2 */
|
|
|
973 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int03") */ /* 0xFFE6 Port 2 */ /* CCE V2 Style */
|
|
|
974 |
#endif
|
|
|
975 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
976 |
#define ADC10_VECTOR ".int05" /* 0xFFEA ADC10 */
|
|
|
977 |
#else
|
|
|
978 |
#define ADC10_VECTOR (5 * 1u) /* 0xFFEA ADC10 */
|
|
|
979 |
/*#define ADC10_ISR(func) ISR_VECTOR(func, ".int05") */ /* 0xFFEA ADC10 */ /* CCE V2 Style */
|
|
|
980 |
#endif
|
|
|
981 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
982 |
#define USCIAB0TX_VECTOR ".int06" /* 0xFFEC USCI A0/B0 Transmit */
|
|
|
983 |
#else
|
|
|
984 |
#define USCIAB0TX_VECTOR (6 * 1u) /* 0xFFEC USCI A0/B0 Transmit */
|
|
|
985 |
/*#define USCIAB0TX_ISR(func) ISR_VECTOR(func, ".int06") */ /* 0xFFEC USCI A0/B0 Transmit */ /* CCE V2 Style */
|
|
|
986 |
#endif
|
|
|
987 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
988 |
#define USCIAB0RX_VECTOR ".int07" /* 0xFFEE USCI A0/B0 Receive */
|
|
|
989 |
#else
|
|
|
990 |
#define USCIAB0RX_VECTOR (7 * 1u) /* 0xFFEE USCI A0/B0 Receive */
|
|
|
991 |
/*#define USCIAB0RX_ISR(func) ISR_VECTOR(func, ".int07") */ /* 0xFFEE USCI A0/B0 Receive */ /* CCE V2 Style */
|
|
|
992 |
#endif
|
|
|
993 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
994 |
#define TIMERA1_VECTOR ".int08" /* 0xFFF0 Timer A CC1-2, TA */
|
|
|
995 |
#else
|
|
|
996 |
#define TIMERA1_VECTOR (8 * 1u) /* 0xFFF0 Timer A CC1-2, TA */
|
|
|
997 |
/*#define TIMERA1_ISR(func) ISR_VECTOR(func, ".int08") */ /* 0xFFF0 Timer A CC1-2, TA */ /* CCE V2 Style */
|
|
|
998 |
#endif
|
|
|
999 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1000 |
#define TIMERA0_VECTOR ".int09" /* 0xFFF2 Timer A CC0 */
|
|
|
1001 |
#else
|
|
|
1002 |
#define TIMERA0_VECTOR (9 * 1u) /* 0xFFF2 Timer A CC0 */
|
|
|
1003 |
/*#define TIMERA0_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 Timer A CC0 */ /* CCE V2 Style */
|
|
|
1004 |
#endif
|
|
|
1005 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1006 |
#define WDT_VECTOR ".int10" /* 0xFFF4 Watchdog Timer */
|
|
|
1007 |
#else
|
|
|
1008 |
#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */
|
|
|
1009 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
|
|
|
1010 |
#endif
|
|
|
1011 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1012 |
#define TIMERB1_VECTOR ".int12" /* 0xFFF8 Timer B CC1-2, TB */
|
|
|
1013 |
#else
|
|
|
1014 |
#define TIMERB1_VECTOR (12 * 1u) /* 0xFFF8 Timer B CC1-2, TB */
|
|
|
1015 |
/*#define TIMERB1_ISR(func) ISR_VECTOR(func, ".int12") */ /* 0xFFF8 Timer B CC1-2, TB */ /* CCE V2 Style */
|
|
|
1016 |
#endif
|
|
|
1017 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1018 |
#define TIMERB0_VECTOR ".int13" /* 0xFFFA Timer B CC0 */
|
|
|
1019 |
#else
|
|
|
1020 |
#define TIMERB0_VECTOR (13 * 1u) /* 0xFFFA Timer B CC0 */
|
|
|
1021 |
/*#define TIMERB0_ISR(func) ISR_VECTOR(func, ".int13") */ /* 0xFFFA Timer B CC0 */ /* CCE V2 Style */
|
|
|
1022 |
#endif
|
|
|
1023 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1024 |
#define NMI_VECTOR ".int14" /* 0xFFFC Non-maskable */
|
|
|
1025 |
#else
|
|
|
1026 |
#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */
|
|
|
1027 |
/*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
|
|
|
1028 |
#endif
|
|
|
1029 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1030 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
1031 |
#else
|
|
|
1032 |
#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
1033 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
1034 |
#endif
|
|
|
1035 |
|
|
|
1036 |
/************************************************************
|
|
|
1037 |
* End of Modules
|
|
|
1038 |
************************************************************/
|
|
|
1039 |
|
|
|
1040 |
#ifdef __cplusplus
|
|
|
1041 |
}
|
|
|
1042 |
#endif /* extern "C" */
|
|
|
1043 |
|
|
|
1044 |
#endif /* #ifndef __msp430x22x4 */
|
|
|
1045 |
|