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dpurdie |
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/******************************************************************************/
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/* Legacy Header File */
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/* Not recommended for use in new projects. */
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/* Please use the msp430.h file or the device specific header file */
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/******************************************************************************/
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* MSP430x12x2 devices.
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*
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* Texas Instruments, Version 2.4
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*
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* Rev. 1.1, Defined vectors for USART (in addition to UART)
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* Rev. 1.2, Added USART special function labels (UxME, UxIE, UxIFG)
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* Rev. 2.1, Alignment of defintions in Users Guide and of version numbers
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* Rev. 2.2, Removed unused def of TASSEL2
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* Rev. 2.3, added definitions for Interrupt Vectors xxIV
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* Rev. 2.4, Fixed typo in ADC10: SREF3 -> SREF2
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*
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********************************************************************/
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#ifndef __msp430x12x2
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#define __msp430x12x2
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
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************************************************************/
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SFR_8BIT(IE1); /* Interrupt Enable 1 */
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#define WDTIE (0x01)
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#define OFIE (0x02)
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#define NMIIE (0x10)
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#define ACCVIE (0x20)
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SFR_8BIT(IFG1); /* Interrupt Flag 1 */
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#define WDTIFG (0x01)
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#define OFIFG (0x02)
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#define NMIIFG (0x10)
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SFR_8BIT(IE2); /* Interrupt Enable 2 */
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#define U0IE IE2 /* UART0 Interrupt Enable Register */
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#define URXIE0 (0x01)
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#define UTXIE0 (0x02)
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SFR_8BIT(IFG2); /* Interrupt Flag 2 */
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#define U0IFG IFG2 /* UART0 Interrupt Flag Register */
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#define URXIFG0 (0x01)
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#define UTXIFG0 (0x02)
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SFR_8BIT(ME2); /* Module Enable 2 */
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#define U0ME ME2 /* UART0 Module Enable Register */
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#define URXE0 (0x01)
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#define UTXE0 (0x02)
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#define USPIE0 (0x01)
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/************************************************************
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* WATCHDOG TIMER
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************************************************************/
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#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
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SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
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/* The bit names have been prefixed with "WDT" */
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#define WDTIS0 (0x0001)
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#define WDTIS1 (0x0002)
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#define WDTSSEL (0x0004)
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#define WDTCNTCL (0x0008)
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#define WDTTMSEL (0x0010)
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#define WDTNMI (0x0020)
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#define WDTNMIES (0x0040)
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#define WDTHOLD (0x0080)
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#define WDTPW (0x5A00)
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/* WDT-interval times [1ms] coded with Bits 0-2 */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* Watchdog mode -> reset after expired time */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* INTERRUPT CONTROL */
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/* These two bits are defined in the Special Function Registers */
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/* #define WDTIE 0x01 */
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/* #define WDTIFG 0x01 */
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/************************************************************
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* DIGITAL I/O Port1/2
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************************************************************/
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#define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */
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#define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */
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SFR_8BIT(P1IN); /* Port 1 Input */
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SFR_8BIT(P1OUT); /* Port 1 Output */
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SFR_8BIT(P1DIR); /* Port 1 Direction */
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SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */
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SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */
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SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */
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SFR_8BIT(P1SEL); /* Port 1 Selection */
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SFR_8BIT(P2IN); /* Port 2 Input */
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SFR_8BIT(P2OUT); /* Port 2 Output */
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SFR_8BIT(P2DIR); /* Port 2 Direction */
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SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */
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SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */
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SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */
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SFR_8BIT(P2SEL); /* Port 2 Selection */
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/************************************************************
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* DIGITAL I/O Port3
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************************************************************/
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#define __MSP430_HAS_PORT3__ /* Definition to show that Module is available */
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SFR_8BIT(P3IN); /* Port 3 Input */
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SFR_8BIT(P3OUT); /* Port 3 Output */
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SFR_8BIT(P3DIR); /* Port 3 Direction */
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SFR_8BIT(P3SEL); /* Port 3 Selection */
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/************************************************************
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* USART
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************************************************************/
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/* UxCTL */
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#define PENA (0x80) /* Parity enable */
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#define PEV (0x40) /* Parity 0:odd / 1:even */
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#define SPB (0x20) /* Stop Bits 0:one / 1: two */
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#define CHAR (0x10) /* Data 0:7-bits / 1:8-bits */
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#define LISTEN (0x08) /* Listen mode */
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#define SYNC (0x04) /* UART / SPI mode */
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#define MM (0x02) /* Master Mode off/on */
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#define SWRST (0x01) /* USART Software Reset */
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/* UxTCTL */
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#define CKPH (0x80) /* SPI: Clock Phase */
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#define CKPL (0x40) /* Clock Polarity */
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#define SSEL1 (0x20) /* Clock Source Select 1 */
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#define SSEL0 (0x10) /* Clock Source Select 0 */
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#define URXSE (0x08) /* Receive Start edge select */
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#define TXWAKE (0x04) /* TX Wake up mode */
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#define STC (0x02) /* SPI: STC enable 0:on / 1:off */
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#define TXEPT (0x01) /* TX Buffer empty */
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/* UxRCTL */
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#define FE (0x80) /* Frame Error */
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#define PE (0x40) /* Parity Error */
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#define OE (0x20) /* Overrun Error */
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#define BRK (0x10) /* Break detected */
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#define URXEIE (0x08) /* RX Error interrupt enable */
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#define URXWIE (0x04) /* RX Wake up interrupt enable */
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#define RXWAKE (0x02) /* RX Wake up detect */
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#define RXERR (0x01) /* RX Error Error */
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/************************************************************
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* USART 0
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************************************************************/
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#define __MSP430_HAS_UART0__ /* Definition to show that Module is available */
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SFR_8BIT(U0CTL); /* USART 0 Control */
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SFR_8BIT(U0TCTL); /* USART 0 Transmit Control */
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SFR_8BIT(U0RCTL); /* USART 0 Receive Control */
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SFR_8BIT(U0MCTL); /* USART 0 Modulation Control */
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SFR_8BIT(U0BR0); /* USART 0 Baud Rate 0 */
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SFR_8BIT(U0BR1); /* USART 0 Baud Rate 1 */
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SFR_8BIT(U0RXBUF); /* USART 0 Receive Buffer */
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SFR_8BIT(U0TXBUF); /* USART 0 Transmit Buffer */
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/* Alternate register names */
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#define UCTL0 U0CTL /* USART 0 Control */
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#define UTCTL0 U0TCTL /* USART 0 Transmit Control */
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#define URCTL0 U0RCTL /* USART 0 Receive Control */
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#define UMCTL0 U0MCTL /* USART 0 Modulation Control */
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#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */
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#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */
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#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */
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#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */
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#define UCTL0_ U0CTL_ /* USART 0 Control */
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#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */
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#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */
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#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */
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#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */
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#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */
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#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */
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#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */
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#define UCTL_0 U0CTL /* USART 0 Control */
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#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */
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#define URCTL_0 U0RCTL /* USART 0 Receive Control */
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#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */
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#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */
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#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */
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#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */
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#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */
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#define UCTL_0_ U0CTL_ /* USART 0 Control */
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#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */
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#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */
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#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */
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300 |
#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */
|
|
|
301 |
#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */
|
|
|
302 |
#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */
|
|
|
303 |
#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */
|
|
|
304 |
|
|
|
305 |
/************************************************************
|
|
|
306 |
* Timer A3
|
|
|
307 |
************************************************************/
|
|
|
308 |
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
|
|
|
309 |
|
|
|
310 |
SFR_16BIT(TAIV); /* Timer A Interrupt Vector Word */
|
|
|
311 |
SFR_16BIT(TACTL); /* Timer A Control */
|
|
|
312 |
SFR_16BIT(TACCTL0); /* Timer A Capture/Compare Control 0 */
|
|
|
313 |
SFR_16BIT(TACCTL1); /* Timer A Capture/Compare Control 1 */
|
|
|
314 |
SFR_16BIT(TACCTL2); /* Timer A Capture/Compare Control 2 */
|
|
|
315 |
SFR_16BIT(TAR); /* Timer A Counter Register */
|
|
|
316 |
SFR_16BIT(TACCR0); /* Timer A Capture/Compare 0 */
|
|
|
317 |
SFR_16BIT(TACCR1); /* Timer A Capture/Compare 1 */
|
|
|
318 |
SFR_16BIT(TACCR2); /* Timer A Capture/Compare 2 */
|
|
|
319 |
|
|
|
320 |
/* Alternate register names */
|
|
|
321 |
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
322 |
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
323 |
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
324 |
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
325 |
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
326 |
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
327 |
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
328 |
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
329 |
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
330 |
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
331 |
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
332 |
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
333 |
/* Alternate register names - 5xx style */
|
|
|
334 |
#define TA0IV TAIV /* Timer A Interrupt Vector Word */
|
|
|
335 |
#define TA0CTL TACTL /* Timer A Control */
|
|
|
336 |
#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
337 |
#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
338 |
#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
339 |
#define TA0R TAR /* Timer A Counter Register */
|
|
|
340 |
#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
341 |
#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
342 |
#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
343 |
#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */
|
|
|
344 |
#define TA0CTL_ TACTL_ /* Timer A Control */
|
|
|
345 |
#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
346 |
#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
347 |
#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
348 |
#define TA0R_ TAR_ /* Timer A Counter Register */
|
|
|
349 |
#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
350 |
#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
351 |
#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
352 |
|
|
|
353 |
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
|
|
|
354 |
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
|
|
|
355 |
#define ID1 (0x0080) /* Timer A clock input divider 1 */
|
|
|
356 |
#define ID0 (0x0040) /* Timer A clock input divider 0 */
|
|
|
357 |
#define MC1 (0x0020) /* Timer A mode control 1 */
|
|
|
358 |
#define MC0 (0x0010) /* Timer A mode control 0 */
|
|
|
359 |
#define TACLR (0x0004) /* Timer A counter clear */
|
|
|
360 |
#define TAIE (0x0002) /* Timer A counter interrupt enable */
|
|
|
361 |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
|
|
|
362 |
|
|
|
363 |
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
364 |
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
365 |
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
366 |
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
367 |
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
368 |
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
369 |
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
370 |
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
371 |
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
372 |
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
373 |
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
374 |
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
375 |
|
|
|
376 |
#define CM1 (0x8000) /* Capture mode 1 */
|
|
|
377 |
#define CM0 (0x4000) /* Capture mode 0 */
|
|
|
378 |
#define CCIS1 (0x2000) /* Capture input select 1 */
|
|
|
379 |
#define CCIS0 (0x1000) /* Capture input select 0 */
|
|
|
380 |
#define SCS (0x0800) /* Capture sychronize */
|
|
|
381 |
#define SCCI (0x0400) /* Latched capture signal (read) */
|
|
|
382 |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
|
|
|
383 |
#define OUTMOD2 (0x0080) /* Output mode 2 */
|
|
|
384 |
#define OUTMOD1 (0x0040) /* Output mode 1 */
|
|
|
385 |
#define OUTMOD0 (0x0020) /* Output mode 0 */
|
|
|
386 |
#define CCIE (0x0010) /* Capture/compare interrupt enable */
|
|
|
387 |
#define CCI (0x0008) /* Capture input signal (read) */
|
|
|
388 |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
|
|
|
389 |
#define COV (0x0002) /* Capture/compare overflow flag */
|
|
|
390 |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
|
|
|
391 |
|
|
|
392 |
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
|
|
|
393 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
|
|
|
394 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
|
|
|
395 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
|
|
|
396 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
|
|
|
397 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
|
|
|
398 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
|
|
|
399 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
|
|
|
400 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
|
|
|
401 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
|
|
|
402 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
|
|
|
403 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
|
|
|
404 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
|
|
|
405 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
|
|
|
406 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
|
|
|
407 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
|
|
|
408 |
|
|
|
409 |
/* TA3IV Definitions */
|
|
|
410 |
#define TAIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
411 |
#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */
|
|
|
412 |
#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */
|
|
|
413 |
#define TAIV_6 (0x0006) /* Reserved */
|
|
|
414 |
#define TAIV_8 (0x0008) /* Reserved */
|
|
|
415 |
#define TAIV_TAIFG (0x000A) /* TAIFG */
|
|
|
416 |
|
|
|
417 |
/************************************************************
|
|
|
418 |
* Basic Clock Module
|
|
|
419 |
************************************************************/
|
|
|
420 |
#define __MSP430_HAS_BASIC_CLOCK__ /* Definition to show that Module is available */
|
|
|
421 |
|
|
|
422 |
SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */
|
|
|
423 |
SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */
|
|
|
424 |
SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */
|
|
|
425 |
|
|
|
426 |
#define MOD0 (0x01) /* Modulation Bit 0 */
|
|
|
427 |
#define MOD1 (0x02) /* Modulation Bit 1 */
|
|
|
428 |
#define MOD2 (0x04) /* Modulation Bit 2 */
|
|
|
429 |
#define MOD3 (0x08) /* Modulation Bit 3 */
|
|
|
430 |
#define MOD4 (0x10) /* Modulation Bit 4 */
|
|
|
431 |
#define DCO0 (0x20) /* DCO Select Bit 0 */
|
|
|
432 |
#define DCO1 (0x40) /* DCO Select Bit 1 */
|
|
|
433 |
#define DCO2 (0x80) /* DCO Select Bit 2 */
|
|
|
434 |
|
|
|
435 |
#define RSEL0 (0x01) /* Range Select Bit 0 */
|
|
|
436 |
#define RSEL1 (0x02) /* Range Select Bit 1 */
|
|
|
437 |
#define RSEL2 (0x04) /* Range Select Bit 2 */
|
|
|
438 |
#define XT5V (0x08) /* XT5V should always be reset */
|
|
|
439 |
#define DIVA0 (0x10) /* ACLK Divider 0 */
|
|
|
440 |
#define DIVA1 (0x20) /* ACLK Divider 1 */
|
|
|
441 |
#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */
|
|
|
442 |
#define XT2OFF (0x80) /* Enable XT2CLK */
|
|
|
443 |
|
|
|
444 |
#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */
|
|
|
445 |
#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */
|
|
|
446 |
#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */
|
|
|
447 |
#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */
|
|
|
448 |
|
|
|
449 |
#define DCOR (0x01) /* Enable External Resistor : 1 */
|
|
|
450 |
#define DIVS0 (0x02) /* SMCLK Divider 0 */
|
|
|
451 |
#define DIVS1 (0x04) /* SMCLK Divider 1 */
|
|
|
452 |
#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
|
|
|
453 |
#define DIVM0 (0x10) /* MCLK Divider 0 */
|
|
|
454 |
#define DIVM1 (0x20) /* MCLK Divider 1 */
|
|
|
455 |
#define SELM0 (0x40) /* MCLK Source Select 0 */
|
|
|
456 |
#define SELM1 (0x80) /* MCLK Source Select 1 */
|
|
|
457 |
|
|
|
458 |
#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */
|
|
|
459 |
#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */
|
|
|
460 |
#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */
|
|
|
461 |
#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */
|
|
|
462 |
|
|
|
463 |
#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */
|
|
|
464 |
#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */
|
|
|
465 |
#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */
|
|
|
466 |
#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */
|
|
|
467 |
|
|
|
468 |
#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */
|
|
|
469 |
#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */
|
|
|
470 |
#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
|
|
|
471 |
#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */
|
|
|
472 |
|
|
|
473 |
/*************************************************************
|
|
|
474 |
* Flash Memory
|
|
|
475 |
*************************************************************/
|
|
|
476 |
#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
|
|
|
477 |
|
|
|
478 |
SFR_16BIT(FCTL1); /* FLASH Control 1 */
|
|
|
479 |
SFR_16BIT(FCTL2); /* FLASH Control 2 */
|
|
|
480 |
SFR_16BIT(FCTL3); /* FLASH Control 3 */
|
|
|
481 |
|
|
|
482 |
#define FRKEY (0x9600) /* Flash key returned by read */
|
|
|
483 |
#define FWKEY (0xA500) /* Flash key for write */
|
|
|
484 |
#define FXKEY (0x3300) /* for use with XOR instruction */
|
|
|
485 |
|
|
|
486 |
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
|
|
|
487 |
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
|
|
|
488 |
#define WRT (0x0040) /* Enable bit for Flash write */
|
|
|
489 |
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
|
|
|
490 |
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
|
|
|
491 |
|
|
|
492 |
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
|
|
|
493 |
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
|
|
|
494 |
#ifndef FN2
|
|
|
495 |
#define FN2 (0x0004)
|
|
|
496 |
#endif
|
|
|
497 |
#ifndef FN3
|
|
|
498 |
#define FN3 (0x0008)
|
|
|
499 |
#endif
|
|
|
500 |
#ifndef FN4
|
|
|
501 |
#define FN4 (0x0010)
|
|
|
502 |
#endif
|
|
|
503 |
#define FN5 (0x0020)
|
|
|
504 |
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
|
|
|
505 |
#define FSSEL1 (0x0080) /* Flash clock select 1 */
|
|
|
506 |
|
|
|
507 |
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
|
|
|
508 |
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
|
|
|
509 |
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
|
|
|
510 |
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
|
|
|
511 |
|
|
|
512 |
#define BUSY (0x0001) /* Flash busy: 1 */
|
|
|
513 |
#define KEYV (0x0002) /* Flash Key violation flag */
|
|
|
514 |
#define ACCVIFG (0x0004) /* Flash Access violation flag */
|
|
|
515 |
#define WAIT (0x0008) /* Wait flag for segment write */
|
|
|
516 |
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
517 |
#define EMEX (0x0020) /* Flash Emergency Exit */
|
|
|
518 |
|
|
|
519 |
/************************************************************
|
|
|
520 |
* ADC10
|
|
|
521 |
************************************************************/
|
|
|
522 |
#define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */
|
|
|
523 |
|
|
|
524 |
SFR_8BIT(ADC10DTC0); /* ADC10 Data Transfer Control 0 */
|
|
|
525 |
SFR_8BIT(ADC10DTC1); /* ADC10 Data Transfer Control 1 */
|
|
|
526 |
SFR_8BIT(ADC10AE); /* ADC10 Analog Enable */
|
|
|
527 |
|
|
|
528 |
SFR_16BIT(ADC10CTL0); /* ADC10 Control 0 */
|
|
|
529 |
SFR_16BIT(ADC10CTL1); /* ADC10 Control 1 */
|
|
|
530 |
SFR_16BIT(ADC10MEM); /* ADC10 Memory */
|
|
|
531 |
SFR_16BIT(ADC10SA); /* ADC10 Data Transfer Start Address */
|
|
|
532 |
|
|
|
533 |
/* ADC10CTL0 */
|
|
|
534 |
#define ADC10SC (0x001) /* ADC10 Start Conversion */
|
|
|
535 |
#define ENC (0x002) /* ADC10 Enable Conversion */
|
|
|
536 |
#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */
|
|
|
537 |
#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */
|
|
|
538 |
#define ADC10ON (0x010) /* ADC10 On/Enable */
|
|
|
539 |
#define REFON (0x020) /* ADC10 Reference on */
|
|
|
540 |
#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */
|
|
|
541 |
#define MSC (0x080) /* ADC10 Multiple SampleConversion */
|
|
|
542 |
#define REFBURST (0x100) /* ADC10 Reference Burst Mode */
|
|
|
543 |
#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */
|
|
|
544 |
#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */
|
|
|
545 |
#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */
|
|
|
546 |
#define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select Bit: 1 */
|
|
|
547 |
#define SREF0 (0x2000) /* ADC10 Reference Select Bit: 0 */
|
|
|
548 |
#define SREF1 (0x4000) /* ADC10 Reference Select Bit: 1 */
|
|
|
549 |
#define SREF2 (0x8000) /* ADC10 Reference Select Bit: 2 */
|
|
|
550 |
#define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */
|
|
|
551 |
#define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */
|
|
|
552 |
#define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */
|
|
|
553 |
#define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */
|
|
|
554 |
|
|
|
555 |
#define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */
|
|
|
556 |
#define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */
|
|
|
557 |
#define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
|
|
|
558 |
#define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
|
|
|
559 |
#define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */
|
|
|
560 |
#define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */
|
|
|
561 |
#define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
|
|
|
562 |
#define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
|
|
|
563 |
|
|
|
564 |
/* ADC10CTL1 */
|
|
|
565 |
#define ADC10BUSY (0x0001) /* ADC10 BUSY */
|
|
|
566 |
#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */
|
|
|
567 |
#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */
|
|
|
568 |
#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select Bit: 0 */
|
|
|
569 |
#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select Bit: 1 */
|
|
|
570 |
#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select Bit: 0 */
|
|
|
571 |
#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select Bit: 1 */
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|
|
572 |
#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select Bit: 2 */
|
|
|
573 |
#define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */
|
|
|
574 |
#define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */
|
|
|
575 |
#define SHS0 (0x0400) /* ADC10 Sample/Hold Source Bit: 0 */
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|
|
576 |
#define SHS1 (0x0800) /* ADC10 Sample/Hold Source Bit: 1 */
|
|
|
577 |
#define INCH0 (0x1000) /* ADC10 Input Channel Select Bit: 0 */
|
|
|
578 |
#define INCH1 (0x2000) /* ADC10 Input Channel Select Bit: 1 */
|
|
|
579 |
#define INCH2 (0x4000) /* ADC10 Input Channel Select Bit: 2 */
|
|
|
580 |
#define INCH3 (0x8000) /* ADC10 Input Channel Select Bit: 3 */
|
|
|
581 |
|
|
|
582 |
#define CONSEQ_0 (0*2u) /* Single channel single conversion */
|
|
|
583 |
#define CONSEQ_1 (1*2u) /* Sequence of channels */
|
|
|
584 |
#define CONSEQ_2 (2*2u) /* Repeat single channel */
|
|
|
585 |
#define CONSEQ_3 (3*2u) /* Repeat sequence of channels */
|
|
|
586 |
|
|
|
587 |
#define ADC10SSEL_0 (0*8u) /* ADC10OSC */
|
|
|
588 |
#define ADC10SSEL_1 (1*8u) /* ACLK */
|
|
|
589 |
#define ADC10SSEL_2 (2*8u) /* MCLK */
|
|
|
590 |
#define ADC10SSEL_3 (3*8u) /* SMCLK */
|
|
|
591 |
|
|
|
592 |
#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */
|
|
|
593 |
#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select 1 */
|
|
|
594 |
#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select 2 */
|
|
|
595 |
#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select 3 */
|
|
|
596 |
#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select 4 */
|
|
|
597 |
#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select 5 */
|
|
|
598 |
#define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select 6 */
|
|
|
599 |
#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select 7 */
|
|
|
600 |
|
|
|
601 |
#define SHS_0 (0*0x400u) /* ADC10SC */
|
|
|
602 |
#define SHS_1 (1*0x400u) /* TA3 OUT1 */
|
|
|
603 |
#define SHS_2 (2*0x400u) /* TA3 OUT0 */
|
|
|
604 |
#define SHS_3 (3*0x400u) /* TA3 OUT2 */
|
|
|
605 |
|
|
|
606 |
#define INCH_0 (0*0x1000u) /* Selects Channel 0 */
|
|
|
607 |
#define INCH_1 (1*0x1000u) /* Selects Channel 1 */
|
|
|
608 |
#define INCH_2 (2*0x1000u) /* Selects Channel 2 */
|
|
|
609 |
#define INCH_3 (3*0x1000u) /* Selects Channel 3 */
|
|
|
610 |
#define INCH_4 (4*0x1000u) /* Selects Channel 4 */
|
|
|
611 |
#define INCH_5 (5*0x1000u) /* Selects Channel 5 */
|
|
|
612 |
#define INCH_6 (6*0x1000u) /* Selects Channel 6 */
|
|
|
613 |
#define INCH_7 (7*0x1000u) /* Selects Channel 7 */
|
|
|
614 |
#define INCH_8 (8*0x1000u) /* Selects Channel 8 */
|
|
|
615 |
#define INCH_9 (9*0x1000u) /* Selects Channel 9 */
|
|
|
616 |
#define INCH_10 (10*0x1000u) /* Selects Channel 10 */
|
|
|
617 |
#define INCH_11 (11*0x1000u) /* Selects Channel 11 */
|
|
|
618 |
#define INCH_12 (12*0x1000u) /* Selects Channel 12 */
|
|
|
619 |
#define INCH_13 (13*0x1000u) /* Selects Channel 13 */
|
|
|
620 |
#define INCH_14 (14*0x1000u) /* Selects Channel 14 */
|
|
|
621 |
#define INCH_15 (15*0x1000u) /* Selects Channel 15 */
|
|
|
622 |
|
|
|
623 |
/* ADC10DTC0 */
|
|
|
624 |
#define ADC10FETCH (0x001) /* This bit should normally be reset */
|
|
|
625 |
#define ADC10B1 (0x002) /* ADC10 block one */
|
|
|
626 |
#define ADC10CT (0x004) /* ADC10 continuous transfer */
|
|
|
627 |
#define ADC10TB (0x008) /* ADC10 two-block mode */
|
|
|
628 |
#define ADC10DISABLE (0x000) /* ADC10DTC1 */
|
|
|
629 |
|
|
|
630 |
/* ADC10AE */
|
|
|
631 |
#define ADC10AE0 (0x0001) /* ADC10 External Input Enable 0 */
|
|
|
632 |
#define ADC10AE1 (0x0002) /* ADC10 External Input Enable 1 */
|
|
|
633 |
#define ADC10AE2 (0x0004) /* ADC10 External Input Enable 2 */
|
|
|
634 |
#define ADC10AE3 (0x0008) /* ADC10 External Input Enable 3 */
|
|
|
635 |
#define ADC10AE4 (0x0010) /* ADC10 External Input Enable 4 */
|
|
|
636 |
#define ADC10AE5 (0x0020) /* ADC10 External Input Enable 5 */
|
|
|
637 |
#define ADC10AE6 (0x0040) /* ADC10 External Input Enable 6 */
|
|
|
638 |
#define ADC10AE7 (0x0080) /* ADC10 External Input Enable 7 */
|
|
|
639 |
|
|
|
640 |
/************************************************************
|
|
|
641 |
* Interrupt Vectors (offset from 0xFFE0)
|
|
|
642 |
************************************************************/
|
|
|
643 |
|
|
|
644 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
645 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
646 |
#define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name
|
|
|
647 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
648 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
649 |
PLACE_VECTOR(VECTOR_NAME(func), offset)
|
|
|
650 |
|
|
|
651 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
652 |
#define PORT1_VECTOR ".int02" /* 0xFFE4 Port 1 */
|
|
|
653 |
#else
|
|
|
654 |
#define PORT1_VECTOR (2 * 1u) /* 0xFFE4 Port 1 */
|
|
|
655 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int02") */ /* 0xFFE4 Port 1 */ /* CCE V2 Style */
|
|
|
656 |
#endif
|
|
|
657 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
658 |
#define PORT2_VECTOR ".int03" /* 0xFFE6 Port 2 */
|
|
|
659 |
#else
|
|
|
660 |
#define PORT2_VECTOR (3 * 1u) /* 0xFFE6 Port 2 */
|
|
|
661 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int03") */ /* 0xFFE6 Port 2 */ /* CCE V2 Style */
|
|
|
662 |
#endif
|
|
|
663 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
664 |
#define ADC10_VECTOR ".int05" /* 0xFFEA ADC10 */
|
|
|
665 |
#else
|
|
|
666 |
#define ADC10_VECTOR (5 * 1u) /* 0xFFEA ADC10 */
|
|
|
667 |
/*#define ADC10_ISR(func) ISR_VECTOR(func, ".int05") */ /* 0xFFEA ADC10 */ /* CCE V2 Style */
|
|
|
668 |
#endif
|
|
|
669 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
670 |
#define USART0TX_VECTOR ".int06" /* 0xFFEC USART 0 Transmit */
|
|
|
671 |
#else
|
|
|
672 |
#define USART0TX_VECTOR (6 * 1u) /* 0xFFEC USART 0 Transmit */
|
|
|
673 |
/*#define USART0TX_ISR(func) ISR_VECTOR(func, ".int06") */ /* 0xFFEC USART 0 Transmit */ /* CCE V2 Style */
|
|
|
674 |
#endif
|
|
|
675 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
676 |
#define USART0RX_VECTOR ".int07" /* 0xFFEE USART 0 Receive */
|
|
|
677 |
#else
|
|
|
678 |
#define USART0RX_VECTOR (7 * 1u) /* 0xFFEE USART 0 Receive */
|
|
|
679 |
/*#define USART0RX_ISR(func) ISR_VECTOR(func, ".int07") */ /* 0xFFEE USART 0 Receive */ /* CCE V2 Style */
|
|
|
680 |
#endif
|
|
|
681 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
682 |
#define TIMERA1_VECTOR ".int08" /* 0xFFF0 Timer A CC1-2, TA */
|
|
|
683 |
#else
|
|
|
684 |
#define TIMERA1_VECTOR (8 * 1u) /* 0xFFF0 Timer A CC1-2, TA */
|
|
|
685 |
/*#define TIMERA1_ISR(func) ISR_VECTOR(func, ".int08") */ /* 0xFFF0 Timer A CC1-2, TA */ /* CCE V2 Style */
|
|
|
686 |
#endif
|
|
|
687 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
688 |
#define TIMERA0_VECTOR ".int09" /* 0xFFF2 Timer A CC0 */
|
|
|
689 |
#else
|
|
|
690 |
#define TIMERA0_VECTOR (9 * 1u) /* 0xFFF2 Timer A CC0 */
|
|
|
691 |
/*#define TIMERA0_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 Timer A CC0 */ /* CCE V2 Style */
|
|
|
692 |
#endif
|
|
|
693 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
694 |
#define WDT_VECTOR ".int10" /* 0xFFF4 Watchdog Timer */
|
|
|
695 |
#else
|
|
|
696 |
#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */
|
|
|
697 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
|
|
|
698 |
#endif
|
|
|
699 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
700 |
#define NMI_VECTOR ".int14" /* 0xFFFC Non-maskable */
|
|
|
701 |
#else
|
|
|
702 |
#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */
|
|
|
703 |
/*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
|
|
|
704 |
#endif
|
|
|
705 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
706 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
707 |
#else
|
|
|
708 |
#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
709 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
710 |
#endif
|
|
|
711 |
|
|
|
712 |
|
|
|
713 |
/************************************************************
|
|
|
714 |
* End of Modules
|
|
|
715 |
************************************************************/
|
|
|
716 |
|
|
|
717 |
#ifdef __cplusplus
|
|
|
718 |
}
|
|
|
719 |
#endif /* extern "C" */
|
|
|
720 |
|
|
|
721 |
#endif /* #ifndef __msp430x12x2 */
|
|
|
722 |
|