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/******************************************************************************/
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/* Legacy Header File */
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/* Not recommended for use in new projects. */
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/* Please use the msp430.h file or the device specific header file */
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/******************************************************************************/
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* MSP430x11x devices.
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*
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* Texas Instruments, Version 2.3
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*
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* Rev. 1.2, Additional Timer B bit definitions.
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* Renamed XTOFF to XT2OFF.
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* Rev. 1.3, Removed leading 0 to aviod interpretation as octal
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* values under C
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* Rev. 1.4, Corrected LPMx_EXIT to reference new intrinsic _bic_SR_register_on_exit
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* Changed TAIV to be read-only
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* Rev. 1.5, Enclose all #define statements with parentheses
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* Rev. 2.1, Alignment of defintions in Users Guide and of version numbers
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* Rev. 2.2, Removed unused def of TASSEL2
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* Rev. 2.3, added definitions for Interrupt Vectors xxIV
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*
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********************************************************************/
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#ifndef __msp430x11x
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#define __msp430x11x
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
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************************************************************/
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SFR_8BIT(IE1); /* Interrupt Enable 1 */
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#define WDTIE (0x01)
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#define OFIE (0x02)
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#define NMIIE (0x10)
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#define ACCVIE (0x20)
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SFR_8BIT(IFG1); /* Interrupt Flag 1 */
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#define WDTIFG (0x01)
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#define OFIFG (0x02)
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#define NMIIFG (0x10)
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/************************************************************
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* WATCHDOG TIMER
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************************************************************/
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#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
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SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
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/* The bit names have been prefixed with "WDT" */
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#define WDTIS0 (0x0001)
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#define WDTIS1 (0x0002)
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#define WDTSSEL (0x0004)
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#define WDTCNTCL (0x0008)
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#define WDTTMSEL (0x0010)
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#define WDTNMI (0x0020)
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#define WDTNMIES (0x0040)
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#define WDTHOLD (0x0080)
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#define WDTPW (0x5A00)
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/* WDT-interval times [1ms] coded with Bits 0-2 */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* Watchdog mode -> reset after expired time */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* INTERRUPT CONTROL */
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/* These two bits are defined in the Special Function Registers */
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/* #define WDTIE 0x01 */
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/* #define WDTIFG 0x01 */
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/************************************************************
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* DIGITAL I/O Port1/2
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************************************************************/
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#define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */
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#define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */
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SFR_8BIT(P1IN); /* Port 1 Input */
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SFR_8BIT(P1OUT); /* Port 1 Output */
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SFR_8BIT(P1DIR); /* Port 1 Direction */
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SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */
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SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */
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SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */
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SFR_8BIT(P1SEL); /* Port 1 Selection */
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SFR_8BIT(P2IN); /* Port 2 Input */
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SFR_8BIT(P2OUT); /* Port 2 Output */
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SFR_8BIT(P2DIR); /* Port 2 Direction */
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SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */
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SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */
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SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */
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SFR_8BIT(P2SEL); /* Port 2 Selection */
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/************************************************************
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* Timer A3
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************************************************************/
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#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
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SFR_16BIT(TAIV); /* Timer A Interrupt Vector Word */
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SFR_16BIT(TACTL); /* Timer A Control */
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SFR_16BIT(TACCTL0); /* Timer A Capture/Compare Control 0 */
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SFR_16BIT(TACCTL1); /* Timer A Capture/Compare Control 1 */
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SFR_16BIT(TACCTL2); /* Timer A Capture/Compare Control 2 */
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SFR_16BIT(TAR); /* Timer A Counter Register */
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SFR_16BIT(TACCR0); /* Timer A Capture/Compare 0 */
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SFR_16BIT(TACCR1); /* Timer A Capture/Compare 1 */
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SFR_16BIT(TACCR2); /* Timer A Capture/Compare 2 */
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/* Alternate register names */
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#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
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#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
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#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
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#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
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#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
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#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
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#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
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#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
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#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
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#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
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#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
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#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
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/* Alternate register names - 5xx style */
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#define TA0IV TAIV /* Timer A Interrupt Vector Word */
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#define TA0CTL TACTL /* Timer A Control */
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#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
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#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
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#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
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#define TA0R TAR /* Timer A Counter Register */
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#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */
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#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */
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#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */
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#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */
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#define TA0CTL_ TACTL_ /* Timer A Control */
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#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
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#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
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#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
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#define TA0R_ TAR_ /* Timer A Counter Register */
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#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
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#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
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#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
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#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
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#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
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#define ID1 (0x0080) /* Timer A clock input divider 1 */
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#define ID0 (0x0040) /* Timer A clock input divider 0 */
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#define MC1 (0x0020) /* Timer A mode control 1 */
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#define MC0 (0x0010) /* Timer A mode control 0 */
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#define TACLR (0x0004) /* Timer A counter clear */
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#define TAIE (0x0002) /* Timer A counter interrupt enable */
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#define TAIFG (0x0001) /* Timer A counter interrupt flag */
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#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
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#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
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#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
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#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
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#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
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#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
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#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
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#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
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#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
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#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
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#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
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#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
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#define CM1 (0x8000) /* Capture mode 1 */
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#define CM0 (0x4000) /* Capture mode 0 */
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#define CCIS1 (0x2000) /* Capture input select 1 */
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#define CCIS0 (0x1000) /* Capture input select 0 */
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#define SCS (0x0800) /* Capture sychronize */
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#define SCCI (0x0400) /* Latched capture signal (read) */
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#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
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#define OUTMOD2 (0x0080) /* Output mode 2 */
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#define OUTMOD1 (0x0040) /* Output mode 1 */
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#define OUTMOD0 (0x0020) /* Output mode 0 */
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#define CCIE (0x0010) /* Capture/compare interrupt enable */
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#define CCI (0x0008) /* Capture input signal (read) */
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#define OUT (0x0004) /* PWM Output signal if output mode 0 */
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#define COV (0x0002) /* Capture/compare overflow flag */
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#define CCIFG (0x0001) /* Capture/compare interrupt flag */
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#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
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288 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
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289 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
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290 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
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291 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
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292 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
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|
293 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
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|
294 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
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|
295 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
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|
296 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
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|
297 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
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|
298 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
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|
299 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
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|
300 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
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|
301 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
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|
302 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
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303 |
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|
304 |
/* TA3IV Definitions */
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|
|
305 |
#define TAIV_NONE (0x0000) /* No Interrupt pending */
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|
306 |
#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */
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|
307 |
#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */
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|
308 |
#define TAIV_6 (0x0006) /* Reserved */
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|
309 |
#define TAIV_8 (0x0008) /* Reserved */
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|
310 |
#define TAIV_TAIFG (0x000A) /* TAIFG */
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|
311 |
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|
312 |
/************************************************************
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|
313 |
* Basic Clock Module
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|
|
314 |
************************************************************/
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|
315 |
#define __MSP430_HAS_BASIC_CLOCK__ /* Definition to show that Module is available */
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|
316 |
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|
317 |
SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */
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|
318 |
SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */
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|
319 |
SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */
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|
320 |
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|
321 |
#define MOD0 (0x01) /* Modulation Bit 0 */
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|
322 |
#define MOD1 (0x02) /* Modulation Bit 1 */
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|
323 |
#define MOD2 (0x04) /* Modulation Bit 2 */
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|
324 |
#define MOD3 (0x08) /* Modulation Bit 3 */
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|
325 |
#define MOD4 (0x10) /* Modulation Bit 4 */
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|
326 |
#define DCO0 (0x20) /* DCO Select Bit 0 */
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|
327 |
#define DCO1 (0x40) /* DCO Select Bit 1 */
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|
328 |
#define DCO2 (0x80) /* DCO Select Bit 2 */
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|
329 |
|
|
|
330 |
#define RSEL0 (0x01) /* Range Select Bit 0 */
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|
331 |
#define RSEL1 (0x02) /* Range Select Bit 1 */
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|
332 |
#define RSEL2 (0x04) /* Range Select Bit 2 */
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|
333 |
#define XT5V (0x08) /* XT5V should always be reset */
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|
334 |
#define DIVA0 (0x10) /* ACLK Divider 0 */
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|
335 |
#define DIVA1 (0x20) /* ACLK Divider 1 */
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|
336 |
#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */
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|
337 |
#define XT2OFF (0x80) /* Enable XT2CLK */
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|
338 |
|
|
|
339 |
#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */
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|
|
340 |
#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */
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|
|
341 |
#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */
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|
|
342 |
#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */
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|
|
343 |
|
|
|
344 |
#define DCOR (0x01) /* Enable External Resistor : 1 */
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|
|
345 |
#define DIVS0 (0x02) /* SMCLK Divider 0 */
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|
|
346 |
#define DIVS1 (0x04) /* SMCLK Divider 1 */
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|
|
347 |
#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
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|
|
348 |
#define DIVM0 (0x10) /* MCLK Divider 0 */
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|
|
349 |
#define DIVM1 (0x20) /* MCLK Divider 1 */
|
|
|
350 |
#define SELM0 (0x40) /* MCLK Source Select 0 */
|
|
|
351 |
#define SELM1 (0x80) /* MCLK Source Select 1 */
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|
|
352 |
|
|
|
353 |
#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */
|
|
|
354 |
#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */
|
|
|
355 |
#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */
|
|
|
356 |
#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */
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|
|
357 |
|
|
|
358 |
#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */
|
|
|
359 |
#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */
|
|
|
360 |
#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */
|
|
|
361 |
#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */
|
|
|
362 |
|
|
|
363 |
#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */
|
|
|
364 |
#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */
|
|
|
365 |
#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
|
|
|
366 |
#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */
|
|
|
367 |
|
|
|
368 |
/*************************************************************
|
|
|
369 |
* Flash Memory
|
|
|
370 |
*************************************************************/
|
|
|
371 |
#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
|
|
|
372 |
|
|
|
373 |
SFR_16BIT(FCTL1); /* FLASH Control 1 */
|
|
|
374 |
SFR_16BIT(FCTL2); /* FLASH Control 2 */
|
|
|
375 |
SFR_16BIT(FCTL3); /* FLASH Control 3 */
|
|
|
376 |
|
|
|
377 |
#define FRKEY (0x9600) /* Flash key returned by read */
|
|
|
378 |
#define FWKEY (0xA500) /* Flash key for write */
|
|
|
379 |
#define FXKEY (0x3300) /* for use with XOR instruction */
|
|
|
380 |
|
|
|
381 |
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
|
|
|
382 |
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
|
|
|
383 |
#define WRT (0x0040) /* Enable bit for Flash write */
|
|
|
384 |
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
|
|
|
385 |
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
|
|
|
386 |
|
|
|
387 |
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
|
|
|
388 |
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
|
|
|
389 |
#ifndef FN2
|
|
|
390 |
#define FN2 (0x0004)
|
|
|
391 |
#endif
|
|
|
392 |
#ifndef FN3
|
|
|
393 |
#define FN3 (0x0008)
|
|
|
394 |
#endif
|
|
|
395 |
#ifndef FN4
|
|
|
396 |
#define FN4 (0x0010)
|
|
|
397 |
#endif
|
|
|
398 |
#define FN5 (0x0020)
|
|
|
399 |
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
|
|
|
400 |
#define FSSEL1 (0x0080) /* Flash clock select 1 */
|
|
|
401 |
|
|
|
402 |
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
|
|
|
403 |
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
|
|
|
404 |
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
|
|
|
405 |
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
|
|
|
406 |
|
|
|
407 |
#define BUSY (0x0001) /* Flash busy: 1 */
|
|
|
408 |
#define KEYV (0x0002) /* Flash Key violation flag */
|
|
|
409 |
#define ACCVIFG (0x0004) /* Flash Access violation flag */
|
|
|
410 |
#define WAIT (0x0008) /* Wait flag for segment write */
|
|
|
411 |
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
412 |
#define EMEX (0x0020) /* Flash Emergency Exit */
|
|
|
413 |
|
|
|
414 |
/************************************************************
|
|
|
415 |
* EPROM CONTROL
|
|
|
416 |
************************************************************/
|
|
|
417 |
#define __MSP430_HAS_EPROM__ /* Definition to show that Module is available */
|
|
|
418 |
|
|
|
419 |
SFR_8BIT(EPCTL); /* EPROM Control */
|
|
|
420 |
#define EPEXE (0x01)
|
|
|
421 |
#define EPVPPS (0x02)
|
|
|
422 |
|
|
|
423 |
/************************************************************
|
|
|
424 |
* Interrupt Vectors (offset from 0xFFE0)
|
|
|
425 |
************************************************************/
|
|
|
426 |
|
|
|
427 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
428 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
429 |
#define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name
|
|
|
430 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
431 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
432 |
PLACE_VECTOR(VECTOR_NAME(func), offset)
|
|
|
433 |
|
|
|
434 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
435 |
#define PORT1_VECTOR ".int02" /* 0xFFE4 Port 1 */
|
|
|
436 |
#else
|
|
|
437 |
#define PORT1_VECTOR (2 * 1u) /* 0xFFE4 Port 1 */
|
|
|
438 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int02") */ /* 0xFFE4 Port 1 */ /* CCE V2 Style */
|
|
|
439 |
#endif
|
|
|
440 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
441 |
#define PORT2_VECTOR ".int03" /* 0xFFE6 Port 2 */
|
|
|
442 |
#else
|
|
|
443 |
#define PORT2_VECTOR (3 * 1u) /* 0xFFE6 Port 2 */
|
|
|
444 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int03") */ /* 0xFFE6 Port 2 */ /* CCE V2 Style */
|
|
|
445 |
#endif
|
|
|
446 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
447 |
#define TIMERA1_VECTOR ".int08" /* 0xFFF0 Timer A CC1-2, TA */
|
|
|
448 |
#else
|
|
|
449 |
#define TIMERA1_VECTOR (8 * 1u) /* 0xFFF0 Timer A CC1-2, TA */
|
|
|
450 |
/*#define TIMERA1_ISR(func) ISR_VECTOR(func, ".int08") */ /* 0xFFF0 Timer A CC1-2, TA */ /* CCE V2 Style */
|
|
|
451 |
#endif
|
|
|
452 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
453 |
#define TIMERA0_VECTOR ".int09" /* 0xFFF2 Timer A CC0 */
|
|
|
454 |
#else
|
|
|
455 |
#define TIMERA0_VECTOR (9 * 1u) /* 0xFFF2 Timer A CC0 */
|
|
|
456 |
/*#define TIMERA0_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 Timer A CC0 */ /* CCE V2 Style */
|
|
|
457 |
#endif
|
|
|
458 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
459 |
#define WDT_VECTOR ".int10" /* 0xFFF4 Watchdog Timer */
|
|
|
460 |
#else
|
|
|
461 |
#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */
|
|
|
462 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
|
|
|
463 |
#endif
|
|
|
464 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
465 |
#define NMI_VECTOR ".int14" /* 0xFFFC Non-maskable */
|
|
|
466 |
#else
|
|
|
467 |
#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */
|
|
|
468 |
/*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
|
|
|
469 |
#endif
|
|
|
470 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
471 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
472 |
#else
|
|
|
473 |
#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
474 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
475 |
#endif
|
|
|
476 |
|
|
|
477 |
/************************************************************
|
|
|
478 |
* End of Modules
|
|
|
479 |
************************************************************/
|
|
|
480 |
|
|
|
481 |
#ifdef __cplusplus
|
|
|
482 |
}
|
|
|
483 |
#endif /* extern "C" */
|
|
|
484 |
|
|
|
485 |
#endif /* #ifndef __msp430x11x */
|
|
|
486 |
|