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dpurdie |
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* MSP430xW42x devices.
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*
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* Texas Instruments, Version 2.8
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*
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* Rev. 2.1, Alignment of defintions in Users Guide and of version numbers
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* Rev. 2.11, Added SIFDACR
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* Added unsigned to SIFTSM definition
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* Rev. 2.2, Alignment of defintions in Users Guide and of version numbers
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* Rev. 2.21, Changed Bitname form SIFLCOFF to SIFLCEN
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* Removed definition of LCDLOWR (not available at 4xx devices)
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* Rev. 2.30, fixed Register name type from SIFTPSMV to SIFPSMV
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* Rev. 2.31, fixed Register name for SIFDIV3_x (Dividor is *2)
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* Rev. 2.4, Removed unused def of TASSEL2 / TBSSEL2
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* Rev. 2.5, Added VLD bits in SVS module
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* Rev. 2.6, Removed definitions for BTRESET
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* Rev. 2.7, Fixed some errors in SIFDIV3_xx definitions
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* Rev. 2.8, added definitions for Interrupt Vectors xxIV
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*
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********************************************************************/
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#ifndef __msp430xW42x
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#define __msp430xW42x
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
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************************************************************/
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SFR_8BIT(IE1); /* Interrupt Enable 1 */
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#define WDTIE (0x01)
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#define OFIE (0x02)
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#define NMIIE (0x10)
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#define ACCVIE (0x20)
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SFR_8BIT(IFG1); /* Interrupt Flag 1 */
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#define WDTIFG (0x01)
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#define OFIFG (0x02)
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#define NMIIFG (0x10)
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SFR_8BIT(IE2); /* Interrupt Enable 2 */
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#define BTIE (0x80)
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SFR_8BIT(IFG2); /* Interrupt Flag 2 */
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#define BTIFG (0x80)
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/************************************************************
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* WATCHDOG TIMER
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************************************************************/
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#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
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SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
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/* The bit names have been prefixed with "WDT" */
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#define WDTIS0 (0x0001)
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#define WDTIS1 (0x0002)
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#define WDTSSEL (0x0004)
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#define WDTCNTCL (0x0008)
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#define WDTTMSEL (0x0010)
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#define WDTNMI (0x0020)
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#define WDTNMIES (0x0040)
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#define WDTHOLD (0x0080)
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#define WDTPW (0x5A00)
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/* WDT-interval times [1ms] coded with Bits 0-2 */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* Watchdog mode -> reset after expired time */
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/* WDT is clocked by fSMCLK (assumed 1MHz) */
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#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
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#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
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#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
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#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
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/* WDT is clocked by fACLK (assumed 32KHz) */
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#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
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#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
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#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
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#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
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/* INTERRUPT CONTROL */
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/* These two bits are defined in the Special Function Registers */
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/* #define WDTIE 0x01 */
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/* #define WDTIFG 0x01 */
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/************************************************************
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* DIGITAL I/O Port1/2
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************************************************************/
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#define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */
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#define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */
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SFR_8BIT(P1IN); /* Port 1 Input */
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SFR_8BIT(P1OUT); /* Port 1 Output */
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SFR_8BIT(P1DIR); /* Port 1 Direction */
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SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */
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SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */
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SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */
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SFR_8BIT(P1SEL); /* Port 1 Selection */
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SFR_8BIT(P2IN); /* Port 2 Input */
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SFR_8BIT(P2OUT); /* Port 2 Output */
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SFR_8BIT(P2DIR); /* Port 2 Direction */
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SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */
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SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */
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SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */
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SFR_8BIT(P2SEL); /* Port 2 Selection */
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/************************************************************
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* DIGITAL I/O Port3/4
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************************************************************/
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#define __MSP430_HAS_PORT3__ /* Definition to show that Module is available */
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#define __MSP430_HAS_PORT4__ /* Definition to show that Module is available */
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SFR_8BIT(P3IN); /* Port 3 Input */
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SFR_8BIT(P3OUT); /* Port 3 Output */
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SFR_8BIT(P3DIR); /* Port 3 Direction */
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SFR_8BIT(P3SEL); /* Port 3 Selection */
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SFR_8BIT(P4IN); /* Port 4 Input */
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SFR_8BIT(P4OUT); /* Port 4 Output */
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SFR_8BIT(P4DIR); /* Port 4 Direction */
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SFR_8BIT(P4SEL); /* Port 4 Selection */
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/************************************************************
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* DIGITAL I/O Port5/6
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************************************************************/
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#define __MSP430_HAS_PORT5__ /* Definition to show that Module is available */
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#define __MSP430_HAS_PORT6__ /* Definition to show that Module is available */
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SFR_8BIT(P5IN); /* Port 5 Input */
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SFR_8BIT(P5OUT); /* Port 5 Output */
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SFR_8BIT(P5DIR); /* Port 5 Direction */
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SFR_8BIT(P5SEL); /* Port 5 Selection */
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SFR_8BIT(P6IN); /* Port 6 Input */
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SFR_8BIT(P6OUT); /* Port 6 Output */
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SFR_8BIT(P6DIR); /* Port 6 Direction */
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SFR_8BIT(P6SEL); /* Port 6 Selection */
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/************************************************************
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* BASIC TIMER
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************************************************************/
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#define __MSP430_HAS_BT__ /* Definition to show that Module is available */
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SFR_8BIT(BTCTL); /* Basic Timer Control */
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/* The bit names have been prefixed with "BT" */
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#define BTIP0 (0x01)
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#define BTIP1 (0x02)
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#define BTIP2 (0x04)
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#define BTFRFQ0 (0x08)
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#define BTFRFQ1 (0x10)
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#define BTDIV (0x20) /* fCLK2 = ACLK:256 */
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#define BTHOLD (0x40) /* BT1 is held if this bit is set */
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#define BTSSEL (0x80) /* fBT = fMCLK (main clock) */
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SFR_8BIT(BTCNT1); /* Basic Timer Count 1 */
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SFR_8BIT(BTCNT2); /* Basic Timer Count 2 */
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/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
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#define BT_fCLK2_ACLK (0x00)
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#define BT_fCLK2_ACLK_DIV256 (BTDIV)
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#define BT_fCLK2_MCLK (BTSSEL)
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/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
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#define BT_fCLK2_DIV2 (0x00) /* fINT = fCLK2:2 (default) */
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#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */
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#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */
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#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT = fCLK2:16 */
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#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */
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#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT = fCLK2:64 */
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#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT = fCLK2:128 */
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#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 */
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/* Frequency of LCD coded with Bits 3-4 */
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#define BT_fLCD_DIV32 (0x00) /* fLCD = fACLK:32 (default) */
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#define BT_fLCD_DIV64 (BTFRFQ0) /* fLCD = fACLK:64 */
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#define BT_fLCD_DIV128 (BTFRFQ1) /* fLCD = fACLK:128 */
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#define BT_fLCD_DIV256 (BTFRFQ1+BTFRFQ0) /* fLCD = fACLK:256 */
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/* LCD frequency values with fBT=fACLK */
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#define BT_fLCD_1K (0x00) /* fACLK:32 (default) */
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#define BT_fLCD_512 (BTFRFQ0) /* fACLK:64 */
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#define BT_fLCD_256 (BTFRFQ1) /* fACLK:128 */
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#define BT_fLCD_128 (BTFRFQ1+BTFRFQ0) /* fACLK:256 */
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/* LCD frequency values with fBT=fMCLK */
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#define BT_fLCD_31K (BTSSEL) /* fMCLK:32 */
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#define BT_fLCD_15_5K (BTSSEL+BTFRFQ0) /* fMCLK:64 */
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#define BT_fLCD_7_8K (BTSSEL+BTFRFQ1+BTFRFQ0) /* fMCLK:256 */
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/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
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/* fBT=fACLK is thought for longer interval times */
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#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */
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#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */
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#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */
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#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms " */
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#define BT_ADLY_1 (BTIP2) /* 1ms " */
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#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms " */
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#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms " */
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|
|
291 |
#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms " */
|
|
|
292 |
#define BT_ADLY_16 (BTDIV) /* 16ms " */
|
|
|
293 |
#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms " */
|
|
|
294 |
#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms " */
|
|
|
295 |
#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms " */
|
|
|
296 |
#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms " */
|
|
|
297 |
#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms " */
|
|
|
298 |
#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms " */
|
|
|
299 |
#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms " */
|
|
|
300 |
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
|
|
|
301 |
/* the timing for short intervals is more precise than ACLK */
|
|
|
302 |
/* NOTE */
|
|
|
303 |
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
|
|
|
304 |
/* Too low interval time results in interrupts too frequent for the processor to handle! */
|
|
|
305 |
#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
|
|
|
306 |
#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms " *** too short for */
|
|
|
307 |
#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms " *** interrupt */
|
|
|
308 |
#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms " *** handling */
|
|
|
309 |
#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms " */
|
|
|
310 |
#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms " */
|
|
|
311 |
#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms " */
|
|
|
312 |
#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms " */
|
|
|
313 |
|
|
|
314 |
/* Reset/Hold coded with Bits 6-7 in BT(1)CTL */
|
|
|
315 |
/* this is for BT */
|
|
|
316 |
//#define BTRESET_CNT1 (BTRESET) /* BTCNT1 is reset while BTRESET is set */
|
|
|
317 |
//#define BTRESET_CNT1_2 (BTRESET+BTDIV) /* BTCNT1 .AND. BTCNT2 are reset while ~ is set */
|
|
|
318 |
/* this is for BT1 */
|
|
|
319 |
#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
|
|
|
320 |
#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
|
|
|
321 |
|
|
|
322 |
/* INTERRUPT CONTROL BITS */
|
|
|
323 |
/* #define BTIE 0x80 */
|
|
|
324 |
/* #define BTIFG 0x80 */
|
|
|
325 |
|
|
|
326 |
/************************************************************
|
|
|
327 |
* SYSTEM CLOCK, FLL+ (x41x)
|
|
|
328 |
************************************************************/
|
|
|
329 |
#define __MSP430_HAS_FLLPLUS_SMALL__ /* Definition to show that Module is available */
|
|
|
330 |
|
|
|
331 |
SFR_8BIT(SCFI0); /* System Clock Frequency Integrator 0 */
|
|
|
332 |
#define FN_2 (0x04) /* fDCOCLK = 1.4-12MHz*/
|
|
|
333 |
#define FN_3 (0x08) /* fDCOCLK = 2.2-17Mhz*/
|
|
|
334 |
#define FN_4 (0x10) /* fDCOCLK = 3.2-25Mhz*/
|
|
|
335 |
#define FN_8 (0x20) /* fDCOCLK = 5-40Mhz*/
|
|
|
336 |
#define FLLD0 (0x40) /* Loop Divider Bit : 0 */
|
|
|
337 |
#define FLLD1 (0x80) /* Loop Divider Bit : 1 */
|
|
|
338 |
|
|
|
339 |
#define FLLD_1 (0x00) /* Multiply Selected Loop Freq. By 1 */
|
|
|
340 |
#define FLLD_2 (0x40) /* Multiply Selected Loop Freq. By 2 */
|
|
|
341 |
#define FLLD_4 (0x80) /* Multiply Selected Loop Freq. By 4 */
|
|
|
342 |
#define FLLD_8 (0xC0) /* Multiply Selected Loop Freq. By 8 */
|
|
|
343 |
|
|
|
344 |
SFR_8BIT(SCFI1); /* System Clock Frequency Integrator 1 */
|
|
|
345 |
SFR_8BIT(SCFQCTL); /* System Clock Frequency Control */
|
|
|
346 |
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
|
|
|
347 |
/* #define SCFQ_32K 0x00 fMCLK=1*fACLK only a range from */
|
|
|
348 |
#define SCFQ_64K (0x01) /* fMCLK=2*fACLK 1+1 to 127+1 is possible */
|
|
|
349 |
#define SCFQ_128K (0x03) /* fMCLK=4*fACLK */
|
|
|
350 |
#define SCFQ_256K (0x07) /* fMCLK=8*fACLK */
|
|
|
351 |
#define SCFQ_512K (0x0F) /* fMCLK=16*fACLK */
|
|
|
352 |
#define SCFQ_1M (0x1F) /* fMCLK=32*fACLK */
|
|
|
353 |
#define SCFQ_2M (0x3F) /* fMCLK=64*fACLK */
|
|
|
354 |
#define SCFQ_4M (0x7F) /* fMCLK=128*fACLK */
|
|
|
355 |
#define SCFQ_M (0x80) /* Modulation Disable */
|
|
|
356 |
|
|
|
357 |
SFR_8BIT(FLL_CTL0); /* FLL+ Control 0 */
|
|
|
358 |
#define DCOF (0x01) /* DCO Fault Flag */
|
|
|
359 |
#define LFOF (0x02) /* Low Frequency Oscillator Fault Flag */
|
|
|
360 |
#define XT1OF (0x04) /* High Frequency Oscillator Fault Flag */
|
|
|
361 |
#define OSCCAP0 (0x10) /* XIN/XOUT Cap 0 */
|
|
|
362 |
#define OSCCAP1 (0x20) /* XIN/XOUT Cap 1 */
|
|
|
363 |
#define XTS_FLL (0x40) /* 1: Selects high-freq. oscillator */
|
|
|
364 |
#define DCOPLUS (0x80) /* DCO+ Enable */
|
|
|
365 |
|
|
|
366 |
#define XCAP0PF (0x00) /* XIN Cap = XOUT Cap = 0pf */
|
|
|
367 |
#define XCAP10PF (0x10) /* XIN Cap = XOUT Cap = 10pf */
|
|
|
368 |
#define XCAP14PF (0x20) /* XIN Cap = XOUT Cap = 14pf */
|
|
|
369 |
#define XCAP18PF (0x30) /* XIN Cap = XOUT Cap = 18pf */
|
|
|
370 |
#define OSCCAP_0 (0x00) /* XIN Cap = XOUT Cap = 0pf */
|
|
|
371 |
#define OSCCAP_1 (0x10) /* XIN Cap = XOUT Cap = 10pf */
|
|
|
372 |
#define OSCCAP_2 (0x20) /* XIN Cap = XOUT Cap = 14pf */
|
|
|
373 |
#define OSCCAP_3 (0x30) /* XIN Cap = XOUT Cap = 18pf */
|
|
|
374 |
|
|
|
375 |
SFR_8BIT(FLL_CTL1); /* FLL+ Control 1 */
|
|
|
376 |
#define FLL_DIV0 (0x01) /* FLL+ Divide Px.x/ACLK 0 */
|
|
|
377 |
#define FLL_DIV1 (0x02) /* FLL+ Divide Px.x/ACLK 1 */
|
|
|
378 |
|
|
|
379 |
#define FLL_DIV_1 (0x00) /* FLL+ Divide Px.x/ACLK By 1 */
|
|
|
380 |
#define FLL_DIV_2 (0x01) /* FLL+ Divide Px.x/ACLK By 2 */
|
|
|
381 |
#define FLL_DIV_4 (0x02) /* FLL+ Divide Px.x/ACLK By 4 */
|
|
|
382 |
#define FLL_DIV_8 (0x03) /* FLL+ Divide Px.x/ACLK By 8 */
|
|
|
383 |
|
|
|
384 |
/* INTERRUPT CONTROL BITS */
|
|
|
385 |
/* These two bits are defined in the Special Function Registers */
|
|
|
386 |
/* #define OFIFG 0x02 */
|
|
|
387 |
/* #define OFIE 0x02 */
|
|
|
388 |
|
|
|
389 |
/************************************************************
|
|
|
390 |
* Brown-Out, Supply Voltage Supervision (SVS)
|
|
|
391 |
************************************************************/
|
|
|
392 |
#define __MSP430_HAS_SVS__ /* Definition to show that Module is available */
|
|
|
393 |
|
|
|
394 |
SFR_8BIT(SVSCTL); /* SVS Control */
|
|
|
395 |
#define SVSFG (0x01) /* SVS Flag */
|
|
|
396 |
#define SVSOP (0x02) /* SVS output (read only) */
|
|
|
397 |
#define SVSON (0x04) /* Switches the SVS on/off */
|
|
|
398 |
#define PORON (0x08) /* Enable POR Generation if Low Voltage */
|
|
|
399 |
#define VLD0 (0x10)
|
|
|
400 |
#define VLD1 (0x20)
|
|
|
401 |
#define VLD2 (0x40)
|
|
|
402 |
#define VLD3 (0x80)
|
|
|
403 |
|
|
|
404 |
#define VLDON (0x10)
|
|
|
405 |
#define VLDOFF (0x00)
|
|
|
406 |
#define VLD_1_8V (0x10)
|
|
|
407 |
|
|
|
408 |
/************************************************************
|
|
|
409 |
* LCD
|
|
|
410 |
************************************************************/
|
|
|
411 |
#define __MSP430_HAS_LCD4__ /* Definition to show that Module is available */
|
|
|
412 |
|
|
|
413 |
SFR_8BIT(LCDCTL); /* LCD Control */
|
|
|
414 |
/* the names of the mode bits are different from the spec */
|
|
|
415 |
#define LCDON (0x01)
|
|
|
416 |
//#define LCDLOWR (0x02)
|
|
|
417 |
#define LCDSON (0x04)
|
|
|
418 |
#define LCDMX0 (0x08)
|
|
|
419 |
#define LCDMX1 (0x10)
|
|
|
420 |
#define LCDP0 (0x20)
|
|
|
421 |
#define LCDP1 (0x40)
|
|
|
422 |
#define LCDP2 (0x80)
|
|
|
423 |
/* Display modes coded with Bits 2-4 */
|
|
|
424 |
#define LCDSTATIC (LCDSON)
|
|
|
425 |
#define LCD2MUX (LCDMX0+LCDSON)
|
|
|
426 |
#define LCD3MUX (LCDMX1+LCDSON)
|
|
|
427 |
#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
|
|
|
428 |
/* Group select code with Bits 5-7 Seg.lines Dig.output */
|
|
|
429 |
#define LCDSG0 (0x00) /* --------- Port Only (default) */
|
|
|
430 |
#define LCDSG0_1 (LCDP0) /* S0 - S15 see Datasheet */
|
|
|
431 |
#define LCDSG0_2 (LCDP1) /* S0 - S19 see Datasheet */
|
|
|
432 |
#define LCDSG0_3 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */
|
|
|
433 |
#define LCDSG0_4 (LCDP2) /* S0 - S27 see Datasheet */
|
|
|
434 |
#define LCDSG0_5 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */
|
|
|
435 |
#define LCDSG0_6 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */
|
|
|
436 |
#define LCDSG0_7 (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */
|
|
|
437 |
/* NOTE: YOU CAN ONLY USE THE 'S' OR 'G' DECLARATIONS FOR A COMMAND */
|
|
|
438 |
/* MOV #LCDSG0_3+LCDOG2_7,&LCDCTL ACTUALY MEANS MOV #LCDP1,&LCDCTL! */
|
|
|
439 |
#define LCDOG1_7 (0x00) /* --------- Port Only (default) */
|
|
|
440 |
#define LCDOG2_7 (LCDP0) /* S0 - S15 see Datasheet */
|
|
|
441 |
#define LCDOG3_7 (LCDP1) /* S0 - S19 see Datasheet */
|
|
|
442 |
#define LCDOG4_7 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */
|
|
|
443 |
#define LCDOG5_7 (LCDP2) /* S0 - S27 see Datasheet */
|
|
|
444 |
#define LCDOG6_7 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */
|
|
|
445 |
#define LCDOG7 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */
|
|
|
446 |
#define LCDOGOFF (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */
|
|
|
447 |
|
|
|
448 |
#define LCDMEM_ (0x0091) /* LCD Memory */
|
|
|
449 |
#ifdef __ASM_HEADER__
|
|
|
450 |
#define LCDMEM (LCDMEM_) /* LCD Memory (for assembler) */
|
|
|
451 |
#else
|
|
|
452 |
#define LCDMEM ((char*) LCDMEM_) /* LCD Memory (for C) */
|
|
|
453 |
#endif
|
|
|
454 |
SFR_8BIT(LCDM1); /* LCD Memory 1 */
|
|
|
455 |
SFR_8BIT(LCDM2); /* LCD Memory 2 */
|
|
|
456 |
SFR_8BIT(LCDM3); /* LCD Memory 3 */
|
|
|
457 |
SFR_8BIT(LCDM4); /* LCD Memory 4 */
|
|
|
458 |
SFR_8BIT(LCDM5); /* LCD Memory 5 */
|
|
|
459 |
SFR_8BIT(LCDM6); /* LCD Memory 6 */
|
|
|
460 |
SFR_8BIT(LCDM7); /* LCD Memory 7 */
|
|
|
461 |
SFR_8BIT(LCDM8); /* LCD Memory 8 */
|
|
|
462 |
SFR_8BIT(LCDM9); /* LCD Memory 9 */
|
|
|
463 |
SFR_8BIT(LCDM10); /* LCD Memory 10 */
|
|
|
464 |
SFR_8BIT(LCDM11); /* LCD Memory 11 */
|
|
|
465 |
SFR_8BIT(LCDM12); /* LCD Memory 12 */
|
|
|
466 |
SFR_8BIT(LCDM13); /* LCD Memory 13 */
|
|
|
467 |
SFR_8BIT(LCDM14); /* LCD Memory 14 */
|
|
|
468 |
SFR_8BIT(LCDM15); /* LCD Memory 15 */
|
|
|
469 |
SFR_8BIT(LCDM16); /* LCD Memory 16 */
|
|
|
470 |
SFR_8BIT(LCDM17); /* LCD Memory 17 */
|
|
|
471 |
SFR_8BIT(LCDM18); /* LCD Memory 18 */
|
|
|
472 |
SFR_8BIT(LCDM19); /* LCD Memory 19 */
|
|
|
473 |
SFR_8BIT(LCDM20); /* LCD Memory 20 */
|
|
|
474 |
|
|
|
475 |
#define LCDMA (LCDM10) /* LCD Memory A */
|
|
|
476 |
#define LCDMB (LCDM11) /* LCD Memory B */
|
|
|
477 |
#define LCDMC (LCDM12) /* LCD Memory C */
|
|
|
478 |
#define LCDMD (LCDM13) /* LCD Memory D */
|
|
|
479 |
#define LCDME (LCDM14) /* LCD Memory E */
|
|
|
480 |
#define LCDMF (LCDM15) /* LCD Memory F */
|
|
|
481 |
|
|
|
482 |
/************************************************************
|
|
|
483 |
* Timer0_A3
|
|
|
484 |
************************************************************/
|
|
|
485 |
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
|
|
|
486 |
|
|
|
487 |
SFR_16BIT(TA0IV); /* Timer0_A3 Interrupt Vector Word */
|
|
|
488 |
SFR_16BIT(TA0CTL); /* Timer0_A3 Control */
|
|
|
489 |
SFR_16BIT(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */
|
|
|
490 |
SFR_16BIT(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */
|
|
|
491 |
SFR_16BIT(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */
|
|
|
492 |
SFR_16BIT(TA0R); /* Timer0_A3 */
|
|
|
493 |
SFR_16BIT(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */
|
|
|
494 |
SFR_16BIT(TA0CCR1); /* Timer0_A3 Capture/Compare 1 */
|
|
|
495 |
SFR_16BIT(TA0CCR2); /* Timer0_A3 Capture/Compare 2 */
|
|
|
496 |
|
|
|
497 |
/* Alternate register names */
|
|
|
498 |
#define TAIV TA0IV /* Timer A Interrupt Vector Word */
|
|
|
499 |
#define TACTL TA0CTL /* Timer A Control */
|
|
|
500 |
#define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
501 |
#define TACCTL1 TA0CCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
502 |
#define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
503 |
#define TAR TA0R /* Timer A */
|
|
|
504 |
#define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */
|
|
|
505 |
#define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */
|
|
|
506 |
#define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */
|
|
|
507 |
#define TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */
|
|
|
508 |
#define TACTL_ TA0CTL_ /* Timer A Control */
|
|
|
509 |
#define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
510 |
#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
511 |
#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
512 |
#define TAR_ TA0R_ /* Timer A */
|
|
|
513 |
#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */
|
|
|
514 |
#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */
|
|
|
515 |
#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */
|
|
|
516 |
|
|
|
517 |
/* Alternate register names 2 */
|
|
|
518 |
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
519 |
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
520 |
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
521 |
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
522 |
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
523 |
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
524 |
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
525 |
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
526 |
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
527 |
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
528 |
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
529 |
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
530 |
|
|
|
531 |
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
|
|
|
532 |
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
|
|
|
533 |
#define ID1 (0x0080) /* Timer A clock input divider 1 */
|
|
|
534 |
#define ID0 (0x0040) /* Timer A clock input divider 0 */
|
|
|
535 |
#define MC1 (0x0020) /* Timer A mode control 1 */
|
|
|
536 |
#define MC0 (0x0010) /* Timer A mode control 0 */
|
|
|
537 |
#define TACLR (0x0004) /* Timer A counter clear */
|
|
|
538 |
#define TAIE (0x0002) /* Timer A counter interrupt enable */
|
|
|
539 |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
|
|
|
540 |
|
|
|
541 |
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
542 |
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
543 |
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
544 |
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
545 |
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
546 |
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
547 |
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
548 |
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
549 |
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
550 |
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
551 |
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
552 |
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
553 |
|
|
|
554 |
#define CM1 (0x8000) /* Capture mode 1 */
|
|
|
555 |
#define CM0 (0x4000) /* Capture mode 0 */
|
|
|
556 |
#define CCIS1 (0x2000) /* Capture input select 1 */
|
|
|
557 |
#define CCIS0 (0x1000) /* Capture input select 0 */
|
|
|
558 |
#define SCS (0x0800) /* Capture sychronize */
|
|
|
559 |
#define SCCI (0x0400) /* Latched capture signal (read) */
|
|
|
560 |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
|
|
|
561 |
#define OUTMOD2 (0x0080) /* Output mode 2 */
|
|
|
562 |
#define OUTMOD1 (0x0040) /* Output mode 1 */
|
|
|
563 |
#define OUTMOD0 (0x0020) /* Output mode 0 */
|
|
|
564 |
#define CCIE (0x0010) /* Capture/compare interrupt enable */
|
|
|
565 |
#define CCI (0x0008) /* Capture input signal (read) */
|
|
|
566 |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
|
|
|
567 |
#define COV (0x0002) /* Capture/compare overflow flag */
|
|
|
568 |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
|
|
|
569 |
|
|
|
570 |
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
|
|
|
571 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
|
|
|
572 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
|
|
|
573 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
|
|
|
574 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
|
|
|
575 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
|
|
|
576 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
|
|
|
577 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
|
|
|
578 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
|
|
|
579 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
|
|
|
580 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
|
|
|
581 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
|
|
|
582 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
|
|
|
583 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
|
|
|
584 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
|
|
|
585 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
|
|
|
586 |
|
|
|
587 |
/* T0_A3IV Definitions */
|
|
|
588 |
#define TA0IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
589 |
#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */
|
|
|
590 |
#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */
|
|
|
591 |
#define TA0IV_6 (0x0006) /* Reserved */
|
|
|
592 |
#define TA0IV_8 (0x0008) /* Reserved */
|
|
|
593 |
#define TA0IV_TAIFG (0x000A) /* TA0IFG */
|
|
|
594 |
|
|
|
595 |
/************************************************************
|
|
|
596 |
* Timer1_A5
|
|
|
597 |
************************************************************/
|
|
|
598 |
#define __MSP430_HAS_T1A5__ /* Definition to show that Module is available */
|
|
|
599 |
|
|
|
600 |
SFR_16BIT(TA1IV); /* Timer1_A5 Interrupt Vector Word */
|
|
|
601 |
SFR_16BIT(TA1CTL); /* Timer1_A5 Control */
|
|
|
602 |
SFR_16BIT(TA1CCTL0); /* Timer1_A5 Capture/Compare Control 0 */
|
|
|
603 |
SFR_16BIT(TA1CCTL1); /* Timer1_A5 Capture/Compare Control 1 */
|
|
|
604 |
SFR_16BIT(TA1CCTL2); /* Timer1_A5 Capture/Compare Control 2 */
|
|
|
605 |
SFR_16BIT(TA1CCTL3); /* Timer1_A5 Capture/Compare Control 3 */
|
|
|
606 |
SFR_16BIT(TA1CCTL4); /* Timer1_A5 Capture/Compare Control 4 */
|
|
|
607 |
SFR_16BIT(TA1R); /* Timer1_A5 */
|
|
|
608 |
SFR_16BIT(TA1CCR0); /* Timer1_A5 Capture/Compare 0 */
|
|
|
609 |
SFR_16BIT(TA1CCR1); /* Timer1_A5 Capture/Compare 1 */
|
|
|
610 |
SFR_16BIT(TA1CCR2); /* Timer1_A5 Capture/Compare 2 */
|
|
|
611 |
SFR_16BIT(TA1CCR3); /* Timer1_A5 Capture/Compare 3 */
|
|
|
612 |
SFR_16BIT(TA1CCR4); /* Timer1_A5 Capture/Compare 4 */
|
|
|
613 |
|
|
|
614 |
/* Bits are already defined within the Timer0_Ax */
|
|
|
615 |
|
|
|
616 |
/* T1_A5IV Definitions */
|
|
|
617 |
#define TA1IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
618 |
#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */
|
|
|
619 |
#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */
|
|
|
620 |
#define TA1IV_TACCR3 (0x0006) /* TA1CCR3_CCIFG */
|
|
|
621 |
#define TA1IV_TACCR4 (0x0008) /* TA1CCR4_CCIFG */
|
|
|
622 |
#define TA1IV_TAIFG (0x000A) /* TA1IFG */
|
|
|
623 |
|
|
|
624 |
/*************************************************************
|
|
|
625 |
* Flash Memory
|
|
|
626 |
*************************************************************/
|
|
|
627 |
#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
|
|
|
628 |
|
|
|
629 |
SFR_16BIT(FCTL1); /* FLASH Control 1 */
|
|
|
630 |
SFR_16BIT(FCTL2); /* FLASH Control 2 */
|
|
|
631 |
SFR_16BIT(FCTL3); /* FLASH Control 3 */
|
|
|
632 |
|
|
|
633 |
#define FRKEY (0x9600) /* Flash key returned by read */
|
|
|
634 |
#define FWKEY (0xA500) /* Flash key for write */
|
|
|
635 |
#define FXKEY (0x3300) /* for use with XOR instruction */
|
|
|
636 |
|
|
|
637 |
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
|
|
|
638 |
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
|
|
|
639 |
#define WRT (0x0040) /* Enable bit for Flash write */
|
|
|
640 |
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
|
|
|
641 |
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
|
|
|
642 |
|
|
|
643 |
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
|
|
|
644 |
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
|
|
|
645 |
#ifndef FN2
|
|
|
646 |
#define FN2 (0x0004)
|
|
|
647 |
#endif
|
|
|
648 |
#ifndef FN3
|
|
|
649 |
#define FN3 (0x0008)
|
|
|
650 |
#endif
|
|
|
651 |
#ifndef FN4
|
|
|
652 |
#define FN4 (0x0010)
|
|
|
653 |
#endif
|
|
|
654 |
#define FN5 (0x0020)
|
|
|
655 |
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
|
|
|
656 |
#define FSSEL1 (0x0080) /* Flash clock select 1 */
|
|
|
657 |
|
|
|
658 |
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
|
|
|
659 |
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
|
|
|
660 |
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
|
|
|
661 |
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
|
|
|
662 |
|
|
|
663 |
#define BUSY (0x0001) /* Flash busy: 1 */
|
|
|
664 |
#define KEYV (0x0002) /* Flash Key violation flag */
|
|
|
665 |
#define ACCVIFG (0x0004) /* Flash Access violation flag */
|
|
|
666 |
#define WAIT (0x0008) /* Wait flag for segment write */
|
|
|
667 |
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
668 |
#define EMEX (0x0020) /* Flash Emergency Exit */
|
|
|
669 |
|
|
|
670 |
/************************************************************
|
|
|
671 |
* Comparator A
|
|
|
672 |
************************************************************/
|
|
|
673 |
#define __MSP430_HAS_COMPA__ /* Definition to show that Module is available */
|
|
|
674 |
|
|
|
675 |
SFR_8BIT(CACTL1); /* Comparator A Control 1 */
|
|
|
676 |
SFR_8BIT(CACTL2); /* Comparator A Control 2 */
|
|
|
677 |
SFR_8BIT(CAPD); /* Comparator A Port Disable */
|
|
|
678 |
|
|
|
679 |
#define CAIFG (0x01) /* Comp. A Interrupt Flag */
|
|
|
680 |
#define CAIE (0x02) /* Comp. A Interrupt Enable */
|
|
|
681 |
#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
|
|
|
682 |
#define CAON (0x08) /* Comp. A enable */
|
|
|
683 |
#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
|
|
|
684 |
#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
|
|
|
685 |
#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
|
|
|
686 |
#define CAEX (0x80) /* Comp. A Exchange Inputs */
|
|
|
687 |
|
|
|
688 |
#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
|
|
|
689 |
#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
|
|
|
690 |
#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
|
|
|
691 |
#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
|
|
|
692 |
|
|
|
693 |
#define CAOUT (0x01) /* Comp. A Output */
|
|
|
694 |
#define CAF (0x02) /* Comp. A Enable Output Filter */
|
|
|
695 |
#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */
|
|
|
696 |
#define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */
|
|
|
697 |
#define CACTL24 (0x10)
|
|
|
698 |
#define CACTL25 (0x20)
|
|
|
699 |
#define CACTL26 (0x40)
|
|
|
700 |
#define CACTL27 (0x80)
|
|
|
701 |
|
|
|
702 |
#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
|
|
|
703 |
#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
|
|
|
704 |
#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
|
|
|
705 |
#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
|
|
|
706 |
#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
|
|
|
707 |
#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
|
|
|
708 |
#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
|
|
|
709 |
#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
|
|
|
710 |
|
|
|
711 |
/************************************************************
|
|
|
712 |
* Scan-I/F
|
|
|
713 |
************************************************************/
|
|
|
714 |
#define __MSP430_HAS_SCANIF__ /* Definition to show that Module is available */
|
|
|
715 |
|
|
|
716 |
SFR_16BIT(SIFDEBUG); /* SIF, Debug Register */
|
|
|
717 |
SFR_16BIT(SIFCNT); /* SIF, Counter1/2 */
|
|
|
718 |
SFR_16BIT(SIFPSMV); /* SIF, Processing State Machine */
|
|
|
719 |
SFR_16BIT(SIFCTL1); /* SIF, Control Register 1 */
|
|
|
720 |
SFR_16BIT(SIFCTL2); /* SIF, Control Register 2 */
|
|
|
721 |
SFR_16BIT(SIFCTL3); /* SIF, Control Register 3 */
|
|
|
722 |
SFR_16BIT(SIFCTL4); /* SIF, Control Register 4 */
|
|
|
723 |
SFR_16BIT(SIFCTL5); /* SIF, Control Register 5 */
|
|
|
724 |
#define SIFDACR_ (0x01C0) /* SIF, Digital to Analog Conv. 0 */
|
|
|
725 |
#ifdef __ASM_HEADER__
|
|
|
726 |
#define SIFDACR (SIFDACR_) /* SIF, Digital to Analog Conv. Memory (for assembler) */
|
|
|
727 |
#else
|
|
|
728 |
#define SIFDACR ((unsigned int*) SIFDACR_) /* SIF, Digital to Analog Conv. Memory (for C) */
|
|
|
729 |
#endif
|
|
|
730 |
SFR_16BIT(SIFDACR0); /* SIF, Digital to Analog Conv. 0 */
|
|
|
731 |
SFR_16BIT(SIFDACR1); /* SIF, Digital to Analog Conv. 1 */
|
|
|
732 |
SFR_16BIT(SIFDACR2); /* SIF, Digital to Analog Conv. 2 */
|
|
|
733 |
SFR_16BIT(SIFDACR3); /* SIF, Digital to Analog Conv. 3 */
|
|
|
734 |
SFR_16BIT(SIFDACR4); /* SIF, Digital to Analog Conv. 4 */
|
|
|
735 |
SFR_16BIT(SIFDACR5); /* SIF, Digital to Analog Conv. 5 */
|
|
|
736 |
SFR_16BIT(SIFDACR6); /* SIF, Digital to Analog Conv. 6 */
|
|
|
737 |
SFR_16BIT(SIFDACR7); /* SIF, Digital to Analog Conv. 7 */
|
|
|
738 |
#define SIFTSM_ (0x01D0) /* SIF, Timing State Machine 0 */
|
|
|
739 |
#ifdef __ASM_HEADER__
|
|
|
740 |
#define SIFTSM (SIFTSM_) /* SIF, Timing State Machine (for assembler) */
|
|
|
741 |
#else
|
|
|
742 |
#define SIFTSM ((unsigned int*) SIFTSM_) /* SIF, Timing State Machine (for C) */
|
|
|
743 |
#endif
|
|
|
744 |
SFR_16BIT(SIFTSM0); /* SIF, Timing State Machine 0 */
|
|
|
745 |
SFR_16BIT(SIFTSM1); /* SIF, Timing State Machine 1 */
|
|
|
746 |
SFR_16BIT(SIFTSM2); /* SIF, Timing State Machine 2 */
|
|
|
747 |
SFR_16BIT(SIFTSM3); /* SIF, Timing State Machine 3 */
|
|
|
748 |
SFR_16BIT(SIFTSM4); /* SIF, Timing State Machine 4 */
|
|
|
749 |
SFR_16BIT(SIFTSM5); /* SIF, Timing State Machine 5 */
|
|
|
750 |
SFR_16BIT(SIFTSM6); /* SIF, Timing State Machine 6 */
|
|
|
751 |
SFR_16BIT(SIFTSM7); /* SIF, Timing State Machine 7 */
|
|
|
752 |
SFR_16BIT(SIFTSM8); /* SIF, Timing State Machine 8 */
|
|
|
753 |
SFR_16BIT(SIFTSM9); /* SIF, Timing State Machine 9 */
|
|
|
754 |
SFR_16BIT(SIFTSM10); /* SIF, Timing State Machine 10 */
|
|
|
755 |
SFR_16BIT(SIFTSM11); /* SIF, Timing State Machine 11 */
|
|
|
756 |
SFR_16BIT(SIFTSM12); /* SIF, Timing State Machine 12 */
|
|
|
757 |
SFR_16BIT(SIFTSM13); /* SIF, Timing State Machine 13 */
|
|
|
758 |
SFR_16BIT(SIFTSM14); /* SIF, Timing State Machine 14 */
|
|
|
759 |
SFR_16BIT(SIFTSM15); /* SIF, Timing State Machine 15 */
|
|
|
760 |
SFR_16BIT(SIFTSM16); /* SIF, Timing State Machine 16 */
|
|
|
761 |
SFR_16BIT(SIFTSM17); /* SIF, Timing State Machine 17 */
|
|
|
762 |
SFR_16BIT(SIFTSM18); /* SIF, Timing State Machine 18 */
|
|
|
763 |
SFR_16BIT(SIFTSM19); /* SIF, Timing State Machine 19 */
|
|
|
764 |
SFR_16BIT(SIFTSM20); /* SIF, Timing State Machine 20 */
|
|
|
765 |
SFR_16BIT(SIFTSM21); /* SIF, Timing State Machine 21 */
|
|
|
766 |
SFR_16BIT(SIFTSM22); /* SIF, Timing State Machine 22 */
|
|
|
767 |
SFR_16BIT(SIFTSM23); /* SIF, Timing State Machine 23 */
|
|
|
768 |
|
|
|
769 |
/* SIFCTL1 */
|
|
|
770 |
#define SIFEN (0x0001) /* SIF Enable */
|
|
|
771 |
#define SIFTESTD (0x0002) /* SIF 0:Normal / 1:Test Mode */
|
|
|
772 |
#define SIFIFG0 (0x0004) /* SIF Interrupt Flag 0 */
|
|
|
773 |
#define SIFIFG1 (0x0008) /* SIF Interrupt Flag 1 */
|
|
|
774 |
#define SIFIFG2 (0x0010) /* SIF Interrupt Flag 2 */
|
|
|
775 |
#define SIFIFG3 (0x0020) /* SIF Interrupt Flag 3 */
|
|
|
776 |
#define SIFIFG4 (0x0040) /* SIF Interrupt Flag 4 */
|
|
|
777 |
#define SIFIFG5 (0x0080) /* SIF Interrupt Flag 5 */
|
|
|
778 |
#define SIFIFG6 (0x0100) /* SIF Interrupt Flag 6 */
|
|
|
779 |
#define SIFIE0 (0x0200) /* SIF Interrupt Enable 0 */
|
|
|
780 |
#define SIFIE1 (0x0400) /* SIF Interrupt Enable 1 */
|
|
|
781 |
#define SIFIE2 (0x0800) /* SIF Interrupt Enable 2 */
|
|
|
782 |
#define SIFIE3 (0x1000) /* SIF Interrupt Enable 3 */
|
|
|
783 |
#define SIFIE4 (0x2000) /* SIF Interrupt Enable 4 */
|
|
|
784 |
#define SIFIE5 (0x4000) /* SIF Interrupt Enable 5 */
|
|
|
785 |
#define SIFIE6 (0x8000) /* SIF Interrupt Enable 6 */
|
|
|
786 |
|
|
|
787 |
/* SIFCTL2 */
|
|
|
788 |
#define SIFTCH0OUT (0x0001) /* SIF TCH0 result */
|
|
|
789 |
#define SIFTCH1OUT (0x0002) /* SIF TCH1 result */
|
|
|
790 |
#define SIFTCH00 (0x0004) /* SIF 1. Channel select 0 */
|
|
|
791 |
#define SIFTCH01 (0x0008) /* SIF 1. Channel select 1 */
|
|
|
792 |
#define SIFTCH10 (0x0010) /* SIF 2. Channel select 0 */
|
|
|
793 |
#define SIFTCH11 (0x0020) /* SIF 2. Channel select 1 */
|
|
|
794 |
#define SIFTEN (0x0040) /* SIF Enable Transistors */
|
|
|
795 |
#define SIFSH (0x0080) /* SIF Sample on/off */
|
|
|
796 |
#define SIFVCC2 (0x0100) /* SIF VCC/2 Generator off/on */
|
|
|
797 |
#define SIFVSS (0x0200) /* SIF Select Terminal for sample Cap. */
|
|
|
798 |
#define SIFCACI3 (0x0400) /* SIF Selection of SIFCI3 */
|
|
|
799 |
#define SIFCISEL (0x0800) /* SIF Comparator Input Select */
|
|
|
800 |
#define SIFCAX (0x1000) /* SIF Select CA Source */
|
|
|
801 |
#define SIFCAINV (0x2000) /* SIF Invert CA Output 0:off/1:on */
|
|
|
802 |
#define SIFCAON (0x4000) /* SIF Switch CA on */
|
|
|
803 |
#define SIFDACON (0x8000) /* SIF Switch DAC on */
|
|
|
804 |
|
|
|
805 |
/* SIFCTL3 */
|
|
|
806 |
#define SIF0OUT (0x0001) /* SIF Sensor 0 Out */
|
|
|
807 |
#define SIF1OUT (0x0002) /* SIF Sensor 1 Out */
|
|
|
808 |
#define SIF2OUT (0x0004) /* SIF Sensor 2 Out */
|
|
|
809 |
#define SIF3OUT (0x0008) /* SIF Sensor 3 Out */
|
|
|
810 |
#define SIFIFGSET0 (0x0010) /* SIF SIFIFG0 level select */
|
|
|
811 |
#define SIFIFGSET1 (0x0020) /* SIF SIFIFG1 level select */
|
|
|
812 |
#define SIFIFGSET2 (0x0040) /* SIF SIFIFG2 level select */
|
|
|
813 |
#define SIFCS (0x0080) /* SIF Capture Select */
|
|
|
814 |
#define SIFIS10 (0x0100) /* SIF SIFIFG3 Int.Flag Source 0 */
|
|
|
815 |
#define SIFIS11 (0x0200) /* SIF SIFIFG3 Int.Flag Source 1 */
|
|
|
816 |
#define SIFIS20 (0x0400) /* SIF SIFIFG4 Int.Flag Source 0 */
|
|
|
817 |
#define SIFIS21 (0x0800) /* SIF SIFIFG4 Int.Flag Source 1 */
|
|
|
818 |
#define SIFS10 (0x1000) /* SIF S1 Source Select 0 */
|
|
|
819 |
#define SIFS11 (0x2000) /* SIF S1 Source Select 1 */
|
|
|
820 |
#define SIFS20 (0x4000) /* SIF S2 Source Select 0 */
|
|
|
821 |
#define SIFS21 (0x8000) /* SIF S2 Source Select 1 */
|
|
|
822 |
|
|
|
823 |
#define SIFIS1_0 (0x0000) /* SIF SIFIFG3 set with each count of SIFCNT1 */
|
|
|
824 |
#define SIFIS1_1 (0x0100) /* SIF SIFIFG3 set if (SIFCNT1 mod 4)=0 */
|
|
|
825 |
#define SIFIS1_2 (0x0200) /* SIF SIFIFG3 set if (SIFCNT1 mod 64)=0 */
|
|
|
826 |
#define SIFIS1_3 (0x0300) /* SIF SIFIFG3 set if SIFCNT1 rolls over */
|
|
|
827 |
#define SIFIS2_0 (0x0000) /* SIF SIFIFG4 set with each count of SIFCNT2 */
|
|
|
828 |
#define SIFIS2_1 (0x0400) /* SIF SIFIFG4 set if (SIFCNT2 mod 4)=0 */
|
|
|
829 |
#define SIFIS2_2 (0x0800) /* SIF SIFIFG4 set if (SIFCNT2 mod 64)=0 */
|
|
|
830 |
#define SIFIS2_3 (0x0C00) /* SIF SIFIFG4 set if SIFCNT2 rolls over */
|
|
|
831 |
#define SIFS1_0 (0x0000) /* SIF S1 Source : SIF0OUT */
|
|
|
832 |
#define SIFS1_1 (0x1000) /* SIF S1 Source : SIF1OUT */
|
|
|
833 |
#define SIFS1_2 (0x2000) /* SIF S1 Source : SIF2OUT */
|
|
|
834 |
#define SIFS1_3 (0x3000) /* SIF S1 Source : SIF3OUT */
|
|
|
835 |
#define SIFS2_0 (0x0000) /* SIF S2 Source : SIF0OUT */
|
|
|
836 |
#define SIFS2_1 (0x4000) /* SIF S2 Source : SIF1OUT */
|
|
|
837 |
#define SIFS2_2 (0x8000) /* SIF S2 Source : SIF2OUT */
|
|
|
838 |
#define SIFS2_3 (0xC000) /* SIF S2 Source : SIF3OUT */
|
|
|
839 |
|
|
|
840 |
/* SIFCTL4 */
|
|
|
841 |
#define SIFDIV10 (0x0001) /* SIF Clock Divider 1.0 */
|
|
|
842 |
#define SIFDIV11 (0x0002) /* SIF Clock Divider 1.1 */
|
|
|
843 |
#define SIFDIV20 (0x0004) /* SIF Clock Divider 2.0 */
|
|
|
844 |
#define SIFDIV21 (0x0008) /* SIF Clock Divider 2.1 */
|
|
|
845 |
#define SIFDIV3A0 (0x0010) /* SIF Clock Divider 3.0 */
|
|
|
846 |
#define SIFDIV3A1 (0x0020) /* SIF Clock Divider 3.1 */
|
|
|
847 |
#define SIFDIV3A2 (0x0040) /* SIF Clock Divider 3.2 */
|
|
|
848 |
#define SIFDIV3B0 (0x0080) /* SIF Clock Divider 3.3 */
|
|
|
849 |
#define SIFDIV3B1 (0x0100) /* SIF Clock Divider 3.4 */
|
|
|
850 |
#define SIFDIV3B2 (0x0200) /* SIF Clock Divider 3.5 */
|
|
|
851 |
#define SIFQ6EN (0x0400) /* SIF Feedback 6 Enable */
|
|
|
852 |
#define SIFQ7EN (0x0800) /* SIF Feedback 7 Enable */
|
|
|
853 |
#define SIFCNT1ENP (0x1000) /* SIF Enable SIFCNT1 up count */
|
|
|
854 |
#define SIFCNT1ENM (0x2000) /* SIF Enable SIFCNT1 down count */
|
|
|
855 |
#define SIFCNT2EN (0x4000) /* SIF Enable SIFCNT2 count */
|
|
|
856 |
#define SIFCNTRST (0x8000) /* SIF Enable Counter Reset on Read */
|
|
|
857 |
|
|
|
858 |
#define SIFDIV1_1 (0x0000) /* SIF Clock Divider 1: /1 */
|
|
|
859 |
#define SIFDIV1_2 (0x0001) /* SIF Clock Divider 1: /2 */
|
|
|
860 |
#define SIFDIV1_4 (0x0002) /* SIF Clock Divider 1: /4 */
|
|
|
861 |
#define SIFDIV1_8 (0x0003) /* SIF Clock Divider 1: /8 */
|
|
|
862 |
#define SIFDIV2_1 (0x0000) /* SIF Clock Divider 2: /1 */
|
|
|
863 |
#define SIFDIV2_2 (0x0004) /* SIF Clock Divider 2: /2 */
|
|
|
864 |
#define SIFDIV2_4 (0x0008) /* SIF Clock Divider 2: /4 */
|
|
|
865 |
#define SIFDIV2_8 (0x000C) /* SIF Clock Divider 2: /8 */
|
|
|
866 |
|
|
|
867 |
#define SIFDIV3_2 (0x0000) /* SIF Clock Divider 3: /2 */
|
|
|
868 |
#define SIFDIV3_6 (0x0010) /* SIF Clock Divider 3: /6 */
|
|
|
869 |
#define SIFDIV3_10 (0x0020) /* SIF Clock Divider 3: /10 */
|
|
|
870 |
#define SIFDIV3_14 (0x0030) /* SIF Clock Divider 3: /14 */
|
|
|
871 |
#define SIFDIV3_18 (0x0040) /* SIF Clock Divider 3: /18 */
|
|
|
872 |
#define SIFDIV3_22 (0x0050) /* SIF Clock Divider 3: /22 */
|
|
|
873 |
#define SIFDIV3_26 (0x0060) /* SIF Clock Divider 3: /26 */
|
|
|
874 |
#define SIFDIV3_30 (0x0070) /* SIF Clock Divider 3: /30 */
|
|
|
875 |
#define SIFDIV3_42 (0x00B0) /* SIF Clock Divider 3: /42 */
|
|
|
876 |
#define SIFDIV3_50 (0x0120) /* SIF Clock Divider 3: /50 */
|
|
|
877 |
#define SIFDIV3_54 (0x00C0) /* SIF Clock Divider 3: /54 */
|
|
|
878 |
#define SIFDIV3_66 (0x00D0) /* SIF Clock Divider 3: /66 */
|
|
|
879 |
#define SIFDIV3_70 (0x0130) /* SIF Clock Divider 3: /70 */
|
|
|
880 |
#define SIFDIV3_78 (0x00E0) /* SIF Clock Divider 3: /78 */
|
|
|
881 |
#define SIFDIV3_90 (0x00F0) /* SIF Clock Divider 3: /90 */
|
|
|
882 |
#define SIFDIV3_98 (0x01B0) /* SIF Clock Divider 3: /98 */
|
|
|
883 |
#define SIFDIV3_110 (0x0150) /* SIF Clock Divider 3: /110 */
|
|
|
884 |
#define SIFDIV3_126 (0x01C0) /* SIF Clock Divider 3: /126 */
|
|
|
885 |
#define SIFDIV3_130 (0x0160) /* SIF Clock Divider 3: /130 */
|
|
|
886 |
#define SIFDIV3_150 (0x0170) /* SIF Clock Divider 3: /150 */
|
|
|
887 |
#define SIFDIV3_154 (0x01D0) /* SIF Clock Divider 3: /154 */
|
|
|
888 |
#define SIFDIV3_162 (0x0240) /* SIF Clock Divider 3: /162 */
|
|
|
889 |
#define SIFDIV3_182 (0x01E0) /* SIF Clock Divider 3: /182 */
|
|
|
890 |
#define SIFDIV3_198 (0x0250) /* SIF Clock Divider 3: /198 */
|
|
|
891 |
#define SIFDIV3_210 (0x01F0) /* SIF Clock Divider 3: /210 */
|
|
|
892 |
#define SIFDIV3_234 (0x0260) /* SIF Clock Divider 3: /234 */
|
|
|
893 |
#define SIFDIV3_242 (0x02D0) /* SIF Clock Divider 3: /242 */
|
|
|
894 |
#define SIFDIV3_270 (0x0270) /* SIF Clock Divider 3: /270 */
|
|
|
895 |
#define SIFDIV3_286 (0x02E0) /* SIF Clock Divider 3: /286 */
|
|
|
896 |
#define SIFDIV3_330 (0x02F0) /* SIF Clock Divider 3: /330 */
|
|
|
897 |
#define SIFDIV3_338 (0x0360) /* SIF Clock Divider 3: /338 */
|
|
|
898 |
#define SIFDIV3_390 (0x0370) /* SIF Clock Divider 3: /390 */
|
|
|
899 |
#define SIFDIV3_450 (0x03F0) /* SIF Clock Divider 3: /450 */
|
|
|
900 |
|
|
|
901 |
/* SIFCTL5 */
|
|
|
902 |
#define SIFCLKEN (0x0001) /* SIF 0:SMCLK for SIFCLK / 1:SIFCLKG for SIFCLK */
|
|
|
903 |
#define SIFCLKGON (0x0002) /* SIF Switch SIFCLKG on */
|
|
|
904 |
#define SIFFNOM (0x0004) /* SIF Select Nominal Frequ. 0:4MHz / 1:1MHz */
|
|
|
905 |
#define SIFCLKFQ0 (0x0008) /* SIF Clock Generator frequency adjust 0 */
|
|
|
906 |
#define SIFCLKFQ1 (0x0010) /* SIF Clock Generator frequency adjust 1 */
|
|
|
907 |
#define SIFCLKFQ2 (0x0020) /* SIF Clock Generator frequency adjust 2 */
|
|
|
908 |
#define SIFCLKFQ3 (0x0040) /* SIF Clock Generator frequency adjust 3 */
|
|
|
909 |
#define SIFTSMRP (0x0080) /* SIF Timing State Machine Repeat mode */
|
|
|
910 |
#define SIFCNT30 (0x0100) /* SIF Counter 3.0 */
|
|
|
911 |
#define SIFCNT31 (0x0200) /* SIF Counter 3.1 */
|
|
|
912 |
#define SIFCNT32 (0x0400) /* SIF Counter 3.2 */
|
|
|
913 |
#define SIFCNT33 (0x0800) /* SIF Counter 3.3 */
|
|
|
914 |
#define SIFCNT34 (0x1000) /* SIF Counter 3.4 */
|
|
|
915 |
#define SIFCNT35 (0x2000) /* SIF Counter 3.5 */
|
|
|
916 |
#define SIFCNT36 (0x4000) /* SIF Counter 3.6 */
|
|
|
917 |
#define SIFCNT37 (0x8000) /* SIF Counter 3.7 */
|
|
|
918 |
|
|
|
919 |
/* SIFTSM */
|
|
|
920 |
#define SIFCH0 (0x0001) /* SIF Select channel for tsm: 0 */
|
|
|
921 |
#define SIFCH1 (0x0002) /* SIF Select channel for tsm: 1 */
|
|
|
922 |
#define SIFLCEN (0x0004) /* SIF LC enable */
|
|
|
923 |
#define SIFEX (0x0008) /* SIF */
|
|
|
924 |
#define SIFCA (0x0010) /* SIF */
|
|
|
925 |
#define SIFCLKON (0x0020) /* SIF */
|
|
|
926 |
#define SIFRSON (0x0040) /* SIF */
|
|
|
927 |
#define SIFTESTS1 (0x0080) /* SIF */
|
|
|
928 |
#define SIFDAC (0x0100) /* SIF */
|
|
|
929 |
#define SIFSTOP (0x0200) /* SIF */
|
|
|
930 |
#define SIFACLK (0x0400) /* SIF */
|
|
|
931 |
#define SIFREPEAT0 (0x0800) /* SIF */
|
|
|
932 |
#define SIFREPEAT1 (0x1000) /* SIF */
|
|
|
933 |
#define SIFREPEAT2 (0x2000) /* SIF */
|
|
|
934 |
#define SIFREPEAT3 (0x4000) /* SIF */
|
|
|
935 |
#define SIFREPEAT4 (0x8000) /* SIF */
|
|
|
936 |
|
|
|
937 |
/************************************************************
|
|
|
938 |
* Interrupt Vectors (offset from 0xFFE0)
|
|
|
939 |
************************************************************/
|
|
|
940 |
|
|
|
941 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
942 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
943 |
#define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name
|
|
|
944 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
945 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
946 |
PLACE_VECTOR(VECTOR_NAME(func), offset)
|
|
|
947 |
|
|
|
948 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
949 |
#define BASICTIMER_VECTOR ".int00" /* 0xFFE0 Basic Timer */
|
|
|
950 |
#else
|
|
|
951 |
#define BASICTIMER_VECTOR (0 * 1u) /* 0xFFE0 Basic Timer */
|
|
|
952 |
/*#define BASICTIMER_ISR(func) ISR_VECTOR(func, ".int00") */ /* 0xFFE0 Basic Timer */ /* CCE V2 Style */
|
|
|
953 |
#endif
|
|
|
954 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
955 |
#define PORT2_VECTOR ".int01" /* 0xFFE2 Port 2 */
|
|
|
956 |
#else
|
|
|
957 |
#define PORT2_VECTOR (1 * 1u) /* 0xFFE2 Port 2 */
|
|
|
958 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int01") */ /* 0xFFE2 Port 2 */ /* CCE V2 Style */
|
|
|
959 |
#endif
|
|
|
960 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
961 |
#define PORT1_VECTOR ".int04" /* 0xFFE8 Port 1 */
|
|
|
962 |
#else
|
|
|
963 |
#define PORT1_VECTOR (4 * 1u) /* 0xFFE8 Port 1 */
|
|
|
964 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int04") */ /* 0xFFE8 Port 1 */ /* CCE V2 Style */
|
|
|
965 |
#endif
|
|
|
966 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
967 |
#define TIMER0_A1_VECTOR ".int05" /* 0xFFEA Timer0_A CC1-2, TA0 */
|
|
|
968 |
#else
|
|
|
969 |
#define TIMER0_A1_VECTOR (5 * 1u) /* 0xFFEA Timer0_A CC1-2, TA0 */
|
|
|
970 |
/*#define TIMER0_A1_ISR(func) ISR_VECTOR(func, ".int05") */ /* 0xFFEA Timer0_A CC1-2, TA0 */ /* CCE V2 Style */
|
|
|
971 |
#endif
|
|
|
972 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
973 |
#define TIMER0_A0_VECTOR ".int06" /* 0xFFEC Timer0_A CC0 */
|
|
|
974 |
#else
|
|
|
975 |
#define TIMER0_A0_VECTOR (6 * 1u) /* 0xFFEC Timer0_A CC0 */
|
|
|
976 |
/*#define TIMER0_A0_ISR(func) ISR_VECTOR(func, ".int06") */ /* 0xFFEC Timer0_A CC0 */ /* CCE V2 Style */
|
|
|
977 |
#endif
|
|
|
978 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
979 |
#define SCANIF_VECTOR ".int09" /* 0xFFF2 Scan Inteface */
|
|
|
980 |
#else
|
|
|
981 |
#define SCANIF_VECTOR (9 * 1u) /* 0xFFF2 Scan Inteface */
|
|
|
982 |
/*#define SCANIF_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 Scan Inteface */ /* CCE V2 Style */
|
|
|
983 |
#endif
|
|
|
984 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
985 |
#define WDT_VECTOR ".int10" /* 0xFFF4 Watchdog Timer */
|
|
|
986 |
#else
|
|
|
987 |
#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */
|
|
|
988 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
|
|
|
989 |
#endif
|
|
|
990 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
991 |
#define COMPARATORA_VECTOR ".int11" /* 0xFFF6 Comparator A */
|
|
|
992 |
#else
|
|
|
993 |
#define COMPARATORA_VECTOR (11 * 1u) /* 0xFFF6 Comparator A */
|
|
|
994 |
/*#define COMPARATORA_ISR(func) ISR_VECTOR(func, ".int11") */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */
|
|
|
995 |
#endif
|
|
|
996 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
997 |
#define TIMER1_A1_VECTOR ".int12" /* 0xFFF8 Timer1_A CC1-4, TA1 */
|
|
|
998 |
#else
|
|
|
999 |
#define TIMER1_A1_VECTOR (12 * 1u) /* 0xFFF8 Timer1_A CC1-4, TA1 */
|
|
|
1000 |
/*#define TIMER1_A1_ISR(func) ISR_VECTOR(func, ".int12") */ /* 0xFFF8 Timer1_A CC1-4, TA1 */ /* CCE V2 Style */
|
|
|
1001 |
#endif
|
|
|
1002 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1003 |
#define TIMER1_A0_VECTOR ".int13" /* 0xFFFA Timer1_A CC0 */
|
|
|
1004 |
#else
|
|
|
1005 |
#define TIMER1_A0_VECTOR (13 * 1u) /* 0xFFFA Timer1_A CC0 */
|
|
|
1006 |
/*#define TIMER1_A0_ISR(func) ISR_VECTOR(func, ".int13") */ /* 0xFFFA Timer1_A CC0 */ /* CCE V2 Style */
|
|
|
1007 |
#endif
|
|
|
1008 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1009 |
#define NMI_VECTOR ".int14" /* 0xFFFC Non-maskable */
|
|
|
1010 |
#else
|
|
|
1011 |
#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */
|
|
|
1012 |
/*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
|
|
|
1013 |
#endif
|
|
|
1014 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1015 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
1016 |
#else
|
|
|
1017 |
#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
1018 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
1019 |
#endif
|
|
|
1020 |
|
|
|
1021 |
/* Alternate Names */
|
|
|
1022 |
|
|
|
1023 |
/************************************************************
|
|
|
1024 |
* End of Modules
|
|
|
1025 |
************************************************************/
|
|
|
1026 |
|
|
|
1027 |
#ifdef __cplusplus
|
|
|
1028 |
}
|
|
|
1029 |
#endif /* extern "C" */
|
|
|
1030 |
|
|
|
1031 |
#endif /* #ifndef __msp430xW42x */
|
|
|
1032 |
|