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dpurdie |
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* MSP430FR5720 devices.
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*
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* Texas Instruments, Version 1.1
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*
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* Rev. 1.0, Setup
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* Rev. 1.1 Fixed definition of RTCTEV__0000 and RTCTEV__1200
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* Removed not availabe bits RTCMODE and RTCSSELx
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* Added PxSELC registers
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*
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*
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********************************************************************/
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#ifndef __MSP430FR5720
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#define __MSP430FR5720
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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//#define SFR_20BIT(address) extern volatile unsigned int address
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typedef void (* __SFR_FARPTR)();
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#define SFR_20BIT(address) extern __SFR_FARPTR address
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#define SFR_32BIT(address) extern volatile unsigned long address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* CPU
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************************************************************/
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#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* ADC10_B
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************************************************************/
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#define __MSP430_HAS_ADC10_B__ /* Definition to show that Module is available */
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#define __MSP430_BASEADDRESS_ADC10_B__ 0x0700
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SFR_16BIT(ADC10CTL0); /* ADC10 Control 0 */
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SFR_8BIT(ADC10CTL0_L); /* ADC10 Control 0 */
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SFR_8BIT(ADC10CTL0_H); /* ADC10 Control 0 */
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SFR_16BIT(ADC10CTL1); /* ADC10 Control 1 */
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SFR_8BIT(ADC10CTL1_L); /* ADC10 Control 1 */
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SFR_8BIT(ADC10CTL1_H); /* ADC10 Control 1 */
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SFR_16BIT(ADC10CTL2); /* ADC10 Control 2 */
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SFR_8BIT(ADC10CTL2_L); /* ADC10 Control 2 */
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SFR_8BIT(ADC10CTL2_H); /* ADC10 Control 2 */
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SFR_16BIT(ADC10LO); /* ADC10 Window Comparator High Threshold */
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SFR_8BIT(ADC10LO_L); /* ADC10 Window Comparator High Threshold */
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SFR_8BIT(ADC10LO_H); /* ADC10 Window Comparator High Threshold */
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SFR_16BIT(ADC10HI); /* ADC10 Window Comparator High Threshold */
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SFR_8BIT(ADC10HI_L); /* ADC10 Window Comparator High Threshold */
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SFR_8BIT(ADC10HI_H); /* ADC10 Window Comparator High Threshold */
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SFR_16BIT(ADC10MCTL0); /* ADC10 Memory Control 0 */
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SFR_8BIT(ADC10MCTL0_L); /* ADC10 Memory Control 0 */
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SFR_8BIT(ADC10MCTL0_H); /* ADC10 Memory Control 0 */
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SFR_16BIT(ADC10MEM0); /* ADC10 Conversion Memory 0 */
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SFR_8BIT(ADC10MEM0_L); /* ADC10 Conversion Memory 0 */
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SFR_8BIT(ADC10MEM0_H); /* ADC10 Conversion Memory 0 */
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SFR_16BIT(ADC10IE); /* ADC10 Interrupt Enable */
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SFR_8BIT(ADC10IE_L); /* ADC10 Interrupt Enable */
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SFR_8BIT(ADC10IE_H); /* ADC10 Interrupt Enable */
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SFR_16BIT(ADC10IFG); /* ADC10 Interrupt Flag */
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SFR_8BIT(ADC10IFG_L); /* ADC10 Interrupt Flag */
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SFR_8BIT(ADC10IFG_H); /* ADC10 Interrupt Flag */
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SFR_16BIT(ADC10IV); /* ADC10 Interrupt Vector Word */
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SFR_8BIT(ADC10IV_L); /* ADC10 Interrupt Vector Word */
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SFR_8BIT(ADC10IV_H); /* ADC10 Interrupt Vector Word */
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/* ADC10CTL0 Control Bits */
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#define ADC10SC (0x0001) /* ADC10 Start Conversion */
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#define ADC10ENC (0x0002) /* ADC10 Enable Conversion */
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#define ADC10ON (0x0010) /* ADC10 On/enable */
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#define ADC10MSC (0x0080) /* ADC10 Multiple SampleConversion */
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#define ADC10SHT0 (0x0100) /* ADC10 Sample Hold Select Bit: 0 */
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#define ADC10SHT1 (0x0200) /* ADC10 Sample Hold Select Bit: 1 */
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#define ADC10SHT2 (0x0400) /* ADC10 Sample Hold Select Bit: 2 */
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#define ADC10SHT3 (0x0800) /* ADC10 Sample Hold Select Bit: 3 */
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/* ADC10CTL0 Control Bits */
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#define ADC10SC_L (0x0001) /* ADC10 Start Conversion */
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#define ADC10ENC_L (0x0002) /* ADC10 Enable Conversion */
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#define ADC10ON_L (0x0010) /* ADC10 On/enable */
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#define ADC10MSC_L (0x0080) /* ADC10 Multiple SampleConversion */
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/* ADC10CTL0 Control Bits */
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#define ADC10SHT0_H (0x0001) /* ADC10 Sample Hold Select Bit: 0 */
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#define ADC10SHT1_H (0x0002) /* ADC10 Sample Hold Select Bit: 1 */
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#define ADC10SHT2_H (0x0004) /* ADC10 Sample Hold Select Bit: 2 */
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#define ADC10SHT3_H (0x0008) /* ADC10 Sample Hold Select Bit: 3 */
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#define ADC10SHT_0 (0*0x100u) /* ADC10 Sample Hold Select 0 */
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#define ADC10SHT_1 (1*0x100u) /* ADC10 Sample Hold Select 1 */
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#define ADC10SHT_2 (2*0x100u) /* ADC10 Sample Hold Select 2 */
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#define ADC10SHT_3 (3*0x100u) /* ADC10 Sample Hold Select 3 */
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#define ADC10SHT_4 (4*0x100u) /* ADC10 Sample Hold Select 4 */
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#define ADC10SHT_5 (5*0x100u) /* ADC10 Sample Hold Select 5 */
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#define ADC10SHT_6 (6*0x100u) /* ADC10 Sample Hold Select 6 */
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#define ADC10SHT_7 (7*0x100u) /* ADC10 Sample Hold Select 7 */
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#define ADC10SHT_8 (8*0x100u) /* ADC10 Sample Hold Select 8 */
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#define ADC10SHT_9 (9*0x100u) /* ADC10 Sample Hold Select 9 */
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#define ADC10SHT_10 (10*0x100u) /* ADC10 Sample Hold Select 10 */
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#define ADC10SHT_11 (11*0x100u) /* ADC10 Sample Hold Select 11 */
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#define ADC10SHT_12 (12*0x100u) /* ADC10 Sample Hold Select 12 */
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#define ADC10SHT_13 (13*0x100u) /* ADC10 Sample Hold Select 13 */
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#define ADC10SHT_14 (14*0x100u) /* ADC10 Sample Hold Select 14 */
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#define ADC10SHT_15 (15*0x100u) /* ADC10 Sample Hold Select 15 */
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/* ADC10CTL1 Control Bits */
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#define ADC10BUSY (0x0001) /* ADC10 Busy */
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#define ADC10CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */
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#define ADC10CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */
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#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select 0 */
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#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select 1 */
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#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select 0 */
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#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select 1 */
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#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select 2 */
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#define ADC10ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */
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#define ADC10SHP (0x0200) /* ADC10 Sample/Hold Pulse Mode */
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#define ADC10SHS0 (0x0400) /* ADC10 Sample/Hold Source 0 */
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#define ADC10SHS1 (0x0800) /* ADC10 Sample/Hold Source 1 */
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/* ADC10CTL1 Control Bits */
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#define ADC10BUSY_L (0x0001) /* ADC10 Busy */
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#define ADC10CONSEQ0_L (0x0002) /* ADC10 Conversion Sequence Select 0 */
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#define ADC10CONSEQ1_L (0x0004) /* ADC10 Conversion Sequence Select 1 */
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#define ADC10SSEL0_L (0x0008) /* ADC10 Clock Source Select 0 */
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#define ADC10SSEL1_L (0x0010) /* ADC10 Clock Source Select 1 */
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#define ADC10DIV0_L (0x0020) /* ADC10 Clock Divider Select 0 */
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#define ADC10DIV1_L (0x0040) /* ADC10 Clock Divider Select 1 */
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#define ADC10DIV2_L (0x0080) /* ADC10 Clock Divider Select 2 */
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/* ADC10CTL1 Control Bits */
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#define ADC10ISSH_H (0x0001) /* ADC10 Invert Sample Hold Signal */
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#define ADC10SHP_H (0x0002) /* ADC10 Sample/Hold Pulse Mode */
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#define ADC10SHS0_H (0x0004) /* ADC10 Sample/Hold Source 0 */
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#define ADC10SHS1_H (0x0008) /* ADC10 Sample/Hold Source 1 */
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#define ADC10CONSEQ_0 (0*2u) /* ADC10 Conversion Sequence Select: 0 */
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#define ADC10CONSEQ_1 (1*2u) /* ADC10 Conversion Sequence Select: 1 */
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#define ADC10CONSEQ_2 (2*2u) /* ADC10 Conversion Sequence Select: 2 */
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#define ADC10CONSEQ_3 (3*2u) /* ADC10 Conversion Sequence Select: 3 */
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#define ADC10SSEL_0 (0*8u) /* ADC10 Clock Source Select: 0 */
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#define ADC10SSEL_1 (1*8u) /* ADC10 Clock Source Select: 1 */
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#define ADC10SSEL_2 (2*8u) /* ADC10 Clock Source Select: 2 */
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#define ADC10SSEL_3 (3*8u) /* ADC10 Clock Source Select: 3 */
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#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select: 0 */
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#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select: 1 */
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#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select: 2 */
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#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select: 3 */
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#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select: 4 */
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#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select: 5 */
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#define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select: 6 */
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#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select: 7 */
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#define ADC10SHS_0 (0*0x400u) /* ADC10 Sample/Hold Source: 0 */
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#define ADC10SHS_1 (1*0x400u) /* ADC10 Sample/Hold Source: 1 */
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#define ADC10SHS_2 (2*0x400u) /* ADC10 Sample/Hold Source: 2 */
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#define ADC10SHS_3 (3*0x400u) /* ADC10 Sample/Hold Source: 3 */
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/* ADC10CTL2 Control Bits */
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#define ADC10REFBURST (0x0001) /* ADC10 Reference Burst */
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#define ADC10SR (0x0004) /* ADC10 Sampling Rate */
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#define ADC10DF (0x0008) /* ADC10 Data Format */
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#define ADC10RES (0x0010) /* ADC10 Resolution Bit */
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#define ADC10PDIV0 (0x0100) /* ADC10 predivider Bit: 0 */
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#define ADC10PDIV1 (0x0200) /* ADC10 predivider Bit: 1 */
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/* ADC10CTL2 Control Bits */
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#define ADC10REFBURST_L (0x0001) /* ADC10 Reference Burst */
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#define ADC10SR_L (0x0004) /* ADC10 Sampling Rate */
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#define ADC10DF_L (0x0008) /* ADC10 Data Format */
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#define ADC10RES_L (0x0010) /* ADC10 Resolution Bit */
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/* ADC10CTL2 Control Bits */
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#define ADC10PDIV0_H (0x0001) /* ADC10 predivider Bit: 0 */
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#define ADC10PDIV1_H (0x0002) /* ADC10 predivider Bit: 1 */
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#define ADC10PDIV_0 (0x0000) /* ADC10 predivider /1 */
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#define ADC10PDIV_1 (0x0100) /* ADC10 predivider /2 */
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#define ADC10PDIV_2 (0x0200) /* ADC10 predivider /64 */
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#define ADC10PDIV_3 (0x0300) /* ADC10 predivider reserved */
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#define ADC10PDIV__1 (0x0000) /* ADC10 predivider /1 */
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#define ADC10PDIV__4 (0x0100) /* ADC10 predivider /2 */
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#define ADC10PDIV__64 (0x0200) /* ADC10 predivider /64 */
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/* ADC10MCTL0 Control Bits */
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#define ADC10INCH0 (0x0001) /* ADC10 Input Channel Select Bit 0 */
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#define ADC10INCH1 (0x0002) /* ADC10 Input Channel Select Bit 1 */
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#define ADC10INCH2 (0x0004) /* ADC10 Input Channel Select Bit 2 */
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#define ADC10INCH3 (0x0008) /* ADC10 Input Channel Select Bit 3 */
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#define ADC10SREF0 (0x0010) /* ADC10 Select Reference Bit 0 */
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#define ADC10SREF1 (0x0020) /* ADC10 Select Reference Bit 1 */
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#define ADC10SREF2 (0x0040) /* ADC10 Select Reference Bit 2 */
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281 |
|
|
|
282 |
/* ADC10MCTL0 Control Bits */
|
|
|
283 |
#define ADC10INCH0_L (0x0001) /* ADC10 Input Channel Select Bit 0 */
|
|
|
284 |
#define ADC10INCH1_L (0x0002) /* ADC10 Input Channel Select Bit 1 */
|
|
|
285 |
#define ADC10INCH2_L (0x0004) /* ADC10 Input Channel Select Bit 2 */
|
|
|
286 |
#define ADC10INCH3_L (0x0008) /* ADC10 Input Channel Select Bit 3 */
|
|
|
287 |
#define ADC10SREF0_L (0x0010) /* ADC10 Select Reference Bit 0 */
|
|
|
288 |
#define ADC10SREF1_L (0x0020) /* ADC10 Select Reference Bit 1 */
|
|
|
289 |
#define ADC10SREF2_L (0x0040) /* ADC10 Select Reference Bit 2 */
|
|
|
290 |
|
|
|
291 |
/* ADC10MCTL0 Control Bits */
|
|
|
292 |
|
|
|
293 |
#define ADC10INCH_0 (0) /* ADC10 Input Channel 0 */
|
|
|
294 |
#define ADC10INCH_1 (1) /* ADC10 Input Channel 1 */
|
|
|
295 |
#define ADC10INCH_2 (2) /* ADC10 Input Channel 2 */
|
|
|
296 |
#define ADC10INCH_3 (3) /* ADC10 Input Channel 3 */
|
|
|
297 |
#define ADC10INCH_4 (4) /* ADC10 Input Channel 4 */
|
|
|
298 |
#define ADC10INCH_5 (5) /* ADC10 Input Channel 5 */
|
|
|
299 |
#define ADC10INCH_6 (6) /* ADC10 Input Channel 6 */
|
|
|
300 |
#define ADC10INCH_7 (7) /* ADC10 Input Channel 7 */
|
|
|
301 |
#define ADC10INCH_8 (8) /* ADC10 Input Channel 8 */
|
|
|
302 |
#define ADC10INCH_9 (9) /* ADC10 Input Channel 9 */
|
|
|
303 |
#define ADC10INCH_10 (10) /* ADC10 Input Channel 10 */
|
|
|
304 |
#define ADC10INCH_11 (11) /* ADC10 Input Channel 11 */
|
|
|
305 |
#define ADC10INCH_12 (12) /* ADC10 Input Channel 12 */
|
|
|
306 |
#define ADC10INCH_13 (13) /* ADC10 Input Channel 13 */
|
|
|
307 |
#define ADC10INCH_14 (14) /* ADC10 Input Channel 14 */
|
|
|
308 |
#define ADC10INCH_15 (15) /* ADC10 Input Channel 15 */
|
|
|
309 |
|
|
|
310 |
#define ADC10SREF_0 (0*0x10u) /* ADC10 Select Reference 0 */
|
|
|
311 |
#define ADC10SREF_1 (1*0x10u) /* ADC10 Select Reference 1 */
|
|
|
312 |
#define ADC10SREF_2 (2*0x10u) /* ADC10 Select Reference 2 */
|
|
|
313 |
#define ADC10SREF_3 (3*0x10u) /* ADC10 Select Reference 3 */
|
|
|
314 |
#define ADC10SREF_4 (4*0x10u) /* ADC10 Select Reference 4 */
|
|
|
315 |
#define ADC10SREF_5 (5*0x10u) /* ADC10 Select Reference 5 */
|
|
|
316 |
#define ADC10SREF_6 (6*0x10u) /* ADC10 Select Reference 6 */
|
|
|
317 |
#define ADC10SREF_7 (7*0x10u) /* ADC10 Select Reference 7 */
|
|
|
318 |
|
|
|
319 |
/* ADC10IE Interrupt Enable Bits */
|
|
|
320 |
#define ADC10IE0 (0x0001) /* ADC10_A Interrupt enable */
|
|
|
321 |
#define ADC10INIE (0x0002) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
|
|
|
322 |
#define ADC10LOIE (0x0004) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
|
|
|
323 |
#define ADC10HIIE (0x0008) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
|
|
|
324 |
#define ADC10OVIE (0x0010) /* ADC10_A ADC10MEM overflow Interrupt enable */
|
|
|
325 |
#define ADC10TOVIE (0x0020) /* ADC10_A conversion-time-overflow Interrupt enable */
|
|
|
326 |
|
|
|
327 |
/* ADC10IE Interrupt Enable Bits */
|
|
|
328 |
#define ADC10IE0_L (0x0001) /* ADC10_A Interrupt enable */
|
|
|
329 |
#define ADC10INIE_L (0x0002) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
|
|
|
330 |
#define ADC10LOIE_L (0x0004) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
|
|
|
331 |
#define ADC10HIIE_L (0x0008) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
|
|
|
332 |
#define ADC10OVIE_L (0x0010) /* ADC10_A ADC10MEM overflow Interrupt enable */
|
|
|
333 |
#define ADC10TOVIE_L (0x0020) /* ADC10_A conversion-time-overflow Interrupt enable */
|
|
|
334 |
|
|
|
335 |
/* ADC10IE Interrupt Enable Bits */
|
|
|
336 |
|
|
|
337 |
/* ADC10IFG Interrupt Flag Bits */
|
|
|
338 |
#define ADC10IFG0 (0x0001) /* ADC10_A Interrupt Flag */
|
|
|
339 |
#define ADC10INIFG (0x0002) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
|
|
|
340 |
#define ADC10LOIFG (0x0004) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
|
|
|
341 |
#define ADC10HIIFG (0x0008) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
|
|
|
342 |
#define ADC10OVIFG (0x0010) /* ADC10_A ADC10MEM overflow Interrupt Flag */
|
|
|
343 |
#define ADC10TOVIFG (0x0020) /* ADC10_A conversion-time-overflow Interrupt Flag */
|
|
|
344 |
|
|
|
345 |
/* ADC10IFG Interrupt Flag Bits */
|
|
|
346 |
#define ADC10IFG0_L (0x0001) /* ADC10_A Interrupt Flag */
|
|
|
347 |
#define ADC10INIFG_L (0x0002) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
|
|
|
348 |
#define ADC10LOIFG_L (0x0004) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
|
|
|
349 |
#define ADC10HIIFG_L (0x0008) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
|
|
|
350 |
#define ADC10OVIFG_L (0x0010) /* ADC10_A ADC10MEM overflow Interrupt Flag */
|
|
|
351 |
#define ADC10TOVIFG_L (0x0020) /* ADC10_A conversion-time-overflow Interrupt Flag */
|
|
|
352 |
|
|
|
353 |
/* ADC10IFG Interrupt Flag Bits */
|
|
|
354 |
|
|
|
355 |
/* ADC10IV Definitions */
|
|
|
356 |
#define ADC10IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
357 |
#define ADC10IV_ADC10OVIFG (0x0002) /* ADC10OVIFG */
|
|
|
358 |
#define ADC10IV_ADC10TOVIFG (0x0004) /* ADC10TOVIFG */
|
|
|
359 |
#define ADC10IV_ADC10HIIFG (0x0006) /* ADC10HIIFG */
|
|
|
360 |
#define ADC10IV_ADC10LOIFG (0x0008) /* ADC10LOIFG */
|
|
|
361 |
#define ADC10IV_ADC10INIFG (0x000A) /* ADC10INIFG */
|
|
|
362 |
#define ADC10IV_ADC10IFG (0x000C) /* ADC10IFG */
|
|
|
363 |
|
|
|
364 |
/************************************************************
|
|
|
365 |
* CLOCK SYSTEM
|
|
|
366 |
************************************************************/
|
|
|
367 |
#define __MSP430_HAS_CS__ /* Definition to show that Module is available */
|
|
|
368 |
#define __MSP430_BASEADDRESS_CS__ 0x0160
|
|
|
369 |
|
|
|
370 |
SFR_16BIT(CSCTL0); /* CS Control Register 0 */
|
|
|
371 |
SFR_8BIT(CSCTL0_L); /* CS Control Register 0 */
|
|
|
372 |
SFR_8BIT(CSCTL0_H); /* CS Control Register 0 */
|
|
|
373 |
SFR_16BIT(CSCTL1); /* CS Control Register 1 */
|
|
|
374 |
SFR_8BIT(CSCTL1_L); /* CS Control Register 1 */
|
|
|
375 |
SFR_8BIT(CSCTL1_H); /* CS Control Register 1 */
|
|
|
376 |
SFR_16BIT(CSCTL2); /* CS Control Register 2 */
|
|
|
377 |
SFR_8BIT(CSCTL2_L); /* CS Control Register 2 */
|
|
|
378 |
SFR_8BIT(CSCTL2_H); /* CS Control Register 2 */
|
|
|
379 |
SFR_16BIT(CSCTL3); /* CS Control Register 3 */
|
|
|
380 |
SFR_8BIT(CSCTL3_L); /* CS Control Register 3 */
|
|
|
381 |
SFR_8BIT(CSCTL3_H); /* CS Control Register 3 */
|
|
|
382 |
SFR_16BIT(CSCTL4); /* CS Control Register 4 */
|
|
|
383 |
SFR_8BIT(CSCTL4_L); /* CS Control Register 4 */
|
|
|
384 |
SFR_8BIT(CSCTL4_H); /* CS Control Register 4 */
|
|
|
385 |
SFR_16BIT(CSCTL5); /* CS Control Register 5 */
|
|
|
386 |
SFR_8BIT(CSCTL5_L); /* CS Control Register 5 */
|
|
|
387 |
SFR_8BIT(CSCTL5_H); /* CS Control Register 5 */
|
|
|
388 |
SFR_16BIT(CSCTL6); /* CS Control Register 6 */
|
|
|
389 |
SFR_8BIT(CSCTL6_L); /* CS Control Register 6 */
|
|
|
390 |
SFR_8BIT(CSCTL6_H); /* CS Control Register 6 */
|
|
|
391 |
|
|
|
392 |
/* CSCTL0 Control Bits */
|
|
|
393 |
|
|
|
394 |
/* CSCTL0 Control Bits */
|
|
|
395 |
|
|
|
396 |
/* CSCTL0 Control Bits */
|
|
|
397 |
#define CSKEY (0xA500) /* CS Password */
|
|
|
398 |
|
|
|
399 |
/* CSCTL1 Control Bits */
|
|
|
400 |
#define DCOFSEL0 (0x0002) /* DCO frequency select Bit: 0 */
|
|
|
401 |
#define DCOFSEL1 (0x0004) /* DCO frequency select Bit: 1 */
|
|
|
402 |
#define DCORSEL (0x0080) /* DCO range select. */
|
|
|
403 |
|
|
|
404 |
/* CSCTL1 Control Bits */
|
|
|
405 |
#define DCOFSEL0_L (0x0002) /* DCO frequency select Bit: 0 */
|
|
|
406 |
#define DCOFSEL1_L (0x0004) /* DCO frequency select Bit: 1 */
|
|
|
407 |
#define DCORSEL_L (0x0080) /* DCO range select. */
|
|
|
408 |
|
|
|
409 |
/* CSCTL1 Control Bits */
|
|
|
410 |
|
|
|
411 |
#define DCOFSEL_0 (0x0000) /* DCO frequency select: 0 */
|
|
|
412 |
#define DCOFSEL_1 (0x0002) /* DCO frequency select: 1 */
|
|
|
413 |
#define DCOFSEL_2 (0x0004) /* DCO frequency select: 2 */
|
|
|
414 |
#define DCOFSEL_3 (0x0006) /* DCO frequency select: 3 */
|
|
|
415 |
|
|
|
416 |
/* CSCTL2 Control Bits */
|
|
|
417 |
#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
|
|
|
418 |
#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
|
|
|
419 |
#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
|
|
|
420 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
421 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
422 |
#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
|
|
|
423 |
#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
|
|
|
424 |
#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
|
|
|
425 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
426 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
427 |
#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
|
|
|
428 |
#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
|
|
|
429 |
#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
|
|
|
430 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
431 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
432 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
433 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
434 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
435 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
436 |
|
|
|
437 |
/* CSCTL2 Control Bits */
|
|
|
438 |
#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
|
|
|
439 |
#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
|
|
|
440 |
#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
|
|
|
441 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
442 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
443 |
#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
|
|
|
444 |
#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
|
|
|
445 |
#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
|
|
|
446 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
447 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
448 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
449 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
450 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
451 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
452 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
453 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
454 |
|
|
|
455 |
/* CSCTL2 Control Bits */
|
|
|
456 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
457 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
458 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
459 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
460 |
#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
|
|
|
461 |
#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
|
|
|
462 |
#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
|
|
|
463 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
464 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
465 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
466 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
467 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
468 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
469 |
|
|
|
470 |
#define SELM_0 (0x0000) /* MCLK Source Select 0 */
|
|
|
471 |
#define SELM_1 (0x0001) /* MCLK Source Select 1 */
|
|
|
472 |
#define SELM_2 (0x0002) /* MCLK Source Select 2 */
|
|
|
473 |
#define SELM_3 (0x0003) /* MCLK Source Select 3 */
|
|
|
474 |
#define SELM_4 (0x0004) /* MCLK Source Select 4 */
|
|
|
475 |
#define SELM_5 (0x0005) /* MCLK Source Select 5 */
|
|
|
476 |
#define SELM_6 (0x0006) /* MCLK Source Select 6 */
|
|
|
477 |
#define SELM_7 (0x0007) /* MCLK Source Select 7 */
|
|
|
478 |
#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */
|
|
|
479 |
#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
|
|
|
480 |
#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
|
|
|
481 |
#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */
|
|
|
482 |
|
|
|
483 |
#define SELS_0 (0x0000) /* SMCLK Source Select 0 */
|
|
|
484 |
#define SELS_1 (0x0010) /* SMCLK Source Select 1 */
|
|
|
485 |
#define SELS_2 (0x0020) /* SMCLK Source Select 2 */
|
|
|
486 |
#define SELS_3 (0x0030) /* SMCLK Source Select 3 */
|
|
|
487 |
#define SELS_4 (0x0040) /* SMCLK Source Select 4 */
|
|
|
488 |
#define SELS_5 (0x0050) /* SMCLK Source Select 5 */
|
|
|
489 |
#define SELS_6 (0x0060) /* SMCLK Source Select 6 */
|
|
|
490 |
#define SELS_7 (0x0070) /* SMCLK Source Select 7 */
|
|
|
491 |
#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */
|
|
|
492 |
#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
|
|
|
493 |
#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
|
|
|
494 |
#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */
|
|
|
495 |
|
|
|
496 |
#define SELA_0 (0x0000) /* ACLK Source Select 0 */
|
|
|
497 |
#define SELA_1 (0x0100) /* ACLK Source Select 1 */
|
|
|
498 |
#define SELA_2 (0x0200) /* ACLK Source Select 2 */
|
|
|
499 |
#define SELA_3 (0x0300) /* ACLK Source Select 3 */
|
|
|
500 |
#define SELA_4 (0x0400) /* ACLK Source Select 4 */
|
|
|
501 |
#define SELA_5 (0x0500) /* ACLK Source Select 5 */
|
|
|
502 |
#define SELA_6 (0x0600) /* ACLK Source Select 6 */
|
|
|
503 |
#define SELA_7 (0x0700) /* ACLK Source Select 7 */
|
|
|
504 |
#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */
|
|
|
505 |
#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
|
|
|
506 |
#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */
|
|
|
507 |
#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */
|
|
|
508 |
|
|
|
509 |
/* CSCTL3 Control Bits */
|
|
|
510 |
#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
|
|
|
511 |
#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
|
|
|
512 |
#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
|
|
|
513 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
514 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
515 |
#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
|
|
|
516 |
#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
|
|
|
517 |
#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
|
|
|
518 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
519 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
520 |
#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
|
|
|
521 |
#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
|
|
|
522 |
#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
|
|
|
523 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
524 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
525 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
526 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
527 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
528 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
529 |
|
|
|
530 |
/* CSCTL3 Control Bits */
|
|
|
531 |
#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
|
|
|
532 |
#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
|
|
|
533 |
#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
|
|
|
534 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
535 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
536 |
#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
|
|
|
537 |
#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
|
|
|
538 |
#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
|
|
|
539 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
540 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
541 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
542 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
543 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
544 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
545 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
546 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
547 |
|
|
|
548 |
/* CSCTL3 Control Bits */
|
|
|
549 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
550 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
551 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
552 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
553 |
#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
|
|
|
554 |
#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
|
|
|
555 |
#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
|
|
|
556 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
557 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
558 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
559 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
560 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
561 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
562 |
|
|
|
563 |
#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
|
|
|
564 |
#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
|
|
|
565 |
#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
|
|
|
566 |
#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
|
|
|
567 |
#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
|
|
|
568 |
#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
|
|
|
569 |
#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
|
|
|
570 |
#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
|
|
|
571 |
#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
|
|
|
572 |
#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
|
|
|
573 |
#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
|
|
|
574 |
#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
|
|
|
575 |
|
|
|
576 |
#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
|
|
|
577 |
#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
|
|
|
578 |
#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
|
|
|
579 |
#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
|
|
|
580 |
#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
|
|
|
581 |
#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
|
|
|
582 |
#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
|
|
|
583 |
#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
|
|
|
584 |
#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
|
|
|
585 |
#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
|
|
|
586 |
#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
|
|
|
587 |
#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
|
|
|
588 |
|
|
|
589 |
#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
|
|
|
590 |
#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
|
|
|
591 |
#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
|
|
|
592 |
#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
|
|
|
593 |
#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
|
|
|
594 |
#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
|
|
|
595 |
#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
|
|
|
596 |
#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
|
|
|
597 |
#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
|
|
|
598 |
#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
|
|
|
599 |
#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
|
|
|
600 |
#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
|
|
|
601 |
|
|
|
602 |
/* CSCTL4 Control Bits */
|
|
|
603 |
#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
|
|
|
604 |
#define SMCLKOFF (0x0002) /* SMCLK Off */
|
|
|
605 |
#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
|
|
|
606 |
#define XTS (0x0020) /* 1: Selects high-freq. oscillator */
|
|
|
607 |
#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */
|
|
|
608 |
#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */
|
|
|
609 |
#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */
|
|
|
610 |
#define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
|
|
|
611 |
#define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */
|
|
|
612 |
#define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */
|
|
|
613 |
|
|
|
614 |
/* CSCTL4 Control Bits */
|
|
|
615 |
#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
|
|
|
616 |
#define SMCLKOFF_L (0x0002) /* SMCLK Off */
|
|
|
617 |
#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
|
|
|
618 |
#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */
|
|
|
619 |
#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */
|
|
|
620 |
#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */
|
|
|
621 |
|
|
|
622 |
/* CSCTL4 Control Bits */
|
|
|
623 |
#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */
|
|
|
624 |
#define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
|
|
|
625 |
#define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */
|
|
|
626 |
#define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */
|
|
|
627 |
|
|
|
628 |
#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */
|
|
|
629 |
#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */
|
|
|
630 |
#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */
|
|
|
631 |
#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */
|
|
|
632 |
#define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */
|
|
|
633 |
#define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */
|
|
|
634 |
#define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */
|
|
|
635 |
#define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */
|
|
|
636 |
|
|
|
637 |
/* CSCTL5 Control Bits */
|
|
|
638 |
#define XT1OFFG (0x0001) /* XT1 Low Frequency Oscillator Fault Flag */
|
|
|
639 |
#define XT2OFFG (0x0002) /* High Frequency Oscillator 2 Fault Flag */
|
|
|
640 |
#define ENSTFCNT1 (0x0040) /* Enable start counter for XT1 */
|
|
|
641 |
#define ENSTFCNT2 (0x0080) /* Enable start counter for XT2 */
|
|
|
642 |
|
|
|
643 |
/* CSCTL5 Control Bits */
|
|
|
644 |
#define XT1OFFG_L (0x0001) /* XT1 Low Frequency Oscillator Fault Flag */
|
|
|
645 |
#define XT2OFFG_L (0x0002) /* High Frequency Oscillator 2 Fault Flag */
|
|
|
646 |
#define ENSTFCNT1_L (0x0040) /* Enable start counter for XT1 */
|
|
|
647 |
#define ENSTFCNT2_L (0x0080) /* Enable start counter for XT2 */
|
|
|
648 |
|
|
|
649 |
/* CSCTL5 Control Bits */
|
|
|
650 |
|
|
|
651 |
/* CSCTL6 Control Bits */
|
|
|
652 |
#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
|
|
|
653 |
#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
|
|
|
654 |
#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
|
|
|
655 |
#define MODCLKREQEN (0x0008) /* MODOSC Clock Request Enable */
|
|
|
656 |
|
|
|
657 |
/* CSCTL6 Control Bits */
|
|
|
658 |
#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
|
|
|
659 |
#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
|
|
|
660 |
#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
|
|
|
661 |
#define MODCLKREQEN_L (0x0008) /* MODOSC Clock Request Enable */
|
|
|
662 |
|
|
|
663 |
/* CSCTL6 Control Bits */
|
|
|
664 |
|
|
|
665 |
/************************************************************
|
|
|
666 |
* Comparator D
|
|
|
667 |
************************************************************/
|
|
|
668 |
#define __MSP430_HAS_COMPD__ /* Definition to show that Module is available */
|
|
|
669 |
#define __MSP430_BASEADDRESS_COMPD__ 0x08C0
|
|
|
670 |
|
|
|
671 |
SFR_16BIT(CDCTL0); /* Comparator D Control Register 0 */
|
|
|
672 |
SFR_8BIT(CDCTL0_L); /* Comparator D Control Register 0 */
|
|
|
673 |
SFR_8BIT(CDCTL0_H); /* Comparator D Control Register 0 */
|
|
|
674 |
SFR_16BIT(CDCTL1); /* Comparator D Control Register 1 */
|
|
|
675 |
SFR_8BIT(CDCTL1_L); /* Comparator D Control Register 1 */
|
|
|
676 |
SFR_8BIT(CDCTL1_H); /* Comparator D Control Register 1 */
|
|
|
677 |
SFR_16BIT(CDCTL2); /* Comparator D Control Register 2 */
|
|
|
678 |
SFR_8BIT(CDCTL2_L); /* Comparator D Control Register 2 */
|
|
|
679 |
SFR_8BIT(CDCTL2_H); /* Comparator D Control Register 2 */
|
|
|
680 |
SFR_16BIT(CDCTL3); /* Comparator D Control Register 3 */
|
|
|
681 |
SFR_8BIT(CDCTL3_L); /* Comparator D Control Register 3 */
|
|
|
682 |
SFR_8BIT(CDCTL3_H); /* Comparator D Control Register 3 */
|
|
|
683 |
SFR_16BIT(CDINT); /* Comparator D Interrupt Register */
|
|
|
684 |
SFR_8BIT(CDINT_L); /* Comparator D Interrupt Register */
|
|
|
685 |
SFR_8BIT(CDINT_H); /* Comparator D Interrupt Register */
|
|
|
686 |
SFR_16BIT(CDIV); /* Comparator D Interrupt Vector Word */
|
|
|
687 |
SFR_8BIT(CDIV_L); /* Comparator D Interrupt Vector Word */
|
|
|
688 |
SFR_8BIT(CDIV_H); /* Comparator D Interrupt Vector Word */
|
|
|
689 |
|
|
|
690 |
/* CDCTL0 Control Bits */
|
|
|
691 |
#define CDIPSEL0 (0x0001) /* Comp. D Pos. Channel Input Select 0 */
|
|
|
692 |
#define CDIPSEL1 (0x0002) /* Comp. D Pos. Channel Input Select 1 */
|
|
|
693 |
#define CDIPSEL2 (0x0004) /* Comp. D Pos. Channel Input Select 2 */
|
|
|
694 |
#define CDIPSEL3 (0x0008) /* Comp. D Pos. Channel Input Select 3 */
|
|
|
695 |
//#define RESERVED (0x0010) /* Comp. D */
|
|
|
696 |
//#define RESERVED (0x0020) /* Comp. D */
|
|
|
697 |
//#define RESERVED (0x0040) /* Comp. D */
|
|
|
698 |
#define CDIPEN (0x0080) /* Comp. D Pos. Channel Input Enable */
|
|
|
699 |
#define CDIMSEL0 (0x0100) /* Comp. D Neg. Channel Input Select 0 */
|
|
|
700 |
#define CDIMSEL1 (0x0200) /* Comp. D Neg. Channel Input Select 1 */
|
|
|
701 |
#define CDIMSEL2 (0x0400) /* Comp. D Neg. Channel Input Select 2 */
|
|
|
702 |
#define CDIMSEL3 (0x0800) /* Comp. D Neg. Channel Input Select 3 */
|
|
|
703 |
//#define RESERVED (0x1000) /* Comp. D */
|
|
|
704 |
//#define RESERVED (0x2000) /* Comp. D */
|
|
|
705 |
//#define RESERVED (0x4000) /* Comp. D */
|
|
|
706 |
#define CDIMEN (0x8000) /* Comp. D Neg. Channel Input Enable */
|
|
|
707 |
|
|
|
708 |
/* CDCTL0 Control Bits */
|
|
|
709 |
#define CDIPSEL0_L (0x0001) /* Comp. D Pos. Channel Input Select 0 */
|
|
|
710 |
#define CDIPSEL1_L (0x0002) /* Comp. D Pos. Channel Input Select 1 */
|
|
|
711 |
#define CDIPSEL2_L (0x0004) /* Comp. D Pos. Channel Input Select 2 */
|
|
|
712 |
#define CDIPSEL3_L (0x0008) /* Comp. D Pos. Channel Input Select 3 */
|
|
|
713 |
//#define RESERVED (0x0010) /* Comp. D */
|
|
|
714 |
//#define RESERVED (0x0020) /* Comp. D */
|
|
|
715 |
//#define RESERVED (0x0040) /* Comp. D */
|
|
|
716 |
#define CDIPEN_L (0x0080) /* Comp. D Pos. Channel Input Enable */
|
|
|
717 |
//#define RESERVED (0x1000) /* Comp. D */
|
|
|
718 |
//#define RESERVED (0x2000) /* Comp. D */
|
|
|
719 |
//#define RESERVED (0x4000) /* Comp. D */
|
|
|
720 |
|
|
|
721 |
/* CDCTL0 Control Bits */
|
|
|
722 |
//#define RESERVED (0x0010) /* Comp. D */
|
|
|
723 |
//#define RESERVED (0x0020) /* Comp. D */
|
|
|
724 |
//#define RESERVED (0x0040) /* Comp. D */
|
|
|
725 |
#define CDIMSEL0_H (0x0001) /* Comp. D Neg. Channel Input Select 0 */
|
|
|
726 |
#define CDIMSEL1_H (0x0002) /* Comp. D Neg. Channel Input Select 1 */
|
|
|
727 |
#define CDIMSEL2_H (0x0004) /* Comp. D Neg. Channel Input Select 2 */
|
|
|
728 |
#define CDIMSEL3_H (0x0008) /* Comp. D Neg. Channel Input Select 3 */
|
|
|
729 |
//#define RESERVED (0x1000) /* Comp. D */
|
|
|
730 |
//#define RESERVED (0x2000) /* Comp. D */
|
|
|
731 |
//#define RESERVED (0x4000) /* Comp. D */
|
|
|
732 |
#define CDIMEN_H (0x0080) /* Comp. D Neg. Channel Input Enable */
|
|
|
733 |
|
|
|
734 |
#define CDIPSEL_0 (0x0000) /* Comp. D V+ terminal Input Select: Channel 0 */
|
|
|
735 |
#define CDIPSEL_1 (0x0001) /* Comp. D V+ terminal Input Select: Channel 1 */
|
|
|
736 |
#define CDIPSEL_2 (0x0002) /* Comp. D V+ terminal Input Select: Channel 2 */
|
|
|
737 |
#define CDIPSEL_3 (0x0003) /* Comp. D V+ terminal Input Select: Channel 3 */
|
|
|
738 |
#define CDIPSEL_4 (0x0004) /* Comp. D V+ terminal Input Select: Channel 4 */
|
|
|
739 |
#define CDIPSEL_5 (0x0005) /* Comp. D V+ terminal Input Select: Channel 5 */
|
|
|
740 |
#define CDIPSEL_6 (0x0006) /* Comp. D V+ terminal Input Select: Channel 6 */
|
|
|
741 |
#define CDIPSEL_7 (0x0007) /* Comp. D V+ terminal Input Select: Channel 7 */
|
|
|
742 |
#define CDIPSEL_8 (0x0008) /* Comp. D V+ terminal Input Select: Channel 8 */
|
|
|
743 |
#define CDIPSEL_9 (0x0009) /* Comp. D V+ terminal Input Select: Channel 9 */
|
|
|
744 |
#define CDIPSEL_10 (0x000A) /* Comp. D V+ terminal Input Select: Channel 10 */
|
|
|
745 |
#define CDIPSEL_11 (0x000B) /* Comp. D V+ terminal Input Select: Channel 11 */
|
|
|
746 |
#define CDIPSEL_12 (0x000C) /* Comp. D V+ terminal Input Select: Channel 12 */
|
|
|
747 |
#define CDIPSEL_13 (0x000D) /* Comp. D V+ terminal Input Select: Channel 13 */
|
|
|
748 |
#define CDIPSEL_14 (0x000E) /* Comp. D V+ terminal Input Select: Channel 14 */
|
|
|
749 |
#define CDIPSEL_15 (0x000F) /* Comp. D V+ terminal Input Select: Channel 15 */
|
|
|
750 |
|
|
|
751 |
#define CDIMSEL_0 (0x0000) /* Comp. D V- Terminal Input Select: Channel 0 */
|
|
|
752 |
#define CDIMSEL_1 (0x0100) /* Comp. D V- Terminal Input Select: Channel 1 */
|
|
|
753 |
#define CDIMSEL_2 (0x0200) /* Comp. D V- Terminal Input Select: Channel 2 */
|
|
|
754 |
#define CDIMSEL_3 (0x0300) /* Comp. D V- Terminal Input Select: Channel 3 */
|
|
|
755 |
#define CDIMSEL_4 (0x0400) /* Comp. D V- Terminal Input Select: Channel 4 */
|
|
|
756 |
#define CDIMSEL_5 (0x0500) /* Comp. D V- Terminal Input Select: Channel 5 */
|
|
|
757 |
#define CDIMSEL_6 (0x0600) /* Comp. D V- Terminal Input Select: Channel 6 */
|
|
|
758 |
#define CDIMSEL_7 (0x0700) /* Comp. D V- Terminal Input Select: Channel 7 */
|
|
|
759 |
#define CDIMSEL_8 (0x0800) /* Comp. D V- terminal Input Select: Channel 8 */
|
|
|
760 |
#define CDIMSEL_9 (0x0900) /* Comp. D V- terminal Input Select: Channel 9 */
|
|
|
761 |
#define CDIMSEL_10 (0x0A00) /* Comp. D V- terminal Input Select: Channel 10 */
|
|
|
762 |
#define CDIMSEL_11 (0x0B00) /* Comp. D V- terminal Input Select: Channel 11 */
|
|
|
763 |
#define CDIMSEL_12 (0x0C00) /* Comp. D V- terminal Input Select: Channel 12 */
|
|
|
764 |
#define CDIMSEL_13 (0x0D00) /* Comp. D V- terminal Input Select: Channel 13 */
|
|
|
765 |
#define CDIMSEL_14 (0x0E00) /* Comp. D V- terminal Input Select: Channel 14 */
|
|
|
766 |
#define CDIMSEL_15 (0x0F00) /* Comp. D V- terminal Input Select: Channel 15 */
|
|
|
767 |
|
|
|
768 |
/* CDCTL1 Control Bits */
|
|
|
769 |
#define CDOUT (0x0001) /* Comp. D Output */
|
|
|
770 |
#define CDOUTPOL (0x0002) /* Comp. D Output Polarity */
|
|
|
771 |
#define CDF (0x0004) /* Comp. D Enable Output Filter */
|
|
|
772 |
#define CDIES (0x0008) /* Comp. D Interrupt Edge Select */
|
|
|
773 |
#define CDSHORT (0x0010) /* Comp. D Input Short */
|
|
|
774 |
#define CDEX (0x0020) /* Comp. D Exchange Inputs */
|
|
|
775 |
#define CDFDLY0 (0x0040) /* Comp. D Filter delay Bit 0 */
|
|
|
776 |
#define CDFDLY1 (0x0080) /* Comp. D Filter delay Bit 1 */
|
|
|
777 |
//#define RESERVED (0x0100) /* Comp. D */
|
|
|
778 |
//#define RESERVED (0x0200) /* Comp. D */
|
|
|
779 |
#define CDON (0x0400) /* Comp. D enable */
|
|
|
780 |
#define CDMRVL (0x0800) /* Comp. D CDMRV Level */
|
|
|
781 |
#define CDMRVS (0x1000) /* Comp. D Output selects between VREF0 or VREF1*/
|
|
|
782 |
//#define RESERVED (0x2000) /* Comp. D */
|
|
|
783 |
//#define RESERVED (0x4000) /* Comp. D */
|
|
|
784 |
//#define RESERVED (0x8000) /* Comp. D */
|
|
|
785 |
|
|
|
786 |
/* CDCTL1 Control Bits */
|
|
|
787 |
#define CDOUT_L (0x0001) /* Comp. D Output */
|
|
|
788 |
#define CDOUTPOL_L (0x0002) /* Comp. D Output Polarity */
|
|
|
789 |
#define CDF_L (0x0004) /* Comp. D Enable Output Filter */
|
|
|
790 |
#define CDIES_L (0x0008) /* Comp. D Interrupt Edge Select */
|
|
|
791 |
#define CDSHORT_L (0x0010) /* Comp. D Input Short */
|
|
|
792 |
#define CDEX_L (0x0020) /* Comp. D Exchange Inputs */
|
|
|
793 |
#define CDFDLY0_L (0x0040) /* Comp. D Filter delay Bit 0 */
|
|
|
794 |
#define CDFDLY1_L (0x0080) /* Comp. D Filter delay Bit 1 */
|
|
|
795 |
//#define RESERVED (0x0100) /* Comp. D */
|
|
|
796 |
//#define RESERVED (0x0200) /* Comp. D */
|
|
|
797 |
//#define RESERVED (0x2000) /* Comp. D */
|
|
|
798 |
//#define RESERVED (0x4000) /* Comp. D */
|
|
|
799 |
//#define RESERVED (0x8000) /* Comp. D */
|
|
|
800 |
|
|
|
801 |
/* CDCTL1 Control Bits */
|
|
|
802 |
//#define RESERVED (0x0100) /* Comp. D */
|
|
|
803 |
//#define RESERVED (0x0200) /* Comp. D */
|
|
|
804 |
#define CDON_H (0x0004) /* Comp. D enable */
|
|
|
805 |
#define CDMRVL_H (0x0008) /* Comp. D CDMRV Level */
|
|
|
806 |
#define CDMRVS_H (0x0010) /* Comp. D Output selects between VREF0 or VREF1*/
|
|
|
807 |
//#define RESERVED (0x2000) /* Comp. D */
|
|
|
808 |
//#define RESERVED (0x4000) /* Comp. D */
|
|
|
809 |
//#define RESERVED (0x8000) /* Comp. D */
|
|
|
810 |
|
|
|
811 |
#define CDFDLY_0 (0x0000) /* Comp. D Filter delay 0 : 450ns */
|
|
|
812 |
#define CDFDLY_1 (0x0040) /* Comp. D Filter delay 1 : 900ns */
|
|
|
813 |
#define CDFDLY_2 (0x0080) /* Comp. D Filter delay 2 : 1800ns */
|
|
|
814 |
#define CDFDLY_3 (0x00C0) /* Comp. D Filter delay 3 : 3600ns */
|
|
|
815 |
|
|
|
816 |
/* CDCTL2 Control Bits */
|
|
|
817 |
#define CDREF00 (0x0001) /* Comp. D Reference 0 Resistor Select Bit : 0 */
|
|
|
818 |
#define CDREF01 (0x0002) /* Comp. D Reference 0 Resistor Select Bit : 1 */
|
|
|
819 |
#define CDREF02 (0x0004) /* Comp. D Reference 0 Resistor Select Bit : 2 */
|
|
|
820 |
#define CDREF03 (0x0008) /* Comp. D Reference 0 Resistor Select Bit : 3 */
|
|
|
821 |
#define CDREF04 (0x0010) /* Comp. D Reference 0 Resistor Select Bit : 4 */
|
|
|
822 |
#define CDRSEL (0x0020) /* Comp. D Reference select */
|
|
|
823 |
#define CDRS0 (0x0040) /* Comp. D Reference Source Bit : 0 */
|
|
|
824 |
#define CDRS1 (0x0080) /* Comp. D Reference Source Bit : 1 */
|
|
|
825 |
#define CDREF10 (0x0100) /* Comp. D Reference 1 Resistor Select Bit : 0 */
|
|
|
826 |
#define CDREF11 (0x0200) /* Comp. D Reference 1 Resistor Select Bit : 1 */
|
|
|
827 |
#define CDREF12 (0x0400) /* Comp. D Reference 1 Resistor Select Bit : 2 */
|
|
|
828 |
#define CDREF13 (0x0800) /* Comp. D Reference 1 Resistor Select Bit : 3 */
|
|
|
829 |
#define CDREF14 (0x1000) /* Comp. D Reference 1 Resistor Select Bit : 4 */
|
|
|
830 |
#define CDREFL0 (0x2000) /* Comp. D Reference voltage level Bit : 0 */
|
|
|
831 |
#define CDREFL1 (0x4000) /* Comp. D Reference voltage level Bit : 1 */
|
|
|
832 |
#define CDREFACC (0x8000) /* Comp. D Reference Accuracy */
|
|
|
833 |
|
|
|
834 |
/* CDCTL2 Control Bits */
|
|
|
835 |
#define CDREF00_L (0x0001) /* Comp. D Reference 0 Resistor Select Bit : 0 */
|
|
|
836 |
#define CDREF01_L (0x0002) /* Comp. D Reference 0 Resistor Select Bit : 1 */
|
|
|
837 |
#define CDREF02_L (0x0004) /* Comp. D Reference 0 Resistor Select Bit : 2 */
|
|
|
838 |
#define CDREF03_L (0x0008) /* Comp. D Reference 0 Resistor Select Bit : 3 */
|
|
|
839 |
#define CDREF04_L (0x0010) /* Comp. D Reference 0 Resistor Select Bit : 4 */
|
|
|
840 |
#define CDRSEL_L (0x0020) /* Comp. D Reference select */
|
|
|
841 |
#define CDRS0_L (0x0040) /* Comp. D Reference Source Bit : 0 */
|
|
|
842 |
#define CDRS1_L (0x0080) /* Comp. D Reference Source Bit : 1 */
|
|
|
843 |
|
|
|
844 |
/* CDCTL2 Control Bits */
|
|
|
845 |
#define CDREF10_H (0x0001) /* Comp. D Reference 1 Resistor Select Bit : 0 */
|
|
|
846 |
#define CDREF11_H (0x0002) /* Comp. D Reference 1 Resistor Select Bit : 1 */
|
|
|
847 |
#define CDREF12_H (0x0004) /* Comp. D Reference 1 Resistor Select Bit : 2 */
|
|
|
848 |
#define CDREF13_H (0x0008) /* Comp. D Reference 1 Resistor Select Bit : 3 */
|
|
|
849 |
#define CDREF14_H (0x0010) /* Comp. D Reference 1 Resistor Select Bit : 4 */
|
|
|
850 |
#define CDREFL0_H (0x0020) /* Comp. D Reference voltage level Bit : 0 */
|
|
|
851 |
#define CDREFL1_H (0x0040) /* Comp. D Reference voltage level Bit : 1 */
|
|
|
852 |
#define CDREFACC_H (0x0080) /* Comp. D Reference Accuracy */
|
|
|
853 |
|
|
|
854 |
#define CDREF0_0 (0x0000) /* Comp. D Int. Ref.0 Select 0 : 1/32 */
|
|
|
855 |
#define CDREF0_1 (0x0001) /* Comp. D Int. Ref.0 Select 1 : 2/32 */
|
|
|
856 |
#define CDREF0_2 (0x0002) /* Comp. D Int. Ref.0 Select 2 : 3/32 */
|
|
|
857 |
#define CDREF0_3 (0x0003) /* Comp. D Int. Ref.0 Select 3 : 4/32 */
|
|
|
858 |
#define CDREF0_4 (0x0004) /* Comp. D Int. Ref.0 Select 4 : 5/32 */
|
|
|
859 |
#define CDREF0_5 (0x0005) /* Comp. D Int. Ref.0 Select 5 : 6/32 */
|
|
|
860 |
#define CDREF0_6 (0x0006) /* Comp. D Int. Ref.0 Select 6 : 7/32 */
|
|
|
861 |
#define CDREF0_7 (0x0007) /* Comp. D Int. Ref.0 Select 7 : 8/32 */
|
|
|
862 |
#define CDREF0_8 (0x0008) /* Comp. D Int. Ref.0 Select 0 : 9/32 */
|
|
|
863 |
#define CDREF0_9 (0x0009) /* Comp. D Int. Ref.0 Select 1 : 10/32 */
|
|
|
864 |
#define CDREF0_10 (0x000A) /* Comp. D Int. Ref.0 Select 2 : 11/32 */
|
|
|
865 |
#define CDREF0_11 (0x000B) /* Comp. D Int. Ref.0 Select 3 : 12/32 */
|
|
|
866 |
#define CDREF0_12 (0x000C) /* Comp. D Int. Ref.0 Select 4 : 13/32 */
|
|
|
867 |
#define CDREF0_13 (0x000D) /* Comp. D Int. Ref.0 Select 5 : 14/32 */
|
|
|
868 |
#define CDREF0_14 (0x000E) /* Comp. D Int. Ref.0 Select 6 : 15/32 */
|
|
|
869 |
#define CDREF0_15 (0x000F) /* Comp. D Int. Ref.0 Select 7 : 16/32 */
|
|
|
870 |
#define CDREF0_16 (0x0010) /* Comp. D Int. Ref.0 Select 0 : 17/32 */
|
|
|
871 |
#define CDREF0_17 (0x0011) /* Comp. D Int. Ref.0 Select 1 : 18/32 */
|
|
|
872 |
#define CDREF0_18 (0x0012) /* Comp. D Int. Ref.0 Select 2 : 19/32 */
|
|
|
873 |
#define CDREF0_19 (0x0013) /* Comp. D Int. Ref.0 Select 3 : 20/32 */
|
|
|
874 |
#define CDREF0_20 (0x0014) /* Comp. D Int. Ref.0 Select 4 : 21/32 */
|
|
|
875 |
#define CDREF0_21 (0x0015) /* Comp. D Int. Ref.0 Select 5 : 22/32 */
|
|
|
876 |
#define CDREF0_22 (0x0016) /* Comp. D Int. Ref.0 Select 6 : 23/32 */
|
|
|
877 |
#define CDREF0_23 (0x0017) /* Comp. D Int. Ref.0 Select 7 : 24/32 */
|
|
|
878 |
#define CDREF0_24 (0x0018) /* Comp. D Int. Ref.0 Select 0 : 25/32 */
|
|
|
879 |
#define CDREF0_25 (0x0019) /* Comp. D Int. Ref.0 Select 1 : 26/32 */
|
|
|
880 |
#define CDREF0_26 (0x001A) /* Comp. D Int. Ref.0 Select 2 : 27/32 */
|
|
|
881 |
#define CDREF0_27 (0x001B) /* Comp. D Int. Ref.0 Select 3 : 28/32 */
|
|
|
882 |
#define CDREF0_28 (0x001C) /* Comp. D Int. Ref.0 Select 4 : 29/32 */
|
|
|
883 |
#define CDREF0_29 (0x001D) /* Comp. D Int. Ref.0 Select 5 : 30/32 */
|
|
|
884 |
#define CDREF0_30 (0x001E) /* Comp. D Int. Ref.0 Select 6 : 31/32 */
|
|
|
885 |
#define CDREF0_31 (0x001F) /* Comp. D Int. Ref.0 Select 7 : 32/32 */
|
|
|
886 |
|
|
|
887 |
#define CDRS_0 (0x0000) /* Comp. D Reference Source 0 : Off */
|
|
|
888 |
#define CDRS_1 (0x0040) /* Comp. D Reference Source 1 : Vcc */
|
|
|
889 |
#define CDRS_2 (0x0080) /* Comp. D Reference Source 2 : Shared Ref. */
|
|
|
890 |
#define CDRS_3 (0x00C0) /* Comp. D Reference Source 3 : Shared Ref. / Off */
|
|
|
891 |
|
|
|
892 |
#define CDREF1_0 (0x0000) /* Comp. D Int. Ref.1 Select 0 : 1/32 */
|
|
|
893 |
#define CDREF1_1 (0x0100) /* Comp. D Int. Ref.1 Select 1 : 2/32 */
|
|
|
894 |
#define CDREF1_2 (0x0200) /* Comp. D Int. Ref.1 Select 2 : 3/32 */
|
|
|
895 |
#define CDREF1_3 (0x0300) /* Comp. D Int. Ref.1 Select 3 : 4/32 */
|
|
|
896 |
#define CDREF1_4 (0x0400) /* Comp. D Int. Ref.1 Select 4 : 5/32 */
|
|
|
897 |
#define CDREF1_5 (0x0500) /* Comp. D Int. Ref.1 Select 5 : 6/32 */
|
|
|
898 |
#define CDREF1_6 (0x0600) /* Comp. D Int. Ref.1 Select 6 : 7/32 */
|
|
|
899 |
#define CDREF1_7 (0x0700) /* Comp. D Int. Ref.1 Select 7 : 8/32 */
|
|
|
900 |
#define CDREF1_8 (0x0800) /* Comp. D Int. Ref.1 Select 0 : 9/32 */
|
|
|
901 |
#define CDREF1_9 (0x0900) /* Comp. D Int. Ref.1 Select 1 : 10/32 */
|
|
|
902 |
#define CDREF1_10 (0x0A00) /* Comp. D Int. Ref.1 Select 2 : 11/32 */
|
|
|
903 |
#define CDREF1_11 (0x0B00) /* Comp. D Int. Ref.1 Select 3 : 12/32 */
|
|
|
904 |
#define CDREF1_12 (0x0C00) /* Comp. D Int. Ref.1 Select 4 : 13/32 */
|
|
|
905 |
#define CDREF1_13 (0x0D00) /* Comp. D Int. Ref.1 Select 5 : 14/32 */
|
|
|
906 |
#define CDREF1_14 (0x0E00) /* Comp. D Int. Ref.1 Select 6 : 15/32 */
|
|
|
907 |
#define CDREF1_15 (0x0F00) /* Comp. D Int. Ref.1 Select 7 : 16/32 */
|
|
|
908 |
#define CDREF1_16 (0x1000) /* Comp. D Int. Ref.1 Select 0 : 17/32 */
|
|
|
909 |
#define CDREF1_17 (0x1100) /* Comp. D Int. Ref.1 Select 1 : 18/32 */
|
|
|
910 |
#define CDREF1_18 (0x1200) /* Comp. D Int. Ref.1 Select 2 : 19/32 */
|
|
|
911 |
#define CDREF1_19 (0x1300) /* Comp. D Int. Ref.1 Select 3 : 20/32 */
|
|
|
912 |
#define CDREF1_20 (0x1400) /* Comp. D Int. Ref.1 Select 4 : 21/32 */
|
|
|
913 |
#define CDREF1_21 (0x1500) /* Comp. D Int. Ref.1 Select 5 : 22/32 */
|
|
|
914 |
#define CDREF1_22 (0x1600) /* Comp. D Int. Ref.1 Select 6 : 23/32 */
|
|
|
915 |
#define CDREF1_23 (0x1700) /* Comp. D Int. Ref.1 Select 7 : 24/32 */
|
|
|
916 |
#define CDREF1_24 (0x1800) /* Comp. D Int. Ref.1 Select 0 : 25/32 */
|
|
|
917 |
#define CDREF1_25 (0x1900) /* Comp. D Int. Ref.1 Select 1 : 26/32 */
|
|
|
918 |
#define CDREF1_26 (0x1A00) /* Comp. D Int. Ref.1 Select 2 : 27/32 */
|
|
|
919 |
#define CDREF1_27 (0x1B00) /* Comp. D Int. Ref.1 Select 3 : 28/32 */
|
|
|
920 |
#define CDREF1_28 (0x1C00) /* Comp. D Int. Ref.1 Select 4 : 29/32 */
|
|
|
921 |
#define CDREF1_29 (0x1D00) /* Comp. D Int. Ref.1 Select 5 : 30/32 */
|
|
|
922 |
#define CDREF1_30 (0x1E00) /* Comp. D Int. Ref.1 Select 6 : 31/32 */
|
|
|
923 |
#define CDREF1_31 (0x1F00) /* Comp. D Int. Ref.1 Select 7 : 32/32 */
|
|
|
924 |
|
|
|
925 |
#define CDREFL_0 (0x0000) /* Comp. D Reference voltage level 0 : None */
|
|
|
926 |
#define CDREFL_1 (0x2000) /* Comp. D Reference voltage level 1 : 1.5V */
|
|
|
927 |
#define CDREFL_2 (0x4000) /* Comp. D Reference voltage level 2 : 2.0V */
|
|
|
928 |
#define CDREFL_3 (0x6000) /* Comp. D Reference voltage level 3 : 2.5V */
|
|
|
929 |
|
|
|
930 |
#define CDPD0 (0x0001) /* Comp. D Disable Input Buffer of Port Register .0 */
|
|
|
931 |
#define CDPD1 (0x0002) /* Comp. D Disable Input Buffer of Port Register .1 */
|
|
|
932 |
#define CDPD2 (0x0004) /* Comp. D Disable Input Buffer of Port Register .2 */
|
|
|
933 |
#define CDPD3 (0x0008) /* Comp. D Disable Input Buffer of Port Register .3 */
|
|
|
934 |
#define CDPD4 (0x0010) /* Comp. D Disable Input Buffer of Port Register .4 */
|
|
|
935 |
#define CDPD5 (0x0020) /* Comp. D Disable Input Buffer of Port Register .5 */
|
|
|
936 |
#define CDPD6 (0x0040) /* Comp. D Disable Input Buffer of Port Register .6 */
|
|
|
937 |
#define CDPD7 (0x0080) /* Comp. D Disable Input Buffer of Port Register .7 */
|
|
|
938 |
#define CDPD8 (0x0100) /* Comp. D Disable Input Buffer of Port Register .8 */
|
|
|
939 |
#define CDPD9 (0x0200) /* Comp. D Disable Input Buffer of Port Register .9 */
|
|
|
940 |
#define CDPD10 (0x0400) /* Comp. D Disable Input Buffer of Port Register .10 */
|
|
|
941 |
#define CDPD11 (0x0800) /* Comp. D Disable Input Buffer of Port Register .11 */
|
|
|
942 |
#define CDPD12 (0x1000) /* Comp. D Disable Input Buffer of Port Register .12 */
|
|
|
943 |
#define CDPD13 (0x2000) /* Comp. D Disable Input Buffer of Port Register .13 */
|
|
|
944 |
#define CDPD14 (0x4000) /* Comp. D Disable Input Buffer of Port Register .14 */
|
|
|
945 |
#define CDPD15 (0x8000) /* Comp. D Disable Input Buffer of Port Register .15 */
|
|
|
946 |
|
|
|
947 |
#define CDPD0_L (0x0001) /* Comp. D Disable Input Buffer of Port Register .0 */
|
|
|
948 |
#define CDPD1_L (0x0002) /* Comp. D Disable Input Buffer of Port Register .1 */
|
|
|
949 |
#define CDPD2_L (0x0004) /* Comp. D Disable Input Buffer of Port Register .2 */
|
|
|
950 |
#define CDPD3_L (0x0008) /* Comp. D Disable Input Buffer of Port Register .3 */
|
|
|
951 |
#define CDPD4_L (0x0010) /* Comp. D Disable Input Buffer of Port Register .4 */
|
|
|
952 |
#define CDPD5_L (0x0020) /* Comp. D Disable Input Buffer of Port Register .5 */
|
|
|
953 |
#define CDPD6_L (0x0040) /* Comp. D Disable Input Buffer of Port Register .6 */
|
|
|
954 |
#define CDPD7_L (0x0080) /* Comp. D Disable Input Buffer of Port Register .7 */
|
|
|
955 |
|
|
|
956 |
#define CDPD8_H (0x0001) /* Comp. D Disable Input Buffer of Port Register .8 */
|
|
|
957 |
#define CDPD9_H (0x0002) /* Comp. D Disable Input Buffer of Port Register .9 */
|
|
|
958 |
#define CDPD10_H (0x0004) /* Comp. D Disable Input Buffer of Port Register .10 */
|
|
|
959 |
#define CDPD11_H (0x0008) /* Comp. D Disable Input Buffer of Port Register .11 */
|
|
|
960 |
#define CDPD12_H (0x0010) /* Comp. D Disable Input Buffer of Port Register .12 */
|
|
|
961 |
#define CDPD13_H (0x0020) /* Comp. D Disable Input Buffer of Port Register .13 */
|
|
|
962 |
#define CDPD14_H (0x0040) /* Comp. D Disable Input Buffer of Port Register .14 */
|
|
|
963 |
#define CDPD15_H (0x0080) /* Comp. D Disable Input Buffer of Port Register .15 */
|
|
|
964 |
|
|
|
965 |
/* CDINT Control Bits */
|
|
|
966 |
#define CDIFG (0x0001) /* Comp. D Interrupt Flag */
|
|
|
967 |
#define CDIIFG (0x0002) /* Comp. D Interrupt Flag Inverted Polarity */
|
|
|
968 |
//#define RESERVED (0x0004) /* Comp. D */
|
|
|
969 |
//#define RESERVED (0x0008) /* Comp. D */
|
|
|
970 |
//#define RESERVED (0x0010) /* Comp. D */
|
|
|
971 |
//#define RESERVED (0x0020) /* Comp. D */
|
|
|
972 |
//#define RESERVED (0x0040) /* Comp. D */
|
|
|
973 |
//#define RESERVED (0x0080) /* Comp. D */
|
|
|
974 |
#define CDIE (0x0100) /* Comp. D Interrupt Enable */
|
|
|
975 |
#define CDIIE (0x0200) /* Comp. D Interrupt Enable Inverted Polarity */
|
|
|
976 |
//#define RESERVED (0x0400) /* Comp. D */
|
|
|
977 |
//#define RESERVED (0x0800) /* Comp. D */
|
|
|
978 |
//#define RESERVED (0x1000) /* Comp. D */
|
|
|
979 |
//#define RESERVED (0x2000) /* Comp. D */
|
|
|
980 |
//#define RESERVED (0x4000) /* Comp. D */
|
|
|
981 |
//#define RESERVED (0x8000) /* Comp. D */
|
|
|
982 |
|
|
|
983 |
/* CDINT Control Bits */
|
|
|
984 |
#define CDIFG_L (0x0001) /* Comp. D Interrupt Flag */
|
|
|
985 |
#define CDIIFG_L (0x0002) /* Comp. D Interrupt Flag Inverted Polarity */
|
|
|
986 |
//#define RESERVED (0x0004) /* Comp. D */
|
|
|
987 |
//#define RESERVED (0x0008) /* Comp. D */
|
|
|
988 |
//#define RESERVED (0x0010) /* Comp. D */
|
|
|
989 |
//#define RESERVED (0x0020) /* Comp. D */
|
|
|
990 |
//#define RESERVED (0x0040) /* Comp. D */
|
|
|
991 |
//#define RESERVED (0x0080) /* Comp. D */
|
|
|
992 |
//#define RESERVED (0x0400) /* Comp. D */
|
|
|
993 |
//#define RESERVED (0x0800) /* Comp. D */
|
|
|
994 |
//#define RESERVED (0x1000) /* Comp. D */
|
|
|
995 |
//#define RESERVED (0x2000) /* Comp. D */
|
|
|
996 |
//#define RESERVED (0x4000) /* Comp. D */
|
|
|
997 |
//#define RESERVED (0x8000) /* Comp. D */
|
|
|
998 |
|
|
|
999 |
/* CDINT Control Bits */
|
|
|
1000 |
//#define RESERVED (0x0004) /* Comp. D */
|
|
|
1001 |
//#define RESERVED (0x0008) /* Comp. D */
|
|
|
1002 |
//#define RESERVED (0x0010) /* Comp. D */
|
|
|
1003 |
//#define RESERVED (0x0020) /* Comp. D */
|
|
|
1004 |
//#define RESERVED (0x0040) /* Comp. D */
|
|
|
1005 |
//#define RESERVED (0x0080) /* Comp. D */
|
|
|
1006 |
#define CDIE_H (0x0001) /* Comp. D Interrupt Enable */
|
|
|
1007 |
#define CDIIE_H (0x0002) /* Comp. D Interrupt Enable Inverted Polarity */
|
|
|
1008 |
//#define RESERVED (0x0400) /* Comp. D */
|
|
|
1009 |
//#define RESERVED (0x0800) /* Comp. D */
|
|
|
1010 |
//#define RESERVED (0x1000) /* Comp. D */
|
|
|
1011 |
//#define RESERVED (0x2000) /* Comp. D */
|
|
|
1012 |
//#define RESERVED (0x4000) /* Comp. D */
|
|
|
1013 |
//#define RESERVED (0x8000) /* Comp. D */
|
|
|
1014 |
|
|
|
1015 |
/* CDIV Definitions */
|
|
|
1016 |
#define CDIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1017 |
#define CDIV_CDIFG (0x0002) /* CDIFG */
|
|
|
1018 |
#define CDIV_CDIIFG (0x0004) /* CDIIFG */
|
|
|
1019 |
|
|
|
1020 |
/*************************************************************
|
|
|
1021 |
* CRC Module
|
|
|
1022 |
*************************************************************/
|
|
|
1023 |
#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */
|
|
|
1024 |
#define __MSP430_BASEADDRESS_CRC__ 0x0150
|
|
|
1025 |
|
|
|
1026 |
SFR_16BIT(CRCDI); /* CRC Data In Register */
|
|
|
1027 |
SFR_8BIT(CRCDI_L); /* CRC Data In Register */
|
|
|
1028 |
SFR_8BIT(CRCDI_H); /* CRC Data In Register */
|
|
|
1029 |
SFR_16BIT(CRCDIRB); /* CRC data in reverse byte Register */
|
|
|
1030 |
SFR_8BIT(CRCDIRB_L); /* CRC data in reverse byte Register */
|
|
|
1031 |
SFR_8BIT(CRCDIRB_H); /* CRC data in reverse byte Register */
|
|
|
1032 |
SFR_16BIT(CRCINIRES); /* CRC Initialisation Register and Result Register */
|
|
|
1033 |
SFR_8BIT(CRCINIRES_L); /* CRC Initialisation Register and Result Register */
|
|
|
1034 |
SFR_8BIT(CRCINIRES_H); /* CRC Initialisation Register and Result Register */
|
|
|
1035 |
SFR_16BIT(CRCRESR); /* CRC reverse result Register */
|
|
|
1036 |
SFR_8BIT(CRCRESR_L); /* CRC reverse result Register */
|
|
|
1037 |
SFR_8BIT(CRCRESR_H); /* CRC reverse result Register */
|
|
|
1038 |
|
|
|
1039 |
/************************************************************
|
|
|
1040 |
* DMA_X
|
|
|
1041 |
************************************************************/
|
|
|
1042 |
#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
|
|
|
1043 |
#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500
|
|
|
1044 |
|
|
|
1045 |
SFR_16BIT(DMACTL0); /* DMA Module Control 0 */
|
|
|
1046 |
SFR_8BIT(DMACTL0_L); /* DMA Module Control 0 */
|
|
|
1047 |
SFR_8BIT(DMACTL0_H); /* DMA Module Control 0 */
|
|
|
1048 |
SFR_16BIT(DMACTL1); /* DMA Module Control 1 */
|
|
|
1049 |
SFR_8BIT(DMACTL1_L); /* DMA Module Control 1 */
|
|
|
1050 |
SFR_8BIT(DMACTL1_H); /* DMA Module Control 1 */
|
|
|
1051 |
SFR_16BIT(DMACTL2); /* DMA Module Control 2 */
|
|
|
1052 |
SFR_8BIT(DMACTL2_L); /* DMA Module Control 2 */
|
|
|
1053 |
SFR_8BIT(DMACTL2_H); /* DMA Module Control 2 */
|
|
|
1054 |
SFR_16BIT(DMACTL3); /* DMA Module Control 3 */
|
|
|
1055 |
SFR_8BIT(DMACTL3_L); /* DMA Module Control 3 */
|
|
|
1056 |
SFR_8BIT(DMACTL3_H); /* DMA Module Control 3 */
|
|
|
1057 |
SFR_16BIT(DMACTL4); /* DMA Module Control 4 */
|
|
|
1058 |
SFR_8BIT(DMACTL4_L); /* DMA Module Control 4 */
|
|
|
1059 |
SFR_8BIT(DMACTL4_H); /* DMA Module Control 4 */
|
|
|
1060 |
SFR_16BIT(DMAIV); /* DMA Interrupt Vector Word */
|
|
|
1061 |
SFR_8BIT(DMAIV_L); /* DMA Interrupt Vector Word */
|
|
|
1062 |
SFR_8BIT(DMAIV_H); /* DMA Interrupt Vector Word */
|
|
|
1063 |
|
|
|
1064 |
SFR_16BIT(DMA0CTL); /* DMA Channel 0 Control */
|
|
|
1065 |
SFR_8BIT(DMA0CTL_L); /* DMA Channel 0 Control */
|
|
|
1066 |
SFR_8BIT(DMA0CTL_H); /* DMA Channel 0 Control */
|
|
|
1067 |
SFR_20BIT(DMA0SA); /* DMA Channel 0 Source Address */
|
|
|
1068 |
SFR_16BIT(DMA0SAL); /* DMA Channel 0 Source Address */
|
|
|
1069 |
SFR_20BIT(DMA0DA); /* DMA Channel 0 Destination Address */
|
|
|
1070 |
SFR_16BIT(DMA0DAL); /* DMA Channel 0 Destination Address */
|
|
|
1071 |
SFR_16BIT(DMA0SZ); /* DMA Channel 0 Transfer Size */
|
|
|
1072 |
|
|
|
1073 |
SFR_16BIT(DMA1CTL); /* DMA Channel 1 Control */
|
|
|
1074 |
SFR_8BIT(DMA1CTL_L); /* DMA Channel 1 Control */
|
|
|
1075 |
SFR_8BIT(DMA1CTL_H); /* DMA Channel 1 Control */
|
|
|
1076 |
SFR_20BIT(DMA1SA); /* DMA Channel 1 Source Address */
|
|
|
1077 |
SFR_16BIT(DMA1SAL); /* DMA Channel 1 Source Address */
|
|
|
1078 |
SFR_20BIT(DMA1DA); /* DMA Channel 1 Destination Address */
|
|
|
1079 |
SFR_16BIT(DMA1DAL); /* DMA Channel 1 Destination Address */
|
|
|
1080 |
SFR_16BIT(DMA1SZ); /* DMA Channel 1 Transfer Size */
|
|
|
1081 |
|
|
|
1082 |
SFR_16BIT(DMA2CTL); /* DMA Channel 2 Control */
|
|
|
1083 |
SFR_8BIT(DMA2CTL_L); /* DMA Channel 2 Control */
|
|
|
1084 |
SFR_8BIT(DMA2CTL_H); /* DMA Channel 2 Control */
|
|
|
1085 |
SFR_20BIT(DMA2SA); /* DMA Channel 2 Source Address */
|
|
|
1086 |
SFR_16BIT(DMA2SAL); /* DMA Channel 2 Source Address */
|
|
|
1087 |
SFR_20BIT(DMA2DA); /* DMA Channel 2 Destination Address */
|
|
|
1088 |
SFR_16BIT(DMA2DAL); /* DMA Channel 2 Destination Address */
|
|
|
1089 |
SFR_16BIT(DMA2SZ); /* DMA Channel 2 Transfer Size */
|
|
|
1090 |
|
|
|
1091 |
/* DMACTL0 Control Bits */
|
|
|
1092 |
#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
|
|
|
1093 |
#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
|
|
|
1094 |
#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
|
|
|
1095 |
#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
|
|
|
1096 |
#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
|
|
|
1097 |
#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
|
|
|
1098 |
#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
|
|
|
1099 |
#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
|
|
|
1100 |
#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
|
|
|
1101 |
#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
|
|
|
1102 |
|
|
|
1103 |
/* DMACTL0 Control Bits */
|
|
|
1104 |
#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
|
|
|
1105 |
#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
|
|
|
1106 |
#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
|
|
|
1107 |
#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
|
|
|
1108 |
#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
|
|
|
1109 |
|
|
|
1110 |
/* DMACTL0 Control Bits */
|
|
|
1111 |
#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
|
|
|
1112 |
#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
|
|
|
1113 |
#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
|
|
|
1114 |
#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
|
|
|
1115 |
#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
|
|
|
1116 |
|
|
|
1117 |
/* DMACTL01 Control Bits */
|
|
|
1118 |
#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
|
|
|
1119 |
#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
|
|
|
1120 |
#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
|
|
|
1121 |
#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
|
|
|
1122 |
#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
|
|
|
1123 |
|
|
|
1124 |
/* DMACTL01 Control Bits */
|
|
|
1125 |
#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
|
|
|
1126 |
#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
|
|
|
1127 |
#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
|
|
|
1128 |
#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
|
|
|
1129 |
#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
|
|
|
1130 |
|
|
|
1131 |
/* DMACTL01 Control Bits */
|
|
|
1132 |
|
|
|
1133 |
/* DMACTL4 Control Bits */
|
|
|
1134 |
#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
|
|
|
1135 |
#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
|
|
|
1136 |
#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
|
|
|
1137 |
|
|
|
1138 |
/* DMACTL4 Control Bits */
|
|
|
1139 |
#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
|
|
|
1140 |
#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
|
|
|
1141 |
#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
|
|
|
1142 |
|
|
|
1143 |
/* DMACTL4 Control Bits */
|
|
|
1144 |
|
|
|
1145 |
/* DMAxCTL Control Bits */
|
|
|
1146 |
#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
|
|
|
1147 |
#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
|
|
|
1148 |
#define DMAIE (0x0004) /* DMA interrupt enable */
|
|
|
1149 |
#define DMAIFG (0x0008) /* DMA interrupt flag */
|
|
|
1150 |
#define DMAEN (0x0010) /* DMA enable */
|
|
|
1151 |
#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
|
|
|
1152 |
#define DMASRCBYTE (0x0040) /* DMA source byte */
|
|
|
1153 |
#define DMADSTBYTE (0x0080) /* DMA destination byte */
|
|
|
1154 |
#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
|
|
|
1155 |
#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
|
|
|
1156 |
#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
|
|
|
1157 |
#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
|
|
|
1158 |
#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
|
|
|
1159 |
#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
|
|
|
1160 |
#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
|
|
|
1161 |
|
|
|
1162 |
/* DMAxCTL Control Bits */
|
|
|
1163 |
#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
|
|
|
1164 |
#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
|
|
|
1165 |
#define DMAIE_L (0x0004) /* DMA interrupt enable */
|
|
|
1166 |
#define DMAIFG_L (0x0008) /* DMA interrupt flag */
|
|
|
1167 |
#define DMAEN_L (0x0010) /* DMA enable */
|
|
|
1168 |
#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
|
|
|
1169 |
#define DMASRCBYTE_L (0x0040) /* DMA source byte */
|
|
|
1170 |
#define DMADSTBYTE_L (0x0080) /* DMA destination byte */
|
|
|
1171 |
|
|
|
1172 |
/* DMAxCTL Control Bits */
|
|
|
1173 |
#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
|
|
|
1174 |
#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
|
|
|
1175 |
#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
|
|
|
1176 |
#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
|
|
|
1177 |
#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
|
|
|
1178 |
#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
|
|
|
1179 |
#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
|
|
|
1180 |
|
|
|
1181 |
#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
|
|
|
1182 |
#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
|
|
|
1183 |
#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
|
|
|
1184 |
#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
|
|
|
1185 |
|
|
|
1186 |
#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
|
|
|
1187 |
#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
|
|
|
1188 |
#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
|
|
|
1189 |
#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
|
|
|
1190 |
|
|
|
1191 |
#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
|
|
|
1192 |
#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
|
|
|
1193 |
#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
|
|
|
1194 |
#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
|
|
|
1195 |
|
|
|
1196 |
#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
|
|
|
1197 |
#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
|
|
|
1198 |
#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
|
|
|
1199 |
#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
|
|
|
1200 |
#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
|
|
|
1201 |
#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
|
|
|
1202 |
#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
|
|
|
1203 |
#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
|
|
|
1204 |
|
|
|
1205 |
/* DMAIV Definitions */
|
|
|
1206 |
#define DMAIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1207 |
#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
|
|
|
1208 |
#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
|
|
|
1209 |
#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
|
|
|
1210 |
|
|
|
1211 |
#define DMA0TSEL_0 (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
|
|
|
1212 |
#define DMA0TSEL_1 (1*0x0001u) /* DMA channel 0 transfer select 1: */
|
|
|
1213 |
#define DMA0TSEL_2 (2*0x0001u) /* DMA channel 0 transfer select 2: */
|
|
|
1214 |
#define DMA0TSEL_3 (3*0x0001u) /* DMA channel 0 transfer select 3: */
|
|
|
1215 |
#define DMA0TSEL_4 (4*0x0001u) /* DMA channel 0 transfer select 4: */
|
|
|
1216 |
#define DMA0TSEL_5 (5*0x0001u) /* DMA channel 0 transfer select 5: */
|
|
|
1217 |
#define DMA0TSEL_6 (6*0x0001u) /* DMA channel 0 transfer select 6: */
|
|
|
1218 |
#define DMA0TSEL_7 (7*0x0001u) /* DMA channel 0 transfer select 7: */
|
|
|
1219 |
#define DMA0TSEL_8 (8*0x0001u) /* DMA channel 0 transfer select 8: */
|
|
|
1220 |
#define DMA0TSEL_9 (9*0x0001u) /* DMA channel 0 transfer select 9: */
|
|
|
1221 |
#define DMA0TSEL_10 (10*0x0001u) /* DMA channel 0 transfer select 10: */
|
|
|
1222 |
#define DMA0TSEL_11 (11*0x0001u) /* DMA channel 0 transfer select 11: */
|
|
|
1223 |
#define DMA0TSEL_12 (12*0x0001u) /* DMA channel 0 transfer select 12: */
|
|
|
1224 |
#define DMA0TSEL_13 (13*0x0001u) /* DMA channel 0 transfer select 13: */
|
|
|
1225 |
#define DMA0TSEL_14 (14*0x0001u) /* DMA channel 0 transfer select 14: */
|
|
|
1226 |
#define DMA0TSEL_15 (15*0x0001u) /* DMA channel 0 transfer select 15: */
|
|
|
1227 |
#define DMA0TSEL_16 (16*0x0001u) /* DMA channel 0 transfer select 16: */
|
|
|
1228 |
#define DMA0TSEL_17 (17*0x0001u) /* DMA channel 0 transfer select 17: */
|
|
|
1229 |
#define DMA0TSEL_18 (18*0x0001u) /* DMA channel 0 transfer select 18: */
|
|
|
1230 |
#define DMA0TSEL_19 (19*0x0001u) /* DMA channel 0 transfer select 19: */
|
|
|
1231 |
#define DMA0TSEL_20 (20*0x0001u) /* DMA channel 0 transfer select 20: */
|
|
|
1232 |
#define DMA0TSEL_21 (21*0x0001u) /* DMA channel 0 transfer select 21: */
|
|
|
1233 |
#define DMA0TSEL_22 (22*0x0001u) /* DMA channel 0 transfer select 22: */
|
|
|
1234 |
#define DMA0TSEL_23 (23*0x0001u) /* DMA channel 0 transfer select 23: */
|
|
|
1235 |
#define DMA0TSEL_24 (24*0x0001u) /* DMA channel 0 transfer select 24: */
|
|
|
1236 |
#define DMA0TSEL_25 (25*0x0001u) /* DMA channel 0 transfer select 25: */
|
|
|
1237 |
#define DMA0TSEL_26 (26*0x0001u) /* DMA channel 0 transfer select 26: */
|
|
|
1238 |
#define DMA0TSEL_27 (27*0x0001u) /* DMA channel 0 transfer select 27: */
|
|
|
1239 |
#define DMA0TSEL_28 (28*0x0001u) /* DMA channel 0 transfer select 28: */
|
|
|
1240 |
#define DMA0TSEL_29 (29*0x0001u) /* DMA channel 0 transfer select 29: */
|
|
|
1241 |
#define DMA0TSEL_30 (30*0x0001u) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
|
|
|
1242 |
#define DMA0TSEL_31 (31*0x0001u) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
|
|
|
1243 |
|
|
|
1244 |
#define DMA1TSEL_0 (0*0x0100u) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
|
|
|
1245 |
#define DMA1TSEL_1 (1*0x0100u) /* DMA channel 1 transfer select 1: */
|
|
|
1246 |
#define DMA1TSEL_2 (2*0x0100u) /* DMA channel 1 transfer select 2: */
|
|
|
1247 |
#define DMA1TSEL_3 (3*0x0100u) /* DMA channel 1 transfer select 3: */
|
|
|
1248 |
#define DMA1TSEL_4 (4*0x0100u) /* DMA channel 1 transfer select 4: */
|
|
|
1249 |
#define DMA1TSEL_5 (5*0x0100u) /* DMA channel 1 transfer select 5: */
|
|
|
1250 |
#define DMA1TSEL_6 (6*0x0100u) /* DMA channel 1 transfer select 6: */
|
|
|
1251 |
#define DMA1TSEL_7 (7*0x0100u) /* DMA channel 1 transfer select 7: */
|
|
|
1252 |
#define DMA1TSEL_8 (8*0x0100u) /* DMA channel 1 transfer select 8: */
|
|
|
1253 |
#define DMA1TSEL_9 (9*0x0100u) /* DMA channel 1 transfer select 9: */
|
|
|
1254 |
#define DMA1TSEL_10 (10*0x0100u) /* DMA channel 1 transfer select 10: */
|
|
|
1255 |
#define DMA1TSEL_11 (11*0x0100u) /* DMA channel 1 transfer select 11: */
|
|
|
1256 |
#define DMA1TSEL_12 (12*0x0100u) /* DMA channel 1 transfer select 12: */
|
|
|
1257 |
#define DMA1TSEL_13 (13*0x0100u) /* DMA channel 1 transfer select 13: */
|
|
|
1258 |
#define DMA1TSEL_14 (14*0x0100u) /* DMA channel 1 transfer select 14: */
|
|
|
1259 |
#define DMA1TSEL_15 (15*0x0100u) /* DMA channel 1 transfer select 15: */
|
|
|
1260 |
#define DMA1TSEL_16 (16*0x0100u) /* DMA channel 1 transfer select 16: */
|
|
|
1261 |
#define DMA1TSEL_17 (17*0x0100u) /* DMA channel 1 transfer select 17: */
|
|
|
1262 |
#define DMA1TSEL_18 (18*0x0100u) /* DMA channel 1 transfer select 18: */
|
|
|
1263 |
#define DMA1TSEL_19 (19*0x0100u) /* DMA channel 1 transfer select 19: */
|
|
|
1264 |
#define DMA1TSEL_20 (20*0x0100u) /* DMA channel 1 transfer select 20: */
|
|
|
1265 |
#define DMA1TSEL_21 (21*0x0100u) /* DMA channel 1 transfer select 21: */
|
|
|
1266 |
#define DMA1TSEL_22 (22*0x0100u) /* DMA channel 1 transfer select 22: */
|
|
|
1267 |
#define DMA1TSEL_23 (23*0x0100u) /* DMA channel 1 transfer select 23: */
|
|
|
1268 |
#define DMA1TSEL_24 (24*0x0100u) /* DMA channel 1 transfer select 24: */
|
|
|
1269 |
#define DMA1TSEL_25 (25*0x0100u) /* DMA channel 1 transfer select 25: */
|
|
|
1270 |
#define DMA1TSEL_26 (26*0x0100u) /* DMA channel 1 transfer select 26: */
|
|
|
1271 |
#define DMA1TSEL_27 (27*0x0100u) /* DMA channel 1 transfer select 27: */
|
|
|
1272 |
#define DMA1TSEL_28 (28*0x0100u) /* DMA channel 1 transfer select 28: */
|
|
|
1273 |
#define DMA1TSEL_29 (29*0x0100u) /* DMA channel 1 transfer select 29: */
|
|
|
1274 |
#define DMA1TSEL_30 (30*0x0100u) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
|
|
|
1275 |
#define DMA1TSEL_31 (31*0x0100u) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
|
|
|
1276 |
|
|
|
1277 |
#define DMA2TSEL_0 (0*0x0001u) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
|
|
|
1278 |
#define DMA2TSEL_1 (1*0x0001u) /* DMA channel 2 transfer select 1: */
|
|
|
1279 |
#define DMA2TSEL_2 (2*0x0001u) /* DMA channel 2 transfer select 2: */
|
|
|
1280 |
#define DMA2TSEL_3 (3*0x0001u) /* DMA channel 2 transfer select 3: */
|
|
|
1281 |
#define DMA2TSEL_4 (4*0x0001u) /* DMA channel 2 transfer select 4: */
|
|
|
1282 |
#define DMA2TSEL_5 (5*0x0001u) /* DMA channel 2 transfer select 5: */
|
|
|
1283 |
#define DMA2TSEL_6 (6*0x0001u) /* DMA channel 2 transfer select 6: */
|
|
|
1284 |
#define DMA2TSEL_7 (7*0x0001u) /* DMA channel 2 transfer select 7: */
|
|
|
1285 |
#define DMA2TSEL_8 (8*0x0001u) /* DMA channel 2 transfer select 8: */
|
|
|
1286 |
#define DMA2TSEL_9 (9*0x0001u) /* DMA channel 2 transfer select 9: */
|
|
|
1287 |
#define DMA2TSEL_10 (10*0x0001u) /* DMA channel 2 transfer select 10: */
|
|
|
1288 |
#define DMA2TSEL_11 (11*0x0001u) /* DMA channel 2 transfer select 11: */
|
|
|
1289 |
#define DMA2TSEL_12 (12*0x0001u) /* DMA channel 2 transfer select 12: */
|
|
|
1290 |
#define DMA2TSEL_13 (13*0x0001u) /* DMA channel 2 transfer select 13: */
|
|
|
1291 |
#define DMA2TSEL_14 (14*0x0001u) /* DMA channel 2 transfer select 14: */
|
|
|
1292 |
#define DMA2TSEL_15 (15*0x0001u) /* DMA channel 2 transfer select 15: */
|
|
|
1293 |
#define DMA2TSEL_16 (16*0x0001u) /* DMA channel 2 transfer select 16: */
|
|
|
1294 |
#define DMA2TSEL_17 (17*0x0001u) /* DMA channel 2 transfer select 17: */
|
|
|
1295 |
#define DMA2TSEL_18 (18*0x0001u) /* DMA channel 2 transfer select 18: */
|
|
|
1296 |
#define DMA2TSEL_19 (19*0x0001u) /* DMA channel 2 transfer select 19: */
|
|
|
1297 |
#define DMA2TSEL_20 (20*0x0001u) /* DMA channel 2 transfer select 20: */
|
|
|
1298 |
#define DMA2TSEL_21 (21*0x0001u) /* DMA channel 2 transfer select 21: */
|
|
|
1299 |
#define DMA2TSEL_22 (22*0x0001u) /* DMA channel 2 transfer select 22: */
|
|
|
1300 |
#define DMA2TSEL_23 (23*0x0001u) /* DMA channel 2 transfer select 23: */
|
|
|
1301 |
#define DMA2TSEL_24 (24*0x0001u) /* DMA channel 2 transfer select 24: */
|
|
|
1302 |
#define DMA2TSEL_25 (25*0x0001u) /* DMA channel 2 transfer select 25: */
|
|
|
1303 |
#define DMA2TSEL_26 (26*0x0001u) /* DMA channel 2 transfer select 26: */
|
|
|
1304 |
#define DMA2TSEL_27 (27*0x0001u) /* DMA channel 2 transfer select 27: */
|
|
|
1305 |
#define DMA2TSEL_28 (28*0x0001u) /* DMA channel 2 transfer select 28: */
|
|
|
1306 |
#define DMA2TSEL_29 (29*0x0001u) /* DMA channel 2 transfer select 29: */
|
|
|
1307 |
#define DMA2TSEL_30 (30*0x0001u) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
|
|
|
1308 |
#define DMA2TSEL_31 (31*0x0001u) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
|
|
|
1309 |
|
|
|
1310 |
#define DMA0TSEL__DMAREQ (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
|
|
|
1311 |
#define DMA0TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 0 transfer select 1: TA0CCR0 */
|
|
|
1312 |
#define DMA0TSEL__TA0CCR2 (2*0x0001u) /* DMA channel 0 transfer select 2: TA0CCR2 */
|
|
|
1313 |
#define DMA0TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 0 transfer select 3: TA1CCR0 */
|
|
|
1314 |
#define DMA0TSEL__TA1CCR2 (4*0x0001u) /* DMA channel 0 transfer select 4: TA1CCR2 */
|
|
|
1315 |
#define DMA0TSEL__RES5 (5*0x0001u) /* DMA channel 0 transfer select 5: RES5 */
|
|
|
1316 |
#define DMA0TSEL__RES6 (6*0x0001u) /* DMA channel 0 transfer select 6: RES6 */
|
|
|
1317 |
#define DMA0TSEL__TB0CCR0 (7*0x0001u) /* DMA channel 0 transfer select 7: TB0CCR0 */
|
|
|
1318 |
#define DMA0TSEL__TB0CCR2 (8*0x0001u) /* DMA channel 0 transfer select 8: TB0CCR2 */
|
|
|
1319 |
#define DMA0TSEL__TB1CCR0 (9*0x0001u) /* DMA channel 0 transfer select 9: TB1CCR0 */
|
|
|
1320 |
#define DMA0TSEL__TB1CCR2 (10*0x0001u) /* DMA channel 0 transfer select 10: TB1CCR2 */
|
|
|
1321 |
#define DMA0TSEL__TB2CCR0 (11*0x0001u) /* DMA channel 0 transfer select 11: TB2CCR0 */
|
|
|
1322 |
#define DMA0TSEL__TB2CCR2 (12*0x0001u) /* DMA channel 0 transfer select 12: TB2CCR2 */
|
|
|
1323 |
#define DMA0TSEL__RES13 (13*0x0001u) /* DMA channel 0 transfer select 13: RES13 */
|
|
|
1324 |
#define DMA0TSEL__UCA0RXIFG (14*0x0001u) /* DMA channel 0 transfer select 14: UCA0RXIFG */
|
|
|
1325 |
#define DMA0TSEL__UCA0TXIFG (15*0x0001u) /* DMA channel 0 transfer select 15: UCA0TXIFG */
|
|
|
1326 |
#define DMA0TSEL__UCA1RXIFG (16*0x0001u) /* DMA channel 0 transfer select 16: UCA1RXIFG */
|
|
|
1327 |
#define DMA0TSEL__UCA1TXIFG (17*0x0001u) /* DMA channel 0 transfer select 17: UCA1TXIFG */
|
|
|
1328 |
#define DMA0TSEL__UCB0RXIFG0 (18*0x0001u) /* DMA channel 0 transfer select 18: UCB0RXIFG0 */
|
|
|
1329 |
#define DMA0TSEL__UCB0TXIFG0 (19*0x0001u) /* DMA channel 0 transfer select 19: UCB0TXIFG0 */
|
|
|
1330 |
#define DMA0TSEL__UCB0RXIFG1 (20*0x0001u) /* DMA channel 0 transfer select 20: UCB0RXIFG1 */
|
|
|
1331 |
#define DMA0TSEL__UCB0TXIFG1 (21*0x0001u) /* DMA channel 0 transfer select 21: UCB0TXIFG1 */
|
|
|
1332 |
#define DMA0TSEL__UCB0RXIFG2 (22*0x0001u) /* DMA channel 0 transfer select 22: UCB0RXIFG2 */
|
|
|
1333 |
#define DMA0TSEL__UCB0TXIFG2 (23*0x0001u) /* DMA channel 0 transfer select 23: UCB0TXIFG2 */
|
|
|
1334 |
#define DMA0TSEL__UCB0RXIFG3 (24*0x0001u) /* DMA channel 0 transfer select 24: UCB0RXIFG3 */
|
|
|
1335 |
#define DMA0TSEL__UCB0TXIFG3 (25*0x0001u) /* DMA channel 0 transfer select 25: UCB0TXIFG3 */
|
|
|
1336 |
#define DMA0TSEL__ADC10IFG (26*0x0001u) /* DMA channel 0 transfer select 26: ADC10IFG */
|
|
|
1337 |
#define DMA0TSEL__RES27 (27*0x0001u) /* DMA channel 0 transfer select 27: RES27 */
|
|
|
1338 |
#define DMA0TSEL__RES28 (28*0x0001u) /* DMA channel 0 transfer select 28: RES28 */
|
|
|
1339 |
#define DMA0TSEL__MPY (29*0x0001u) /* DMA channel 0 transfer select 29: MPY */
|
|
|
1340 |
#define DMA0TSEL__DMA2IFG (30*0x0001u) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
|
|
|
1341 |
#define DMA0TSEL__DMAE0 (31*0x0001u) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
|
|
|
1342 |
|
|
|
1343 |
#define DMA1TSEL__DMAREQ (0*0x0100u) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
|
|
|
1344 |
#define DMA1TSEL__TA0CCR0 (1*0x0100u) /* DMA channel 1 transfer select 1: TA0CCR0 */
|
|
|
1345 |
#define DMA1TSEL__TA0CCR2 (2*0x0100u) /* DMA channel 1 transfer select 2: TA0CCR2 */
|
|
|
1346 |
#define DMA1TSEL__TA1CCR0 (3*0x0100u) /* DMA channel 1 transfer select 3: TA1CCR0 */
|
|
|
1347 |
#define DMA1TSEL__TA1CCR2 (4*0x0100u) /* DMA channel 1 transfer select 4: TA1CCR2 */
|
|
|
1348 |
#define DMA1TSEL__RES5 (5*0x0100u) /* DMA channel 1 transfer select 5: RES5 */
|
|
|
1349 |
#define DMA1TSEL__RES6 (6*0x0100u) /* DMA channel 1 transfer select 6: RES6 */
|
|
|
1350 |
#define DMA1TSEL__TB0CCR0 (7*0x0100u) /* DMA channel 1 transfer select 7: TB0CCR0 */
|
|
|
1351 |
#define DMA1TSEL__TB0CCR2 (8*0x0100u) /* DMA channel 1 transfer select 8: TB0CCR2 */
|
|
|
1352 |
#define DMA1TSEL__TB1CCR0 (9*0x0100u) /* DMA channel 1 transfer select 9: TB1CCR0 */
|
|
|
1353 |
#define DMA1TSEL__TB1CCR2 (10*0x0100u) /* DMA channel 1 transfer select 10: TB1CCR2 */
|
|
|
1354 |
#define DMA1TSEL__TB2CCR0 (11*0x0100u) /* DMA channel 1 transfer select 11: TB2CCR0 */
|
|
|
1355 |
#define DMA1TSEL__TB2CCR2 (12*0x0100u) /* DMA channel 1 transfer select 12: TB2CCR2 */
|
|
|
1356 |
#define DMA1TSEL__RES13 (13*0x0100u) /* DMA channel 1 transfer select 13: RES13 */
|
|
|
1357 |
#define DMA1TSEL__UCA0RXIFG (14*0x0100u) /* DMA channel 1 transfer select 14: UCA0RXIFG */
|
|
|
1358 |
#define DMA1TSEL__UCA0TXIFG (15*0x0100u) /* DMA channel 1 transfer select 15: UCA0TXIFG */
|
|
|
1359 |
#define DMA1TSEL__UCA1RXIFG (16*0x0100u) /* DMA channel 1 transfer select 16: UCA1RXIFG */
|
|
|
1360 |
#define DMA1TSEL__UCA1TXIFG (17*0x0100u) /* DMA channel 1 transfer select 17: UCA1TXIFG */
|
|
|
1361 |
#define DMA1TSEL__UCB0RXIFG0 (18*0x0100u) /* DMA channel 1 transfer select 18: UCB0RXIFG0 */
|
|
|
1362 |
#define DMA1TSEL__UCB0TXIFG0 (19*0x0100u) /* DMA channel 1 transfer select 19: UCB0TXIFG0 */
|
|
|
1363 |
#define DMA1TSEL__UCB0RXIFG1 (20*0x0100u) /* DMA channel 1 transfer select 20: UCB0RXIFG1 */
|
|
|
1364 |
#define DMA1TSEL__UCB0TXIFG1 (21*0x0100u) /* DMA channel 1 transfer select 21: UCB0TXIFG1 */
|
|
|
1365 |
#define DMA1TSEL__UCB0RXIFG2 (22*0x0100u) /* DMA channel 1 transfer select 22: UCB0RXIFG2 */
|
|
|
1366 |
#define DMA1TSEL__UCB0TXIFG2 (23*0x0100u) /* DMA channel 1 transfer select 23: UCB0TXIFG2 */
|
|
|
1367 |
#define DMA1TSEL__UCB0RXIFG3 (24*0x0100u) /* DMA channel 1 transfer select 24: UCB0RXIFG3 */
|
|
|
1368 |
#define DMA1TSEL__UCB0TXIFG3 (25*0x0100u) /* DMA channel 1 transfer select 25: UCB0TXIFG3 */
|
|
|
1369 |
#define DMA1TSEL__ADC10IFG (26*0x0100u) /* DMA channel 1 transfer select 26: ADC10IFG */
|
|
|
1370 |
#define DMA1TSEL__RES27 (27*0x0100u) /* DMA channel 1 transfer select 27: RES27 */
|
|
|
1371 |
#define DMA1TSEL__RES28 (28*0x0100u) /* DMA channel 1 transfer select 28: RES28 */
|
|
|
1372 |
#define DMA1TSEL__MPY (29*0x0100u) /* DMA channel 1 transfer select 29: MPY */
|
|
|
1373 |
#define DMA1TSEL__DMA0IFG (30*0x0100u) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
|
|
|
1374 |
#define DMA1TSEL__DMAE0 (31*0x0100u) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
|
|
|
1375 |
|
|
|
1376 |
#define DMA2TSEL__DMAREQ (0*0x0001u) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
|
|
|
1377 |
#define DMA2TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 2 transfer select 1: TA0CCR0 */
|
|
|
1378 |
#define DMA2TSEL__TA0CCR2 (2*0x0001u) /* DMA channel 2 transfer select 2: TA0CCR2 */
|
|
|
1379 |
#define DMA2TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 2 transfer select 3: TA1CCR0 */
|
|
|
1380 |
#define DMA2TSEL__TA1CCR2 (4*0x0001u) /* DMA channel 2 transfer select 4: TA1CCR2 */
|
|
|
1381 |
#define DMA2TSEL__RES5 (5*0x0001u) /* DMA channel 2 transfer select 5: RES5 */
|
|
|
1382 |
#define DMA2TSEL__RES6 (6*0x0001u) /* DMA channel 2 transfer select 6: RES6 */
|
|
|
1383 |
#define DMA2TSEL__TB0CCR0 (7*0x0001u) /* DMA channel 2 transfer select 7: TB0CCR0 */
|
|
|
1384 |
#define DMA2TSEL__TB0CCR2 (8*0x0001u) /* DMA channel 2 transfer select 8: TB0CCR2 */
|
|
|
1385 |
#define DMA2TSEL__TB1CCR0 (9*0x0001u) /* DMA channel 2 transfer select 9: TB1CCR0 */
|
|
|
1386 |
#define DMA2TSEL__TB1CCR2 (10*0x0001u) /* DMA channel 2 transfer select 10: TB1CCR2 */
|
|
|
1387 |
#define DMA2TSEL__TB2CCR0 (11*0x0001u) /* DMA channel 2 transfer select 11: TB2CCR0 */
|
|
|
1388 |
#define DMA2TSEL__TB2CCR2 (12*0x0001u) /* DMA channel 2 transfer select 12: TB2CCR2 */
|
|
|
1389 |
#define DMA2TSEL__RES13 (13*0x0001u) /* DMA channel 2 transfer select 13: RES13 */
|
|
|
1390 |
#define DMA2TSEL__UCA0RXIFG (14*0x0001u) /* DMA channel 2 transfer select 14: UCA0RXIFG */
|
|
|
1391 |
#define DMA2TSEL__UCA0TXIFG (15*0x0001u) /* DMA channel 2 transfer select 15: UCA0TXIFG */
|
|
|
1392 |
#define DMA2TSEL__UCA1RXIFG (16*0x0001u) /* DMA channel 2 transfer select 16: UCA1RXIFG */
|
|
|
1393 |
#define DMA2TSEL__UCA1TXIFG (17*0x0001u) /* DMA channel 2 transfer select 17: UCA1TXIFG */
|
|
|
1394 |
#define DMA2TSEL__UCB0RXIFG0 (18*0x0001u) /* DMA channel 2 transfer select 18: UCB0RXIFG0 */
|
|
|
1395 |
#define DMA2TSEL__UCB0TXIFG0 (19*0x0001u) /* DMA channel 2 transfer select 19: UCB0TXIFG0 */
|
|
|
1396 |
#define DMA2TSEL__UCB0RXIFG1 (20*0x0001u) /* DMA channel 2 transfer select 20: UCB0RXIFG1 */
|
|
|
1397 |
#define DMA2TSEL__UCB0TXIFG1 (21*0x0001u) /* DMA channel 2 transfer select 21: UCB0TXIFG1 */
|
|
|
1398 |
#define DMA2TSEL__UCB0RXIFG2 (22*0x0001u) /* DMA channel 2 transfer select 22: UCB0RXIFG2 */
|
|
|
1399 |
#define DMA2TSEL__UCB0TXIFG2 (23*0x0001u) /* DMA channel 2 transfer select 23: UCB0TXIFG2 */
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|
|
1400 |
#define DMA2TSEL__UCB0RXIFG3 (24*0x0001u) /* DMA channel 2 transfer select 24: UCB0RXIFG3 */
|
|
|
1401 |
#define DMA2TSEL__UCB0TXIFG3 (25*0x0001u) /* DMA channel 2 transfer select 25: UCB0TXIFG3 */
|
|
|
1402 |
#define DMA2TSEL__ADC10IFG (26*0x0001u) /* DMA channel 2 transfer select 26: ADC10IFG */
|
|
|
1403 |
#define DMA2TSEL__RES27 (27*0x0001u) /* DMA channel 2 transfer select 27: RES27 */
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|
|
1404 |
#define DMA2TSEL__RES28 (28*0x0001u) /* DMA channel 2 transfer select 28: RES28 */
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|
|
1405 |
#define DMA2TSEL__MPY (29*0x0001u) /* DMA channel 2 transfer select 29: MPY */
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|
|
1406 |
#define DMA2TSEL__DMA1IFG (30*0x0001u) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
|
|
|
1407 |
#define DMA2TSEL__DMAE0 (31*0x0001u) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
|
|
|
1408 |
|
|
|
1409 |
/*************************************************************
|
|
|
1410 |
* FRAM Memory
|
|
|
1411 |
*************************************************************/
|
|
|
1412 |
#define __MSP430_HAS_FRAM_FR5XX__ /* Definition to show that Module is available */
|
|
|
1413 |
#define __MSP430_BASEADDRESS_FRAM_FR5XX__ 0x0140
|
|
|
1414 |
|
|
|
1415 |
SFR_16BIT(FRCTL0); /* FRAM Controller Control 0 */
|
|
|
1416 |
SFR_8BIT(FRCTL0_L); /* FRAM Controller Control 0 */
|
|
|
1417 |
SFR_8BIT(FRCTL0_H); /* FRAM Controller Control 0 */
|
|
|
1418 |
SFR_16BIT(GCCTL0); /* General Control 0 */
|
|
|
1419 |
SFR_8BIT(GCCTL0_L); /* General Control 0 */
|
|
|
1420 |
SFR_8BIT(GCCTL0_H); /* General Control 0 */
|
|
|
1421 |
SFR_16BIT(GCCTL1); /* General Control 1 */
|
|
|
1422 |
SFR_8BIT(GCCTL1_L); /* General Control 1 */
|
|
|
1423 |
SFR_8BIT(GCCTL1_H); /* General Control 1 */
|
|
|
1424 |
|
|
|
1425 |
#define FRPW (0x9600) /* FRAM password returned by read */
|
|
|
1426 |
#define FWPW (0xA500) /* FRAM password for write */
|
|
|
1427 |
#define FXPW (0x3300) /* for use with XOR instruction */
|
|
|
1428 |
|
|
|
1429 |
/* FRCTL0 Control Bits */
|
|
|
1430 |
#define NPRECHG0 (0x0001) /* FRAM Wait state Generator Precharge Time control Bit: 0 */
|
|
|
1431 |
#define NPRECHG1 (0x0002) /* FRAM Wait state Generator Precharge Time control Bit: 1 */
|
|
|
1432 |
#define NPRECHG2 (0x0004) /* FRAM Wait state Generator Precharge Time control Bit: 2 */
|
|
|
1433 |
#define NAUTO (0x0008) /* FRAM Disables the wait state generator */
|
|
|
1434 |
#define NACCESS0 (0x0010) /* FRAM Wait state Generator Access Time control Bit: 0 */
|
|
|
1435 |
#define NACCESS1 (0x0020) /* FRAM Wait state Generator Access Time control Bit: 1 */
|
|
|
1436 |
#define NACCESS2 (0x0040) /* FRAM Wait state Generator Access Time control Bit: 2 */
|
|
|
1437 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
1438 |
|
|
|
1439 |
/* FRCTL0 Control Bits */
|
|
|
1440 |
#define NPRECHG0_L (0x0001) /* FRAM Wait state Generator Precharge Time control Bit: 0 */
|
|
|
1441 |
#define NPRECHG1_L (0x0002) /* FRAM Wait state Generator Precharge Time control Bit: 1 */
|
|
|
1442 |
#define NPRECHG2_L (0x0004) /* FRAM Wait state Generator Precharge Time control Bit: 2 */
|
|
|
1443 |
#define NAUTO_L (0x0008) /* FRAM Disables the wait state generator */
|
|
|
1444 |
#define NACCESS0_L (0x0010) /* FRAM Wait state Generator Access Time control Bit: 0 */
|
|
|
1445 |
#define NACCESS1_L (0x0020) /* FRAM Wait state Generator Access Time control Bit: 1 */
|
|
|
1446 |
#define NACCESS2_L (0x0040) /* FRAM Wait state Generator Access Time control Bit: 2 */
|
|
|
1447 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
1448 |
|
|
|
1449 |
/* FRCTL0 Control Bits */
|
|
|
1450 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
1451 |
|
|
|
1452 |
#define NPRECHG_0 (0x0000) /* FRAM Wait state Generator Precharge Time control: 0 */
|
|
|
1453 |
#define NPRECHG_1 (0x0001) /* FRAM Wait state Generator Precharge Time control: 1 */
|
|
|
1454 |
#define NPRECHG_2 (0x0002) /* FRAM Wait state Generator Precharge Time control: 2 */
|
|
|
1455 |
#define NPRECHG_3 (0x0003) /* FRAM Wait state Generator Precharge Time control: 3 */
|
|
|
1456 |
#define NPRECHG_4 (0x0004) /* FRAM Wait state Generator Precharge Time control: 4 */
|
|
|
1457 |
#define NPRECHG_5 (0x0005) /* FRAM Wait state Generator Precharge Time control: 5 */
|
|
|
1458 |
#define NPRECHG_6 (0x0006) /* FRAM Wait state Generator Precharge Time control: 6 */
|
|
|
1459 |
#define NPRECHG_7 (0x0007) /* FRAM Wait state Generator Precharge Time control: 7 */
|
|
|
1460 |
|
|
|
1461 |
#define NACCESS_0 (0x0000) /* FRAM Wait state Generator Access Time control: 0 */
|
|
|
1462 |
#define NACCESS_1 (0x0010) /* FRAM Wait state Generator Access Time control: 1 */
|
|
|
1463 |
#define NACCESS_2 (0x0020) /* FRAM Wait state Generator Access Time control: 2 */
|
|
|
1464 |
#define NACCESS_3 (0x0030) /* FRAM Wait state Generator Access Time control: 3 */
|
|
|
1465 |
#define NACCESS_4 (0x0040) /* FRAM Wait state Generator Access Time control: 4 */
|
|
|
1466 |
#define NACCESS_5 (0x0050) /* FRAM Wait state Generator Access Time control: 5 */
|
|
|
1467 |
#define NACCESS_6 (0x0060) /* FRAM Wait state Generator Access Time control: 6 */
|
|
|
1468 |
#define NACCESS_7 (0x0070) /* FRAM Wait state Generator Access Time control: 7 */
|
|
|
1469 |
|
|
|
1470 |
/* GCCTL0 Control Bits */
|
|
|
1471 |
#define BUSY (0x0001) /* FRAM is currently busy programming */
|
|
|
1472 |
//#define RESERVED (0x0002) /* RESERVED */
|
|
|
1473 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
1474 |
#define ACCTEIE (0x0008) /* Enable NMI event if Access time error occurs */
|
|
|
1475 |
#define ACCVIE (0x0010) /* Enable NMI event if Access Violation occurs */
|
|
|
1476 |
#define SBDIEN (0x0020) /* Enable NMI event if single bit error detected */
|
|
|
1477 |
#define DBDIEN (0x0040) /* Enable NMI event if double bit error detected */
|
|
|
1478 |
#define DBDRSTEN (0x0080) /* Enable Power Up Clear on double bit error */
|
|
|
1479 |
|
|
|
1480 |
/* GCCTL0 Control Bits */
|
|
|
1481 |
#define BUSY_L (0x0001) /* FRAM is currently busy programming */
|
|
|
1482 |
//#define RESERVED (0x0002) /* RESERVED */
|
|
|
1483 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
1484 |
#define ACCTEIE_L (0x0008) /* Enable NMI event if Access time error occurs */
|
|
|
1485 |
#define ACCVIE_L (0x0010) /* Enable NMI event if Access Violation occurs */
|
|
|
1486 |
#define SBDIEN_L (0x0020) /* Enable NMI event if single bit error detected */
|
|
|
1487 |
#define DBDIEN_L (0x0040) /* Enable NMI event if double bit error detected */
|
|
|
1488 |
#define DBDRSTEN_L (0x0080) /* Enable Power Up Clear on double bit error */
|
|
|
1489 |
|
|
|
1490 |
/* GCCTL0 Control Bits */
|
|
|
1491 |
//#define RESERVED (0x0002) /* RESERVED */
|
|
|
1492 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
1493 |
|
|
|
1494 |
/* GCCTL1 Control Bits */
|
|
|
1495 |
#define ACCVIFG (0x0001) /* Access Violation Interrupt Flag */
|
|
|
1496 |
#define SBDIFG (0x0002) /* FRAM single bit error flag */
|
|
|
1497 |
#define DBDIFG (0x0004) /* FRAM double bit error flag */
|
|
|
1498 |
#define ACCTEIFG (0x0008) /* Access time error flag */
|
|
|
1499 |
|
|
|
1500 |
/* GCCTL1 Control Bits */
|
|
|
1501 |
#define ACCVIFG_L (0x0001) /* Access Violation Interrupt Flag */
|
|
|
1502 |
#define SBDIFG_L (0x0002) /* FRAM single bit error flag */
|
|
|
1503 |
#define DBDIFG_L (0x0004) /* FRAM double bit error flag */
|
|
|
1504 |
#define ACCTEIFG_L (0x0008) /* Access time error flag */
|
|
|
1505 |
|
|
|
1506 |
/* GCCTL1 Control Bits */
|
|
|
1507 |
|
|
|
1508 |
/************************************************************
|
|
|
1509 |
* Memory Protection Unit
|
|
|
1510 |
************************************************************/
|
|
|
1511 |
#define __MSP430_HAS_MPU__ /* Definition to show that Module is available */
|
|
|
1512 |
#define __MSP430_BASEADDRESS_MPU__ 0x05A0
|
|
|
1513 |
|
|
|
1514 |
SFR_16BIT(MPUCTL0); /* MPU Control Register 0 */
|
|
|
1515 |
SFR_8BIT(MPUCTL0_L); /* MPU Control Register 0 */
|
|
|
1516 |
SFR_8BIT(MPUCTL0_H); /* MPU Control Register 0 */
|
|
|
1517 |
SFR_16BIT(MPUCTL1); /* MPU Control Register 1 */
|
|
|
1518 |
SFR_8BIT(MPUCTL1_L); /* MPU Control Register 1 */
|
|
|
1519 |
SFR_8BIT(MPUCTL1_H); /* MPU Control Register 1 */
|
|
|
1520 |
SFR_16BIT(MPUSEG); /* MPU Segmentation Register */
|
|
|
1521 |
SFR_8BIT(MPUSEG_L); /* MPU Segmentation Register */
|
|
|
1522 |
SFR_8BIT(MPUSEG_H); /* MPU Segmentation Register */
|
|
|
1523 |
SFR_16BIT(MPUSAM); /* MPU Access Management Register */
|
|
|
1524 |
SFR_8BIT(MPUSAM_L); /* MPU Access Management Register */
|
|
|
1525 |
SFR_8BIT(MPUSAM_H); /* MPU Access Management Register */
|
|
|
1526 |
|
|
|
1527 |
/* MPUCTL0 Control Bits */
|
|
|
1528 |
#define MPUENA (0x0001) /* MPU Enable */
|
|
|
1529 |
#define MPULOCK (0x0002) /* MPU Lock */
|
|
|
1530 |
#define MPUSEGIE (0x0010) /* MPU Enable NMI on Segment violation */
|
|
|
1531 |
|
|
|
1532 |
/* MPUCTL0 Control Bits */
|
|
|
1533 |
#define MPUENA_L (0x0001) /* MPU Enable */
|
|
|
1534 |
#define MPULOCK_L (0x0002) /* MPU Lock */
|
|
|
1535 |
#define MPUSEGIE_L (0x0010) /* MPU Enable NMI on Segment violation */
|
|
|
1536 |
|
|
|
1537 |
/* MPUCTL0 Control Bits */
|
|
|
1538 |
#define MPUPW (0xA500) /* MPU Access Password */
|
|
|
1539 |
#define MPUPW_H (0xA5) /* MPU Access Password */
|
|
|
1540 |
|
|
|
1541 |
/* MPUCTL1 Control Bits */
|
|
|
1542 |
#define MPUSEG1IFG (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */
|
|
|
1543 |
#define MPUSEG2IFG (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */
|
|
|
1544 |
#define MPUSEG3IFG (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */
|
|
|
1545 |
#define MPUSEGIIFG (0x0008) /* MPU Info Memory Segment violation interupt flag */
|
|
|
1546 |
|
|
|
1547 |
/* MPUCTL1 Control Bits */
|
|
|
1548 |
#define MPUSEG1IFG_L (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */
|
|
|
1549 |
#define MPUSEG2IFG_L (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */
|
|
|
1550 |
#define MPUSEG3IFG_L (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */
|
|
|
1551 |
#define MPUSEGIIFG_L (0x0008) /* MPU Info Memory Segment violation interupt flag */
|
|
|
1552 |
|
|
|
1553 |
/* MPUCTL1 Control Bits */
|
|
|
1554 |
|
|
|
1555 |
/* MPUSEG Control Bits */
|
|
|
1556 |
#define MPUSB10 (0x0001) /* MPU Segment Border 1 Bit: 0 */
|
|
|
1557 |
#define MPUSB11 (0x0002) /* MPU Segment Border 1 Bit: 1 */
|
|
|
1558 |
#define MPUSB12 (0x0004) /* MPU Segment Border 1 Bit: 2 */
|
|
|
1559 |
#define MPUSB13 (0x0008) /* MPU Segment Border 1 Bit: 3 */
|
|
|
1560 |
#define MPUSB14 (0x0010) /* MPU Segment Border 1 Bit: 4 */
|
|
|
1561 |
#define MPUSB20 (0x0100) /* MPU Segment Border 2 Bit: 0 */
|
|
|
1562 |
#define MPUSB21 (0x0200) /* MPU Segment Border 2 Bit: 1 */
|
|
|
1563 |
#define MPUSB22 (0x0400) /* MPU Segment Border 2 Bit: 2 */
|
|
|
1564 |
#define MPUSB23 (0x0800) /* MPU Segment Border 2 Bit: 3 */
|
|
|
1565 |
#define MPUSB24 (0x1000) /* MPU Segment Border 2 Bit: 4 */
|
|
|
1566 |
|
|
|
1567 |
/* MPUSEG Control Bits */
|
|
|
1568 |
#define MPUSB10_L (0x0001) /* MPU Segment Border 1 Bit: 0 */
|
|
|
1569 |
#define MPUSB11_L (0x0002) /* MPU Segment Border 1 Bit: 1 */
|
|
|
1570 |
#define MPUSB12_L (0x0004) /* MPU Segment Border 1 Bit: 2 */
|
|
|
1571 |
#define MPUSB13_L (0x0008) /* MPU Segment Border 1 Bit: 3 */
|
|
|
1572 |
#define MPUSB14_L (0x0010) /* MPU Segment Border 1 Bit: 4 */
|
|
|
1573 |
|
|
|
1574 |
/* MPUSEG Control Bits */
|
|
|
1575 |
#define MPUSB20_H (0x0001) /* MPU Segment Border 2 Bit: 0 */
|
|
|
1576 |
#define MPUSB21_H (0x0002) /* MPU Segment Border 2 Bit: 1 */
|
|
|
1577 |
#define MPUSB22_H (0x0004) /* MPU Segment Border 2 Bit: 2 */
|
|
|
1578 |
#define MPUSB23_H (0x0008) /* MPU Segment Border 2 Bit: 3 */
|
|
|
1579 |
#define MPUSB24_H (0x0010) /* MPU Segment Border 2 Bit: 4 */
|
|
|
1580 |
|
|
|
1581 |
/* MPUSAM Control Bits */
|
|
|
1582 |
#define MPUSEG1RE (0x0001) /* MPU Main memory Segment 1 Read enable */
|
|
|
1583 |
#define MPUSEG1WE (0x0002) /* MPU Main memory Segment 1 Write enable */
|
|
|
1584 |
#define MPUSEG1XE (0x0004) /* MPU Main memory Segment 1 Execute enable */
|
|
|
1585 |
#define MPUSEG1VS (0x0008) /* MPU Main memory Segment 1 Violation select */
|
|
|
1586 |
#define MPUSEG2RE (0x0010) /* MPU Main memory Segment 2 Read enable */
|
|
|
1587 |
#define MPUSEG2WE (0x0020) /* MPU Main memory Segment 2 Write enable */
|
|
|
1588 |
#define MPUSEG2XE (0x0040) /* MPU Main memory Segment 2 Execute enable */
|
|
|
1589 |
#define MPUSEG2VS (0x0080) /* MPU Main memory Segment 2 Violation select */
|
|
|
1590 |
#define MPUSEG3RE (0x0100) /* MPU Main memory Segment 3 Read enable */
|
|
|
1591 |
#define MPUSEG3WE (0x0200) /* MPU Main memory Segment 3 Write enable */
|
|
|
1592 |
#define MPUSEG3XE (0x0400) /* MPU Main memory Segment 3 Execute enable */
|
|
|
1593 |
#define MPUSEG3VS (0x0800) /* MPU Main memory Segment 3 Violation select */
|
|
|
1594 |
#define MPUSEGIRE (0x1000) /* MPU Info memory Segment Read enable */
|
|
|
1595 |
#define MPUSEGIWE (0x2000) /* MPU Info memory Segment Write enable */
|
|
|
1596 |
#define MPUSEGIXE (0x4000) /* MPU Info memory Segment Execute enable */
|
|
|
1597 |
#define MPUSEGIVS (0x8000) /* MPU Info memory Segment Violation select */
|
|
|
1598 |
|
|
|
1599 |
/* MPUSAM Control Bits */
|
|
|
1600 |
#define MPUSEG1RE_L (0x0001) /* MPU Main memory Segment 1 Read enable */
|
|
|
1601 |
#define MPUSEG1WE_L (0x0002) /* MPU Main memory Segment 1 Write enable */
|
|
|
1602 |
#define MPUSEG1XE_L (0x0004) /* MPU Main memory Segment 1 Execute enable */
|
|
|
1603 |
#define MPUSEG1VS_L (0x0008) /* MPU Main memory Segment 1 Violation select */
|
|
|
1604 |
#define MPUSEG2RE_L (0x0010) /* MPU Main memory Segment 2 Read enable */
|
|
|
1605 |
#define MPUSEG2WE_L (0x0020) /* MPU Main memory Segment 2 Write enable */
|
|
|
1606 |
#define MPUSEG2XE_L (0x0040) /* MPU Main memory Segment 2 Execute enable */
|
|
|
1607 |
#define MPUSEG2VS_L (0x0080) /* MPU Main memory Segment 2 Violation select */
|
|
|
1608 |
|
|
|
1609 |
/* MPUSAM Control Bits */
|
|
|
1610 |
#define MPUSEG3RE_H (0x0001) /* MPU Main memory Segment 3 Read enable */
|
|
|
1611 |
#define MPUSEG3WE_H (0x0002) /* MPU Main memory Segment 3 Write enable */
|
|
|
1612 |
#define MPUSEG3XE_H (0x0004) /* MPU Main memory Segment 3 Execute enable */
|
|
|
1613 |
#define MPUSEG3VS_H (0x0008) /* MPU Main memory Segment 3 Violation select */
|
|
|
1614 |
#define MPUSEGIRE_H (0x0010) /* MPU Info memory Segment Read enable */
|
|
|
1615 |
#define MPUSEGIWE_H (0x0020) /* MPU Info memory Segment Write enable */
|
|
|
1616 |
#define MPUSEGIXE_H (0x0040) /* MPU Info memory Segment Execute enable */
|
|
|
1617 |
#define MPUSEGIVS_H (0x0080) /* MPU Info memory Segment Violation select */
|
|
|
1618 |
|
|
|
1619 |
/************************************************************
|
|
|
1620 |
* HARDWARE MULTIPLIER 32Bit
|
|
|
1621 |
************************************************************/
|
|
|
1622 |
#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
|
|
|
1623 |
#define __MSP430_BASEADDRESS_MPY32__ 0x04C0
|
|
|
1624 |
|
|
|
1625 |
SFR_16BIT(MPY); /* Multiply Unsigned/Operand 1 */
|
|
|
1626 |
SFR_8BIT(MPY_L); /* Multiply Unsigned/Operand 1 */
|
|
|
1627 |
SFR_8BIT(MPY_H); /* Multiply Unsigned/Operand 1 */
|
|
|
1628 |
SFR_16BIT(MPYS); /* Multiply Signed/Operand 1 */
|
|
|
1629 |
SFR_8BIT(MPYS_L); /* Multiply Signed/Operand 1 */
|
|
|
1630 |
SFR_8BIT(MPYS_H); /* Multiply Signed/Operand 1 */
|
|
|
1631 |
SFR_16BIT(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */
|
|
|
1632 |
SFR_8BIT(MAC_L); /* Multiply Unsigned and Accumulate/Operand 1 */
|
|
|
1633 |
SFR_8BIT(MAC_H); /* Multiply Unsigned and Accumulate/Operand 1 */
|
|
|
1634 |
SFR_16BIT(MACS); /* Multiply Signed and Accumulate/Operand 1 */
|
|
|
1635 |
SFR_8BIT(MACS_L); /* Multiply Signed and Accumulate/Operand 1 */
|
|
|
1636 |
SFR_8BIT(MACS_H); /* Multiply Signed and Accumulate/Operand 1 */
|
|
|
1637 |
SFR_16BIT(OP2); /* Operand 2 */
|
|
|
1638 |
SFR_8BIT(OP2_L); /* Operand 2 */
|
|
|
1639 |
SFR_8BIT(OP2_H); /* Operand 2 */
|
|
|
1640 |
SFR_16BIT(RESLO); /* Result Low Word */
|
|
|
1641 |
SFR_8BIT(RESLO_L); /* Result Low Word */
|
|
|
1642 |
SFR_8BIT(RESLO_H); /* Result Low Word */
|
|
|
1643 |
SFR_16BIT(RESHI); /* Result High Word */
|
|
|
1644 |
SFR_8BIT(RESHI_L); /* Result High Word */
|
|
|
1645 |
SFR_8BIT(RESHI_H); /* Result High Word */
|
|
|
1646 |
SFR_16BIT(SUMEXT); /* Sum Extend */
|
|
|
1647 |
SFR_8BIT(SUMEXT_L); /* Sum Extend */
|
|
|
1648 |
SFR_8BIT(SUMEXT_H); /* Sum Extend */
|
|
|
1649 |
|
|
|
1650 |
SFR_16BIT(MPY32L); /* 32-bit operand 1 - multiply - low word */
|
|
|
1651 |
SFR_8BIT(MPY32L_L); /* 32-bit operand 1 - multiply - low word */
|
|
|
1652 |
SFR_8BIT(MPY32L_H); /* 32-bit operand 1 - multiply - low word */
|
|
|
1653 |
SFR_16BIT(MPY32H); /* 32-bit operand 1 - multiply - high word */
|
|
|
1654 |
SFR_8BIT(MPY32H_L); /* 32-bit operand 1 - multiply - high word */
|
|
|
1655 |
SFR_8BIT(MPY32H_H); /* 32-bit operand 1 - multiply - high word */
|
|
|
1656 |
SFR_16BIT(MPYS32L); /* 32-bit operand 1 - signed multiply - low word */
|
|
|
1657 |
SFR_8BIT(MPYS32L_L); /* 32-bit operand 1 - signed multiply - low word */
|
|
|
1658 |
SFR_8BIT(MPYS32L_H); /* 32-bit operand 1 - signed multiply - low word */
|
|
|
1659 |
SFR_16BIT(MPYS32H); /* 32-bit operand 1 - signed multiply - high word */
|
|
|
1660 |
SFR_8BIT(MPYS32H_L); /* 32-bit operand 1 - signed multiply - high word */
|
|
|
1661 |
SFR_8BIT(MPYS32H_H); /* 32-bit operand 1 - signed multiply - high word */
|
|
|
1662 |
SFR_16BIT(MAC32L); /* 32-bit operand 1 - multiply accumulate - low word */
|
|
|
1663 |
SFR_8BIT(MAC32L_L); /* 32-bit operand 1 - multiply accumulate - low word */
|
|
|
1664 |
SFR_8BIT(MAC32L_H); /* 32-bit operand 1 - multiply accumulate - low word */
|
|
|
1665 |
SFR_16BIT(MAC32H); /* 32-bit operand 1 - multiply accumulate - high word */
|
|
|
1666 |
SFR_8BIT(MAC32H_L); /* 32-bit operand 1 - multiply accumulate - high word */
|
|
|
1667 |
SFR_8BIT(MAC32H_H); /* 32-bit operand 1 - multiply accumulate - high word */
|
|
|
1668 |
SFR_16BIT(MACS32L); /* 32-bit operand 1 - signed multiply accumulate - low word */
|
|
|
1669 |
SFR_8BIT(MACS32L_L); /* 32-bit operand 1 - signed multiply accumulate - low word */
|
|
|
1670 |
SFR_8BIT(MACS32L_H); /* 32-bit operand 1 - signed multiply accumulate - low word */
|
|
|
1671 |
SFR_16BIT(MACS32H); /* 32-bit operand 1 - signed multiply accumulate - high word */
|
|
|
1672 |
SFR_8BIT(MACS32H_L); /* 32-bit operand 1 - signed multiply accumulate - high word */
|
|
|
1673 |
SFR_8BIT(MACS32H_H); /* 32-bit operand 1 - signed multiply accumulate - high word */
|
|
|
1674 |
SFR_16BIT(OP2L); /* 32-bit operand 2 - low word */
|
|
|
1675 |
SFR_8BIT(OP2L_L); /* 32-bit operand 2 - low word */
|
|
|
1676 |
SFR_8BIT(OP2L_H); /* 32-bit operand 2 - low word */
|
|
|
1677 |
SFR_16BIT(OP2H); /* 32-bit operand 2 - high word */
|
|
|
1678 |
SFR_8BIT(OP2H_L); /* 32-bit operand 2 - high word */
|
|
|
1679 |
SFR_8BIT(OP2H_H); /* 32-bit operand 2 - high word */
|
|
|
1680 |
SFR_16BIT(RES0); /* 32x32-bit result 0 - least significant word */
|
|
|
1681 |
SFR_8BIT(RES0_L); /* 32x32-bit result 0 - least significant word */
|
|
|
1682 |
SFR_8BIT(RES0_H); /* 32x32-bit result 0 - least significant word */
|
|
|
1683 |
SFR_16BIT(RES1); /* 32x32-bit result 1 */
|
|
|
1684 |
SFR_8BIT(RES1_L); /* 32x32-bit result 1 */
|
|
|
1685 |
SFR_8BIT(RES1_H); /* 32x32-bit result 1 */
|
|
|
1686 |
SFR_16BIT(RES2); /* 32x32-bit result 2 */
|
|
|
1687 |
SFR_8BIT(RES2_L); /* 32x32-bit result 2 */
|
|
|
1688 |
SFR_8BIT(RES2_H); /* 32x32-bit result 2 */
|
|
|
1689 |
SFR_16BIT(RES3); /* 32x32-bit result 3 - most significant word */
|
|
|
1690 |
SFR_8BIT(RES3_L); /* 32x32-bit result 3 - most significant word */
|
|
|
1691 |
SFR_8BIT(RES3_H); /* 32x32-bit result 3 - most significant word */
|
|
|
1692 |
SFR_16BIT(MPY32CTL0); /* MPY32 Control Register 0 */
|
|
|
1693 |
SFR_8BIT(MPY32CTL0_L); /* MPY32 Control Register 0 */
|
|
|
1694 |
SFR_8BIT(MPY32CTL0_H); /* MPY32 Control Register 0 */
|
|
|
1695 |
|
|
|
1696 |
#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
|
|
|
1697 |
#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
|
|
|
1698 |
#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
|
|
|
1699 |
#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
|
|
|
1700 |
#define OP2_B OP2_L /* Operand 2 (Byte Access) */
|
|
|
1701 |
#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
|
|
|
1702 |
#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
|
|
|
1703 |
#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
|
|
|
1704 |
#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
|
|
|
1705 |
#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
|
|
|
1706 |
#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
|
|
|
1707 |
#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
|
|
|
1708 |
#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
|
|
|
1709 |
#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
|
|
|
1710 |
#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
|
|
|
1711 |
|
|
|
1712 |
/* MPY32CTL0 Control Bits */
|
|
|
1713 |
#define MPYC (0x0001) /* Carry of the multiplier */
|
|
|
1714 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
1715 |
#define MPYFRAC (0x0004) /* Fractional mode */
|
|
|
1716 |
#define MPYSAT (0x0008) /* Saturation mode */
|
|
|
1717 |
#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */
|
|
|
1718 |
#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */
|
|
|
1719 |
#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
|
|
|
1720 |
#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
|
|
|
1721 |
#define MPYDLYWRTEN (0x0100) /* Delayed write enable */
|
|
|
1722 |
#define MPYDLY32 (0x0200) /* Delayed write mode */
|
|
|
1723 |
|
|
|
1724 |
/* MPY32CTL0 Control Bits */
|
|
|
1725 |
#define MPYC_L (0x0001) /* Carry of the multiplier */
|
|
|
1726 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
1727 |
#define MPYFRAC_L (0x0004) /* Fractional mode */
|
|
|
1728 |
#define MPYSAT_L (0x0008) /* Saturation mode */
|
|
|
1729 |
#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */
|
|
|
1730 |
#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */
|
|
|
1731 |
#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
|
|
|
1732 |
#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
|
|
|
1733 |
|
|
|
1734 |
/* MPY32CTL0 Control Bits */
|
|
|
1735 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
1736 |
#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */
|
|
|
1737 |
#define MPYDLY32_H (0x0002) /* Delayed write mode */
|
|
|
1738 |
|
|
|
1739 |
#define MPYM_0 (0x0000) /* Multiplier mode: MPY */
|
|
|
1740 |
#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */
|
|
|
1741 |
#define MPYM_2 (0x0020) /* Multiplier mode: MAC */
|
|
|
1742 |
#define MPYM_3 (0x0030) /* Multiplier mode: MACS */
|
|
|
1743 |
#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */
|
|
|
1744 |
#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */
|
|
|
1745 |
#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */
|
|
|
1746 |
#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */
|
|
|
1747 |
|
|
|
1748 |
/************************************************************
|
|
|
1749 |
* PMM - Power Management System
|
|
|
1750 |
************************************************************/
|
|
|
1751 |
#define __MSP430_HAS_PMM_FR5xx__ /* Definition to show that Module is available */
|
|
|
1752 |
#define __MSP430_BASEADDRESS_PMM_FR5xx__ 0x0120
|
|
|
1753 |
|
|
|
1754 |
SFR_16BIT(PMMCTL0); /* PMM Control 0 */
|
|
|
1755 |
SFR_8BIT(PMMCTL0_L); /* PMM Control 0 */
|
|
|
1756 |
SFR_8BIT(PMMCTL0_H); /* PMM Control 0 */
|
|
|
1757 |
SFR_16BIT(PMMIFG); /* PMM Interrupt Flag */
|
|
|
1758 |
SFR_8BIT(PMMIFG_L); /* PMM Interrupt Flag */
|
|
|
1759 |
SFR_8BIT(PMMIFG_H); /* PMM Interrupt Flag */
|
|
|
1760 |
SFR_16BIT(PM5CTL0); /* PMM Power Mode 5 Control Register 0 */
|
|
|
1761 |
SFR_8BIT(PM5CTL0_L); /* PMM Power Mode 5 Control Register 0 */
|
|
|
1762 |
SFR_8BIT(PM5CTL0_H); /* PMM Power Mode 5 Control Register 0 */
|
|
|
1763 |
|
|
|
1764 |
#define PMMPW (0xA500) /* PMM Register Write Password */
|
|
|
1765 |
#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
|
|
|
1766 |
|
|
|
1767 |
/* PMMCTL0 Control Bits */
|
|
|
1768 |
#define PMMSWBOR (0x0004) /* PMM Software BOR */
|
|
|
1769 |
#define PMMSWPOR (0x0008) /* PMM Software POR */
|
|
|
1770 |
#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */
|
|
|
1771 |
#define SVSLE (0x0020) /* SVS low side enable */
|
|
|
1772 |
#define SVSHE (0x0040) /* SVS high side enable */
|
|
|
1773 |
|
|
|
1774 |
/* PMMCTL0 Control Bits */
|
|
|
1775 |
#define PMMSWBOR_L (0x0004) /* PMM Software BOR */
|
|
|
1776 |
#define PMMSWPOR_L (0x0008) /* PMM Software POR */
|
|
|
1777 |
#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */
|
|
|
1778 |
#define SVSLE_L (0x0020) /* SVS low side enable */
|
|
|
1779 |
#define SVSHE_L (0x0040) /* SVS high side enable */
|
|
|
1780 |
|
|
|
1781 |
/* PMMCTL0 Control Bits */
|
|
|
1782 |
|
|
|
1783 |
/* PMMIFG Control Bits */
|
|
|
1784 |
#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */
|
|
|
1785 |
#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */
|
|
|
1786 |
#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */
|
|
|
1787 |
#define SVSLIFG (0x1000) /* SVS high side interrupt flag */
|
|
|
1788 |
#define SVSHIFG (0x2000) /* SVS low side interrupt flag */
|
|
|
1789 |
#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */
|
|
|
1790 |
|
|
|
1791 |
/* PMMIFG Control Bits */
|
|
|
1792 |
|
|
|
1793 |
/* PMMIFG Control Bits */
|
|
|
1794 |
#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */
|
|
|
1795 |
#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */
|
|
|
1796 |
#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */
|
|
|
1797 |
#define SVSLIFG_H (0x0010) /* SVS high side interrupt flag */
|
|
|
1798 |
#define SVSHIFG_H (0x0020) /* SVS low side interrupt flag */
|
|
|
1799 |
#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */
|
|
|
1800 |
|
|
|
1801 |
/* PM5CTL0 Power Mode 5 Control Bits */
|
|
|
1802 |
#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
|
|
|
1803 |
|
|
|
1804 |
/* PM5CTL0 Power Mode 5 Control Bits */
|
|
|
1805 |
#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
|
|
|
1806 |
|
|
|
1807 |
/* PM5CTL0 Power Mode 5 Control Bits */
|
|
|
1808 |
|
|
|
1809 |
/************************************************************
|
|
|
1810 |
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
|
|
|
1811 |
************************************************************/
|
|
|
1812 |
#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
|
|
|
1813 |
#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
|
|
|
1814 |
#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
|
|
|
1815 |
#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
|
|
|
1816 |
#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
|
|
|
1817 |
#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
|
|
|
1818 |
|
|
|
1819 |
SFR_16BIT(PAIN); /* Port A Input */
|
|
|
1820 |
SFR_8BIT(PAIN_L); /* Port A Input */
|
|
|
1821 |
SFR_8BIT(PAIN_H); /* Port A Input */
|
|
|
1822 |
SFR_16BIT(PAOUT); /* Port A Output */
|
|
|
1823 |
SFR_8BIT(PAOUT_L); /* Port A Output */
|
|
|
1824 |
SFR_8BIT(PAOUT_H); /* Port A Output */
|
|
|
1825 |
SFR_16BIT(PADIR); /* Port A Direction */
|
|
|
1826 |
SFR_8BIT(PADIR_L); /* Port A Direction */
|
|
|
1827 |
SFR_8BIT(PADIR_H); /* Port A Direction */
|
|
|
1828 |
SFR_16BIT(PAREN); /* Port A Resistor Enable */
|
|
|
1829 |
SFR_8BIT(PAREN_L); /* Port A Resistor Enable */
|
|
|
1830 |
SFR_8BIT(PAREN_H); /* Port A Resistor Enable */
|
|
|
1831 |
SFR_16BIT(PADS); /* Port A Resistor Drive Strenght */
|
|
|
1832 |
SFR_8BIT(PADS_L); /* Port A Resistor Drive Strenght */
|
|
|
1833 |
SFR_8BIT(PADS_H); /* Port A Resistor Drive Strenght */
|
|
|
1834 |
SFR_16BIT(PASEL0); /* Port A Selection 0 */
|
|
|
1835 |
SFR_8BIT(PASEL0_L); /* Port A Selection 0 */
|
|
|
1836 |
SFR_8BIT(PASEL0_H); /* Port A Selection 0 */
|
|
|
1837 |
SFR_16BIT(PASEL1); /* Port A Selection 1 */
|
|
|
1838 |
SFR_8BIT(PASEL1_L); /* Port A Selection 1 */
|
|
|
1839 |
SFR_8BIT(PASEL1_H); /* Port A Selection 1 */
|
|
|
1840 |
SFR_16BIT(PASELC); /* Port A Complement Selection */
|
|
|
1841 |
SFR_8BIT(PASELC_L); /* Port A Complement Selection */
|
|
|
1842 |
SFR_8BIT(PASELC_H); /* Port A Complement Selection */
|
|
|
1843 |
SFR_16BIT(PAIES); /* Port A Interrupt Edge Select */
|
|
|
1844 |
SFR_8BIT(PAIES_L); /* Port A Interrupt Edge Select */
|
|
|
1845 |
SFR_8BIT(PAIES_H); /* Port A Interrupt Edge Select */
|
|
|
1846 |
SFR_16BIT(PAIE); /* Port A Interrupt Enable */
|
|
|
1847 |
SFR_8BIT(PAIE_L); /* Port A Interrupt Enable */
|
|
|
1848 |
SFR_8BIT(PAIE_H); /* Port A Interrupt Enable */
|
|
|
1849 |
SFR_16BIT(PAIFG); /* Port A Interrupt Flag */
|
|
|
1850 |
SFR_8BIT(PAIFG_L); /* Port A Interrupt Flag */
|
|
|
1851 |
SFR_8BIT(PAIFG_H); /* Port A Interrupt Flag */
|
|
|
1852 |
|
|
|
1853 |
|
|
|
1854 |
SFR_16BIT(P1IV); /* Port 1 Interrupt Vector Word */
|
|
|
1855 |
SFR_16BIT(P2IV); /* Port 2 Interrupt Vector Word */
|
|
|
1856 |
#define P1IN (PAIN_L) /* Port 1 Input */
|
|
|
1857 |
#define P1OUT (PAOUT_L) /* Port 1 Output */
|
|
|
1858 |
#define P1DIR (PADIR_L) /* Port 1 Direction */
|
|
|
1859 |
#define P1REN (PAREN_L) /* Port 1 Resistor Enable */
|
|
|
1860 |
#define P1DS (PADS_L) /* Port 1 Resistor Drive Strenght */
|
|
|
1861 |
#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */
|
|
|
1862 |
#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */
|
|
|
1863 |
#define P1SELC (PASELC_L) /* Port 1 Complement Selection */
|
|
|
1864 |
#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
|
|
|
1865 |
#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
|
|
|
1866 |
#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
|
|
|
1867 |
|
|
|
1868 |
//Definitions for P1IV
|
|
|
1869 |
#define P1IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1870 |
#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */
|
|
|
1871 |
#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */
|
|
|
1872 |
#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */
|
|
|
1873 |
#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */
|
|
|
1874 |
#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */
|
|
|
1875 |
#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */
|
|
|
1876 |
#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */
|
|
|
1877 |
#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */
|
|
|
1878 |
|
|
|
1879 |
#define P2IN (PAIN_H) /* Port 2 Input */
|
|
|
1880 |
#define P2OUT (PAOUT_H) /* Port 2 Output */
|
|
|
1881 |
#define P2DIR (PADIR_H) /* Port 2 Direction */
|
|
|
1882 |
#define P2REN (PAREN_H) /* Port 2 Resistor Enable */
|
|
|
1883 |
#define P2DS (PADS_H) /* Port 2 Resistor Drive Strenght */
|
|
|
1884 |
#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */
|
|
|
1885 |
#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */
|
|
|
1886 |
#define P2SELC (PASELC_H) /* Port 2 Complement Selection */
|
|
|
1887 |
#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
|
|
|
1888 |
#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
|
|
|
1889 |
#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
|
|
|
1890 |
|
|
|
1891 |
//Definitions for P2IV
|
|
|
1892 |
#define P2IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1893 |
#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */
|
|
|
1894 |
#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */
|
|
|
1895 |
#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */
|
|
|
1896 |
#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */
|
|
|
1897 |
#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */
|
|
|
1898 |
#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */
|
|
|
1899 |
#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */
|
|
|
1900 |
#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */
|
|
|
1901 |
|
|
|
1902 |
|
|
|
1903 |
/************************************************************
|
|
|
1904 |
* DIGITAL I/O PortJ Pull up / Pull down Resistors
|
|
|
1905 |
************************************************************/
|
|
|
1906 |
#define __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */
|
|
|
1907 |
#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320
|
|
|
1908 |
|
|
|
1909 |
SFR_16BIT(PJIN); /* Port J Input */
|
|
|
1910 |
SFR_8BIT(PJIN_L); /* Port J Input */
|
|
|
1911 |
SFR_8BIT(PJIN_H); /* Port J Input */
|
|
|
1912 |
SFR_16BIT(PJOUT); /* Port J Output */
|
|
|
1913 |
SFR_8BIT(PJOUT_L); /* Port J Output */
|
|
|
1914 |
SFR_8BIT(PJOUT_H); /* Port J Output */
|
|
|
1915 |
SFR_16BIT(PJDIR); /* Port J Direction */
|
|
|
1916 |
SFR_8BIT(PJDIR_L); /* Port J Direction */
|
|
|
1917 |
SFR_8BIT(PJDIR_H); /* Port J Direction */
|
|
|
1918 |
SFR_16BIT(PJREN); /* Port J Resistor Enable */
|
|
|
1919 |
SFR_8BIT(PJREN_L); /* Port J Resistor Enable */
|
|
|
1920 |
SFR_8BIT(PJREN_H); /* Port J Resistor Enable */
|
|
|
1921 |
SFR_16BIT(PJDS); /* Port J Resistor Drive Strenght */
|
|
|
1922 |
SFR_8BIT(PJDS_L); /* Port J Resistor Drive Strenght */
|
|
|
1923 |
SFR_8BIT(PJDS_H); /* Port J Resistor Drive Strenght */
|
|
|
1924 |
SFR_16BIT(PJSEL0); /* Port J Selection 0 */
|
|
|
1925 |
SFR_8BIT(PJSEL0_L); /* Port J Selection 0 */
|
|
|
1926 |
SFR_8BIT(PJSEL0_H); /* Port J Selection 0 */
|
|
|
1927 |
SFR_16BIT(PJSEL1); /* Port J Selection 1 */
|
|
|
1928 |
SFR_8BIT(PJSEL1_L); /* Port J Selection 1 */
|
|
|
1929 |
SFR_8BIT(PJSEL1_H); /* Port J Selection 1 */
|
|
|
1930 |
|
|
|
1931 |
/************************************************************
|
|
|
1932 |
* Shared Reference
|
|
|
1933 |
************************************************************/
|
|
|
1934 |
#define __MSP430_HAS_REF__ /* Definition to show that Module is available */
|
|
|
1935 |
#define __MSP430_BASEADDRESS_REF__ 0x01B0
|
|
|
1936 |
|
|
|
1937 |
SFR_16BIT(REFCTL0); /* REF Shared Reference control register 0 */
|
|
|
1938 |
SFR_8BIT(REFCTL0_L); /* REF Shared Reference control register 0 */
|
|
|
1939 |
SFR_8BIT(REFCTL0_H); /* REF Shared Reference control register 0 */
|
|
|
1940 |
|
|
|
1941 |
/* REFCTL0 Control Bits */
|
|
|
1942 |
#define REFON (0x0001) /* REF Reference On */
|
|
|
1943 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
1944 |
//#define RESERVED (0x0004) /* Reserved */
|
|
|
1945 |
#define REFTCOFF (0x0008) /* REF Temp.Sensor off */
|
|
|
1946 |
#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
|
|
|
1947 |
#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
|
|
|
1948 |
//#define RESERVED (0x0040) /* Reserved */
|
|
|
1949 |
//#define RESERVED (0x0080) /* Reserved */
|
|
|
1950 |
#define REFGENACT (0x0100) /* REF Reference generator active */
|
|
|
1951 |
#define REFBGACT (0x0200) /* REF Reference bandgap active */
|
|
|
1952 |
#define REFGENBUSY (0x0400) /* REF Reference generator busy */
|
|
|
1953 |
#define BGMODE (0x0800) /* REF Bandgap mode */
|
|
|
1954 |
//#define RESERVED (0x1000) /* Reserved */
|
|
|
1955 |
//#define RESERVED (0x2000) /* Reserved */
|
|
|
1956 |
//#define RESERVED (0x4000) /* Reserved */
|
|
|
1957 |
//#define RESERVED (0x8000) /* Reserved */
|
|
|
1958 |
|
|
|
1959 |
/* REFCTL0 Control Bits */
|
|
|
1960 |
#define REFON_L (0x0001) /* REF Reference On */
|
|
|
1961 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
1962 |
//#define RESERVED (0x0004) /* Reserved */
|
|
|
1963 |
#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
|
|
|
1964 |
#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
|
|
|
1965 |
#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
|
|
|
1966 |
//#define RESERVED (0x0040) /* Reserved */
|
|
|
1967 |
//#define RESERVED (0x0080) /* Reserved */
|
|
|
1968 |
//#define RESERVED (0x1000) /* Reserved */
|
|
|
1969 |
//#define RESERVED (0x2000) /* Reserved */
|
|
|
1970 |
//#define RESERVED (0x4000) /* Reserved */
|
|
|
1971 |
//#define RESERVED (0x8000) /* Reserved */
|
|
|
1972 |
|
|
|
1973 |
/* REFCTL0 Control Bits */
|
|
|
1974 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
1975 |
//#define RESERVED (0x0004) /* Reserved */
|
|
|
1976 |
//#define RESERVED (0x0040) /* Reserved */
|
|
|
1977 |
//#define RESERVED (0x0080) /* Reserved */
|
|
|
1978 |
#define REFGENACT_H (0x0001) /* REF Reference generator active */
|
|
|
1979 |
#define REFBGACT_H (0x0002) /* REF Reference bandgap active */
|
|
|
1980 |
#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
|
|
|
1981 |
#define BGMODE_H (0x0008) /* REF Bandgap mode */
|
|
|
1982 |
//#define RESERVED (0x1000) /* Reserved */
|
|
|
1983 |
//#define RESERVED (0x2000) /* Reserved */
|
|
|
1984 |
//#define RESERVED (0x4000) /* Reserved */
|
|
|
1985 |
//#define RESERVED (0x8000) /* Reserved */
|
|
|
1986 |
|
|
|
1987 |
#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */
|
|
|
1988 |
#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
|
|
|
1989 |
#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
|
|
|
1990 |
#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
|
|
|
1991 |
|
|
|
1992 |
/************************************************************
|
|
|
1993 |
* Real Time Clock
|
|
|
1994 |
************************************************************/
|
|
|
1995 |
#define __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */
|
|
|
1996 |
#define __MSP430_BASEADDRESS_RTC_B__ 0x04A0
|
|
|
1997 |
|
|
|
1998 |
SFR_16BIT(RTCCTL01); /* Real Timer Control 0/1 */
|
|
|
1999 |
SFR_8BIT(RTCCTL01_L); /* Real Timer Control 0/1 */
|
|
|
2000 |
SFR_8BIT(RTCCTL01_H); /* Real Timer Control 0/1 */
|
|
|
2001 |
SFR_16BIT(RTCCTL23); /* Real Timer Control 2/3 */
|
|
|
2002 |
SFR_8BIT(RTCCTL23_L); /* Real Timer Control 2/3 */
|
|
|
2003 |
SFR_8BIT(RTCCTL23_H); /* Real Timer Control 2/3 */
|
|
|
2004 |
SFR_16BIT(RTCPS0CTL); /* Real Timer Prescale Timer 0 Control */
|
|
|
2005 |
SFR_8BIT(RTCPS0CTL_L); /* Real Timer Prescale Timer 0 Control */
|
|
|
2006 |
SFR_8BIT(RTCPS0CTL_H); /* Real Timer Prescale Timer 0 Control */
|
|
|
2007 |
SFR_16BIT(RTCPS1CTL); /* Real Timer Prescale Timer 1 Control */
|
|
|
2008 |
SFR_8BIT(RTCPS1CTL_L); /* Real Timer Prescale Timer 1 Control */
|
|
|
2009 |
SFR_8BIT(RTCPS1CTL_H); /* Real Timer Prescale Timer 1 Control */
|
|
|
2010 |
SFR_16BIT(RTCPS); /* Real Timer Prescale Timer Control */
|
|
|
2011 |
SFR_8BIT(RTCPS_L); /* Real Timer Prescale Timer Control */
|
|
|
2012 |
SFR_8BIT(RTCPS_H); /* Real Timer Prescale Timer Control */
|
|
|
2013 |
SFR_16BIT(RTCIV); /* Real Time Clock Interrupt Vector */
|
|
|
2014 |
SFR_16BIT(RTCTIM0); /* Real Time Clock Time 0 */
|
|
|
2015 |
SFR_8BIT(RTCTIM0_L); /* Real Time Clock Time 0 */
|
|
|
2016 |
SFR_8BIT(RTCTIM0_H); /* Real Time Clock Time 0 */
|
|
|
2017 |
SFR_16BIT(RTCTIM1); /* Real Time Clock Time 1 */
|
|
|
2018 |
SFR_8BIT(RTCTIM1_L); /* Real Time Clock Time 1 */
|
|
|
2019 |
SFR_8BIT(RTCTIM1_H); /* Real Time Clock Time 1 */
|
|
|
2020 |
SFR_16BIT(RTCDATE); /* Real Time Clock Date */
|
|
|
2021 |
SFR_8BIT(RTCDATE_L); /* Real Time Clock Date */
|
|
|
2022 |
SFR_8BIT(RTCDATE_H); /* Real Time Clock Date */
|
|
|
2023 |
SFR_16BIT(RTCYEAR); /* Real Time Clock Year */
|
|
|
2024 |
SFR_8BIT(RTCYEAR_L); /* Real Time Clock Year */
|
|
|
2025 |
SFR_8BIT(RTCYEAR_H); /* Real Time Clock Year */
|
|
|
2026 |
SFR_16BIT(RTCAMINHR); /* Real Time Clock Alarm Min/Hour */
|
|
|
2027 |
SFR_8BIT(RTCAMINHR_L); /* Real Time Clock Alarm Min/Hour */
|
|
|
2028 |
SFR_8BIT(RTCAMINHR_H); /* Real Time Clock Alarm Min/Hour */
|
|
|
2029 |
SFR_16BIT(RTCADOWDAY); /* Real Time Clock Alarm day of week/day */
|
|
|
2030 |
SFR_8BIT(RTCADOWDAY_L); /* Real Time Clock Alarm day of week/day */
|
|
|
2031 |
SFR_8BIT(RTCADOWDAY_H); /* Real Time Clock Alarm day of week/day */
|
|
|
2032 |
SFR_16BIT(BIN2BCD); /* Real Time Binary-to-BCD conversion register */
|
|
|
2033 |
SFR_16BIT(BCD2BIN); /* Real Time BCD-to-binary conversion register */
|
|
|
2034 |
|
|
|
2035 |
#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
|
|
|
2036 |
#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
|
|
|
2037 |
#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
|
|
|
2038 |
#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
|
|
|
2039 |
#define RTCNT12 RTCTIM0
|
|
|
2040 |
#define RTCNT34 RTCTIM1
|
|
|
2041 |
#define RTCNT1 RTCTIM0_L
|
|
|
2042 |
#define RTCNT2 RTCTIM0_H
|
|
|
2043 |
#define RTCNT3 RTCTIM1_L
|
|
|
2044 |
#define RTCNT4 RTCTIM1_H
|
|
|
2045 |
#define RTCSEC RTCTIM0_L
|
|
|
2046 |
#define RTCMIN RTCTIM0_H
|
|
|
2047 |
#define RTCHOUR RTCTIM1_L
|
|
|
2048 |
#define RTCDOW RTCTIM1_H
|
|
|
2049 |
#define RTCDAY RTCDATE_L
|
|
|
2050 |
#define RTCMON RTCDATE_H
|
|
|
2051 |
#define RTCYEARL RTCYEAR_L
|
|
|
2052 |
#define RTCYEARH RTCYEAR_H
|
|
|
2053 |
#define RT0PS RTCPS_L
|
|
|
2054 |
#define RT1PS RTCPS_H
|
|
|
2055 |
#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
|
|
|
2056 |
#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
|
|
|
2057 |
#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
|
|
|
2058 |
#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
|
|
|
2059 |
|
|
|
2060 |
/* RTCCTL01 Control Bits */
|
|
|
2061 |
#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */
|
|
|
2062 |
#define RTCHOLD (0x4000) /* RTC Hold */
|
|
|
2063 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2064 |
#define RTCRDY (0x1000) /* RTC Ready */
|
|
|
2065 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2066 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2067 |
#define RTCTEV1 (0x0200) /* RTC Time Event 1 */
|
|
|
2068 |
#define RTCTEV0 (0x0100) /* RTC Time Event 0 */
|
|
|
2069 |
#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
|
|
|
2070 |
#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
|
|
|
2071 |
#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
|
|
|
2072 |
#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
|
|
|
2073 |
#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
|
|
|
2074 |
#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
|
|
|
2075 |
#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
|
|
|
2076 |
#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
|
|
|
2077 |
|
|
|
2078 |
/* RTCCTL01 Control Bits */
|
|
|
2079 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2080 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2081 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2082 |
#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
|
|
|
2083 |
#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
|
|
|
2084 |
#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
|
|
|
2085 |
#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
|
|
|
2086 |
#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
|
|
|
2087 |
#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
|
|
|
2088 |
#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
|
|
|
2089 |
#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
|
|
|
2090 |
|
|
|
2091 |
/* RTCCTL01 Control Bits */
|
|
|
2092 |
#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */
|
|
|
2093 |
#define RTCHOLD_H (0x0040) /* RTC Hold */
|
|
|
2094 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2095 |
#define RTCRDY_H (0x0010) /* RTC Ready */
|
|
|
2096 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2097 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2098 |
#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */
|
|
|
2099 |
#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */
|
|
|
2100 |
|
|
|
2101 |
#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
|
|
|
2102 |
#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */
|
|
|
2103 |
#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
|
|
|
2104 |
#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
|
|
|
2105 |
#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
|
|
|
2106 |
#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */
|
|
|
2107 |
#define RTCTEV__0000 (0x0200) /* RTC Time Event: 3 (00:00 changed) */
|
|
|
2108 |
#define RTCTEV__1200 (0x0300) /* RTC Time Event: 2 (12:00 changed) */
|
|
|
2109 |
|
|
|
2110 |
/* RTCCTL23 Control Bits */
|
|
|
2111 |
#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
|
|
|
2112 |
#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
|
|
|
2113 |
#define RTCCALS (0x0080) /* RTC Calibration Sign */
|
|
|
2114 |
//#define Reserved (0x0040)
|
|
|
2115 |
#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */
|
|
|
2116 |
#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */
|
|
|
2117 |
#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */
|
|
|
2118 |
#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */
|
|
|
2119 |
#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */
|
|
|
2120 |
#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */
|
|
|
2121 |
|
|
|
2122 |
/* RTCCTL23 Control Bits */
|
|
|
2123 |
#define RTCCALS_L (0x0080) /* RTC Calibration Sign */
|
|
|
2124 |
//#define Reserved (0x0040)
|
|
|
2125 |
#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */
|
|
|
2126 |
#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */
|
|
|
2127 |
#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */
|
|
|
2128 |
#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */
|
|
|
2129 |
#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */
|
|
|
2130 |
#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */
|
|
|
2131 |
|
|
|
2132 |
/* RTCCTL23 Control Bits */
|
|
|
2133 |
#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
|
|
|
2134 |
#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
|
|
|
2135 |
//#define Reserved (0x0040)
|
|
|
2136 |
|
|
|
2137 |
#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
|
|
|
2138 |
#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
|
|
|
2139 |
#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
|
|
|
2140 |
#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
|
|
|
2141 |
|
|
|
2142 |
/* RTCPS0CTL Control Bits */
|
|
|
2143 |
//#define Reserved (0x0080)
|
|
|
2144 |
//#define Reserved (0x0040)
|
|
|
2145 |
//#define Reserved (0x0020)
|
|
|
2146 |
#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
|
|
|
2147 |
#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
|
|
|
2148 |
#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
|
|
|
2149 |
#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
|
|
|
2150 |
#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
|
|
|
2151 |
|
|
|
2152 |
/* RTCPS0CTL Control Bits */
|
|
|
2153 |
//#define Reserved (0x0080)
|
|
|
2154 |
//#define Reserved (0x0040)
|
|
|
2155 |
//#define Reserved (0x0020)
|
|
|
2156 |
#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
|
|
|
2157 |
#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
|
|
|
2158 |
#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
|
|
|
2159 |
#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
|
|
|
2160 |
#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
|
|
|
2161 |
|
|
|
2162 |
/* RTCPS0CTL Control Bits */
|
|
|
2163 |
//#define Reserved (0x0080)
|
|
|
2164 |
//#define Reserved (0x0040)
|
|
|
2165 |
//#define Reserved (0x0020)
|
|
|
2166 |
|
|
|
2167 |
#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
|
|
|
2168 |
#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
|
|
|
2169 |
#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
|
|
|
2170 |
#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
|
|
|
2171 |
#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
|
|
|
2172 |
#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
|
|
|
2173 |
#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
|
|
|
2174 |
#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
|
|
|
2175 |
|
|
|
2176 |
#define RT0IP__2 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
|
|
|
2177 |
#define RT0IP__4 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
|
|
|
2178 |
#define RT0IP__8 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
|
|
|
2179 |
#define RT0IP__16 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
|
|
|
2180 |
#define RT0IP__32 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
|
|
|
2181 |
#define RT0IP__64 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
|
|
|
2182 |
#define RT0IP__128 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
|
|
|
2183 |
#define RT0IP__256 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
|
|
|
2184 |
|
|
|
2185 |
/* RTCPS1CTL Control Bits */
|
|
|
2186 |
//#define Reserved (0x0080)
|
|
|
2187 |
//#define Reserved (0x0040)
|
|
|
2188 |
//#define Reserved (0x0020)
|
|
|
2189 |
#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
|
|
|
2190 |
#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
|
|
|
2191 |
#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
|
|
|
2192 |
#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
|
|
|
2193 |
#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
|
|
|
2194 |
|
|
|
2195 |
/* RTCPS1CTL Control Bits */
|
|
|
2196 |
//#define Reserved (0x0080)
|
|
|
2197 |
//#define Reserved (0x0040)
|
|
|
2198 |
//#define Reserved (0x0020)
|
|
|
2199 |
#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
|
|
|
2200 |
#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
|
|
|
2201 |
#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
|
|
|
2202 |
#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
|
|
|
2203 |
#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
|
|
|
2204 |
|
|
|
2205 |
/* RTCPS1CTL Control Bits */
|
|
|
2206 |
//#define Reserved (0x0080)
|
|
|
2207 |
//#define Reserved (0x0040)
|
|
|
2208 |
//#define Reserved (0x0020)
|
|
|
2209 |
|
|
|
2210 |
#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
|
|
|
2211 |
#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
|
|
|
2212 |
#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
|
|
|
2213 |
#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
|
|
|
2214 |
#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
|
|
|
2215 |
#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
|
|
|
2216 |
#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
|
|
|
2217 |
#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
|
|
|
2218 |
|
|
|
2219 |
#define RT1IP__2 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
|
|
|
2220 |
#define RT1IP__4 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
|
|
|
2221 |
#define RT1IP__8 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
|
|
|
2222 |
#define RT1IP__16 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
|
|
|
2223 |
#define RT1IP__32 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
|
|
|
2224 |
#define RT1IP__64 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
|
|
|
2225 |
#define RT1IP__128 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
|
|
|
2226 |
#define RT1IP__256 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
|
|
|
2227 |
|
|
|
2228 |
/* RTC Definitions */
|
|
|
2229 |
#define RTCIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2230 |
#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
|
|
|
2231 |
#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
|
|
|
2232 |
#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
|
|
|
2233 |
#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
|
|
|
2234 |
#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
|
|
|
2235 |
#define RTCIV_RTCOFIFG (0x000C) /* RTC Oscillator fault */
|
|
|
2236 |
|
|
|
2237 |
/* Legacy Definitions */
|
|
|
2238 |
#define RTC_NONE (0x0000) /* No Interrupt pending */
|
|
|
2239 |
#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
|
|
|
2240 |
#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
|
|
|
2241 |
#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
|
|
|
2242 |
#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
|
|
|
2243 |
#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
|
|
|
2244 |
#define RTC_RTCOFIFG (0x000C) /* RTC Oscillator fault */
|
|
|
2245 |
|
|
|
2246 |
/************************************************************
|
|
|
2247 |
* SFR - Special Function Register Module
|
|
|
2248 |
************************************************************/
|
|
|
2249 |
#define __MSP430_HAS_SFR__ /* Definition to show that Module is available */
|
|
|
2250 |
#define __MSP430_BASEADDRESS_SFR__ 0x0100
|
|
|
2251 |
|
|
|
2252 |
SFR_16BIT(SFRIE1); /* Interrupt Enable 1 */
|
|
|
2253 |
SFR_8BIT(SFRIE1_L); /* Interrupt Enable 1 */
|
|
|
2254 |
SFR_8BIT(SFRIE1_H); /* Interrupt Enable 1 */
|
|
|
2255 |
|
|
|
2256 |
/* SFRIE1 Control Bits */
|
|
|
2257 |
#define WDTIE (0x0001) /* WDT Interrupt Enable */
|
|
|
2258 |
#define OFIE (0x0002) /* Osc Fault Enable */
|
|
|
2259 |
//#define Reserved (0x0004)
|
|
|
2260 |
#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */
|
|
|
2261 |
#define NMIIE (0x0010) /* NMI Interrupt Enable */
|
|
|
2262 |
#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */
|
|
|
2263 |
#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */
|
|
|
2264 |
|
|
|
2265 |
#define WDTIE_L (0x0001) /* WDT Interrupt Enable */
|
|
|
2266 |
#define OFIE_L (0x0002) /* Osc Fault Enable */
|
|
|
2267 |
//#define Reserved (0x0004)
|
|
|
2268 |
#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */
|
|
|
2269 |
#define NMIIE_L (0x0010) /* NMI Interrupt Enable */
|
|
|
2270 |
#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */
|
|
|
2271 |
#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */
|
|
|
2272 |
|
|
|
2273 |
//#define Reserved (0x0004)
|
|
|
2274 |
|
|
|
2275 |
SFR_16BIT(SFRIFG1); /* Interrupt Flag 1 */
|
|
|
2276 |
SFR_8BIT(SFRIFG1_L); /* Interrupt Flag 1 */
|
|
|
2277 |
SFR_8BIT(SFRIFG1_H); /* Interrupt Flag 1 */
|
|
|
2278 |
/* SFRIFG1 Control Bits */
|
|
|
2279 |
#define WDTIFG (0x0001) /* WDT Interrupt Flag */
|
|
|
2280 |
#define OFIFG (0x0002) /* Osc Fault Flag */
|
|
|
2281 |
//#define Reserved (0x0004)
|
|
|
2282 |
#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */
|
|
|
2283 |
#define NMIIFG (0x0010) /* NMI Interrupt Flag */
|
|
|
2284 |
//#define Reserved (0x0020)
|
|
|
2285 |
#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */
|
|
|
2286 |
#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */
|
|
|
2287 |
|
|
|
2288 |
#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */
|
|
|
2289 |
#define OFIFG_L (0x0002) /* Osc Fault Flag */
|
|
|
2290 |
//#define Reserved (0x0004)
|
|
|
2291 |
#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */
|
|
|
2292 |
#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */
|
|
|
2293 |
//#define Reserved (0x0020)
|
|
|
2294 |
#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */
|
|
|
2295 |
#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */
|
|
|
2296 |
|
|
|
2297 |
//#define Reserved (0x0004)
|
|
|
2298 |
//#define Reserved (0x0020)
|
|
|
2299 |
|
|
|
2300 |
SFR_16BIT(SFRRPCR); /* RESET Pin Control Register */
|
|
|
2301 |
SFR_8BIT(SFRRPCR_L); /* RESET Pin Control Register */
|
|
|
2302 |
SFR_8BIT(SFRRPCR_H); /* RESET Pin Control Register */
|
|
|
2303 |
/* SFRRPCR Control Bits */
|
|
|
2304 |
#define SYSNMI (0x0001) /* NMI select */
|
|
|
2305 |
#define SYSNMIIES (0x0002) /* NMI edge select */
|
|
|
2306 |
#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */
|
|
|
2307 |
#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */
|
|
|
2308 |
|
|
|
2309 |
#define SYSNMI_L (0x0001) /* NMI select */
|
|
|
2310 |
#define SYSNMIIES_L (0x0002) /* NMI edge select */
|
|
|
2311 |
#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */
|
|
|
2312 |
#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */
|
|
|
2313 |
|
|
|
2314 |
/************************************************************
|
|
|
2315 |
* SYS - System Module
|
|
|
2316 |
************************************************************/
|
|
|
2317 |
#define __MSP430_HAS_SYS__ /* Definition to show that Module is available */
|
|
|
2318 |
#define __MSP430_BASEADDRESS_SYS__ 0x0180
|
|
|
2319 |
|
|
|
2320 |
SFR_16BIT(SYSCTL); /* System control */
|
|
|
2321 |
SFR_8BIT(SYSCTL_L); /* System control */
|
|
|
2322 |
SFR_8BIT(SYSCTL_H); /* System control */
|
|
|
2323 |
SFR_16BIT(SYSBSLC); /* Boot strap configuration area */
|
|
|
2324 |
SFR_8BIT(SYSBSLC_L); /* Boot strap configuration area */
|
|
|
2325 |
SFR_8BIT(SYSBSLC_H); /* Boot strap configuration area */
|
|
|
2326 |
SFR_16BIT(SYSJMBC); /* JTAG mailbox control */
|
|
|
2327 |
SFR_8BIT(SYSJMBC_L); /* JTAG mailbox control */
|
|
|
2328 |
SFR_8BIT(SYSJMBC_H); /* JTAG mailbox control */
|
|
|
2329 |
SFR_16BIT(SYSJMBI0); /* JTAG mailbox input 0 */
|
|
|
2330 |
SFR_8BIT(SYSJMBI0_L); /* JTAG mailbox input 0 */
|
|
|
2331 |
SFR_8BIT(SYSJMBI0_H); /* JTAG mailbox input 0 */
|
|
|
2332 |
SFR_16BIT(SYSJMBI1); /* JTAG mailbox input 1 */
|
|
|
2333 |
SFR_8BIT(SYSJMBI1_L); /* JTAG mailbox input 1 */
|
|
|
2334 |
SFR_8BIT(SYSJMBI1_H); /* JTAG mailbox input 1 */
|
|
|
2335 |
SFR_16BIT(SYSJMBO0); /* JTAG mailbox output 0 */
|
|
|
2336 |
SFR_8BIT(SYSJMBO0_L); /* JTAG mailbox output 0 */
|
|
|
2337 |
SFR_8BIT(SYSJMBO0_H); /* JTAG mailbox output 0 */
|
|
|
2338 |
SFR_16BIT(SYSJMBO1); /* JTAG mailbox output 1 */
|
|
|
2339 |
SFR_8BIT(SYSJMBO1_L); /* JTAG mailbox output 1 */
|
|
|
2340 |
SFR_8BIT(SYSJMBO1_H); /* JTAG mailbox output 1 */
|
|
|
2341 |
|
|
|
2342 |
SFR_16BIT(SYSBERRIV); /* Bus Error vector generator */
|
|
|
2343 |
SFR_8BIT(SYSBERRIV_L); /* Bus Error vector generator */
|
|
|
2344 |
SFR_8BIT(SYSBERRIV_H); /* Bus Error vector generator */
|
|
|
2345 |
SFR_16BIT(SYSUNIV); /* User NMI vector generator */
|
|
|
2346 |
SFR_8BIT(SYSUNIV_L); /* User NMI vector generator */
|
|
|
2347 |
SFR_8BIT(SYSUNIV_H); /* User NMI vector generator */
|
|
|
2348 |
SFR_16BIT(SYSSNIV); /* System NMI vector generator */
|
|
|
2349 |
SFR_8BIT(SYSSNIV_L); /* System NMI vector generator */
|
|
|
2350 |
SFR_8BIT(SYSSNIV_H); /* System NMI vector generator */
|
|
|
2351 |
SFR_16BIT(SYSRSTIV); /* Reset vector generator */
|
|
|
2352 |
SFR_8BIT(SYSRSTIV_L); /* Reset vector generator */
|
|
|
2353 |
SFR_8BIT(SYSRSTIV_H); /* Reset vector generator */
|
|
|
2354 |
|
|
|
2355 |
/* SYSCTL Control Bits */
|
|
|
2356 |
#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */
|
|
|
2357 |
//#define RESERVED (0x0002) /* SYS - Reserved */
|
|
|
2358 |
#define SYSPMMPE (0x0004) /* SYS - PMM access protect */
|
|
|
2359 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
2360 |
#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */
|
|
|
2361 |
#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */
|
|
|
2362 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
2363 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
2364 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
2365 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
2366 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
2367 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
2368 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
2369 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
2370 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
2371 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
2372 |
|
|
|
2373 |
/* SYSCTL Control Bits */
|
|
|
2374 |
#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */
|
|
|
2375 |
//#define RESERVED (0x0002) /* SYS - Reserved */
|
|
|
2376 |
#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */
|
|
|
2377 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
2378 |
#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */
|
|
|
2379 |
#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */
|
|
|
2380 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
2381 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
2382 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
2383 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
2384 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
2385 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
2386 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
2387 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
2388 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
2389 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
2390 |
|
|
|
2391 |
/* SYSCTL Control Bits */
|
|
|
2392 |
//#define RESERVED (0x0002) /* SYS - Reserved */
|
|
|
2393 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
2394 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
2395 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
2396 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
2397 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
2398 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
2399 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
2400 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
2401 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
2402 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
2403 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
2404 |
|
|
|
2405 |
/* SYSBSLC Control Bits */
|
|
|
2406 |
#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */
|
|
|
2407 |
#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */
|
|
|
2408 |
#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */
|
|
|
2409 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
2410 |
//#define RESERVED (0x0010) /* SYS - Reserved */
|
|
|
2411 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
2412 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
2413 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
2414 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
2415 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
2416 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
2417 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
2418 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
2419 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
2420 |
#define SYSBSLOFF (0x4000) /* SYS - BSL Memeory disabled */
|
|
|
2421 |
#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */
|
|
|
2422 |
|
|
|
2423 |
/* SYSBSLC Control Bits */
|
|
|
2424 |
#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */
|
|
|
2425 |
#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */
|
|
|
2426 |
#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */
|
|
|
2427 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
2428 |
//#define RESERVED (0x0010) /* SYS - Reserved */
|
|
|
2429 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
2430 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
2431 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
2432 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
2433 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
2434 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
2435 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
2436 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
2437 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
2438 |
|
|
|
2439 |
/* SYSBSLC Control Bits */
|
|
|
2440 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
2441 |
//#define RESERVED (0x0010) /* SYS - Reserved */
|
|
|
2442 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
2443 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
2444 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
2445 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
2446 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
2447 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
2448 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
2449 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
2450 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
2451 |
#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memeory disabled */
|
|
|
2452 |
#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */
|
|
|
2453 |
|
|
|
2454 |
/* SYSJMBC Control Bits */
|
|
|
2455 |
#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
|
|
|
2456 |
#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
|
|
|
2457 |
#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
|
|
|
2458 |
#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
|
|
|
2459 |
#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */
|
|
|
2460 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
2461 |
#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
|
|
|
2462 |
#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
|
|
|
2463 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
2464 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
2465 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
2466 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
2467 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
2468 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
2469 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
2470 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
2471 |
|
|
|
2472 |
/* SYSJMBC Control Bits */
|
|
|
2473 |
#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
|
|
|
2474 |
#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
|
|
|
2475 |
#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
|
|
|
2476 |
#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
|
|
|
2477 |
#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */
|
|
|
2478 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
2479 |
#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
|
|
|
2480 |
#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
|
|
|
2481 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
2482 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
2483 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
2484 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
2485 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
2486 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
2487 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
2488 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
2489 |
|
|
|
2490 |
/* SYSJMBC Control Bits */
|
|
|
2491 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
2492 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
2493 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
2494 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
2495 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
2496 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
2497 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
2498 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
2499 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
2500 |
|
|
|
2501 |
/* SYSUNIV Definitions */
|
|
|
2502 |
#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2503 |
#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */
|
|
|
2504 |
#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */
|
|
|
2505 |
|
|
|
2506 |
/* SYSSNIV Definitions */
|
|
|
2507 |
#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2508 |
#define SYSSNIV_DBDIFG (0x0002) /* SYSSNIV : FRAM Double bit Error */
|
|
|
2509 |
#define SYSSNIV_ACCTIMIFG (0x0004) /* SYSSNIV : Access time error */
|
|
|
2510 |
#define SYSSNIV_MPUSEGIIFG (0x0006) /* SYSSNIV : MPUSEGIIFG violation */
|
|
|
2511 |
#define SYSSNIV_MPUSEG1IFG (0x0008) /* SYSSNIV : MPUSEG1IFG violation */
|
|
|
2512 |
#define SYSSNIV_MPUSEG2IFG (0x000A) /* SYSSNIV : MPUSEG2IFG violation */
|
|
|
2513 |
#define SYSSNIV_MPUSEG3IFG (0x000C) /* SYSSNIV : MPUSEG3IFG violation */
|
|
|
2514 |
#define SYSSNIV_ACCVIFG (0x000E) /* SYSSNIV : Access violation */
|
|
|
2515 |
#define SYSSNIV_VMAIFG (0x0010) /* SYSSNIV : VMAIFG */
|
|
|
2516 |
#define SYSSNIV_JMBINIFG (0x0012) /* SYSSNIV : JMBINIFG */
|
|
|
2517 |
#define SYSSNIV_JMBOUTIFG (0x0014) /* SYSSNIV : JMBOUTIFG */
|
|
|
2518 |
#define SYSSNIV_SBDIFG (0x0016) /* SYSSNIV : FRAM Single Bit error */
|
|
|
2519 |
|
|
|
2520 |
/* SYSRSTIV Definitions */
|
|
|
2521 |
#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2522 |
#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */
|
|
|
2523 |
#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */
|
|
|
2524 |
#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */
|
|
|
2525 |
#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */
|
|
|
2526 |
#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */
|
|
|
2527 |
#define SYSRSTIV_SVSLIFG (0x000C) /* SYSRSTIV : SVSLIFG */
|
|
|
2528 |
#define SYSRSTIV_SVSHIFG (0x000E) /* SYSRSTIV : SVSHIFG */
|
|
|
2529 |
#define SYSRSTIV_RES10 (0x0010) /* SYSRSTIV : Reserved */
|
|
|
2530 |
#define SYSRSTIV_RES12 (0x0012) /* SYSRSTIV : Reserved */
|
|
|
2531 |
#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */
|
|
|
2532 |
#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */
|
|
|
2533 |
#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */
|
|
|
2534 |
#define SYSRSTIV_FRCTLPW (0x001A) /* SYSRSTIV : FRAM Key violation */
|
|
|
2535 |
#define SYSRSTIV_DBDIFG (0x001C) /* SYSRSTIV : FRAM Double bit Error */
|
|
|
2536 |
#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */
|
|
|
2537 |
#define SYSRSTIV_PMMKEY (0x0020) /* SYSRSTIV : PMMKEY violation */
|
|
|
2538 |
#define SYSRSTIV_MPUKEY (0x0022) /* SYSRSTIV : MPUKEY violation */
|
|
|
2539 |
#define SYSRSTIV_CSKEY (0x0024) /* SYSRSTIV : CSKEY violation */
|
|
|
2540 |
#define SYSRSTIV_MPUSEGIIFG (0x0026) /* SYSRSTIV : MPUSEGIIFG violation */
|
|
|
2541 |
#define SYSRSTIV_MPUSEG1IFG (0x0028) /* SYSRSTIV : MPUSEG1IFG violation */
|
|
|
2542 |
#define SYSRSTIV_MPUSEG2IFG (0x002A) /* SYSRSTIV : MPUSEG2IFG violation */
|
|
|
2543 |
#define SYSRSTIV_MPUSEG3IFG (0x002C) /* SYSRSTIV : MPUSEG3IFG violation */
|
|
|
2544 |
|
|
|
2545 |
/************************************************************
|
|
|
2546 |
* Timer0_A3
|
|
|
2547 |
************************************************************/
|
|
|
2548 |
#define __MSP430_HAS_T0A3__ /* Definition to show that Module is available */
|
|
|
2549 |
#define __MSP430_BASEADDRESS_T0A3__ 0x0340
|
|
|
2550 |
|
|
|
2551 |
SFR_16BIT(TA0CTL); /* Timer0_A3 Control */
|
|
|
2552 |
SFR_16BIT(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */
|
|
|
2553 |
SFR_16BIT(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */
|
|
|
2554 |
SFR_16BIT(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */
|
|
|
2555 |
SFR_16BIT(TA0R); /* Timer0_A3 */
|
|
|
2556 |
SFR_16BIT(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */
|
|
|
2557 |
SFR_16BIT(TA0CCR1); /* Timer0_A3 Capture/Compare 1 */
|
|
|
2558 |
SFR_16BIT(TA0CCR2); /* Timer0_A3 Capture/Compare 2 */
|
|
|
2559 |
SFR_16BIT(TA0IV); /* Timer0_A3 Interrupt Vector Word */
|
|
|
2560 |
SFR_16BIT(TA0EX0); /* Timer0_A3 Expansion Register 0 */
|
|
|
2561 |
|
|
|
2562 |
/* TAxCTL Control Bits */
|
|
|
2563 |
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
|
|
|
2564 |
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
|
|
|
2565 |
#define ID1 (0x0080) /* Timer A clock input divider 1 */
|
|
|
2566 |
#define ID0 (0x0040) /* Timer A clock input divider 0 */
|
|
|
2567 |
#define MC1 (0x0020) /* Timer A mode control 1 */
|
|
|
2568 |
#define MC0 (0x0010) /* Timer A mode control 0 */
|
|
|
2569 |
#define TACLR (0x0004) /* Timer A counter clear */
|
|
|
2570 |
#define TAIE (0x0002) /* Timer A counter interrupt enable */
|
|
|
2571 |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
|
|
|
2572 |
|
|
|
2573 |
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
2574 |
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
2575 |
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
2576 |
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
2577 |
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
2578 |
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
2579 |
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
2580 |
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
2581 |
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
2582 |
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
2583 |
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
2584 |
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
2585 |
#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
2586 |
#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
2587 |
#define MC__CONTINOUS (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
2588 |
#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
2589 |
#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
2590 |
#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
2591 |
#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
2592 |
#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
2593 |
#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
2594 |
#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
2595 |
#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
2596 |
#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
2597 |
|
|
|
2598 |
/* TAxCCTLx Control Bits */
|
|
|
2599 |
#define CM1 (0x8000) /* Capture mode 1 */
|
|
|
2600 |
#define CM0 (0x4000) /* Capture mode 0 */
|
|
|
2601 |
#define CCIS1 (0x2000) /* Capture input select 1 */
|
|
|
2602 |
#define CCIS0 (0x1000) /* Capture input select 0 */
|
|
|
2603 |
#define SCS (0x0800) /* Capture sychronize */
|
|
|
2604 |
#define SCCI (0x0400) /* Latched capture signal (read) */
|
|
|
2605 |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
|
|
|
2606 |
#define OUTMOD2 (0x0080) /* Output mode 2 */
|
|
|
2607 |
#define OUTMOD1 (0x0040) /* Output mode 1 */
|
|
|
2608 |
#define OUTMOD0 (0x0020) /* Output mode 0 */
|
|
|
2609 |
#define CCIE (0x0010) /* Capture/compare interrupt enable */
|
|
|
2610 |
#define CCI (0x0008) /* Capture input signal (read) */
|
|
|
2611 |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
|
|
|
2612 |
#define COV (0x0002) /* Capture/compare overflow flag */
|
|
|
2613 |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
|
|
|
2614 |
|
|
|
2615 |
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
|
|
|
2616 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
|
|
|
2617 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
|
|
|
2618 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
|
|
|
2619 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
|
|
|
2620 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
|
|
|
2621 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
|
|
|
2622 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
|
|
|
2623 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
|
|
|
2624 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
|
|
|
2625 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
|
|
|
2626 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
|
|
|
2627 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
|
|
|
2628 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
|
|
|
2629 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
|
|
|
2630 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
|
|
|
2631 |
|
|
|
2632 |
/* TAxEX0 Control Bits */
|
|
|
2633 |
#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */
|
|
|
2634 |
#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */
|
|
|
2635 |
#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */
|
|
|
2636 |
|
|
|
2637 |
#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */
|
|
|
2638 |
#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */
|
|
|
2639 |
#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */
|
|
|
2640 |
#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */
|
|
|
2641 |
#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */
|
|
|
2642 |
#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */
|
|
|
2643 |
#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */
|
|
|
2644 |
#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */
|
|
|
2645 |
|
|
|
2646 |
/* T0A3IV Definitions */
|
|
|
2647 |
#define TA0IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2648 |
#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */
|
|
|
2649 |
#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */
|
|
|
2650 |
#define TA0IV_3 (0x0006) /* Reserved */
|
|
|
2651 |
#define TA0IV_4 (0x0008) /* Reserved */
|
|
|
2652 |
#define TA0IV_5 (0x000A) /* Reserved */
|
|
|
2653 |
#define TA0IV_6 (0x000C) /* Reserved */
|
|
|
2654 |
#define TA0IV_TA0IFG (0x000E) /* TA0IFG */
|
|
|
2655 |
|
|
|
2656 |
/************************************************************
|
|
|
2657 |
* Timer1_A3
|
|
|
2658 |
************************************************************/
|
|
|
2659 |
#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */
|
|
|
2660 |
#define __MSP430_BASEADDRESS_T1A3__ 0x0380
|
|
|
2661 |
|
|
|
2662 |
SFR_16BIT(TA1CTL); /* Timer1_A3 Control */
|
|
|
2663 |
SFR_16BIT(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */
|
|
|
2664 |
SFR_16BIT(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */
|
|
|
2665 |
SFR_16BIT(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */
|
|
|
2666 |
SFR_16BIT(TA1R); /* Timer1_A3 */
|
|
|
2667 |
SFR_16BIT(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */
|
|
|
2668 |
SFR_16BIT(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */
|
|
|
2669 |
SFR_16BIT(TA1CCR2); /* Timer1_A3 Capture/Compare 2 */
|
|
|
2670 |
SFR_16BIT(TA1IV); /* Timer1_A3 Interrupt Vector Word */
|
|
|
2671 |
SFR_16BIT(TA1EX0); /* Timer1_A3 Expansion Register 0 */
|
|
|
2672 |
|
|
|
2673 |
/* Bits are already defined within the Timer0_Ax */
|
|
|
2674 |
|
|
|
2675 |
/* TA1IV Definitions */
|
|
|
2676 |
#define TA1IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2677 |
#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */
|
|
|
2678 |
#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */
|
|
|
2679 |
#define TA1IV_3 (0x0006) /* Reserved */
|
|
|
2680 |
#define TA1IV_4 (0x0008) /* Reserved */
|
|
|
2681 |
#define TA1IV_5 (0x000A) /* Reserved */
|
|
|
2682 |
#define TA1IV_6 (0x000C) /* Reserved */
|
|
|
2683 |
#define TA1IV_TA1IFG (0x000E) /* TA1IFG */
|
|
|
2684 |
|
|
|
2685 |
/************************************************************
|
|
|
2686 |
* Timer0_B3
|
|
|
2687 |
************************************************************/
|
|
|
2688 |
#define __MSP430_HAS_T0B3__ /* Definition to show that Module is available */
|
|
|
2689 |
#define __MSP430_BASEADDRESS_T0B3__ 0x03C0
|
|
|
2690 |
|
|
|
2691 |
SFR_16BIT(TB0CTL); /* Timer0_B7 Control */
|
|
|
2692 |
SFR_16BIT(TB0CCTL0); /* Timer0_B7 Capture/Compare Control 0 */
|
|
|
2693 |
SFR_16BIT(TB0CCTL1); /* Timer0_B7 Capture/Compare Control 1 */
|
|
|
2694 |
SFR_16BIT(TB0CCTL2); /* Timer0_B7 Capture/Compare Control 2 */
|
|
|
2695 |
SFR_16BIT(TB0R); /* Timer0_B7 */
|
|
|
2696 |
SFR_16BIT(TB0CCR0); /* Timer0_B7 Capture/Compare 0 */
|
|
|
2697 |
SFR_16BIT(TB0CCR1); /* Timer0_B7 Capture/Compare 1 */
|
|
|
2698 |
SFR_16BIT(TB0CCR2); /* Timer0_B7 Capture/Compare 2 */
|
|
|
2699 |
SFR_16BIT(TB0EX0); /* Timer0_B7 Expansion Register 0 */
|
|
|
2700 |
SFR_16BIT(TB0IV); /* Timer0_B7 Interrupt Vector Word */
|
|
|
2701 |
|
|
|
2702 |
/* Legacy Type Definitions for TimerB */
|
|
|
2703 |
#define TBCTL TB0CTL /* Timer0_B7 Control */
|
|
|
2704 |
#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */
|
|
|
2705 |
#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */
|
|
|
2706 |
#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */
|
|
|
2707 |
#define TBR TB0R /* Timer0_B7 */
|
|
|
2708 |
#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */
|
|
|
2709 |
#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */
|
|
|
2710 |
#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */
|
|
|
2711 |
#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */
|
|
|
2712 |
#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */
|
|
|
2713 |
#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
|
|
|
2714 |
#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
|
|
|
2715 |
|
|
|
2716 |
/* TBxCTL Control Bits */
|
|
|
2717 |
#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
|
|
|
2718 |
#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
|
|
|
2719 |
#define CNTL1 (0x1000) /* Counter lenght 1 */
|
|
|
2720 |
#define CNTL0 (0x0800) /* Counter lenght 0 */
|
|
|
2721 |
#define TBSSEL1 (0x0200) /* Clock source 1 */
|
|
|
2722 |
#define TBSSEL0 (0x0100) /* Clock source 0 */
|
|
|
2723 |
#define TBCLR (0x0004) /* Timer0_B7 counter clear */
|
|
|
2724 |
#define TBIE (0x0002) /* Timer0_B7 interrupt enable */
|
|
|
2725 |
#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */
|
|
|
2726 |
|
|
|
2727 |
#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
|
|
|
2728 |
#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
|
|
|
2729 |
|
|
|
2730 |
#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
|
|
|
2731 |
#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
|
|
|
2732 |
#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
|
|
|
2733 |
#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
|
|
|
2734 |
#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
|
|
|
2735 |
#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
|
|
|
2736 |
#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
|
|
|
2737 |
#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
|
|
|
2738 |
#define SHR_0 (0*0x2000u) /* Timer0_B7 Group: 0 - individually */
|
|
|
2739 |
#define SHR_1 (1*0x2000u) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
2740 |
#define SHR_2 (2*0x2000u) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
2741 |
#define SHR_3 (3*0x2000u) /* Timer0_B7 Group: 3 - 1 group (all) */
|
|
|
2742 |
#define TBCLGRP_0 (0*0x2000u) /* Timer0_B7 Group: 0 - individually */
|
|
|
2743 |
#define TBCLGRP_1 (1*0x2000u) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
2744 |
#define TBCLGRP_2 (2*0x2000u) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
2745 |
#define TBCLGRP_3 (3*0x2000u) /* Timer0_B7 Group: 3 - 1 group (all) */
|
|
|
2746 |
#define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TACLK */
|
|
|
2747 |
#define TBSSEL__ACLK (1*0x100u) /* Timer0_B7 clock source select: 1 - ACLK */
|
|
|
2748 |
#define TBSSEL__SMCLK (2*0x100u) /* Timer0_B7 clock source select: 2 - SMCLK */
|
|
|
2749 |
#define TBSSEL__INCLK (3*0x100u) /* Timer0_B7 clock source select: 3 - INCLK */
|
|
|
2750 |
#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */
|
|
|
2751 |
#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */
|
|
|
2752 |
#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */
|
|
|
2753 |
#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */
|
|
|
2754 |
|
|
|
2755 |
/* Additional Timer B Control Register bits are defined in Timer A */
|
|
|
2756 |
/* TBxCCTLx Control Bits */
|
|
|
2757 |
#define CLLD1 (0x0400) /* Compare latch load source 1 */
|
|
|
2758 |
#define CLLD0 (0x0200) /* Compare latch load source 0 */
|
|
|
2759 |
|
|
|
2760 |
#define SLSHR1 (0x0400) /* Compare latch load source 1 */
|
|
|
2761 |
#define SLSHR0 (0x0200) /* Compare latch load source 0 */
|
|
|
2762 |
|
|
|
2763 |
#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
2764 |
#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
|
|
|
2765 |
#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
2766 |
#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
|
|
|
2767 |
|
|
|
2768 |
#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
2769 |
#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
|
|
|
2770 |
#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
2771 |
#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
|
|
|
2772 |
|
|
|
2773 |
/* TBxEX0 Control Bits */
|
|
|
2774 |
#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */
|
|
|
2775 |
#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */
|
|
|
2776 |
#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */
|
|
|
2777 |
|
|
|
2778 |
#define TBIDEX_0 (0*0x0001u) /* Timer0_B7 Input divider expansion : /1 */
|
|
|
2779 |
#define TBIDEX_1 (1*0x0001u) /* Timer0_B7 Input divider expansion : /2 */
|
|
|
2780 |
#define TBIDEX_2 (2*0x0001u) /* Timer0_B7 Input divider expansion : /3 */
|
|
|
2781 |
#define TBIDEX_3 (3*0x0001u) /* Timer0_B7 Input divider expansion : /4 */
|
|
|
2782 |
#define TBIDEX_4 (4*0x0001u) /* Timer0_B7 Input divider expansion : /5 */
|
|
|
2783 |
#define TBIDEX_5 (5*0x0001u) /* Timer0_B7 Input divider expansion : /6 */
|
|
|
2784 |
#define TBIDEX_6 (6*0x0001u) /* Timer0_B7 Input divider expansion : /7 */
|
|
|
2785 |
#define TBIDEX_7 (7*0x0001u) /* Timer0_B7 Input divider expansion : /8 */
|
|
|
2786 |
#define TBIDEX__1 (0*0x0001u) /* Timer0_B7 Input divider expansion : /1 */
|
|
|
2787 |
#define TBIDEX__2 (1*0x0001u) /* Timer0_B7 Input divider expansion : /2 */
|
|
|
2788 |
#define TBIDEX__3 (2*0x0001u) /* Timer0_B7 Input divider expansion : /3 */
|
|
|
2789 |
#define TBIDEX__4 (3*0x0001u) /* Timer0_B7 Input divider expansion : /4 */
|
|
|
2790 |
#define TBIDEX__5 (4*0x0001u) /* Timer0_B7 Input divider expansion : /5 */
|
|
|
2791 |
#define TBIDEX__6 (5*0x0001u) /* Timer0_B7 Input divider expansion : /6 */
|
|
|
2792 |
#define TBIDEX__7 (6*0x0001u) /* Timer0_B7 Input divider expansion : /7 */
|
|
|
2793 |
#define TBIDEX__8 (7*0x0001u) /* Timer0_B7 Input divider expansion : /8 */
|
|
|
2794 |
|
|
|
2795 |
/* TB0IV Definitions */
|
|
|
2796 |
#define TB0IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2797 |
#define TB0IV_TB1CCR1 (0x0002) /* TBCCR1_CCIFG */
|
|
|
2798 |
#define TB0IV_TB1CCR2 (0x0004) /* TBCCR2_CCIFG */
|
|
|
2799 |
#define TB0IV_3 (0x0006) /* Reserved */
|
|
|
2800 |
#define TB0IV_4 (0x0008) /* Reserved */
|
|
|
2801 |
#define TB0IV_5 (0x000A) /* Reserved */
|
|
|
2802 |
#define TB0IV_6 (0x000C) /* Reserved */
|
|
|
2803 |
#define TB0IV_TB0IFG (0x000E) /* TBIFG */
|
|
|
2804 |
|
|
|
2805 |
|
|
|
2806 |
/************************************************************
|
|
|
2807 |
* USCI A0
|
|
|
2808 |
************************************************************/
|
|
|
2809 |
#define __MSP430_HAS_EUSCI_A0__ /* Definition to show that Module is available */
|
|
|
2810 |
#define __MSP430_BASEADDRESS_EUSCI_A0__ 0x05C0
|
|
|
2811 |
|
|
|
2812 |
SFR_16BIT(UCA0CTLW0); /* USCI A0 Control Word Register 0 */
|
|
|
2813 |
SFR_8BIT(UCA0CTLW0_L); /* USCI A0 Control Word Register 0 */
|
|
|
2814 |
SFR_8BIT(UCA0CTLW0_H); /* USCI A0 Control Word Register 0 */
|
|
|
2815 |
#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */
|
|
|
2816 |
#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */
|
|
|
2817 |
SFR_16BIT(UCA0CTLW1); /* USCI A0 Control Word Register 1 */
|
|
|
2818 |
SFR_8BIT(UCA0CTLW1_L); /* USCI A0 Control Word Register 1 */
|
|
|
2819 |
SFR_8BIT(UCA0CTLW1_H); /* USCI A0 Control Word Register 1 */
|
|
|
2820 |
SFR_16BIT(UCA0BRW); /* USCI A0 Baud Word Rate 0 */
|
|
|
2821 |
SFR_8BIT(UCA0BRW_L); /* USCI A0 Baud Word Rate 0 */
|
|
|
2822 |
SFR_8BIT(UCA0BRW_H); /* USCI A0 Baud Word Rate 0 */
|
|
|
2823 |
#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */
|
|
|
2824 |
#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */
|
|
|
2825 |
SFR_16BIT(UCA0MCTLW); /* USCI A0 Modulation Control */
|
|
|
2826 |
SFR_8BIT(UCA0MCTLW_L); /* USCI A0 Modulation Control */
|
|
|
2827 |
SFR_8BIT(UCA0MCTLW_H); /* USCI A0 Modulation Control */
|
|
|
2828 |
SFR_8BIT(UCA0STATW); /* USCI A0 Status Register */
|
|
|
2829 |
SFR_16BIT(UCA0RXBUF); /* USCI A0 Receive Buffer */
|
|
|
2830 |
SFR_8BIT(UCA0RXBUF_L); /* USCI A0 Receive Buffer */
|
|
|
2831 |
SFR_8BIT(UCA0RXBUF_H); /* USCI A0 Receive Buffer */
|
|
|
2832 |
SFR_16BIT(UCA0TXBUF); /* USCI A0 Transmit Buffer */
|
|
|
2833 |
SFR_8BIT(UCA0TXBUF_L); /* USCI A0 Transmit Buffer */
|
|
|
2834 |
SFR_8BIT(UCA0TXBUF_H); /* USCI A0 Transmit Buffer */
|
|
|
2835 |
SFR_8BIT(UCA0ABCTL); /* USCI A0 LIN Control */
|
|
|
2836 |
SFR_16BIT(UCA0IRCTL); /* USCI A0 IrDA Transmit Control */
|
|
|
2837 |
SFR_8BIT(UCA0IRCTL_L); /* USCI A0 IrDA Transmit Control */
|
|
|
2838 |
SFR_8BIT(UCA0IRCTL_H); /* USCI A0 IrDA Transmit Control */
|
|
|
2839 |
#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */
|
|
|
2840 |
#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */
|
|
|
2841 |
SFR_16BIT(UCA0IE); /* USCI A0 Interrupt Enable Register */
|
|
|
2842 |
SFR_8BIT(UCA0IE_L); /* USCI A0 Interrupt Enable Register */
|
|
|
2843 |
SFR_8BIT(UCA0IE_H); /* USCI A0 Interrupt Enable Register */
|
|
|
2844 |
SFR_16BIT(UCA0IFG); /* USCI A0 Interrupt Flags Register */
|
|
|
2845 |
SFR_8BIT(UCA0IFG_L); /* USCI A0 Interrupt Flags Register */
|
|
|
2846 |
SFR_8BIT(UCA0IFG_H); /* USCI A0 Interrupt Flags Register */
|
|
|
2847 |
SFR_16BIT(UCA0IV); /* USCI A0 Interrupt Vector Register */
|
|
|
2848 |
|
|
|
2849 |
|
|
|
2850 |
/************************************************************
|
|
|
2851 |
* USCI B0
|
|
|
2852 |
************************************************************/
|
|
|
2853 |
#define __MSP430_HAS_EUSCI_B0__ /* Definition to show that Module is available */
|
|
|
2854 |
#define __MSP430_BASEADDRESS_EUSCI_B0__ 0x0640
|
|
|
2855 |
|
|
|
2856 |
|
|
|
2857 |
SFR_16BIT(UCB0CTLW0); /* USCI B0 Control Word Register 0 */
|
|
|
2858 |
SFR_8BIT(UCB0CTLW0_L); /* USCI B0 Control Word Register 0 */
|
|
|
2859 |
SFR_8BIT(UCB0CTLW0_H); /* USCI B0 Control Word Register 0 */
|
|
|
2860 |
#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */
|
|
|
2861 |
#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */
|
|
|
2862 |
SFR_16BIT(UCB0CTLW1); /* USCI B0 Control Word Register 1 */
|
|
|
2863 |
SFR_8BIT(UCB0CTLW1_L); /* USCI B0 Control Word Register 1 */
|
|
|
2864 |
SFR_8BIT(UCB0CTLW1_H); /* USCI B0 Control Word Register 1 */
|
|
|
2865 |
SFR_16BIT(UCB0BRW); /* USCI B0 Baud Word Rate 0 */
|
|
|
2866 |
SFR_8BIT(UCB0BRW_L); /* USCI B0 Baud Word Rate 0 */
|
|
|
2867 |
SFR_8BIT(UCB0BRW_H); /* USCI B0 Baud Word Rate 0 */
|
|
|
2868 |
#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */
|
|
|
2869 |
#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */
|
|
|
2870 |
SFR_16BIT(UCB0STATW); /* USCI B0 Status Word Register */
|
|
|
2871 |
SFR_8BIT(UCB0STATW_L); /* USCI B0 Status Word Register */
|
|
|
2872 |
SFR_8BIT(UCB0STATW_H); /* USCI B0 Status Word Register */
|
|
|
2873 |
#define UCB0STAT UCB0STATW_L /* USCI B0 Status Register */
|
|
|
2874 |
#define UCB0BCNT UCB0STATW_H /* USCI B0 Byte Counter Register */
|
|
|
2875 |
SFR_16BIT(UCB0TBCNT); /* USCI B0 Byte Counter Threshold Register */
|
|
|
2876 |
SFR_8BIT(UCB0TBCNT_L); /* USCI B0 Byte Counter Threshold Register */
|
|
|
2877 |
SFR_8BIT(UCB0TBCNT_H); /* USCI B0 Byte Counter Threshold Register */
|
|
|
2878 |
SFR_16BIT(UCB0RXBUF); /* USCI B0 Receive Buffer */
|
|
|
2879 |
SFR_8BIT(UCB0RXBUF_L); /* USCI B0 Receive Buffer */
|
|
|
2880 |
SFR_8BIT(UCB0RXBUF_H); /* USCI B0 Receive Buffer */
|
|
|
2881 |
SFR_16BIT(UCB0TXBUF); /* USCI B0 Transmit Buffer */
|
|
|
2882 |
SFR_8BIT(UCB0TXBUF_L); /* USCI B0 Transmit Buffer */
|
|
|
2883 |
SFR_8BIT(UCB0TXBUF_H); /* USCI B0 Transmit Buffer */
|
|
|
2884 |
SFR_16BIT(UCB0I2COA0); /* USCI B0 I2C Own Address 0 */
|
|
|
2885 |
SFR_8BIT(UCB0I2COA0_L); /* USCI B0 I2C Own Address 0 */
|
|
|
2886 |
SFR_8BIT(UCB0I2COA0_H); /* USCI B0 I2C Own Address 0 */
|
|
|
2887 |
SFR_16BIT(UCB0I2COA1); /* USCI B0 I2C Own Address 1 */
|
|
|
2888 |
SFR_8BIT(UCB0I2COA1_L); /* USCI B0 I2C Own Address 1 */
|
|
|
2889 |
SFR_8BIT(UCB0I2COA1_H); /* USCI B0 I2C Own Address 1 */
|
|
|
2890 |
SFR_16BIT(UCB0I2COA2); /* USCI B0 I2C Own Address 2 */
|
|
|
2891 |
SFR_8BIT(UCB0I2COA2_L); /* USCI B0 I2C Own Address 2 */
|
|
|
2892 |
SFR_8BIT(UCB0I2COA2_H); /* USCI B0 I2C Own Address 2 */
|
|
|
2893 |
SFR_16BIT(UCB0I2COA3); /* USCI B0 I2C Own Address 3 */
|
|
|
2894 |
SFR_8BIT(UCB0I2COA3_L); /* USCI B0 I2C Own Address 3 */
|
|
|
2895 |
SFR_8BIT(UCB0I2COA3_H); /* USCI B0 I2C Own Address 3 */
|
|
|
2896 |
SFR_16BIT(UCB0ADDRX); /* USCI B0 Received Address Register */
|
|
|
2897 |
SFR_8BIT(UCB0ADDRX_L); /* USCI B0 Received Address Register */
|
|
|
2898 |
SFR_8BIT(UCB0ADDRX_H); /* USCI B0 Received Address Register */
|
|
|
2899 |
SFR_16BIT(UCB0ADDMASK); /* USCI B0 Address Mask Register */
|
|
|
2900 |
SFR_8BIT(UCB0ADDMASK_L); /* USCI B0 Address Mask Register */
|
|
|
2901 |
SFR_8BIT(UCB0ADDMASK_H); /* USCI B0 Address Mask Register */
|
|
|
2902 |
SFR_16BIT(UCB0I2CSA); /* USCI B0 I2C Slave Address */
|
|
|
2903 |
SFR_8BIT(UCB0I2CSA_L); /* USCI B0 I2C Slave Address */
|
|
|
2904 |
SFR_8BIT(UCB0I2CSA_H); /* USCI B0 I2C Slave Address */
|
|
|
2905 |
SFR_16BIT(UCB0IE); /* USCI B0 Interrupt Enable Register */
|
|
|
2906 |
SFR_8BIT(UCB0IE_L); /* USCI B0 Interrupt Enable Register */
|
|
|
2907 |
SFR_8BIT(UCB0IE_H); /* USCI B0 Interrupt Enable Register */
|
|
|
2908 |
SFR_16BIT(UCB0IFG); /* USCI B0 Interrupt Flags Register */
|
|
|
2909 |
SFR_8BIT(UCB0IFG_L); /* USCI B0 Interrupt Flags Register */
|
|
|
2910 |
SFR_8BIT(UCB0IFG_H); /* USCI B0 Interrupt Flags Register */
|
|
|
2911 |
SFR_16BIT(UCB0IV); /* USCI B0 Interrupt Vector Register */
|
|
|
2912 |
|
|
|
2913 |
// UCAxCTLW0 UART-Mode Control Bits
|
|
|
2914 |
#define UCPEN (0x8000) /* Async. Mode: Parity enable */
|
|
|
2915 |
#define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */
|
|
|
2916 |
#define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */
|
|
|
2917 |
#define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
|
|
|
2918 |
#define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */
|
|
|
2919 |
#define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */
|
|
|
2920 |
#define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */
|
|
|
2921 |
#define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
|
|
|
2922 |
#define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */
|
|
|
2923 |
#define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */
|
|
|
2924 |
#define UCRXEIE (0x0020) /* RX Error interrupt enable */
|
|
|
2925 |
#define UCBRKIE (0x0010) /* Break interrupt enable */
|
|
|
2926 |
#define UCDORM (0x0008) /* Dormant (Sleep) Mode */
|
|
|
2927 |
#define UCTXADDR (0x0004) /* Send next Data as Address */
|
|
|
2928 |
#define UCTXBRK (0x0002) /* Send next Data as Break */
|
|
|
2929 |
#define UCSWRST (0x0001) /* USCI Software Reset */
|
|
|
2930 |
|
|
|
2931 |
// UCAxCTLW0 UART-Mode Control Bits
|
|
|
2932 |
#define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */
|
|
|
2933 |
#define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */
|
|
|
2934 |
#define UCRXEIE_L (0x0020) /* RX Error interrupt enable */
|
|
|
2935 |
#define UCBRKIE_L (0x0010) /* Break interrupt enable */
|
|
|
2936 |
#define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */
|
|
|
2937 |
#define UCTXADDR_L (0x0004) /* Send next Data as Address */
|
|
|
2938 |
#define UCTXBRK_L (0x0002) /* Send next Data as Break */
|
|
|
2939 |
#define UCSWRST_L (0x0001) /* USCI Software Reset */
|
|
|
2940 |
|
|
|
2941 |
// UCAxCTLW0 UART-Mode Control Bits
|
|
|
2942 |
#define UCPEN_H (0x0080) /* Async. Mode: Parity enable */
|
|
|
2943 |
#define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */
|
|
|
2944 |
#define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */
|
|
|
2945 |
#define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
|
|
|
2946 |
#define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */
|
|
|
2947 |
#define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */
|
|
|
2948 |
#define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */
|
|
|
2949 |
#define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
|
|
|
2950 |
|
|
|
2951 |
// UCxxCTLW0 SPI-Mode Control Bits
|
|
|
2952 |
#define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */
|
|
|
2953 |
#define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */
|
|
|
2954 |
#define UCMST (0x0800) /* Sync. Mode: Master Select */
|
|
|
2955 |
//#define res (0x0020) /* reserved */
|
|
|
2956 |
//#define res (0x0010) /* reserved */
|
|
|
2957 |
//#define res (0x0008) /* reserved */
|
|
|
2958 |
//#define res (0x0004) /* reserved */
|
|
|
2959 |
#define UCSTEM (0x0002) /* USCI STE Mode */
|
|
|
2960 |
|
|
|
2961 |
// UCBxCTLW0 I2C-Mode Control Bits
|
|
|
2962 |
#define UCA10 (0x8000) /* 10-bit Address Mode */
|
|
|
2963 |
#define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */
|
|
|
2964 |
#define UCMM (0x2000) /* Multi-Master Environment */
|
|
|
2965 |
//#define res (0x1000) /* reserved */
|
|
|
2966 |
//#define res (0x0100) /* reserved */
|
|
|
2967 |
#define UCTXACK (0x0020) /* Transmit ACK */
|
|
|
2968 |
#define UCTR (0x0010) /* Transmit/Receive Select/Flag */
|
|
|
2969 |
#define UCTXNACK (0x0008) /* Transmit NACK */
|
|
|
2970 |
#define UCTXSTP (0x0004) /* Transmit STOP */
|
|
|
2971 |
#define UCTXSTT (0x0002) /* Transmit START */
|
|
|
2972 |
|
|
|
2973 |
// UCBxCTLW0 I2C-Mode Control Bits
|
|
|
2974 |
//#define res (0x1000) /* reserved */
|
|
|
2975 |
//#define res (0x0100) /* reserved */
|
|
|
2976 |
#define UCTXACK_L (0x0020) /* Transmit ACK */
|
|
|
2977 |
#define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */
|
|
|
2978 |
#define UCTXNACK_L (0x0008) /* Transmit NACK */
|
|
|
2979 |
#define UCTXSTP_L (0x0004) /* Transmit STOP */
|
|
|
2980 |
#define UCTXSTT_L (0x0002) /* Transmit START */
|
|
|
2981 |
|
|
|
2982 |
// UCBxCTLW0 I2C-Mode Control Bits
|
|
|
2983 |
#define UCA10_H (0x0080) /* 10-bit Address Mode */
|
|
|
2984 |
#define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */
|
|
|
2985 |
#define UCMM_H (0x0020) /* Multi-Master Environment */
|
|
|
2986 |
//#define res (0x1000) /* reserved */
|
|
|
2987 |
//#define res (0x0100) /* reserved */
|
|
|
2988 |
|
|
|
2989 |
#define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */
|
|
|
2990 |
#define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */
|
|
|
2991 |
#define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */
|
|
|
2992 |
#define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */
|
|
|
2993 |
|
|
|
2994 |
#define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */
|
|
|
2995 |
#define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */
|
|
|
2996 |
#define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */
|
|
|
2997 |
#define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */
|
|
|
2998 |
#define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */
|
|
|
2999 |
#define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */
|
|
|
3000 |
#define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */
|
|
|
3001 |
|
|
|
3002 |
// UCAxCTLW1 UART-Mode Control Bits
|
|
|
3003 |
#define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */
|
|
|
3004 |
#define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */
|
|
|
3005 |
|
|
|
3006 |
// UCAxCTLW1 UART-Mode Control Bits
|
|
|
3007 |
#define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */
|
|
|
3008 |
#define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */
|
|
|
3009 |
|
|
|
3010 |
// UCAxCTLW1 UART-Mode Control Bits
|
|
|
3011 |
|
|
|
3012 |
// UCBxCTLW1 I2C-Mode Control Bits
|
|
|
3013 |
#define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */
|
|
|
3014 |
#define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */
|
|
|
3015 |
#define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */
|
|
|
3016 |
#define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */
|
|
|
3017 |
#define UCSWACK (0x0010) /* USCI Software controlled ACK */
|
|
|
3018 |
#define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
|
|
|
3019 |
#define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
|
|
|
3020 |
#define UCGLIT1 (0x0002) /* USCI Deglitch time Bit: 1 */
|
|
|
3021 |
#define UCGLIT0 (0x0001) /* USCI Deglitch time Bit: 0 */
|
|
|
3022 |
|
|
|
3023 |
// UCBxCTLW1 I2C-Mode Control Bits
|
|
|
3024 |
#define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */
|
|
|
3025 |
#define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */
|
|
|
3026 |
#define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */
|
|
|
3027 |
#define UCSWACK_L (0x0010) /* USCI Software controlled ACK */
|
|
|
3028 |
#define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
|
|
|
3029 |
#define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
|
|
|
3030 |
#define UCGLIT1_L (0x0002) /* USCI Deglitch time Bit: 1 */
|
|
|
3031 |
#define UCGLIT0_L (0x0001) /* USCI Deglitch time Bit: 0 */
|
|
|
3032 |
|
|
|
3033 |
// UCBxCTLW1 I2C-Mode Control Bits
|
|
|
3034 |
#define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */
|
|
|
3035 |
|
|
|
3036 |
#define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */
|
|
|
3037 |
#define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */
|
|
|
3038 |
#define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */
|
|
|
3039 |
#define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */
|
|
|
3040 |
|
|
|
3041 |
#define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */
|
|
|
3042 |
#define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */
|
|
|
3043 |
#define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */
|
|
|
3044 |
#define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */
|
|
|
3045 |
|
|
|
3046 |
#define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */
|
|
|
3047 |
#define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */
|
|
|
3048 |
#define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */
|
|
|
3049 |
#define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */
|
|
|
3050 |
|
|
|
3051 |
/* UCAxMCTLW Control Bits */
|
|
|
3052 |
#define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */
|
|
|
3053 |
#define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */
|
|
|
3054 |
#define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */
|
|
|
3055 |
#define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */
|
|
|
3056 |
#define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */
|
|
|
3057 |
#define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */
|
|
|
3058 |
#define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */
|
|
|
3059 |
#define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */
|
|
|
3060 |
#define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */
|
|
|
3061 |
#define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */
|
|
|
3062 |
#define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */
|
|
|
3063 |
#define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */
|
|
|
3064 |
#define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */
|
|
|
3065 |
|
|
|
3066 |
/* UCAxMCTLW Control Bits */
|
|
|
3067 |
#define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */
|
|
|
3068 |
#define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */
|
|
|
3069 |
#define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */
|
|
|
3070 |
#define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */
|
|
|
3071 |
#define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */
|
|
|
3072 |
|
|
|
3073 |
/* UCAxMCTLW Control Bits */
|
|
|
3074 |
#define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */
|
|
|
3075 |
#define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */
|
|
|
3076 |
#define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */
|
|
|
3077 |
#define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */
|
|
|
3078 |
#define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */
|
|
|
3079 |
#define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */
|
|
|
3080 |
#define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */
|
|
|
3081 |
#define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */
|
|
|
3082 |
|
|
|
3083 |
#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
|
|
|
3084 |
#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
|
|
|
3085 |
#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
|
|
|
3086 |
#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
|
|
|
3087 |
#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
|
|
|
3088 |
#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
|
|
|
3089 |
#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
|
|
|
3090 |
#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
|
|
|
3091 |
#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
|
|
|
3092 |
#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
|
|
|
3093 |
#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
|
|
|
3094 |
#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
|
|
|
3095 |
#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
|
|
|
3096 |
#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
|
|
|
3097 |
#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
|
|
|
3098 |
#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
|
|
|
3099 |
|
|
|
3100 |
/* UCAxSTATW Control Bits */
|
|
|
3101 |
#define UCLISTEN (0x0080) /* USCI Listen mode */
|
|
|
3102 |
#define UCFE (0x0040) /* USCI Frame Error Flag */
|
|
|
3103 |
#define UCOE (0x0020) /* USCI Overrun Error Flag */
|
|
|
3104 |
#define UCPE (0x0010) /* USCI Parity Error Flag */
|
|
|
3105 |
#define UCBRK (0x0008) /* USCI Break received */
|
|
|
3106 |
#define UCRXERR (0x0004) /* USCI RX Error Flag */
|
|
|
3107 |
#define UCADDR (0x0002) /* USCI Address received Flag */
|
|
|
3108 |
#define UCBUSY (0x0001) /* USCI Busy Flag */
|
|
|
3109 |
#define UCIDLE (0x0002) /* USCI Idle line detected Flag */
|
|
|
3110 |
|
|
|
3111 |
/* UCBxSTATW I2C Control Bits */
|
|
|
3112 |
#define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */
|
|
|
3113 |
#define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */
|
|
|
3114 |
#define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */
|
|
|
3115 |
#define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */
|
|
|
3116 |
#define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */
|
|
|
3117 |
#define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */
|
|
|
3118 |
#define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */
|
|
|
3119 |
#define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */
|
|
|
3120 |
#define UCSCLLOW (0x0040) /* SCL low */
|
|
|
3121 |
#define UCGC (0x0020) /* General Call address received Flag */
|
|
|
3122 |
#define UCBBUSY (0x0010) /* Bus Busy Flag */
|
|
|
3123 |
|
|
|
3124 |
/* UCBxTBCNT I2C Control Bits */
|
|
|
3125 |
#define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */
|
|
|
3126 |
#define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */
|
|
|
3127 |
#define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */
|
|
|
3128 |
#define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */
|
|
|
3129 |
#define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */
|
|
|
3130 |
#define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */
|
|
|
3131 |
#define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */
|
|
|
3132 |
#define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */
|
|
|
3133 |
|
|
|
3134 |
/* UCAxIRCTL Control Bits */
|
|
|
3135 |
#define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */
|
|
|
3136 |
#define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */
|
|
|
3137 |
#define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */
|
|
|
3138 |
#define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */
|
|
|
3139 |
#define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */
|
|
|
3140 |
#define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */
|
|
|
3141 |
#define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */
|
|
|
3142 |
#define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */
|
|
|
3143 |
#define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */
|
|
|
3144 |
#define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */
|
|
|
3145 |
#define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */
|
|
|
3146 |
#define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */
|
|
|
3147 |
#define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */
|
|
|
3148 |
#define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */
|
|
|
3149 |
#define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */
|
|
|
3150 |
#define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */
|
|
|
3151 |
|
|
|
3152 |
/* UCAxIRCTL Control Bits */
|
|
|
3153 |
#define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */
|
|
|
3154 |
#define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */
|
|
|
3155 |
#define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */
|
|
|
3156 |
#define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */
|
|
|
3157 |
#define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */
|
|
|
3158 |
#define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */
|
|
|
3159 |
#define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */
|
|
|
3160 |
#define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */
|
|
|
3161 |
|
|
|
3162 |
/* UCAxIRCTL Control Bits */
|
|
|
3163 |
#define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */
|
|
|
3164 |
#define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */
|
|
|
3165 |
#define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */
|
|
|
3166 |
#define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */
|
|
|
3167 |
#define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */
|
|
|
3168 |
#define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */
|
|
|
3169 |
#define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */
|
|
|
3170 |
#define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */
|
|
|
3171 |
|
|
|
3172 |
/* UCAxABCTL Control Bits */
|
|
|
3173 |
//#define res (0x80) /* reserved */
|
|
|
3174 |
//#define res (0x40) /* reserved */
|
|
|
3175 |
#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
|
|
|
3176 |
#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
|
|
|
3177 |
#define UCSTOE (0x08) /* Sync-Field Timeout error */
|
|
|
3178 |
#define UCBTOE (0x04) /* Break Timeout error */
|
|
|
3179 |
//#define res (0x02) /* reserved */
|
|
|
3180 |
#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
|
|
|
3181 |
|
|
|
3182 |
/* UCBxI2COA0 Control Bits */
|
|
|
3183 |
#define UCGCEN (0x8000) /* I2C General Call enable */
|
|
|
3184 |
#define UCOAEN (0x0400) /* I2C Own Address enable */
|
|
|
3185 |
#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
|
|
|
3186 |
#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
|
|
|
3187 |
#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
|
|
|
3188 |
#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
|
|
|
3189 |
#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
|
|
|
3190 |
#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
|
|
|
3191 |
#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
|
|
|
3192 |
#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
|
|
|
3193 |
#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
|
|
|
3194 |
#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
|
|
|
3195 |
|
|
|
3196 |
/* UCBxI2COA0 Control Bits */
|
|
|
3197 |
#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
|
|
|
3198 |
#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
|
|
|
3199 |
#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
|
|
|
3200 |
#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
|
|
|
3201 |
#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
|
|
|
3202 |
#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
|
|
|
3203 |
#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
|
|
|
3204 |
#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
|
|
|
3205 |
|
|
|
3206 |
/* UCBxI2COA0 Control Bits */
|
|
|
3207 |
#define UCGCEN_H (0x0080) /* I2C General Call enable */
|
|
|
3208 |
#define UCOAEN_H (0x0004) /* I2C Own Address enable */
|
|
|
3209 |
#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
|
|
|
3210 |
#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
|
|
|
3211 |
|
|
|
3212 |
/* UCBxI2COAx Control Bits */
|
|
|
3213 |
#define UCOAEN (0x0400) /* I2C Own Address enable */
|
|
|
3214 |
#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
|
|
|
3215 |
#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
|
|
|
3216 |
#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
|
|
|
3217 |
#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
|
|
|
3218 |
#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
|
|
|
3219 |
#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
|
|
|
3220 |
#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
|
|
|
3221 |
#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
|
|
|
3222 |
#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
|
|
|
3223 |
#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
|
|
|
3224 |
|
|
|
3225 |
/* UCBxI2COAx Control Bits */
|
|
|
3226 |
#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
|
|
|
3227 |
#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
|
|
|
3228 |
#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
|
|
|
3229 |
#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
|
|
|
3230 |
#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
|
|
|
3231 |
#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
|
|
|
3232 |
#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
|
|
|
3233 |
#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
|
|
|
3234 |
|
|
|
3235 |
/* UCBxI2COAx Control Bits */
|
|
|
3236 |
#define UCOAEN_H (0x0004) /* I2C Own Address enable */
|
|
|
3237 |
#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
|
|
|
3238 |
#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
|
|
|
3239 |
|
|
|
3240 |
/* UCBxADDRX Control Bits */
|
|
|
3241 |
#define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */
|
|
|
3242 |
#define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */
|
|
|
3243 |
#define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */
|
|
|
3244 |
#define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */
|
|
|
3245 |
#define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */
|
|
|
3246 |
#define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */
|
|
|
3247 |
#define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */
|
|
|
3248 |
#define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */
|
|
|
3249 |
#define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */
|
|
|
3250 |
#define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */
|
|
|
3251 |
|
|
|
3252 |
/* UCBxADDRX Control Bits */
|
|
|
3253 |
#define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */
|
|
|
3254 |
#define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */
|
|
|
3255 |
#define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */
|
|
|
3256 |
#define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */
|
|
|
3257 |
#define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */
|
|
|
3258 |
#define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */
|
|
|
3259 |
#define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */
|
|
|
3260 |
#define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */
|
|
|
3261 |
|
|
|
3262 |
/* UCBxADDRX Control Bits */
|
|
|
3263 |
#define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */
|
|
|
3264 |
#define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */
|
|
|
3265 |
|
|
|
3266 |
/* UCBxADDMASK Control Bits */
|
|
|
3267 |
#define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */
|
|
|
3268 |
#define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */
|
|
|
3269 |
#define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */
|
|
|
3270 |
#define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */
|
|
|
3271 |
#define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */
|
|
|
3272 |
#define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */
|
|
|
3273 |
#define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */
|
|
|
3274 |
#define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */
|
|
|
3275 |
#define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */
|
|
|
3276 |
#define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */
|
|
|
3277 |
|
|
|
3278 |
/* UCBxADDMASK Control Bits */
|
|
|
3279 |
#define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */
|
|
|
3280 |
#define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */
|
|
|
3281 |
#define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */
|
|
|
3282 |
#define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */
|
|
|
3283 |
#define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */
|
|
|
3284 |
#define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */
|
|
|
3285 |
#define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */
|
|
|
3286 |
#define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */
|
|
|
3287 |
|
|
|
3288 |
/* UCBxADDMASK Control Bits */
|
|
|
3289 |
#define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */
|
|
|
3290 |
#define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */
|
|
|
3291 |
|
|
|
3292 |
/* UCBxI2CSA Control Bits */
|
|
|
3293 |
#define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */
|
|
|
3294 |
#define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */
|
|
|
3295 |
#define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */
|
|
|
3296 |
#define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */
|
|
|
3297 |
#define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */
|
|
|
3298 |
#define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */
|
|
|
3299 |
#define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */
|
|
|
3300 |
#define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */
|
|
|
3301 |
#define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */
|
|
|
3302 |
#define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */
|
|
|
3303 |
|
|
|
3304 |
/* UCBxI2CSA Control Bits */
|
|
|
3305 |
#define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */
|
|
|
3306 |
#define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */
|
|
|
3307 |
#define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */
|
|
|
3308 |
#define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */
|
|
|
3309 |
#define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */
|
|
|
3310 |
#define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */
|
|
|
3311 |
#define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */
|
|
|
3312 |
#define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */
|
|
|
3313 |
|
|
|
3314 |
/* UCBxI2CSA Control Bits */
|
|
|
3315 |
#define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */
|
|
|
3316 |
#define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */
|
|
|
3317 |
|
|
|
3318 |
/* UCAxIE UART Control Bits */
|
|
|
3319 |
#define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */
|
|
|
3320 |
#define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */
|
|
|
3321 |
#define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */
|
|
|
3322 |
#define UCRXIE (0x0001) /* UART Receive Interrupt Enable */
|
|
|
3323 |
|
|
|
3324 |
/* UCAxIE/UCBxIE SPI Control Bits */
|
|
|
3325 |
|
|
|
3326 |
/* UCBxIE I2C Control Bits */
|
|
|
3327 |
#define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */
|
|
|
3328 |
#define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */
|
|
|
3329 |
#define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */
|
|
|
3330 |
#define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */
|
|
|
3331 |
#define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */
|
|
|
3332 |
#define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */
|
|
|
3333 |
#define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */
|
|
|
3334 |
#define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */
|
|
|
3335 |
#define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */
|
|
|
3336 |
#define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */
|
|
|
3337 |
#define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */
|
|
|
3338 |
#define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */
|
|
|
3339 |
#define UCSTTIE (0x0004) /* I2C START Condition interrupt enable */
|
|
|
3340 |
#define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */
|
|
|
3341 |
#define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */
|
|
|
3342 |
|
|
|
3343 |
/* UCAxIFG UART Control Bits */
|
|
|
3344 |
#define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */
|
|
|
3345 |
#define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */
|
|
|
3346 |
#define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */
|
|
|
3347 |
#define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */
|
|
|
3348 |
|
|
|
3349 |
/* UCAxIFG/UCBxIFG SPI Control Bits */
|
|
|
3350 |
#define UCTXIFG (0x0002) /* SPI Transmit Interrupt Flag */
|
|
|
3351 |
#define UCRXIFG (0x0001) /* SPI Receive Interrupt Flag */
|
|
|
3352 |
|
|
|
3353 |
/* UCBxIFG Control Bits */
|
|
|
3354 |
#define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */
|
|
|
3355 |
#define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */
|
|
|
3356 |
#define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */
|
|
|
3357 |
#define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */
|
|
|
3358 |
#define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */
|
|
|
3359 |
#define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */
|
|
|
3360 |
#define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */
|
|
|
3361 |
#define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */
|
|
|
3362 |
#define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */
|
|
|
3363 |
#define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */
|
|
|
3364 |
#define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */
|
|
|
3365 |
#define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */
|
|
|
3366 |
#define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */
|
|
|
3367 |
#define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */
|
|
|
3368 |
#define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */
|
|
|
3369 |
|
|
|
3370 |
/* USCI UART Definitions */
|
|
|
3371 |
#define USCI_NONE (0x0000) /* No Interrupt pending */
|
|
|
3372 |
#define USCI_UART_UCRXIFG (0x0002) /* USCI UCRXIFG */
|
|
|
3373 |
#define USCI_UART_UCTXIFG (0x0004) /* USCI UCTXIFG */
|
|
|
3374 |
#define USCI_UART_UCSTTIFG (0x0006) /* USCI UCSTTIFG */
|
|
|
3375 |
#define USCI_UART_UCTXCPTIFG (0x0008) /* USCI UCTXCPTIFG */
|
|
|
3376 |
|
|
|
3377 |
/* USCI SPI Definitions */
|
|
|
3378 |
#define USCI_SPI_UCRXIFG (0x0002) /* USCI UCRXIFG */
|
|
|
3379 |
#define USCI_SPI_UCTXIFG (0x0004) /* USCI UCTXIFG */
|
|
|
3380 |
|
|
|
3381 |
/* USCI I2C Definitions */
|
|
|
3382 |
#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */
|
|
|
3383 |
#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */
|
|
|
3384 |
#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/
|
|
|
3385 |
#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/
|
|
|
3386 |
#define USCI_I2C_UCRXIFG3 (0x000A) /* USCI I2C Mode: UCRXIFG3 */
|
|
|
3387 |
#define USCI_I2C_UCTXIFG3 (0x000C) /* USCI I2C Mode: UCTXIFG3 */
|
|
|
3388 |
#define USCI_I2C_UCRXIFG2 (0x000E) /* USCI I2C Mode: UCRXIFG2 */
|
|
|
3389 |
#define USCI_I2C_UCTXIFG2 (0x0010) /* USCI I2C Mode: UCTXIFG2 */
|
|
|
3390 |
#define USCI_I2C_UCRXIFG1 (0x0012) /* USCI I2C Mode: UCRXIFG1 */
|
|
|
3391 |
#define USCI_I2C_UCTXIFG1 (0x0014) /* USCI I2C Mode: UCTXIFG1 */
|
|
|
3392 |
#define USCI_I2C_UCRXIFG0 (0x0016) /* USCI I2C Mode: UCRXIFG0 */
|
|
|
3393 |
#define USCI_I2C_UCTXIFG0 (0x0018) /* USCI I2C Mode: UCTXIFG0 */
|
|
|
3394 |
#define USCI_I2C_UCBCNTIFG (0x001A) /* USCI I2C Mode: UCBCNTIFG */
|
|
|
3395 |
#define USCI_I2C_UCCLTOIFG (0x001C) /* USCI I2C Mode: UCCLTOIFG */
|
|
|
3396 |
#define USCI_I2C_UCBIT9IFG (0x001E) /* USCI I2C Mode: UCBIT9IFG */
|
|
|
3397 |
|
|
|
3398 |
/************************************************************
|
|
|
3399 |
* WATCHDOG TIMER A
|
|
|
3400 |
************************************************************/
|
|
|
3401 |
#define __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */
|
|
|
3402 |
#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
|
|
|
3403 |
|
|
|
3404 |
SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
|
|
|
3405 |
SFR_8BIT(WDTCTL_L); /* Watchdog Timer Control */
|
|
|
3406 |
SFR_8BIT(WDTCTL_H); /* Watchdog Timer Control */
|
|
|
3407 |
/* The bit names have been prefixed with "WDT" */
|
|
|
3408 |
/* WDTCTL Control Bits */
|
|
|
3409 |
#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */
|
|
|
3410 |
#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */
|
|
|
3411 |
#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */
|
|
|
3412 |
#define WDTCNTCL (0x0008) /* WDT - Timer Clear */
|
|
|
3413 |
#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */
|
|
|
3414 |
#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */
|
|
|
3415 |
#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */
|
|
|
3416 |
#define WDTHOLD (0x0080) /* WDT - Timer hold */
|
|
|
3417 |
|
|
|
3418 |
/* WDTCTL Control Bits */
|
|
|
3419 |
#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */
|
|
|
3420 |
#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */
|
|
|
3421 |
#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */
|
|
|
3422 |
#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */
|
|
|
3423 |
#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */
|
|
|
3424 |
#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */
|
|
|
3425 |
#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */
|
|
|
3426 |
#define WDTHOLD_L (0x0080) /* WDT - Timer hold */
|
|
|
3427 |
|
|
|
3428 |
/* WDTCTL Control Bits */
|
|
|
3429 |
|
|
|
3430 |
#define WDTPW (0x5A00)
|
|
|
3431 |
|
|
|
3432 |
#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */
|
|
|
3433 |
#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */
|
|
|
3434 |
#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
|
|
|
3435 |
#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */
|
|
|
3436 |
#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */
|
|
|
3437 |
#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
|
|
|
3438 |
#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
|
|
|
3439 |
#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
|
|
|
3440 |
#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */
|
|
|
3441 |
#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */
|
|
|
3442 |
#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
|
|
|
3443 |
#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */
|
|
|
3444 |
#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */
|
|
|
3445 |
#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
|
|
|
3446 |
#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
|
|
|
3447 |
#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
|
|
|
3448 |
|
|
|
3449 |
#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
|
|
|
3450 |
#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
|
|
|
3451 |
#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
|
|
|
3452 |
#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */
|
|
|
3453 |
#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
|
|
|
3454 |
#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
|
|
|
3455 |
#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
|
|
|
3456 |
|
|
|
3457 |
/* WDT-interval times [1ms] coded with Bits 0-2 */
|
|
|
3458 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
3459 |
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
|
|
|
3460 |
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
|
|
|
3461 |
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
|
|
|
3462 |
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
3463 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
3464 |
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
|
|
|
3465 |
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
|
|
|
3466 |
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
|
|
|
3467 |
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
3468 |
/* Watchdog mode -> reset after expired time */
|
|
|
3469 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
3470 |
#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
|
|
|
3471 |
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
|
|
|
3472 |
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
|
|
|
3473 |
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
3474 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
3475 |
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
|
|
|
3476 |
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
|
|
|
3477 |
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
|
|
|
3478 |
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
3479 |
|
|
|
3480 |
|
|
|
3481 |
/************************************************************
|
|
|
3482 |
* Interrupt Vectors (offset from 0xFF80)
|
|
|
3483 |
************************************************************/
|
|
|
3484 |
|
|
|
3485 |
#pragma diag_suppress 1107
|
|
|
3486 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
3487 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
3488 |
#define CREATE_VECTOR(name) void * const VECTOR_NAME(name) = (void *)(long)&name
|
|
|
3489 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
3490 |
#define PLACE_INTERRUPT(func) EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
|
|
|
3491 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
3492 |
PLACE_VECTOR(VECTOR_NAME(func), offset) \
|
|
|
3493 |
PLACE_INTERRUPT(func)
|
|
|
3494 |
|
|
|
3495 |
|
|
|
3496 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3497 |
#define RTC_VECTOR ".int39" /* 0xFFCE RTC */
|
|
|
3498 |
#else
|
|
|
3499 |
#define RTC_VECTOR (39 * 1u) /* 0xFFCE RTC */
|
|
|
3500 |
/*#define RTC_ISR(func) ISR_VECTOR(func, ".int39") */ /* 0xFFCE RTC */ /* CCE V2 Style */
|
|
|
3501 |
#endif
|
|
|
3502 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3503 |
#define PORT2_VECTOR ".int44" /* 0xFFD8 Port 2 */
|
|
|
3504 |
#else
|
|
|
3505 |
#define PORT2_VECTOR (44 * 1u) /* 0xFFD8 Port 2 */
|
|
|
3506 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int44") */ /* 0xFFD8 Port 2 */ /* CCE V2 Style */
|
|
|
3507 |
#endif
|
|
|
3508 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3509 |
#define PORT1_VECTOR ".int47" /* 0xFFDE Port 1 */
|
|
|
3510 |
#else
|
|
|
3511 |
#define PORT1_VECTOR (47 * 1u) /* 0xFFDE Port 1 */
|
|
|
3512 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int47") */ /* 0xFFDE Port 1 */ /* CCE V2 Style */
|
|
|
3513 |
#endif
|
|
|
3514 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3515 |
#define TIMER1_A1_VECTOR ".int48" /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
|
|
|
3516 |
#else
|
|
|
3517 |
#define TIMER1_A1_VECTOR (48 * 1u) /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
|
|
|
3518 |
/*#define TIMER1_A1_ISR(func) ISR_VECTOR(func, ".int48") */ /* 0xFFE0 Timer1_A3 CC1-2, TA1 */ /* CCE V2 Style */
|
|
|
3519 |
#endif
|
|
|
3520 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3521 |
#define TIMER1_A0_VECTOR ".int49" /* 0xFFE2 Timer1_A3 CC0 */
|
|
|
3522 |
#else
|
|
|
3523 |
#define TIMER1_A0_VECTOR (49 * 1u) /* 0xFFE2 Timer1_A3 CC0 */
|
|
|
3524 |
/*#define TIMER1_A0_ISR(func) ISR_VECTOR(func, ".int49") */ /* 0xFFE2 Timer1_A3 CC0 */ /* CCE V2 Style */
|
|
|
3525 |
#endif
|
|
|
3526 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3527 |
#define DMA_VECTOR ".int50" /* 0xFFE4 DMA */
|
|
|
3528 |
#else
|
|
|
3529 |
#define DMA_VECTOR (50 * 1u) /* 0xFFE4 DMA */
|
|
|
3530 |
/*#define DMA_ISR(func) ISR_VECTOR(func, ".int50") */ /* 0xFFE4 DMA */ /* CCE V2 Style */
|
|
|
3531 |
#endif
|
|
|
3532 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3533 |
#define TIMER0_A1_VECTOR ".int52" /* 0xFFE8 Timer0_A5 CC1-4, TA */
|
|
|
3534 |
#else
|
|
|
3535 |
#define TIMER0_A1_VECTOR (52 * 1u) /* 0xFFE8 Timer0_A5 CC1-4, TA */
|
|
|
3536 |
/*#define TIMER0_A1_ISR(func) ISR_VECTOR(func, ".int52") */ /* 0xFFE8 Timer0_A5 CC1-4, TA */ /* CCE V2 Style */
|
|
|
3537 |
#endif
|
|
|
3538 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3539 |
#define TIMER0_A0_VECTOR ".int53" /* 0xFFEA Timer0_A5 CC0 */
|
|
|
3540 |
#else
|
|
|
3541 |
#define TIMER0_A0_VECTOR (53 * 1u) /* 0xFFEA Timer0_A5 CC0 */
|
|
|
3542 |
/*#define TIMER0_A0_ISR(func) ISR_VECTOR(func, ".int53") */ /* 0xFFEA Timer0_A5 CC0 */ /* CCE V2 Style */
|
|
|
3543 |
#endif
|
|
|
3544 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3545 |
#define ADC10_VECTOR ".int54" /* 0xFFEC ADC */
|
|
|
3546 |
#else
|
|
|
3547 |
#define ADC10_VECTOR (54 * 1u) /* 0xFFEC ADC */
|
|
|
3548 |
/*#define ADC10_ISR(func) ISR_VECTOR(func, ".int54") */ /* 0xFFEC ADC */ /* CCE V2 Style */
|
|
|
3549 |
#endif
|
|
|
3550 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3551 |
#define USCI_B0_VECTOR ".int55" /* 0xFFEE USCI B0 Receive/Transmit */
|
|
|
3552 |
#else
|
|
|
3553 |
#define USCI_B0_VECTOR (55 * 1u) /* 0xFFEE USCI B0 Receive/Transmit */
|
|
|
3554 |
/*#define USCI_B0_ISR(func) ISR_VECTOR(func, ".int55") */ /* 0xFFEE USCI B0 Receive/Transmit */ /* CCE V2 Style */
|
|
|
3555 |
#endif
|
|
|
3556 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3557 |
#define USCI_A0_VECTOR ".int56" /* 0xFFF0 USCI A0 Receive/Transmit */
|
|
|
3558 |
#else
|
|
|
3559 |
#define USCI_A0_VECTOR (56 * 1u) /* 0xFFF0 USCI A0 Receive/Transmit */
|
|
|
3560 |
/*#define USCI_A0_ISR(func) ISR_VECTOR(func, ".int56") */ /* 0xFFF0 USCI A0 Receive/Transmit */ /* CCE V2 Style */
|
|
|
3561 |
#endif
|
|
|
3562 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3563 |
#define WDT_VECTOR ".int57" /* 0xFFF2 Watchdog Timer */
|
|
|
3564 |
#else
|
|
|
3565 |
#define WDT_VECTOR (57 * 1u) /* 0xFFF2 Watchdog Timer */
|
|
|
3566 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int57") */ /* 0xFFF2 Watchdog Timer */ /* CCE V2 Style */
|
|
|
3567 |
#endif
|
|
|
3568 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3569 |
#define TIMER0_B1_VECTOR ".int58" /* 0xFFF4 Timer0_B3 CC1-2, TB */
|
|
|
3570 |
#else
|
|
|
3571 |
#define TIMER0_B1_VECTOR (58 * 1u) /* 0xFFF4 Timer0_B3 CC1-2, TB */
|
|
|
3572 |
/*#define TIMER0_B1_ISR(func) ISR_VECTOR(func, ".int58") */ /* 0xFFF4 Timer0_B3 CC1-2, TB */ /* CCE V2 Style */
|
|
|
3573 |
#endif
|
|
|
3574 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3575 |
#define TIMER0_B0_VECTOR ".int59" /* 0xFFF6 Timer0_B3 CC0 */
|
|
|
3576 |
#else
|
|
|
3577 |
#define TIMER0_B0_VECTOR (59 * 1u) /* 0xFFF6 Timer0_B3 CC0 */
|
|
|
3578 |
/*#define TIMER0_B0_ISR(func) ISR_VECTOR(func, ".int59") */ /* 0xFFF6 Timer0_B3 CC0 */ /* CCE V2 Style */
|
|
|
3579 |
#endif
|
|
|
3580 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3581 |
#define COMP_D_VECTOR ".int60" /* 0xFFF8 Comparator D */
|
|
|
3582 |
#else
|
|
|
3583 |
#define COMP_D_VECTOR (60 * 1u) /* 0xFFF8 Comparator D */
|
|
|
3584 |
/*#define COMP_D_ISR(func) ISR_VECTOR(func, ".int60") */ /* 0xFFF8 Comparator D */ /* CCE V2 Style */
|
|
|
3585 |
#endif
|
|
|
3586 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3587 |
#define UNMI_VECTOR ".int61" /* 0xFFFA User Non-maskable */
|
|
|
3588 |
#else
|
|
|
3589 |
#define UNMI_VECTOR (61 * 1u) /* 0xFFFA User Non-maskable */
|
|
|
3590 |
/*#define UNMI_ISR(func) ISR_VECTOR(func, ".int61") */ /* 0xFFFA User Non-maskable */ /* CCE V2 Style */
|
|
|
3591 |
#endif
|
|
|
3592 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3593 |
#define SYSNMI_VECTOR ".int62" /* 0xFFFC System Non-maskable */
|
|
|
3594 |
#else
|
|
|
3595 |
#define SYSNMI_VECTOR (62 * 1u) /* 0xFFFC System Non-maskable */
|
|
|
3596 |
/*#define SYSNMI_ISR(func) ISR_VECTOR(func, ".int62") */ /* 0xFFFC System Non-maskable */ /* CCE V2 Style */
|
|
|
3597 |
#endif
|
|
|
3598 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3599 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
3600 |
#else
|
|
|
3601 |
#define RESET_VECTOR (63 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
3602 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int63") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
3603 |
#endif
|
|
|
3604 |
|
|
|
3605 |
/************************************************************
|
|
|
3606 |
* End of Modules
|
|
|
3607 |
************************************************************/
|
|
|
3608 |
|
|
|
3609 |
#ifdef __cplusplus
|
|
|
3610 |
}
|
|
|
3611 |
#endif /* extern "C" */
|
|
|
3612 |
|
|
|
3613 |
#endif /* #ifndef __MSP430FR5720 */
|
|
|
3614 |
|