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2850 dpurdie 1 
/********************************************************************
2 
*
3 
* Standard register and bit definitions for the Texas Instruments
4 
* MSP430 microcontroller.
5 
*
6 
* This file supports assembler and C development for
7 
* MSP430F5637 devices.
8 
*
9 
* Texas Instruments, Version 1.2
10 
*
11 
* Rev. 1.0, Setup
12 
* Rev. 1.1  Changed access type of TimerA/B registers to word only
13 
* Rev. 1.2  Fixed definition of RTCTEV__0000 and RTCTEV__1200
14 
*           Removed not availabe bits RTCMODE and RTCSSELx
15 
*
16 
*
17 
********************************************************************/
18 
 
19 
#ifndef __MSP430F5637
20 
#define __MSP430F5637
21 
 
22 
#ifdef __cplusplus
23 
extern "C" {
24 
#endif
25 
 
26 
 
27 
/*----------------------------------------------------------------------------*/
28 
/* PERIPHERAL FILE MAP                                                        */
29 
/*----------------------------------------------------------------------------*/
30 
 
31 
/* External references resolved by a device-specific linker command file */
32 
#define SFR_8BIT(address)   extern volatile unsigned char address
33 
#define SFR_16BIT(address)  extern volatile unsigned int address
34 
//#define SFR_20BIT(address)  extern volatile unsigned int address
35 
typedef void (* __SFR_FARPTR)();
36 
#define SFR_20BIT(address) extern __SFR_FARPTR address
37 
#define SFR_32BIT(address)  extern volatile unsigned long address
38 
 
39 
 
40 
 
41 
/************************************************************
42 
* STANDARD BITS
43 
************************************************************/
44 
 
45 
#define BIT0                   (0x0001)
46 
#define BIT1                   (0x0002)
47 
#define BIT2                   (0x0004)
48 
#define BIT3                   (0x0008)
49 
#define BIT4                   (0x0010)
50 
#define BIT5                   (0x0020)
51 
#define BIT6                   (0x0040)
52 
#define BIT7                   (0x0080)
53 
#define BIT8                   (0x0100)
54 
#define BIT9                   (0x0200)
55 
#define BITA                   (0x0400)
56 
#define BITB                   (0x0800)
57 
#define BITC                   (0x1000)
58 
#define BITD                   (0x2000)
59 
#define BITE                   (0x4000)
60 
#define BITF                   (0x8000)
61 
 
62 
/************************************************************
63 
* STATUS REGISTER BITS
64 
************************************************************/
65 
 
66 
#define C                      (0x0001)
67 
#define Z                      (0x0002)
68 
#define N                      (0x0004)
69 
#define V                      (0x0100)
70 
#define GIE                    (0x0008)
71 
#define CPUOFF                 (0x0010)
72 
#define OSCOFF                 (0x0020)
73 
#define SCG0                   (0x0040)
74 
#define SCG1                   (0x0080)
75 
 
76 
/* Low Power Modes coded with Bits 4-7 in SR */
77 
 
78 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
79 
#define LPM0                   (CPUOFF)
80 
#define LPM1                   (SCG0+CPUOFF)
81 
#define LPM2                   (SCG1+CPUOFF)
82 
#define LPM3                   (SCG1+SCG0+CPUOFF)
83 
#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
84 
/* End #defines for assembler */
85 
 
86 
#else /* Begin #defines for C */
87 
#define LPM0_bits              (CPUOFF)
88 
#define LPM1_bits              (SCG0+CPUOFF)
89 
#define LPM2_bits              (SCG1+CPUOFF)
90 
#define LPM3_bits              (SCG1+SCG0+CPUOFF)
91 
#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
92 
 
93 
#include "in430.h"
94 
 
95 
#define LPM0         _bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
96 
#define LPM0_EXIT    _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
97 
#define LPM1         _bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
98 
#define LPM1_EXIT    _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
99 
#define LPM2         _bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
100 
#define LPM2_EXIT    _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
101 
#define LPM3         _bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
102 
#define LPM3_EXIT    _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
103 
#define LPM4         _bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
104 
#define LPM4_EXIT    _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
105 
#endif /* End #defines for C */
106 
 
107 
/************************************************************
108 
* CPU
109 
************************************************************/
110 
#define __MSP430_HAS_MSP430XV2_CPU__                /* Definition to show that it has MSP430XV2 CPU */
111 
 
112 
/************************************************************
113 
* PERIPHERAL FILE MAP
114 
************************************************************/
115 
 
116 
/************************************************************
117 
* ADC12 PLUS
118 
************************************************************/
119 
#define __MSP430_HAS_ADC12_PLUS__                /* Definition to show that Module is available */
120 
#define __MSP430_BASEADDRESS_ADC12_PLUS__ 0x0700
121 
 
122 
SFR_16BIT(ADC12CTL0);                         /* ADC12+ Control 0 */
123 
SFR_8BIT(ADC12CTL0_L);                        /* ADC12+ Control 0 */
124 
SFR_8BIT(ADC12CTL0_H);                        /* ADC12+ Control 0 */
125 
SFR_16BIT(ADC12CTL1);                         /* ADC12+ Control 1 */
126 
SFR_8BIT(ADC12CTL1_L);                        /* ADC12+ Control 1 */
127 
SFR_8BIT(ADC12CTL1_H);                        /* ADC12+ Control 1 */
128 
SFR_16BIT(ADC12CTL2);                         /* ADC12+ Control 2 */
129 
SFR_8BIT(ADC12CTL2_L);                        /* ADC12+ Control 2 */
130 
SFR_8BIT(ADC12CTL2_H);                        /* ADC12+ Control 2 */
131 
SFR_16BIT(ADC12IFG);                          /* ADC12+ Interrupt Flag */
132 
SFR_8BIT(ADC12IFG_L);                         /* ADC12+ Interrupt Flag */
133 
SFR_8BIT(ADC12IFG_H);                         /* ADC12+ Interrupt Flag */
134 
SFR_16BIT(ADC12IE);                           /* ADC12+ Interrupt Enable */
135 
SFR_8BIT(ADC12IE_L);                          /* ADC12+ Interrupt Enable */
136 
SFR_8BIT(ADC12IE_H);                          /* ADC12+ Interrupt Enable */
137 
SFR_16BIT(ADC12IV);                           /* ADC12+ Interrupt Vector Word */
138 
SFR_8BIT(ADC12IV_L);                          /* ADC12+ Interrupt Vector Word */
139 
SFR_8BIT(ADC12IV_H);                          /* ADC12+ Interrupt Vector Word */
140 
 
141 
SFR_16BIT(ADC12MEM0);                         /* ADC12 Conversion Memory 0 */
142 
SFR_8BIT(ADC12MEM0_L);                        /* ADC12 Conversion Memory 0 */
143 
SFR_8BIT(ADC12MEM0_H);                        /* ADC12 Conversion Memory 0 */
144 
SFR_16BIT(ADC12MEM1);                         /* ADC12 Conversion Memory 1 */
145 
SFR_8BIT(ADC12MEM1_L);                        /* ADC12 Conversion Memory 1 */
146 
SFR_8BIT(ADC12MEM1_H);                        /* ADC12 Conversion Memory 1 */
147 
SFR_16BIT(ADC12MEM2);                         /* ADC12 Conversion Memory 2 */
148 
SFR_8BIT(ADC12MEM2_L);                        /* ADC12 Conversion Memory 2 */
149 
SFR_8BIT(ADC12MEM2_H);                        /* ADC12 Conversion Memory 2 */
150 
SFR_16BIT(ADC12MEM3);                         /* ADC12 Conversion Memory 3 */
151 
SFR_8BIT(ADC12MEM3_L);                        /* ADC12 Conversion Memory 3 */
152 
SFR_8BIT(ADC12MEM3_H);                        /* ADC12 Conversion Memory 3 */
153 
SFR_16BIT(ADC12MEM4);                         /* ADC12 Conversion Memory 4 */
154 
SFR_8BIT(ADC12MEM4_L);                        /* ADC12 Conversion Memory 4 */
155 
SFR_8BIT(ADC12MEM4_H);                        /* ADC12 Conversion Memory 4 */
156 
SFR_16BIT(ADC12MEM5);                         /* ADC12 Conversion Memory 5 */
157 
SFR_8BIT(ADC12MEM5_L);                        /* ADC12 Conversion Memory 5 */
158 
SFR_8BIT(ADC12MEM5_H);                        /* ADC12 Conversion Memory 5 */
159 
SFR_16BIT(ADC12MEM6);                         /* ADC12 Conversion Memory 6 */
160 
SFR_8BIT(ADC12MEM6_L);                        /* ADC12 Conversion Memory 6 */
161 
SFR_8BIT(ADC12MEM6_H);                        /* ADC12 Conversion Memory 6 */
162 
SFR_16BIT(ADC12MEM7);                         /* ADC12 Conversion Memory 7 */
163 
SFR_8BIT(ADC12MEM7_L);                        /* ADC12 Conversion Memory 7 */
164 
SFR_8BIT(ADC12MEM7_H);                        /* ADC12 Conversion Memory 7 */
165 
SFR_16BIT(ADC12MEM8);                         /* ADC12 Conversion Memory 8 */
166 
SFR_8BIT(ADC12MEM8_L);                        /* ADC12 Conversion Memory 8 */
167 
SFR_8BIT(ADC12MEM8_H);                        /* ADC12 Conversion Memory 8 */
168 
SFR_16BIT(ADC12MEM9);                         /* ADC12 Conversion Memory 9 */
169 
SFR_8BIT(ADC12MEM9_L);                        /* ADC12 Conversion Memory 9 */
170 
SFR_8BIT(ADC12MEM9_H);                        /* ADC12 Conversion Memory 9 */
171 
SFR_16BIT(ADC12MEM10);                        /* ADC12 Conversion Memory 10 */
172 
SFR_8BIT(ADC12MEM10_L);                       /* ADC12 Conversion Memory 10 */
173 
SFR_8BIT(ADC12MEM10_H);                       /* ADC12 Conversion Memory 10 */
174 
SFR_16BIT(ADC12MEM11);                        /* ADC12 Conversion Memory 11 */
175 
SFR_8BIT(ADC12MEM11_L);                       /* ADC12 Conversion Memory 11 */
176 
SFR_8BIT(ADC12MEM11_H);                       /* ADC12 Conversion Memory 11 */
177 
SFR_16BIT(ADC12MEM12);                        /* ADC12 Conversion Memory 12 */
178 
SFR_8BIT(ADC12MEM12_L);                       /* ADC12 Conversion Memory 12 */
179 
SFR_8BIT(ADC12MEM12_H);                       /* ADC12 Conversion Memory 12 */
180 
SFR_16BIT(ADC12MEM13);                        /* ADC12 Conversion Memory 13 */
181 
SFR_8BIT(ADC12MEM13_L);                       /* ADC12 Conversion Memory 13 */
182 
SFR_8BIT(ADC12MEM13_H);                       /* ADC12 Conversion Memory 13 */
183 
SFR_16BIT(ADC12MEM14);                        /* ADC12 Conversion Memory 14 */
184 
SFR_8BIT(ADC12MEM14_L);                       /* ADC12 Conversion Memory 14 */
185 
SFR_8BIT(ADC12MEM14_H);                       /* ADC12 Conversion Memory 14 */
186 
SFR_16BIT(ADC12MEM15);                        /* ADC12 Conversion Memory 15 */
187 
SFR_8BIT(ADC12MEM15_L);                       /* ADC12 Conversion Memory 15 */
188 
SFR_8BIT(ADC12MEM15_H);                       /* ADC12 Conversion Memory 15 */
189 
#define ADC12MEM_              ADC12MEM       /* ADC12 Conversion Memory */
190 
#ifdef __ASM_HEADER__
191 
#define ADC12MEM               ADC12MEM0      /* ADC12 Conversion Memory (for assembler) */
192 
#else
193 
#define ADC12MEM               ((int*)        &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
194 
#endif
195 
 
196 
SFR_8BIT(ADC12MCTL0);                         /* ADC12 Memory Control 0 */
197 
SFR_8BIT(ADC12MCTL1);                         /* ADC12 Memory Control 1 */
198 
SFR_8BIT(ADC12MCTL2);                         /* ADC12 Memory Control 2 */
199 
SFR_8BIT(ADC12MCTL3);                         /* ADC12 Memory Control 3 */
200 
SFR_8BIT(ADC12MCTL4);                         /* ADC12 Memory Control 4 */
201 
SFR_8BIT(ADC12MCTL5);                         /* ADC12 Memory Control 5 */
202 
SFR_8BIT(ADC12MCTL6);                         /* ADC12 Memory Control 6 */
203 
SFR_8BIT(ADC12MCTL7);                         /* ADC12 Memory Control 7 */
204 
SFR_8BIT(ADC12MCTL8);                         /* ADC12 Memory Control 8 */
205 
SFR_8BIT(ADC12MCTL9);                         /* ADC12 Memory Control 9 */
206 
SFR_8BIT(ADC12MCTL10);                        /* ADC12 Memory Control 10 */
207 
SFR_8BIT(ADC12MCTL11);                        /* ADC12 Memory Control 11 */
208 
SFR_8BIT(ADC12MCTL12);                        /* ADC12 Memory Control 12 */
209 
SFR_8BIT(ADC12MCTL13);                        /* ADC12 Memory Control 13 */
210 
SFR_8BIT(ADC12MCTL14);                        /* ADC12 Memory Control 14 */
211 
SFR_8BIT(ADC12MCTL15);                        /* ADC12 Memory Control 15 */
212 
#define ADC12MCTL_             ADC12MCTL      /* ADC12 Memory Control */
213 
#ifdef __ASM_HEADER__
214 
#define ADC12MCTL              ADC12MCTL0     /* ADC12 Memory Control (for assembler) */
215 
#else
216 
#define ADC12MCTL              ((char*)       &ADC12MCTL0) /* ADC12 Memory Control (for C) */
217 
#endif
218 
 
219 
/* ADC12CTL0 Control Bits */
220 
#define ADC12SC                (0x0001)       /* ADC12 Start Conversion */
221 
#define ADC12ENC               (0x0002)       /* ADC12 Enable Conversion */
222 
#define ADC12TOVIE             (0x0004)       /* ADC12 Timer Overflow interrupt enable */
223 
#define ADC12OVIE              (0x0008)       /* ADC12 Overflow interrupt enable */
224 
#define ADC12ON                (0x0010)       /* ADC12 On/enable */
225 
#define ADC12REFON             (0x0020)       /* ADC12 Reference on */
226 
#define ADC12REF2_5V           (0x0040)       /* ADC12 Ref 0:1.5V / 1:2.5V */
227 
#define ADC12MSC               (0x0080)       /* ADC12 Multiple SampleConversion */
228 
#define ADC12SHT00             (0x0100)       /* ADC12 Sample Hold 0 Select Bit: 0 */
229 
#define ADC12SHT01             (0x0200)       /* ADC12 Sample Hold 0 Select Bit: 1 */
230 
#define ADC12SHT02             (0x0400)       /* ADC12 Sample Hold 0 Select Bit: 2 */
231 
#define ADC12SHT03             (0x0800)       /* ADC12 Sample Hold 0 Select Bit: 3 */
232 
#define ADC12SHT10             (0x1000)       /* ADC12 Sample Hold 1 Select Bit: 0 */
233 
#define ADC12SHT11             (0x2000)       /* ADC12 Sample Hold 1 Select Bit: 1 */
234 
#define ADC12SHT12             (0x4000)       /* ADC12 Sample Hold 1 Select Bit: 2 */
235 
#define ADC12SHT13             (0x8000)       /* ADC12 Sample Hold 1 Select Bit: 3 */
236 
 
237 
/* ADC12CTL0 Control Bits */
238 
#define ADC12SC_L              (0x0001)       /* ADC12 Start Conversion */
239 
#define ADC12ENC_L             (0x0002)       /* ADC12 Enable Conversion */
240 
#define ADC12TOVIE_L           (0x0004)       /* ADC12 Timer Overflow interrupt enable */
241 
#define ADC12OVIE_L            (0x0008)       /* ADC12 Overflow interrupt enable */
242 
#define ADC12ON_L              (0x0010)       /* ADC12 On/enable */
243 
#define ADC12REFON_L           (0x0020)       /* ADC12 Reference on */
244 
#define ADC12REF2_5V_L         (0x0040)       /* ADC12 Ref 0:1.5V / 1:2.5V */
245 
#define ADC12MSC_L             (0x0080)       /* ADC12 Multiple SampleConversion */
246 
 
247 
/* ADC12CTL0 Control Bits */
248 
#define ADC12SHT00_H           (0x0001)       /* ADC12 Sample Hold 0 Select Bit: 0 */
249 
#define ADC12SHT01_H           (0x0002)       /* ADC12 Sample Hold 0 Select Bit: 1 */
250 
#define ADC12SHT02_H           (0x0004)       /* ADC12 Sample Hold 0 Select Bit: 2 */
251 
#define ADC12SHT03_H           (0x0008)       /* ADC12 Sample Hold 0 Select Bit: 3 */
252 
#define ADC12SHT10_H           (0x0010)       /* ADC12 Sample Hold 1 Select Bit: 0 */
253 
#define ADC12SHT11_H           (0x0020)       /* ADC12 Sample Hold 1 Select Bit: 1 */
254 
#define ADC12SHT12_H           (0x0040)       /* ADC12 Sample Hold 1 Select Bit: 2 */
255 
#define ADC12SHT13_H           (0x0080)       /* ADC12 Sample Hold 1 Select Bit: 3 */
256 
 
257 
#define ADC12SHT0_0            (0*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 0 */
258 
#define ADC12SHT0_1            (1*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 1 */
259 
#define ADC12SHT0_2            (2*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 2 */
260 
#define ADC12SHT0_3            (3*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 3 */
261 
#define ADC12SHT0_4            (4*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 4 */
262 
#define ADC12SHT0_5            (5*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 5 */
263 
#define ADC12SHT0_6            (6*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 6 */
264 
#define ADC12SHT0_7            (7*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 7 */
265 
#define ADC12SHT0_8            (8*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 8 */
266 
#define ADC12SHT0_9            (9*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 9 */
267 
#define ADC12SHT0_10           (10*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 10 */
268 
#define ADC12SHT0_11           (11*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 11 */
269 
#define ADC12SHT0_12           (12*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 12 */
270 
#define ADC12SHT0_13           (13*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 13 */
271 
#define ADC12SHT0_14           (14*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 14 */
272 
#define ADC12SHT0_15           (15*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 15 */
273 
 
274 
#define ADC12SHT1_0            (0*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 0 */
275 
#define ADC12SHT1_1            (1*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 1 */
276 
#define ADC12SHT1_2            (2*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 2 */
277 
#define ADC12SHT1_3            (3*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 3 */
278 
#define ADC12SHT1_4            (4*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 4 */
279 
#define ADC12SHT1_5            (5*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 5 */
280 
#define ADC12SHT1_6            (6*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 6 */
281 
#define ADC12SHT1_7            (7*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 7 */
282 
#define ADC12SHT1_8            (8*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 8 */
283 
#define ADC12SHT1_9            (9*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 9 */
284 
#define ADC12SHT1_10           (10*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 10 */
285 
#define ADC12SHT1_11           (11*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 11 */
286 
#define ADC12SHT1_12           (12*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 12 */
287 
#define ADC12SHT1_13           (13*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 13 */
288 
#define ADC12SHT1_14           (14*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 14 */
289 
#define ADC12SHT1_15           (15*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 15 */
290 
 
291 
/* ADC12CTL1 Control Bits */
292 
#define ADC12BUSY              (0x0001)       /* ADC12 Busy */
293 
#define ADC12CONSEQ0           (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
294 
#define ADC12CONSEQ1           (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
295 
#define ADC12SSEL0             (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
296 
#define ADC12SSEL1             (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
297 
#define ADC12DIV0              (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
298 
#define ADC12DIV1              (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
299 
#define ADC12DIV2              (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
300 
#define ADC12ISSH              (0x0100)       /* ADC12 Invert Sample Hold Signal */
301 
#define ADC12SHP               (0x0200)       /* ADC12 Sample/Hold Pulse Mode */
302 
#define ADC12SHS0              (0x0400)       /* ADC12 Sample/Hold Source Bit: 0 */
303 
#define ADC12SHS1              (0x0800)       /* ADC12 Sample/Hold Source Bit: 1 */
304 
#define ADC12CSTARTADD0        (0x1000)       /* ADC12 Conversion Start Address Bit: 0 */
305 
#define ADC12CSTARTADD1        (0x2000)       /* ADC12 Conversion Start Address Bit: 1 */
306 
#define ADC12CSTARTADD2        (0x4000)       /* ADC12 Conversion Start Address Bit: 2 */
307 
#define ADC12CSTARTADD3        (0x8000)       /* ADC12 Conversion Start Address Bit: 3 */
308 
 
309 
/* ADC12CTL1 Control Bits */
310 
#define ADC12BUSY_L            (0x0001)       /* ADC12 Busy */
311 
#define ADC12CONSEQ0_L         (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
312 
#define ADC12CONSEQ1_L         (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
313 
#define ADC12SSEL0_L           (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
314 
#define ADC12SSEL1_L           (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
315 
#define ADC12DIV0_L            (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
316 
#define ADC12DIV1_L            (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
317 
#define ADC12DIV2_L            (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
318 
 
319 
/* ADC12CTL1 Control Bits */
320 
#define ADC12ISSH_H            (0x0001)       /* ADC12 Invert Sample Hold Signal */
321 
#define ADC12SHP_H             (0x0002)       /* ADC12 Sample/Hold Pulse Mode */
322 
#define ADC12SHS0_H            (0x0004)       /* ADC12 Sample/Hold Source Bit: 0 */
323 
#define ADC12SHS1_H            (0x0008)       /* ADC12 Sample/Hold Source Bit: 1 */
324 
#define ADC12CSTARTADD0_H      (0x0010)       /* ADC12 Conversion Start Address Bit: 0 */
325 
#define ADC12CSTARTADD1_H      (0x0020)       /* ADC12 Conversion Start Address Bit: 1 */
326 
#define ADC12CSTARTADD2_H      (0x0040)       /* ADC12 Conversion Start Address Bit: 2 */
327 
#define ADC12CSTARTADD3_H      (0x0080)       /* ADC12 Conversion Start Address Bit: 3 */
328 
 
329 
#define ADC12CONSEQ_0          (0*2u)         /* ADC12 Conversion Sequence Select: 0 */
330 
#define ADC12CONSEQ_1          (1*2u)         /* ADC12 Conversion Sequence Select: 1 */
331 
#define ADC12CONSEQ_2          (2*2u)         /* ADC12 Conversion Sequence Select: 2 */
332 
#define ADC12CONSEQ_3          (3*2u)         /* ADC12 Conversion Sequence Select: 3 */
333 
 
334 
#define ADC12SSEL_0            (0*8u)         /* ADC12 Clock Source Select: 0 */
335 
#define ADC12SSEL_1            (1*8u)         /* ADC12 Clock Source Select: 1 */
336 
#define ADC12SSEL_2            (2*8u)         /* ADC12 Clock Source Select: 2 */
337 
#define ADC12SSEL_3            (3*8u)         /* ADC12 Clock Source Select: 3 */
338 
 
339 
#define ADC12DIV_0             (0*0x20u)      /* ADC12 Clock Divider Select: 0 */
340 
#define ADC12DIV_1             (1*0x20u)      /* ADC12 Clock Divider Select: 1 */
341 
#define ADC12DIV_2             (2*0x20u)      /* ADC12 Clock Divider Select: 2 */
342 
#define ADC12DIV_3             (3*0x20u)      /* ADC12 Clock Divider Select: 3 */
343 
#define ADC12DIV_4             (4*0x20u)      /* ADC12 Clock Divider Select: 4 */
344 
#define ADC12DIV_5             (5*0x20u)      /* ADC12 Clock Divider Select: 5 */
345 
#define ADC12DIV_6             (6*0x20u)      /* ADC12 Clock Divider Select: 6 */
346 
#define ADC12DIV_7             (7*0x20u)      /* ADC12 Clock Divider Select: 7 */
347 
 
348 
#define ADC12SHS_0             (0*0x400u)     /* ADC12 Sample/Hold Source: 0 */
349 
#define ADC12SHS_1             (1*0x400u)     /* ADC12 Sample/Hold Source: 1 */
350 
#define ADC12SHS_2             (2*0x400u)     /* ADC12 Sample/Hold Source: 2 */
351 
#define ADC12SHS_3             (3*0x400u)     /* ADC12 Sample/Hold Source: 3 */
352 
 
353 
#define ADC12CSTARTADD_0       (0*0x1000u)    /* ADC12 Conversion Start Address: 0 */
354 
#define ADC12CSTARTADD_1       (1*0x1000u)    /* ADC12 Conversion Start Address: 1 */
355 
#define ADC12CSTARTADD_2       (2*0x1000u)    /* ADC12 Conversion Start Address: 2 */
356 
#define ADC12CSTARTADD_3       (3*0x1000u)    /* ADC12 Conversion Start Address: 3 */
357 
#define ADC12CSTARTADD_4       (4*0x1000u)    /* ADC12 Conversion Start Address: 4 */
358 
#define ADC12CSTARTADD_5       (5*0x1000u)    /* ADC12 Conversion Start Address: 5 */
359 
#define ADC12CSTARTADD_6       (6*0x1000u)    /* ADC12 Conversion Start Address: 6 */
360 
#define ADC12CSTARTADD_7       (7*0x1000u)    /* ADC12 Conversion Start Address: 7 */
361 
#define ADC12CSTARTADD_8       (8*0x1000u)    /* ADC12 Conversion Start Address: 8 */
362 
#define ADC12CSTARTADD_9       (9*0x1000u)    /* ADC12 Conversion Start Address: 9 */
363 
#define ADC12CSTARTADD_10      (10*0x1000u)   /* ADC12 Conversion Start Address: 10 */
364 
#define ADC12CSTARTADD_11      (11*0x1000u)   /* ADC12 Conversion Start Address: 11 */
365 
#define ADC12CSTARTADD_12      (12*0x1000u)   /* ADC12 Conversion Start Address: 12 */
366 
#define ADC12CSTARTADD_13      (13*0x1000u)   /* ADC12 Conversion Start Address: 13 */
367 
#define ADC12CSTARTADD_14      (14*0x1000u)   /* ADC12 Conversion Start Address: 14 */
368 
#define ADC12CSTARTADD_15      (15*0x1000u)   /* ADC12 Conversion Start Address: 15 */
369 
 
370 
/* ADC12CTL2 Control Bits */
371 
#define ADC12REFBURST          (0x0001)       /* ADC12+ Reference Burst */
372 
#define ADC12REFOUT            (0x0002)       /* ADC12+ Reference Out */
373 
#define ADC12SR                (0x0004)       /* ADC12+ Sampling Rate */
374 
#define ADC12DF                (0x0008)       /* ADC12+ Data Format */
375 
#define ADC12RES0              (0x0010)       /* ADC12+ Resolution Bit: 0 */
376 
#define ADC12RES1              (0x0020)       /* ADC12+ Resolution Bit: 1 */
377 
#define ADC12TCOFF             (0x0080)       /* ADC12+ Temperature Sensor Off */
378 
#define ADC12PDIV              (0x0100)       /* ADC12+ predivider 0:/1   1:/4 */
379 
 
380 
/* ADC12CTL2 Control Bits */
381 
#define ADC12REFBURST_L        (0x0001)       /* ADC12+ Reference Burst */
382 
#define ADC12REFOUT_L          (0x0002)       /* ADC12+ Reference Out */
383 
#define ADC12SR_L              (0x0004)       /* ADC12+ Sampling Rate */
384 
#define ADC12DF_L              (0x0008)       /* ADC12+ Data Format */
385 
#define ADC12RES0_L            (0x0010)       /* ADC12+ Resolution Bit: 0 */
386 
#define ADC12RES1_L            (0x0020)       /* ADC12+ Resolution Bit: 1 */
387 
#define ADC12TCOFF_L           (0x0080)       /* ADC12+ Temperature Sensor Off */
388 
 
389 
/* ADC12CTL2 Control Bits */
390 
#define ADC12PDIV_H            (0x0001)       /* ADC12+ predivider 0:/1   1:/4 */
391 
 
392 
#define ADC12RES_0             (0x0000)       /* ADC12+ Resolution : 8 Bit */
393 
#define ADC12RES_1             (0x0010)       /* ADC12+ Resolution : 10 Bit */
394 
#define ADC12RES_2             (0x0020)       /* ADC12+ Resolution : 12 Bit */
395 
#define ADC12RES_3             (0x0030)       /* ADC12+ Resolution : reserved */
396 
 
397 
/* ADC12MCTLx Control Bits */
398 
#define ADC12INCH0             (0x0001)       /* ADC12 Input Channel Select Bit 0 */
399 
#define ADC12INCH1             (0x0002)       /* ADC12 Input Channel Select Bit 1 */
400 
#define ADC12INCH2             (0x0004)       /* ADC12 Input Channel Select Bit 2 */
401 
#define ADC12INCH3             (0x0008)       /* ADC12 Input Channel Select Bit 3 */
402 
#define ADC12SREF0             (0x0010)       /* ADC12 Select Reference Bit 0 */
403 
#define ADC12SREF1             (0x0020)       /* ADC12 Select Reference Bit 1 */
404 
#define ADC12SREF2             (0x0040)       /* ADC12 Select Reference Bit 2 */
405 
#define ADC12EOS               (0x0080)       /* ADC12 End of Sequence */
406 
 
407 
#define ADC12INCH_0            (0x0000)       /* ADC12 Input Channel 0 */
408 
#define ADC12INCH_1            (0x0001)       /* ADC12 Input Channel 1 */
409 
#define ADC12INCH_2            (0x0002)       /* ADC12 Input Channel 2 */
410 
#define ADC12INCH_3            (0x0003)       /* ADC12 Input Channel 3 */
411 
#define ADC12INCH_4            (0x0004)       /* ADC12 Input Channel 4 */
412 
#define ADC12INCH_5            (0x0005)       /* ADC12 Input Channel 5 */
413 
#define ADC12INCH_6            (0x0006)       /* ADC12 Input Channel 6 */
414 
#define ADC12INCH_7            (0x0007)       /* ADC12 Input Channel 7 */
415 
#define ADC12INCH_8            (0x0008)       /* ADC12 Input Channel 8 */
416 
#define ADC12INCH_9            (0x0009)       /* ADC12 Input Channel 9 */
417 
#define ADC12INCH_10           (0x000A)       /* ADC12 Input Channel 10 */
418 
#define ADC12INCH_11           (0x000B)       /* ADC12 Input Channel 11 */
419 
#define ADC12INCH_12           (0x000C)       /* ADC12 Input Channel 12 */
420 
#define ADC12INCH_13           (0x000D)       /* ADC12 Input Channel 13 */
421 
#define ADC12INCH_14           (0x000E)       /* ADC12 Input Channel 14 */
422 
#define ADC12INCH_15           (0x000F)       /* ADC12 Input Channel 15 */
423 
 
424 
#define ADC12SREF_0            (0*0x10u)      /* ADC12 Select Reference 0 */
425 
#define ADC12SREF_1            (1*0x10u)      /* ADC12 Select Reference 1 */
426 
#define ADC12SREF_2            (2*0x10u)      /* ADC12 Select Reference 2 */
427 
#define ADC12SREF_3            (3*0x10u)      /* ADC12 Select Reference 3 */
428 
#define ADC12SREF_4            (4*0x10u)      /* ADC12 Select Reference 4 */
429 
#define ADC12SREF_5            (5*0x10u)      /* ADC12 Select Reference 5 */
430 
#define ADC12SREF_6            (6*0x10u)      /* ADC12 Select Reference 6 */
431 
#define ADC12SREF_7            (7*0x10u)      /* ADC12 Select Reference 7 */
432 
 
433 
#define ADC12IE0               (0x0001)       /* ADC12 Memory 0      Interrupt Enable */
434 
#define ADC12IE1               (0x0002)       /* ADC12 Memory 1      Interrupt Enable */
435 
#define ADC12IE2               (0x0004)       /* ADC12 Memory 2      Interrupt Enable */
436 
#define ADC12IE3               (0x0008)       /* ADC12 Memory 3      Interrupt Enable */
437 
#define ADC12IE4               (0x0010)       /* ADC12 Memory 4      Interrupt Enable */
438 
#define ADC12IE5               (0x0020)       /* ADC12 Memory 5      Interrupt Enable */
439 
#define ADC12IE6               (0x0040)       /* ADC12 Memory 6      Interrupt Enable */
440 
#define ADC12IE7               (0x0080)       /* ADC12 Memory 7      Interrupt Enable */
441 
#define ADC12IE8               (0x0100)       /* ADC12 Memory 8      Interrupt Enable */
442 
#define ADC12IE9               (0x0200)       /* ADC12 Memory 9      Interrupt Enable */
443 
#define ADC12IE10              (0x0400)       /* ADC12 Memory 10      Interrupt Enable */
444 
#define ADC12IE11              (0x0800)       /* ADC12 Memory 11      Interrupt Enable */
445 
#define ADC12IE12              (0x1000)       /* ADC12 Memory 12      Interrupt Enable */
446 
#define ADC12IE13              (0x2000)       /* ADC12 Memory 13      Interrupt Enable */
447 
#define ADC12IE14              (0x4000)       /* ADC12 Memory 14      Interrupt Enable */
448 
#define ADC12IE15              (0x8000)       /* ADC12 Memory 15      Interrupt Enable */
449 
 
450 
#define ADC12IE0_L             (0x0001)       /* ADC12 Memory 0      Interrupt Enable */
451 
#define ADC12IE1_L             (0x0002)       /* ADC12 Memory 1      Interrupt Enable */
452 
#define ADC12IE2_L             (0x0004)       /* ADC12 Memory 2      Interrupt Enable */
453 
#define ADC12IE3_L             (0x0008)       /* ADC12 Memory 3      Interrupt Enable */
454 
#define ADC12IE4_L             (0x0010)       /* ADC12 Memory 4      Interrupt Enable */
455 
#define ADC12IE5_L             (0x0020)       /* ADC12 Memory 5      Interrupt Enable */
456 
#define ADC12IE6_L             (0x0040)       /* ADC12 Memory 6      Interrupt Enable */
457 
#define ADC12IE7_L             (0x0080)       /* ADC12 Memory 7      Interrupt Enable */
458 
 
459 
#define ADC12IE8_H             (0x0001)       /* ADC12 Memory 8      Interrupt Enable */
460 
#define ADC12IE9_H             (0x0002)       /* ADC12 Memory 9      Interrupt Enable */
461 
#define ADC12IE10_H            (0x0004)       /* ADC12 Memory 10      Interrupt Enable */
462 
#define ADC12IE11_H            (0x0008)       /* ADC12 Memory 11      Interrupt Enable */
463 
#define ADC12IE12_H            (0x0010)       /* ADC12 Memory 12      Interrupt Enable */
464 
#define ADC12IE13_H            (0x0020)       /* ADC12 Memory 13      Interrupt Enable */
465 
#define ADC12IE14_H            (0x0040)       /* ADC12 Memory 14      Interrupt Enable */
466 
#define ADC12IE15_H            (0x0080)       /* ADC12 Memory 15      Interrupt Enable */
467 
 
468 
#define ADC12IFG0              (0x0001)       /* ADC12 Memory 0      Interrupt Flag */
469 
#define ADC12IFG1              (0x0002)       /* ADC12 Memory 1      Interrupt Flag */
470 
#define ADC12IFG2              (0x0004)       /* ADC12 Memory 2      Interrupt Flag */
471 
#define ADC12IFG3              (0x0008)       /* ADC12 Memory 3      Interrupt Flag */
472 
#define ADC12IFG4              (0x0010)       /* ADC12 Memory 4      Interrupt Flag */
473 
#define ADC12IFG5              (0x0020)       /* ADC12 Memory 5      Interrupt Flag */
474 
#define ADC12IFG6              (0x0040)       /* ADC12 Memory 6      Interrupt Flag */
475 
#define ADC12IFG7              (0x0080)       /* ADC12 Memory 7      Interrupt Flag */
476 
#define ADC12IFG8              (0x0100)       /* ADC12 Memory 8      Interrupt Flag */
477 
#define ADC12IFG9              (0x0200)       /* ADC12 Memory 9      Interrupt Flag */
478 
#define ADC12IFG10             (0x0400)       /* ADC12 Memory 10      Interrupt Flag */
479 
#define ADC12IFG11             (0x0800)       /* ADC12 Memory 11      Interrupt Flag */
480 
#define ADC12IFG12             (0x1000)       /* ADC12 Memory 12      Interrupt Flag */
481 
#define ADC12IFG13             (0x2000)       /* ADC12 Memory 13      Interrupt Flag */
482 
#define ADC12IFG14             (0x4000)       /* ADC12 Memory 14      Interrupt Flag */
483 
#define ADC12IFG15             (0x8000)       /* ADC12 Memory 15      Interrupt Flag */
484 
 
485 
#define ADC12IFG0_L            (0x0001)       /* ADC12 Memory 0      Interrupt Flag */
486 
#define ADC12IFG1_L            (0x0002)       /* ADC12 Memory 1      Interrupt Flag */
487 
#define ADC12IFG2_L            (0x0004)       /* ADC12 Memory 2      Interrupt Flag */
488 
#define ADC12IFG3_L            (0x0008)       /* ADC12 Memory 3      Interrupt Flag */
489 
#define ADC12IFG4_L            (0x0010)       /* ADC12 Memory 4      Interrupt Flag */
490 
#define ADC12IFG5_L            (0x0020)       /* ADC12 Memory 5      Interrupt Flag */
491 
#define ADC12IFG6_L            (0x0040)       /* ADC12 Memory 6      Interrupt Flag */
492 
#define ADC12IFG7_L            (0x0080)       /* ADC12 Memory 7      Interrupt Flag */
493 
 
494 
#define ADC12IFG8_H            (0x0001)       /* ADC12 Memory 8      Interrupt Flag */
495 
#define ADC12IFG9_H            (0x0002)       /* ADC12 Memory 9      Interrupt Flag */
496 
#define ADC12IFG10_H           (0x0004)       /* ADC12 Memory 10      Interrupt Flag */
497 
#define ADC12IFG11_H           (0x0008)       /* ADC12 Memory 11      Interrupt Flag */
498 
#define ADC12IFG12_H           (0x0010)       /* ADC12 Memory 12      Interrupt Flag */
499 
#define ADC12IFG13_H           (0x0020)       /* ADC12 Memory 13      Interrupt Flag */
500 
#define ADC12IFG14_H           (0x0040)       /* ADC12 Memory 14      Interrupt Flag */
501 
#define ADC12IFG15_H           (0x0080)       /* ADC12 Memory 15      Interrupt Flag */
502 
 
503 
/* ADC12IV Definitions */
504 
#define ADC12IV_NONE           (0x0000)       /* No Interrupt pending */
505 
#define ADC12IV_ADC12OVIFG     (0x0002)       /* ADC12OVIFG */
506 
#define ADC12IV_ADC12TOVIFG    (0x0004)       /* ADC12TOVIFG */
507 
#define ADC12IV_ADC12IFG0      (0x0006)       /* ADC12IFG0 */
508 
#define ADC12IV_ADC12IFG1      (0x0008)       /* ADC12IFG1 */
509 
#define ADC12IV_ADC12IFG2      (0x000A)       /* ADC12IFG2 */
510 
#define ADC12IV_ADC12IFG3      (0x000C)       /* ADC12IFG3 */
511 
#define ADC12IV_ADC12IFG4      (0x000E)       /* ADC12IFG4 */
512 
#define ADC12IV_ADC12IFG5      (0x0010)       /* ADC12IFG5 */
513 
#define ADC12IV_ADC12IFG6      (0x0012)       /* ADC12IFG6 */
514 
#define ADC12IV_ADC12IFG7      (0x0014)       /* ADC12IFG7 */
515 
#define ADC12IV_ADC12IFG8      (0x0016)       /* ADC12IFG8 */
516 
#define ADC12IV_ADC12IFG9      (0x0018)       /* ADC12IFG9 */
517 
#define ADC12IV_ADC12IFG10     (0x001A)       /* ADC12IFG10 */
518 
#define ADC12IV_ADC12IFG11     (0x001C)       /* ADC12IFG11 */
519 
#define ADC12IV_ADC12IFG12     (0x001E)       /* ADC12IFG12 */
520 
#define ADC12IV_ADC12IFG13     (0x0020)       /* ADC12IFG13 */
521 
#define ADC12IV_ADC12IFG14     (0x0022)       /* ADC12IFG14 */
522 
#define ADC12IV_ADC12IFG15     (0x0024)       /* ADC12IFG15 */
523 
 
524 
/*************************************************************
525 
* Backup RAM Module
526 
*************************************************************/
527 
#define __MSP430_HAS_BACKUP_RAM__                /* Definition to show that Module is available */
528 
#define __MSP430_BASEADDRESS_BACKUP_RAM__ 0x0480
529 
 
530 
SFR_16BIT(BAKMEM0);                           /* Battery Backup Memory 0 */
531 
SFR_8BIT(BAKMEM0_L);                          /* Battery Backup Memory 0 */
532 
SFR_8BIT(BAKMEM0_H);                          /* Battery Backup Memory 0 */
533 
SFR_16BIT(BAKMEM1);                           /* Battery Backup Memory 0 */
534 
SFR_8BIT(BAKMEM1_L);                          /* Battery Backup Memory 0 */
535 
SFR_8BIT(BAKMEM1_H);                          /* Battery Backup Memory 0 */
536 
SFR_16BIT(BAKMEM2);                           /* Battery Backup Memory 0 */
537 
SFR_8BIT(BAKMEM2_L);                          /* Battery Backup Memory 0 */
538 
SFR_8BIT(BAKMEM2_H);                          /* Battery Backup Memory 0 */
539 
SFR_16BIT(BAKMEM3);                           /* Battery Backup Memory 0 */
540 
SFR_8BIT(BAKMEM3_L);                          /* Battery Backup Memory 0 */
541 
SFR_8BIT(BAKMEM3_H);                          /* Battery Backup Memory 0 */
542 
 
543 
/*************************************************************
544 
* Battery Charger Module
545 
*************************************************************/
546 
#define __MSP430_HAS_BATTERY_CHARGER__                /* Definition to show that Module is available */
547 
#define __MSP430_BASEADDRESS_BATTERY_CHARGER__ 0x049C
548 
 
549 
SFR_16BIT(BAKCTL);                            /* Battery Backup Control */
550 
SFR_8BIT(BAKCTL_L);                           /* Battery Backup Control */
551 
SFR_8BIT(BAKCTL_H);                           /* Battery Backup Control */
552 
SFR_16BIT(BAKCHCTL);                          /* Battery Charger Control */
553 
SFR_8BIT(BAKCHCTL_L);                         /* Battery Charger Control */
554 
SFR_8BIT(BAKCHCTL_H);                         /* Battery Charger Control */
555 
 
556 
/* BAKCTL Control Bits */
557 
#define LOCKBAK                (0x0001)       /* Lock backup sub-system */
558 
#define BAKSW                  (0x0002)       /* Manual switch to battery backup supply */
559 
#define BAKADC                 (0x0004)       /* Battery backup supply to ADC. */
560 
#define BAKDIS                 (0x0008)       /* Disable backup supply switching. */
561 
 
562 
/* BAKCTL Control Bits */
563 
#define LOCKBAK_L              (0x0001)       /* Lock backup sub-system */
564 
#define BAKSW_L                (0x0002)       /* Manual switch to battery backup supply */
565 
#define BAKADC_L               (0x0004)       /* Battery backup supply to ADC. */
566 
#define BAKDIS_L               (0x0008)       /* Disable backup supply switching. */
567 
 
568 
/* BAKCTL Control Bits */
569 
 
570 
/* BAKCHCTL Control Bits */
571 
#define CHEN                   (0x0001)       /* Charger enable */
572 
#define CHC0                   (0x0002)       /* Charger charge current Bit 0 */
573 
#define CHC1                   (0x0004)       /* Charger charge current Bit 1 */
574 
#define CHV0                   (0x0010)       /* Charger end voltage Bit 0 */
575 
#define CHV1                   (0x0020)       /* Charger end voltage Bit 1 */
576 
 
577 
/* BAKCHCTL Control Bits */
578 
#define CHEN_L                 (0x0001)       /* Charger enable */
579 
#define CHC0_L                 (0x0002)       /* Charger charge current Bit 0 */
580 
#define CHC1_L                 (0x0004)       /* Charger charge current Bit 1 */
581 
#define CHV0_L                 (0x0010)       /* Charger end voltage Bit 0 */
582 
#define CHV1_L                 (0x0020)       /* Charger end voltage Bit 1 */
583 
 
584 
/* BAKCHCTL Control Bits */
585 
 
586 
#define CHPWD                  (0x6900)       /* Charger write password. */
587 
 
588 
/************************************************************
589 
* Comparator B
590 
************************************************************/
591 
#define __MSP430_HAS_COMPB__                  /* Definition to show that Module is available */
592 
#define __MSP430_BASEADDRESS_COMPB__ 0x08C0
593 
 
594 
SFR_16BIT(CBCTL0);                            /* Comparator B Control Register 0 */
595 
SFR_8BIT(CBCTL0_L);                           /* Comparator B Control Register 0 */
596 
SFR_8BIT(CBCTL0_H);                           /* Comparator B Control Register 0 */
597 
SFR_16BIT(CBCTL1);                            /* Comparator B Control Register 1 */
598 
SFR_8BIT(CBCTL1_L);                           /* Comparator B Control Register 1 */
599 
SFR_8BIT(CBCTL1_H);                           /* Comparator B Control Register 1 */
600 
SFR_16BIT(CBCTL2);                            /* Comparator B Control Register 2 */
601 
SFR_8BIT(CBCTL2_L);                           /* Comparator B Control Register 2 */
602 
SFR_8BIT(CBCTL2_H);                           /* Comparator B Control Register 2 */
603 
SFR_16BIT(CBCTL3);                            /* Comparator B Control Register 3 */
604 
SFR_8BIT(CBCTL3_L);                           /* Comparator B Control Register 3 */
605 
SFR_8BIT(CBCTL3_H);                           /* Comparator B Control Register 3 */
606 
SFR_16BIT(CBINT);                             /* Comparator B Interrupt Register */
607 
SFR_8BIT(CBINT_L);                            /* Comparator B Interrupt Register */
608 
SFR_8BIT(CBINT_H);                            /* Comparator B Interrupt Register */
609 
SFR_16BIT(CBIV);                              /* Comparator B Interrupt Vector Word */
610 
 
611 
/* CBCTL0 Control Bits */
612 
#define CBIPSEL0               (0x0001)       /* Comp. B Pos. Channel Input Select 0 */
613 
#define CBIPSEL1               (0x0002)       /* Comp. B Pos. Channel Input Select 1 */
614 
#define CBIPSEL2               (0x0004)       /* Comp. B Pos. Channel Input Select 2 */
615 
#define CBIPSEL3               (0x0008)       /* Comp. B Pos. Channel Input Select 3 */
616 
//#define RESERVED            (0x0010)  /* Comp. B */
617 
//#define RESERVED            (0x0020)  /* Comp. B */
618 
//#define RESERVED            (0x0040)  /* Comp. B */
619 
#define CBIPEN                 (0x0080)       /* Comp. B Pos. Channel Input Enable */
620 
#define CBIMSEL0               (0x0100)       /* Comp. B Neg. Channel Input Select 0 */
621 
#define CBIMSEL1               (0x0200)       /* Comp. B Neg. Channel Input Select 1 */
622 
#define CBIMSEL2               (0x0400)       /* Comp. B Neg. Channel Input Select 2 */
623 
#define CBIMSEL3               (0x0800)       /* Comp. B Neg. Channel Input Select 3 */
624 
//#define RESERVED            (0x1000)  /* Comp. B */
625 
//#define RESERVED            (0x2000)  /* Comp. B */
626 
//#define RESERVED            (0x4000)  /* Comp. B */
627 
#define CBIMEN                 (0x8000)       /* Comp. B Neg. Channel Input Enable */
628 
 
629 
/* CBCTL0 Control Bits */
630 
#define CBIPSEL0_L             (0x0001)       /* Comp. B Pos. Channel Input Select 0 */
631 
#define CBIPSEL1_L             (0x0002)       /* Comp. B Pos. Channel Input Select 1 */
632 
#define CBIPSEL2_L             (0x0004)       /* Comp. B Pos. Channel Input Select 2 */
633 
#define CBIPSEL3_L             (0x0008)       /* Comp. B Pos. Channel Input Select 3 */
634 
//#define RESERVED            (0x0010)  /* Comp. B */
635 
//#define RESERVED            (0x0020)  /* Comp. B */
636 
//#define RESERVED            (0x0040)  /* Comp. B */
637 
#define CBIPEN_L               (0x0080)       /* Comp. B Pos. Channel Input Enable */
638 
//#define RESERVED            (0x1000)  /* Comp. B */
639 
//#define RESERVED            (0x2000)  /* Comp. B */
640 
//#define RESERVED            (0x4000)  /* Comp. B */
641 
 
642 
/* CBCTL0 Control Bits */
643 
//#define RESERVED            (0x0010)  /* Comp. B */
644 
//#define RESERVED            (0x0020)  /* Comp. B */
645 
//#define RESERVED            (0x0040)  /* Comp. B */
646 
#define CBIMSEL0_H             (0x0001)       /* Comp. B Neg. Channel Input Select 0 */
647 
#define CBIMSEL1_H             (0x0002)       /* Comp. B Neg. Channel Input Select 1 */
648 
#define CBIMSEL2_H             (0x0004)       /* Comp. B Neg. Channel Input Select 2 */
649 
#define CBIMSEL3_H             (0x0008)       /* Comp. B Neg. Channel Input Select 3 */
650 
//#define RESERVED            (0x1000)  /* Comp. B */
651 
//#define RESERVED            (0x2000)  /* Comp. B */
652 
//#define RESERVED            (0x4000)  /* Comp. B */
653 
#define CBIMEN_H               (0x0080)       /* Comp. B Neg. Channel Input Enable */
654 
 
655 
#define CBIPSEL_0              (0x0000)       /* Comp. B V+ terminal Input Select: Channel 0 */
656 
#define CBIPSEL_1              (0x0001)       /* Comp. B V+ terminal Input Select: Channel 1 */
657 
#define CBIPSEL_2              (0x0002)       /* Comp. B V+ terminal Input Select: Channel 2 */
658 
#define CBIPSEL_3              (0x0003)       /* Comp. B V+ terminal Input Select: Channel 3 */
659 
#define CBIPSEL_4              (0x0004)       /* Comp. B V+ terminal Input Select: Channel 4 */
660 
#define CBIPSEL_5              (0x0005)       /* Comp. B V+ terminal Input Select: Channel 5 */
661 
#define CBIPSEL_6              (0x0006)       /* Comp. B V+ terminal Input Select: Channel 6 */
662 
#define CBIPSEL_7              (0x0007)       /* Comp. B V+ terminal Input Select: Channel 7 */
663 
#define CBIPSEL_8              (0x0008)       /* Comp. B V+ terminal Input Select: Channel 8 */
664 
#define CBIPSEL_9              (0x0009)       /* Comp. B V+ terminal Input Select: Channel 9 */
665 
#define CBIPSEL_10             (0x000A)       /* Comp. B V+ terminal Input Select: Channel 10 */
666 
#define CBIPSEL_11             (0x000B)       /* Comp. B V+ terminal Input Select: Channel 11 */
667 
#define CBIPSEL_12             (0x000C)       /* Comp. B V+ terminal Input Select: Channel 12 */
668 
#define CBIPSEL_13             (0x000D)       /* Comp. B V+ terminal Input Select: Channel 13 */
669 
#define CBIPSEL_14             (0x000E)       /* Comp. B V+ terminal Input Select: Channel 14 */
670 
#define CBIPSEL_15             (0x000F)       /* Comp. B V+ terminal Input Select: Channel 15 */
671 
 
672 
#define CBIMSEL_0              (0x0000)       /* Comp. B V- Terminal Input Select: Channel 0 */
673 
#define CBIMSEL_1              (0x0100)       /* Comp. B V- Terminal Input Select: Channel 1 */
674 
#define CBIMSEL_2              (0x0200)       /* Comp. B V- Terminal Input Select: Channel 2 */
675 
#define CBIMSEL_3              (0x0300)       /* Comp. B V- Terminal Input Select: Channel 3 */
676 
#define CBIMSEL_4              (0x0400)       /* Comp. B V- Terminal Input Select: Channel 4 */
677 
#define CBIMSEL_5              (0x0500)       /* Comp. B V- Terminal Input Select: Channel 5 */
678 
#define CBIMSEL_6              (0x0600)       /* Comp. B V- Terminal Input Select: Channel 6 */
679 
#define CBIMSEL_7              (0x0700)       /* Comp. B V- Terminal Input Select: Channel 7 */
680 
#define CBIMSEL_8              (0x0800)       /* Comp. B V- terminal Input Select: Channel 8 */
681 
#define CBIMSEL_9              (0x0900)       /* Comp. B V- terminal Input Select: Channel 9 */
682 
#define CBIMSEL_10             (0x0A00)       /* Comp. B V- terminal Input Select: Channel 10 */
683 
#define CBIMSEL_11             (0x0B00)       /* Comp. B V- terminal Input Select: Channel 11 */
684 
#define CBIMSEL_12             (0x0C00)       /* Comp. B V- terminal Input Select: Channel 12 */
685 
#define CBIMSEL_13             (0x0D00)       /* Comp. B V- terminal Input Select: Channel 13 */
686 
#define CBIMSEL_14             (0x0E00)       /* Comp. B V- terminal Input Select: Channel 14 */
687 
#define CBIMSEL_15             (0x0F00)       /* Comp. B V- terminal Input Select: Channel 15 */
688 
 
689 
/* CBCTL1 Control Bits */
690 
#define CBOUT                  (0x0001)       /* Comp. B Output */
691 
#define CBOUTPOL               (0x0002)       /* Comp. B Output Polarity */
692 
#define CBF                    (0x0004)       /* Comp. B Enable Output Filter */
693 
#define CBIES                  (0x0008)       /* Comp. B Interrupt Edge Select */
694 
#define CBSHORT                (0x0010)       /* Comp. B Input Short */
695 
#define CBEX                   (0x0020)       /* Comp. B Exchange Inputs */
696 
#define CBFDLY0                (0x0040)       /* Comp. B Filter delay Bit 0 */
697 
#define CBFDLY1                (0x0080)       /* Comp. B Filter delay Bit 1 */
698 
#define CBPWRMD0               (0x0100)       /* Comp. B Power Mode Bit 0 */
699 
#define CBPWRMD1               (0x0200)       /* Comp. B Power Mode Bit 1 */
700 
#define CBON                   (0x0400)       /* Comp. B enable */
701 
#define CBMRVL                 (0x0800)       /* Comp. B CBMRV Level */
702 
#define CBMRVS                 (0x1000)       /* Comp. B Output selects between VREF0 or VREF1*/
703 
//#define RESERVED            (0x2000)  /* Comp. B */
704 
//#define RESERVED            (0x4000)  /* Comp. B */
705 
//#define RESERVED            (0x8000)  /* Comp. B */
706 
 
707 
/* CBCTL1 Control Bits */
708 
#define CBOUT_L                (0x0001)       /* Comp. B Output */
709 
#define CBOUTPOL_L             (0x0002)       /* Comp. B Output Polarity */
710 
#define CBF_L                  (0x0004)       /* Comp. B Enable Output Filter */
711 
#define CBIES_L                (0x0008)       /* Comp. B Interrupt Edge Select */
712 
#define CBSHORT_L              (0x0010)       /* Comp. B Input Short */
713 
#define CBEX_L                 (0x0020)       /* Comp. B Exchange Inputs */
714 
#define CBFDLY0_L              (0x0040)       /* Comp. B Filter delay Bit 0 */
715 
#define CBFDLY1_L              (0x0080)       /* Comp. B Filter delay Bit 1 */
716 
//#define RESERVED            (0x2000)  /* Comp. B */
717 
//#define RESERVED            (0x4000)  /* Comp. B */
718 
//#define RESERVED            (0x8000)  /* Comp. B */
719 
 
720 
/* CBCTL1 Control Bits */
721 
#define CBPWRMD0_H             (0x0001)       /* Comp. B Power Mode Bit 0 */
722 
#define CBPWRMD1_H             (0x0002)       /* Comp. B Power Mode Bit 1 */
723 
#define CBON_H                 (0x0004)       /* Comp. B enable */
724 
#define CBMRVL_H               (0x0008)       /* Comp. B CBMRV Level */
725 
#define CBMRVS_H               (0x0010)       /* Comp. B Output selects between VREF0 or VREF1*/
726 
//#define RESERVED            (0x2000)  /* Comp. B */
727 
//#define RESERVED            (0x4000)  /* Comp. B */
728 
//#define RESERVED            (0x8000)  /* Comp. B */
729 
 
730 
#define CBFDLY_0               (0x0000)       /* Comp. B Filter delay 0 : 450ns */
731 
#define CBFDLY_1               (0x0040)       /* Comp. B Filter delay 1 : 900ns */
732 
#define CBFDLY_2               (0x0080)       /* Comp. B Filter delay 2 : 1800ns */
733 
#define CBFDLY_3               (0x00C0)       /* Comp. B Filter delay 3 : 3600ns */
734 
 
735 
#define CBPWRMD_0              (0x0000)       /* Comp. B Power Mode 0 : High speed */
736 
#define CBPWRMD_1              (0x0100)       /* Comp. B Power Mode 1 : Normal */
737 
#define CBPWRMD_2              (0x0200)       /* Comp. B Power Mode 2 : Ultra-Low*/
738 
#define CBPWRMD_3              (0x0300)       /* Comp. B Power Mode 3 : Reserved */
739 
 
740 
/* CBCTL2 Control Bits */
741 
#define CBREF00                (0x0001)       /* Comp. B Reference 0 Resistor Select Bit : 0 */
742 
#define CBREF01                (0x0002)       /* Comp. B Reference 0 Resistor Select Bit : 1 */
743 
#define CBREF02                (0x0004)       /* Comp. B Reference 0 Resistor Select Bit : 2 */
744 
#define CBREF03                (0x0008)       /* Comp. B Reference 0 Resistor Select Bit : 3 */
745 
#define CBREF04                (0x0010)       /* Comp. B Reference 0 Resistor Select Bit : 4 */
746 
#define CBRSEL                 (0x0020)       /* Comp. B Reference select */
747 
#define CBRS0                  (0x0040)       /* Comp. B Reference Source Bit : 0 */
748 
#define CBRS1                  (0x0080)       /* Comp. B Reference Source Bit : 1 */
749 
#define CBREF10                (0x0100)       /* Comp. B Reference 1 Resistor Select Bit : 0 */
750 
#define CBREF11                (0x0200)       /* Comp. B Reference 1 Resistor Select Bit : 1 */
751 
#define CBREF12                (0x0400)       /* Comp. B Reference 1 Resistor Select Bit : 2 */
752 
#define CBREF13                (0x0800)       /* Comp. B Reference 1 Resistor Select Bit : 3 */
753 
#define CBREF14                (0x1000)       /* Comp. B Reference 1 Resistor Select Bit : 4 */
754 
#define CBREFL0                (0x2000)       /* Comp. B Reference voltage level Bit : 0 */
755 
#define CBREFL1                (0x4000)       /* Comp. B Reference voltage level Bit : 1 */
756 
#define CBREFACC               (0x8000)       /* Comp. B Reference Accuracy */
757 
 
758 
/* CBCTL2 Control Bits */
759 
#define CBREF00_L              (0x0001)       /* Comp. B Reference 0 Resistor Select Bit : 0 */
760 
#define CBREF01_L              (0x0002)       /* Comp. B Reference 0 Resistor Select Bit : 1 */
761 
#define CBREF02_L              (0x0004)       /* Comp. B Reference 0 Resistor Select Bit : 2 */
762 
#define CBREF03_L              (0x0008)       /* Comp. B Reference 0 Resistor Select Bit : 3 */
763 
#define CBREF04_L              (0x0010)       /* Comp. B Reference 0 Resistor Select Bit : 4 */
764 
#define CBRSEL_L               (0x0020)       /* Comp. B Reference select */
765 
#define CBRS0_L                (0x0040)       /* Comp. B Reference Source Bit : 0 */
766 
#define CBRS1_L                (0x0080)       /* Comp. B Reference Source Bit : 1 */
767 
 
768 
/* CBCTL2 Control Bits */
769 
#define CBREF10_H              (0x0001)       /* Comp. B Reference 1 Resistor Select Bit : 0 */
770 
#define CBREF11_H              (0x0002)       /* Comp. B Reference 1 Resistor Select Bit : 1 */
771 
#define CBREF12_H              (0x0004)       /* Comp. B Reference 1 Resistor Select Bit : 2 */
772 
#define CBREF13_H              (0x0008)       /* Comp. B Reference 1 Resistor Select Bit : 3 */
773 
#define CBREF14_H              (0x0010)       /* Comp. B Reference 1 Resistor Select Bit : 4 */
774 
#define CBREFL0_H              (0x0020)       /* Comp. B Reference voltage level Bit : 0 */
775 
#define CBREFL1_H              (0x0040)       /* Comp. B Reference voltage level Bit : 1 */
776 
#define CBREFACC_H             (0x0080)       /* Comp. B Reference Accuracy */
777 
 
778 
#define CBREF0_0               (0x0000)       /* Comp. B Int. Ref.0 Select 0 : 1/32 */
779 
#define CBREF0_1               (0x0001)       /* Comp. B Int. Ref.0 Select 1 : 2/32 */
780 
#define CBREF0_2               (0x0002)       /* Comp. B Int. Ref.0 Select 2 : 3/32 */
781 
#define CBREF0_3               (0x0003)       /* Comp. B Int. Ref.0 Select 3 : 4/32 */
782 
#define CBREF0_4               (0x0004)       /* Comp. B Int. Ref.0 Select 4 : 5/32 */
783 
#define CBREF0_5               (0x0005)       /* Comp. B Int. Ref.0 Select 5 : 6/32 */
784 
#define CBREF0_6               (0x0006)       /* Comp. B Int. Ref.0 Select 6 : 7/32 */
785 
#define CBREF0_7               (0x0007)       /* Comp. B Int. Ref.0 Select 7 : 8/32 */
786 
#define CBREF0_8               (0x0008)       /* Comp. B Int. Ref.0 Select 0 : 9/32 */
787 
#define CBREF0_9               (0x0009)       /* Comp. B Int. Ref.0 Select 1 : 10/32 */
788 
#define CBREF0_10              (0x000A)       /* Comp. B Int. Ref.0 Select 2 : 11/32 */
789 
#define CBREF0_11              (0x000B)       /* Comp. B Int. Ref.0 Select 3 : 12/32 */
790 
#define CBREF0_12              (0x000C)       /* Comp. B Int. Ref.0 Select 4 : 13/32 */
791 
#define CBREF0_13              (0x000D)       /* Comp. B Int. Ref.0 Select 5 : 14/32 */
792 
#define CBREF0_14              (0x000E)       /* Comp. B Int. Ref.0 Select 6 : 15/32 */
793 
#define CBREF0_15              (0x000F)       /* Comp. B Int. Ref.0 Select 7 : 16/32 */
794 
#define CBREF0_16              (0x0010)       /* Comp. B Int. Ref.0 Select 0 : 17/32 */
795 
#define CBREF0_17              (0x0011)       /* Comp. B Int. Ref.0 Select 1 : 18/32 */
796 
#define CBREF0_18              (0x0012)       /* Comp. B Int. Ref.0 Select 2 : 19/32 */
797 
#define CBREF0_19              (0x0013)       /* Comp. B Int. Ref.0 Select 3 : 20/32 */
798 
#define CBREF0_20              (0x0014)       /* Comp. B Int. Ref.0 Select 4 : 21/32 */
799 
#define CBREF0_21              (0x0015)       /* Comp. B Int. Ref.0 Select 5 : 22/32 */
800 
#define CBREF0_22              (0x0016)       /* Comp. B Int. Ref.0 Select 6 : 23/32 */
801 
#define CBREF0_23              (0x0017)       /* Comp. B Int. Ref.0 Select 7 : 24/32 */
802 
#define CBREF0_24              (0x0018)       /* Comp. B Int. Ref.0 Select 0 : 25/32 */
803 
#define CBREF0_25              (0x0019)       /* Comp. B Int. Ref.0 Select 1 : 26/32 */
804 
#define CBREF0_26              (0x001A)       /* Comp. B Int. Ref.0 Select 2 : 27/32 */
805 
#define CBREF0_27              (0x001B)       /* Comp. B Int. Ref.0 Select 3 : 28/32 */
806 
#define CBREF0_28              (0x001C)       /* Comp. B Int. Ref.0 Select 4 : 29/32 */
807 
#define CBREF0_29              (0x001D)       /* Comp. B Int. Ref.0 Select 5 : 30/32 */
808 
#define CBREF0_30              (0x001E)       /* Comp. B Int. Ref.0 Select 6 : 31/32 */
809 
#define CBREF0_31              (0x001F)       /* Comp. B Int. Ref.0 Select 7 : 32/32 */
810 
 
811 
#define CBRS_0                 (0x0000)       /* Comp. B Reference Source 0 : Off */
812 
#define CBRS_1                 (0x0040)       /* Comp. B Reference Source 1 : Vcc */
813 
#define CBRS_2                 (0x0080)       /* Comp. B Reference Source 2 : Shared Ref. */
814 
#define CBRS_3                 (0x00C0)       /* Comp. B Reference Source 3 : Shared Ref. / Off */
815 
 
816 
#define CBREF1_0               (0x0000)       /* Comp. B Int. Ref.1 Select 0 : 1/32 */
817 
#define CBREF1_1               (0x0100)       /* Comp. B Int. Ref.1 Select 1 : 2/32 */
818 
#define CBREF1_2               (0x0200)       /* Comp. B Int. Ref.1 Select 2 : 3/32 */
819 
#define CBREF1_3               (0x0300)       /* Comp. B Int. Ref.1 Select 3 : 4/32 */
820 
#define CBREF1_4               (0x0400)       /* Comp. B Int. Ref.1 Select 4 : 5/32 */
821 
#define CBREF1_5               (0x0500)       /* Comp. B Int. Ref.1 Select 5 : 6/32 */
822 
#define CBREF1_6               (0x0600)       /* Comp. B Int. Ref.1 Select 6 : 7/32 */
823 
#define CBREF1_7               (0x0700)       /* Comp. B Int. Ref.1 Select 7 : 8/32 */
824 
#define CBREF1_8               (0x0800)       /* Comp. B Int. Ref.1 Select 0 : 9/32 */
825 
#define CBREF1_9               (0x0900)       /* Comp. B Int. Ref.1 Select 1 : 10/32 */
826 
#define CBREF1_10              (0x0A00)       /* Comp. B Int. Ref.1 Select 2 : 11/32 */
827 
#define CBREF1_11              (0x0B00)       /* Comp. B Int. Ref.1 Select 3 : 12/32 */
828 
#define CBREF1_12              (0x0C00)       /* Comp. B Int. Ref.1 Select 4 : 13/32 */
829 
#define CBREF1_13              (0x0D00)       /* Comp. B Int. Ref.1 Select 5 : 14/32 */
830 
#define CBREF1_14              (0x0E00)       /* Comp. B Int. Ref.1 Select 6 : 15/32 */
831 
#define CBREF1_15              (0x0F00)       /* Comp. B Int. Ref.1 Select 7 : 16/32 */
832 
#define CBREF1_16              (0x1000)       /* Comp. B Int. Ref.1 Select 0 : 17/32 */
833 
#define CBREF1_17              (0x1100)       /* Comp. B Int. Ref.1 Select 1 : 18/32 */
834 
#define CBREF1_18              (0x1200)       /* Comp. B Int. Ref.1 Select 2 : 19/32 */
835 
#define CBREF1_19              (0x1300)       /* Comp. B Int. Ref.1 Select 3 : 20/32 */
836 
#define CBREF1_20              (0x1400)       /* Comp. B Int. Ref.1 Select 4 : 21/32 */
837 
#define CBREF1_21              (0x1500)       /* Comp. B Int. Ref.1 Select 5 : 22/32 */
838 
#define CBREF1_22              (0x1600)       /* Comp. B Int. Ref.1 Select 6 : 23/32 */
839 
#define CBREF1_23              (0x1700)       /* Comp. B Int. Ref.1 Select 7 : 24/32 */
840 
#define CBREF1_24              (0x1800)       /* Comp. B Int. Ref.1 Select 0 : 25/32 */
841 
#define CBREF1_25              (0x1900)       /* Comp. B Int. Ref.1 Select 1 : 26/32 */
842 
#define CBREF1_26              (0x1A00)       /* Comp. B Int. Ref.1 Select 2 : 27/32 */
843 
#define CBREF1_27              (0x1B00)       /* Comp. B Int. Ref.1 Select 3 : 28/32 */
844 
#define CBREF1_28              (0x1C00)       /* Comp. B Int. Ref.1 Select 4 : 29/32 */
845 
#define CBREF1_29              (0x1D00)       /* Comp. B Int. Ref.1 Select 5 : 30/32 */
846 
#define CBREF1_30              (0x1E00)       /* Comp. B Int. Ref.1 Select 6 : 31/32 */
847 
#define CBREF1_31              (0x1F00)       /* Comp. B Int. Ref.1 Select 7 : 32/32 */
848 
 
849 
#define CBREFL_0               (0x0000)       /* Comp. B Reference voltage level 0 : None */
850 
#define CBREFL_1               (0x2000)       /* Comp. B Reference voltage level 1 : 1.5V */
851 
#define CBREFL_2               (0x4000)       /* Comp. B Reference voltage level 2 : 2.0V  */
852 
#define CBREFL_3               (0x6000)       /* Comp. B Reference voltage level 3 : 2.5V  */
853 
 
854 
#define CBPD0                  (0x0001)       /* Comp. B Disable Input Buffer of Port Register .0 */
855 
#define CBPD1                  (0x0002)       /* Comp. B Disable Input Buffer of Port Register .1 */
856 
#define CBPD2                  (0x0004)       /* Comp. B Disable Input Buffer of Port Register .2 */
857 
#define CBPD3                  (0x0008)       /* Comp. B Disable Input Buffer of Port Register .3 */
858 
#define CBPD4                  (0x0010)       /* Comp. B Disable Input Buffer of Port Register .4 */
859 
#define CBPD5                  (0x0020)       /* Comp. B Disable Input Buffer of Port Register .5 */
860 
#define CBPD6                  (0x0040)       /* Comp. B Disable Input Buffer of Port Register .6 */
861 
#define CBPD7                  (0x0080)       /* Comp. B Disable Input Buffer of Port Register .7 */
862 
#define CBPD8                  (0x0100)       /* Comp. B Disable Input Buffer of Port Register .8 */
863 
#define CBPD9                  (0x0200)       /* Comp. B Disable Input Buffer of Port Register .9 */
864 
#define CBPD10                 (0x0400)       /* Comp. B Disable Input Buffer of Port Register .10 */
865 
#define CBPD11                 (0x0800)       /* Comp. B Disable Input Buffer of Port Register .11 */
866 
#define CBPD12                 (0x1000)       /* Comp. B Disable Input Buffer of Port Register .12 */
867 
#define CBPD13                 (0x2000)       /* Comp. B Disable Input Buffer of Port Register .13 */
868 
#define CBPD14                 (0x4000)       /* Comp. B Disable Input Buffer of Port Register .14 */
869 
#define CBPD15                 (0x8000)       /* Comp. B Disable Input Buffer of Port Register .15 */
870 
 
871 
#define CBPD0_L                (0x0001)       /* Comp. B Disable Input Buffer of Port Register .0 */
872 
#define CBPD1_L                (0x0002)       /* Comp. B Disable Input Buffer of Port Register .1 */
873 
#define CBPD2_L                (0x0004)       /* Comp. B Disable Input Buffer of Port Register .2 */
874 
#define CBPD3_L                (0x0008)       /* Comp. B Disable Input Buffer of Port Register .3 */
875 
#define CBPD4_L                (0x0010)       /* Comp. B Disable Input Buffer of Port Register .4 */
876 
#define CBPD5_L                (0x0020)       /* Comp. B Disable Input Buffer of Port Register .5 */
877 
#define CBPD6_L                (0x0040)       /* Comp. B Disable Input Buffer of Port Register .6 */
878 
#define CBPD7_L                (0x0080)       /* Comp. B Disable Input Buffer of Port Register .7 */
879 
 
880 
#define CBPD8_H                (0x0001)       /* Comp. B Disable Input Buffer of Port Register .8 */
881 
#define CBPD9_H                (0x0002)       /* Comp. B Disable Input Buffer of Port Register .9 */
882 
#define CBPD10_H               (0x0004)       /* Comp. B Disable Input Buffer of Port Register .10 */
883 
#define CBPD11_H               (0x0008)       /* Comp. B Disable Input Buffer of Port Register .11 */
884 
#define CBPD12_H               (0x0010)       /* Comp. B Disable Input Buffer of Port Register .12 */
885 
#define CBPD13_H               (0x0020)       /* Comp. B Disable Input Buffer of Port Register .13 */
886 
#define CBPD14_H               (0x0040)       /* Comp. B Disable Input Buffer of Port Register .14 */
887 
#define CBPD15_H               (0x0080)       /* Comp. B Disable Input Buffer of Port Register .15 */
888 
 
889 
/* CBINT Control Bits */
890 
#define CBIFG                  (0x0001)       /* Comp. B Interrupt Flag */
891 
#define CBIIFG                 (0x0002)       /* Comp. B Interrupt Flag Inverted Polarity */
892 
//#define RESERVED             (0x0004)  /* Comp. B */
893 
//#define RESERVED             (0x0008)  /* Comp. B */
894 
//#define RESERVED             (0x0010)  /* Comp. B */
895 
//#define RESERVED             (0x0020)  /* Comp. B */
896 
//#define RESERVED             (0x0040)  /* Comp. B */
897 
//#define RESERVED             (0x0080)  /* Comp. B */
898 
#define CBIE                   (0x0100)       /* Comp. B Interrupt Enable */
899 
#define CBIIE                  (0x0200)       /* Comp. B Interrupt Enable Inverted Polarity */
900 
//#define RESERVED             (0x0400)  /* Comp. B */
901 
//#define RESERVED             (0x0800)  /* Comp. B */
902 
//#define RESERVED             (0x1000)  /* Comp. B */
903 
//#define RESERVED             (0x2000)  /* Comp. B */
904 
//#define RESERVED             (0x4000)  /* Comp. B */
905 
//#define RESERVED             (0x8000)  /* Comp. B */
906 
 
907 
/* CBINT Control Bits */
908 
#define CBIFG_L                (0x0001)       /* Comp. B Interrupt Flag */
909 
#define CBIIFG_L               (0x0002)       /* Comp. B Interrupt Flag Inverted Polarity */
910 
//#define RESERVED             (0x0004)  /* Comp. B */
911 
//#define RESERVED             (0x0008)  /* Comp. B */
912 
//#define RESERVED             (0x0010)  /* Comp. B */
913 
//#define RESERVED             (0x0020)  /* Comp. B */
914 
//#define RESERVED             (0x0040)  /* Comp. B */
915 
//#define RESERVED             (0x0080)  /* Comp. B */
916 
//#define RESERVED             (0x0400)  /* Comp. B */
917 
//#define RESERVED             (0x0800)  /* Comp. B */
918 
//#define RESERVED             (0x1000)  /* Comp. B */
919 
//#define RESERVED             (0x2000)  /* Comp. B */
920 
//#define RESERVED             (0x4000)  /* Comp. B */
921 
//#define RESERVED             (0x8000)  /* Comp. B */
922 
 
923 
/* CBINT Control Bits */
924 
//#define RESERVED             (0x0004)  /* Comp. B */
925 
//#define RESERVED             (0x0008)  /* Comp. B */
926 
//#define RESERVED             (0x0010)  /* Comp. B */
927 
//#define RESERVED             (0x0020)  /* Comp. B */
928 
//#define RESERVED             (0x0040)  /* Comp. B */
929 
//#define RESERVED             (0x0080)  /* Comp. B */
930 
#define CBIE_H                 (0x0001)       /* Comp. B Interrupt Enable */
931 
#define CBIIE_H                (0x0002)       /* Comp. B Interrupt Enable Inverted Polarity */
932 
//#define RESERVED             (0x0400)  /* Comp. B */
933 
//#define RESERVED             (0x0800)  /* Comp. B */
934 
//#define RESERVED             (0x1000)  /* Comp. B */
935 
//#define RESERVED             (0x2000)  /* Comp. B */
936 
//#define RESERVED             (0x4000)  /* Comp. B */
937 
//#define RESERVED             (0x8000)  /* Comp. B */
938 
 
939 
/* CBIV Definitions */
940 
#define CBIV_NONE              (0x0000)       /* No Interrupt pending */
941 
#define CBIV_CBIFG             (0x0002)       /* CBIFG */
942 
#define CBIV_CBIIFG            (0x0004)       /* CBIIFG */
943 
 
944 
/*************************************************************
945 
* CRC Module
946 
*************************************************************/
947 
#define __MSP430_HAS_CRC__                    /* Definition to show that Module is available */
948 
#define __MSP430_BASEADDRESS_CRC__ 0x0150
949 
 
950 
SFR_16BIT(CRCDI);                             /* CRC Data In Register */
951 
SFR_8BIT(CRCDI_L);                            /* CRC Data In Register */
952 
SFR_8BIT(CRCDI_H);                            /* CRC Data In Register */
953 
SFR_16BIT(CRCDIRB);                           /* CRC data in reverse byte Register */
954 
SFR_8BIT(CRCDIRB_L);                          /* CRC data in reverse byte Register */
955 
SFR_8BIT(CRCDIRB_H);                          /* CRC data in reverse byte Register */
956 
SFR_16BIT(CRCINIRES);                         /* CRC Initialisation Register and Result Register */
957 
SFR_8BIT(CRCINIRES_L);                        /* CRC Initialisation Register and Result Register */
958 
SFR_8BIT(CRCINIRES_H);                        /* CRC Initialisation Register and Result Register */
959 
SFR_16BIT(CRCRESR);                           /* CRC reverse result Register */
960 
SFR_8BIT(CRCRESR_L);                          /* CRC reverse result Register */
961 
SFR_8BIT(CRCRESR_H);                          /* CRC reverse result Register */
962 
 
963 
/************************************************************
964 
* DAC12
965 
************************************************************/
966 
#define __MSP430_HAS_DAC12_2__                /* Definition to show that Module is available */
967 
#define __MSP430_BASEADDRESS_DAC12_2__ 0x0780
968 
 
969 
SFR_16BIT(DAC12_0CTL0);                       /* DAC12_0 Control Register 0 */
970 
SFR_16BIT(DAC12_0CTL1);                       /* DAC12_0 Control Register 1 */
971 
SFR_16BIT(DAC12_0DAT);                        /* DAC12_0 Data */
972 
SFR_16BIT(DAC12_0CALCTL);                     /* DAC12_0 Calibration Control Register */
973 
SFR_16BIT(DAC12_0CALDAT);                     /* DAC12_0 Calibration Data Register */
974 
SFR_16BIT(DAC12_1CTL0);                       /* DAC12_1 Control Register 0 */
975 
SFR_16BIT(DAC12_1CTL1);                       /* DAC12_1 Control Register 1 */
976 
SFR_16BIT(DAC12_1DAT);                        /* DAC12_1 Data */
977 
SFR_16BIT(DAC12_1CALCTL);                     /* DAC12_1 Calibration Control Register */
978 
SFR_16BIT(DAC12_1CALDAT);                     /* DAC12_1 Calibration Data Register */
979 
SFR_16BIT(DAC12_IV);                          /* DAC12   Interrupt Vector Word */
980 
 
981 
/* DAC12_xCTL0 Control Bits */
982 
#define DAC12GRP               (0x0001)       /* DAC12 group */
983 
#define DAC12ENC               (0x0002)       /* DAC12 enable conversion */
984 
#define DAC12IFG               (0x0004)       /* DAC12 interrupt flag */
985 
#define DAC12IE                (0x0008)       /* DAC12 interrupt enable */
986 
#define DAC12DF                (0x0010)       /* DAC12 data format */
987 
#define DAC12AMP0              (0x0020)       /* DAC12 amplifier bit 0 */
988 
#define DAC12AMP1              (0x0040)       /* DAC12 amplifier bit 1 */
989 
#define DAC12AMP2              (0x0080)       /* DAC12 amplifier bit 2 */
990 
#define DAC12IR                (0x0100)       /* DAC12 input reference and output range */
991 
#define DAC12CALON             (0x0200)       /* DAC12 calibration */
992 
#define DAC12LSEL0             (0x0400)       /* DAC12 load select bit 0 */
993 
#define DAC12LSEL1             (0x0800)       /* DAC12 load select bit 1 */
994 
#define DAC12RES               (0x1000)       /* DAC12 resolution */
995 
#define DAC12SREF0             (0x2000)       /* DAC12 reference bit 0 */
996 
#define DAC12SREF1             (0x4000)       /* DAC12 reference bit 1 */
997 
#define DAC12OPS               (0x8000)       /* DAC12 Operation Amp. */
998 
 
999 
#define DAC12AMP_0             (0*0x0020u)    /* DAC12 amplifier 0: off,    3-state */
1000 
#define DAC12AMP_1             (1*0x0020u)    /* DAC12 amplifier 1: off,    off */
1001 
#define DAC12AMP_2             (2*0x0020u)    /* DAC12 amplifier 2: low,    low */
1002 
#define DAC12AMP_3             (3*0x0020u)    /* DAC12 amplifier 3: low,    medium */
1003 
#define DAC12AMP_4             (4*0x0020u)    /* DAC12 amplifier 4: low,    high */
1004 
#define DAC12AMP_5             (5*0x0020u)    /* DAC12 amplifier 5: medium, medium */
1005 
#define DAC12AMP_6             (6*0x0020u)    /* DAC12 amplifier 6: medium, high */
1006 
#define DAC12AMP_7             (7*0x0020u)    /* DAC12 amplifier 7: high,   high */
1007 
 
1008 
#define DAC12LSEL_0            (0*0x0400u)    /* DAC12 load select 0: direct */
1009 
#define DAC12LSEL_1            (1*0x0400u)    /* DAC12 load select 1: latched with DAT */
1010 
#define DAC12LSEL_2            (2*0x0400u)    /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */
1011 
#define DAC12LSEL_3            (3*0x0400u)    /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */
1012 
 
1013 
#define DAC12SREF_0            (0*0x2000u)    /* DAC12 reference 0: Vref+ */
1014 
#define DAC12SREF_1            (1*0x2000u)    /* DAC12 reference 1: Vref+ */
1015 
#define DAC12SREF_2            (2*0x2000u)    /* DAC12 reference 2: Veref+ */
1016 
#define DAC12SREF_3            (3*0x2000u)    /* DAC12 reference 3: Veref+ */
1017 
 
1018 
/* DAC12_xCTL1 Control Bits */
1019 
#define DAC12DFJ               (0x0001)       /* DAC12 Data Format Justification */
1020 
#define DAC12OG                (0x0002)       /* DAC12 output buffer gain: 0: 3x gain / 1: 2x gain */
1021 
 
1022 
/* DAC12_xCALCTL Control Bits */
1023 
#define DAC12LOCK              (0x0001)       /* DAC12 Calibration Lock */
1024 
 
1025 
#define DAC12PW                (0xA500)       /* DAC12 Calibration Register write Password */
1026 
 
1027 
/* DACIV Definitions */
1028 
#define DACIV_NONE             (0x0000)       /* No Interrupt pending */
1029 
#define DACIV_DAC12IFG_0       (0x0002)       /* DAC12IFG_0 */
1030 
#define DACIV_DAC12IFG_1       (0x0004)       /* DAC12IFG_1 */
1031 
 
1032 
/************************************************************
1033 
* DMA_X
1034 
************************************************************/
1035 
#define __MSP430_HAS_DMAX_6__                 /* Definition to show that Module is available */
1036 
#define __MSP430_BASEADDRESS_DMAX_6__ 0x0500
1037 
 
1038 
SFR_16BIT(DMACTL0);                           /* DMA Module Control 0 */
1039 
SFR_8BIT(DMACTL0_L);                          /* DMA Module Control 0 */
1040 
SFR_8BIT(DMACTL0_H);                          /* DMA Module Control 0 */
1041 
SFR_16BIT(DMACTL1);                           /* DMA Module Control 1 */
1042 
SFR_8BIT(DMACTL1_L);                          /* DMA Module Control 1 */
1043 
SFR_8BIT(DMACTL1_H);                          /* DMA Module Control 1 */
1044 
SFR_16BIT(DMACTL2);                           /* DMA Module Control 2 */
1045 
SFR_8BIT(DMACTL2_L);                          /* DMA Module Control 2 */
1046 
SFR_8BIT(DMACTL2_H);                          /* DMA Module Control 2 */
1047 
SFR_16BIT(DMACTL3);                           /* DMA Module Control 3 */
1048 
SFR_8BIT(DMACTL3_L);                          /* DMA Module Control 3 */
1049 
SFR_8BIT(DMACTL3_H);                          /* DMA Module Control 3 */
1050 
SFR_16BIT(DMACTL4);                           /* DMA Module Control 4 */
1051 
SFR_8BIT(DMACTL4_L);                          /* DMA Module Control 4 */
1052 
SFR_8BIT(DMACTL4_H);                          /* DMA Module Control 4 */
1053 
SFR_16BIT(DMAIV);                             /* DMA Interrupt Vector Word */
1054 
SFR_8BIT(DMAIV_L);                            /* DMA Interrupt Vector Word */
1055 
SFR_8BIT(DMAIV_H);                            /* DMA Interrupt Vector Word */
1056 
 
1057 
SFR_16BIT(DMA0CTL);                           /* DMA Channel 0 Control */
1058 
SFR_8BIT(DMA0CTL_L);                          /* DMA Channel 0 Control */
1059 
SFR_8BIT(DMA0CTL_H);                          /* DMA Channel 0 Control */
1060 
SFR_20BIT(DMA0SA);                            /* DMA Channel 0 Source Address */
1061 
SFR_16BIT(DMA0SAL);                           /* DMA Channel 0 Source Address */
1062 
SFR_20BIT(DMA0DA);                            /* DMA Channel 0 Destination Address */
1063 
SFR_16BIT(DMA0DAL);                           /* DMA Channel 0 Destination Address */
1064 
SFR_16BIT(DMA0SZ);                            /* DMA Channel 0 Transfer Size */
1065 
 
1066 
SFR_16BIT(DMA1CTL);                           /* DMA Channel 1 Control */
1067 
SFR_8BIT(DMA1CTL_L);                          /* DMA Channel 1 Control */
1068 
SFR_8BIT(DMA1CTL_H);                          /* DMA Channel 1 Control */
1069 
SFR_20BIT(DMA1SA);                            /* DMA Channel 1 Source Address */
1070 
SFR_16BIT(DMA1SAL);                           /* DMA Channel 1 Source Address */
1071 
SFR_20BIT(DMA1DA);                            /* DMA Channel 1 Destination Address */
1072 
SFR_16BIT(DMA1DAL);                           /* DMA Channel 1 Destination Address */
1073 
SFR_16BIT(DMA1SZ);                            /* DMA Channel 1 Transfer Size */
1074 
 
1075 
SFR_16BIT(DMA2CTL);                           /* DMA Channel 2 Control */
1076 
SFR_8BIT(DMA2CTL_L);                          /* DMA Channel 2 Control */
1077 
SFR_8BIT(DMA2CTL_H);                          /* DMA Channel 2 Control */
1078 
SFR_20BIT(DMA2SA);                            /* DMA Channel 2 Source Address */
1079 
SFR_16BIT(DMA2SAL);                           /* DMA Channel 2 Source Address */
1080 
SFR_20BIT(DMA2DA);                            /* DMA Channel 2 Destination Address */
1081 
SFR_16BIT(DMA2DAL);                           /* DMA Channel 2 Destination Address */
1082 
SFR_16BIT(DMA2SZ);                            /* DMA Channel 2 Transfer Size */
1083 
 
1084 
SFR_16BIT(DMA3CTL);                           /* DMA Channel 3 Control */
1085 
SFR_8BIT(DMA3CTL_L);                          /* DMA Channel 3 Control */
1086 
SFR_8BIT(DMA3CTL_H);                          /* DMA Channel 3 Control */
1087 
SFR_20BIT(DMA3SA);                            /* DMA Channel 3 Source Address */
1088 
SFR_16BIT(DMA3SAL);                           /* DMA Channel 3 Source Address */
1089 
SFR_20BIT(DMA3DA);                            /* DMA Channel 3 Destination Address */
1090 
SFR_16BIT(DMA3DAL);                           /* DMA Channel 3 Destination Address */
1091 
SFR_16BIT(DMA3SZ);                            /* DMA Channel 3 Transfer Size */
1092 
 
1093 
SFR_16BIT(DMA4CTL);                           /* DMA Channel 4 Control */
1094 
SFR_8BIT(DMA4CTL_L);                          /* DMA Channel 4 Control */
1095 
SFR_8BIT(DMA4CTL_H);                          /* DMA Channel 4 Control */
1096 
SFR_20BIT(DMA4SA);                            /* DMA Channel 4 Source Address */
1097 
SFR_16BIT(DMA4SAL);                           /* DMA Channel 4 Source Address */
1098 
SFR_20BIT(DMA4DA);                            /* DMA Channel 4 Destination Address */
1099 
SFR_16BIT(DMA4DAL);                           /* DMA Channel 4 Destination Address */
1100 
SFR_16BIT(DMA4SZ);                            /* DMA Channel 4 Transfer Size */
1101 
 
1102 
SFR_16BIT(DMA5CTL);                           /* DMA Channel 5 Control */
1103 
SFR_8BIT(DMA5CTL_L);                          /* DMA Channel 5 Control */
1104 
SFR_8BIT(DMA5CTL_H);                          /* DMA Channel 5 Control */
1105 
SFR_20BIT(DMA5SA);                            /* DMA Channel 5 Source Address */
1106 
SFR_16BIT(DMA5SAL);                           /* DMA Channel 5 Source Address */
1107 
SFR_20BIT(DMA5DA);                            /* DMA Channel 5 Destination Address */
1108 
SFR_16BIT(DMA5DAL);                           /* DMA Channel 5 Destination Address */
1109 
SFR_16BIT(DMA5SZ);                            /* DMA Channel 5 Transfer Size */
1110 
 
1111 
/* DMACTL0 Control Bits */
1112 
#define DMA0TSEL0              (0x0001)       /* DMA channel 0 transfer select bit 0 */
1113 
#define DMA0TSEL1              (0x0002)       /* DMA channel 0 transfer select bit 1 */
1114 
#define DMA0TSEL2              (0x0004)       /* DMA channel 0 transfer select bit 2 */
1115 
#define DMA0TSEL3              (0x0008)       /* DMA channel 0 transfer select bit 3 */
1116 
#define DMA0TSEL4              (0x0010)       /* DMA channel 0 transfer select bit 4 */
1117 
#define DMA1TSEL0              (0x0100)       /* DMA channel 1 transfer select bit 0 */
1118 
#define DMA1TSEL1              (0x0200)       /* DMA channel 1 transfer select bit 1 */
1119 
#define DMA1TSEL2              (0x0400)       /* DMA channel 1 transfer select bit 2 */
1120 
#define DMA1TSEL3              (0x0800)       /* DMA channel 1 transfer select bit 3 */
1121 
#define DMA1TSEL4              (0x1000)       /* DMA channel 1 transfer select bit 4 */
1122 
 
1123 
/* DMACTL0 Control Bits */
1124 
#define DMA0TSEL0_L            (0x0001)       /* DMA channel 0 transfer select bit 0 */
1125 
#define DMA0TSEL1_L            (0x0002)       /* DMA channel 0 transfer select bit 1 */
1126 
#define DMA0TSEL2_L            (0x0004)       /* DMA channel 0 transfer select bit 2 */
1127 
#define DMA0TSEL3_L            (0x0008)       /* DMA channel 0 transfer select bit 3 */
1128 
#define DMA0TSEL4_L            (0x0010)       /* DMA channel 0 transfer select bit 4 */
1129 
 
1130 
/* DMACTL0 Control Bits */
1131 
#define DMA1TSEL0_H            (0x0001)       /* DMA channel 1 transfer select bit 0 */
1132 
#define DMA1TSEL1_H            (0x0002)       /* DMA channel 1 transfer select bit 1 */
1133 
#define DMA1TSEL2_H            (0x0004)       /* DMA channel 1 transfer select bit 2 */
1134 
#define DMA1TSEL3_H            (0x0008)       /* DMA channel 1 transfer select bit 3 */
1135 
#define DMA1TSEL4_H            (0x0010)       /* DMA channel 1 transfer select bit 4 */
1136 
 
1137 
/* DMACTL01 Control Bits */
1138 
#define DMA2TSEL0              (0x0001)       /* DMA channel 2 transfer select bit 0 */
1139 
#define DMA2TSEL1              (0x0002)       /* DMA channel 2 transfer select bit 1 */
1140 
#define DMA2TSEL2              (0x0004)       /* DMA channel 2 transfer select bit 2 */
1141 
#define DMA2TSEL3              (0x0008)       /* DMA channel 2 transfer select bit 3 */
1142 
#define DMA2TSEL4              (0x0010)       /* DMA channel 2 transfer select bit 4 */
1143 
#define DMA3TSEL0              (0x0100)       /* DMA channel 3 transfer select bit 0 */
1144 
#define DMA3TSEL1              (0x0200)       /* DMA channel 3 transfer select bit 1 */
1145 
#define DMA3TSEL2              (0x0400)       /* DMA channel 3 transfer select bit 2 */
1146 
#define DMA3TSEL3              (0x0800)       /* DMA channel 3 transfer select bit 3 */
1147 
#define DMA3TSEL4              (0x1000)       /* DMA channel 3 transfer select bit 4 */
1148 
 
1149 
/* DMACTL01 Control Bits */
1150 
#define DMA2TSEL0_L            (0x0001)       /* DMA channel 2 transfer select bit 0 */
1151 
#define DMA2TSEL1_L            (0x0002)       /* DMA channel 2 transfer select bit 1 */
1152 
#define DMA2TSEL2_L            (0x0004)       /* DMA channel 2 transfer select bit 2 */
1153 
#define DMA2TSEL3_L            (0x0008)       /* DMA channel 2 transfer select bit 3 */
1154 
#define DMA2TSEL4_L            (0x0010)       /* DMA channel 2 transfer select bit 4 */
1155 
 
1156 
/* DMACTL01 Control Bits */
1157 
#define DMA3TSEL0_H            (0x0001)       /* DMA channel 3 transfer select bit 0 */
1158 
#define DMA3TSEL1_H            (0x0002)       /* DMA channel 3 transfer select bit 1 */
1159 
#define DMA3TSEL2_H            (0x0004)       /* DMA channel 3 transfer select bit 2 */
1160 
#define DMA3TSEL3_H            (0x0008)       /* DMA channel 3 transfer select bit 3 */
1161 
#define DMA3TSEL4_H            (0x0010)       /* DMA channel 3 transfer select bit 4 */
1162 
 
1163 
/* DMACTL0 Control Bits */
1164 
#define DMA4TSEL0              (0x0001)       /* DMA channel 4 transfer select bit 0 */
1165 
#define DMA4TSEL1              (0x0002)       /* DMA channel 4 transfer select bit 1 */
1166 
#define DMA4TSEL2              (0x0004)       /* DMA channel 4 transfer select bit 2 */
1167 
#define DMA4TSEL3              (0x0008)       /* DMA channel 4 transfer select bit 3 */
1168 
#define DMA4TSEL4              (0x0010)       /* DMA channel 4 transfer select bit 4 */
1169 
#define DMA5TSEL0              (0x0100)       /* DMA channel 5 transfer select bit 0 */
1170 
#define DMA5TSEL1              (0x0200)       /* DMA channel 5 transfer select bit 1 */
1171 
#define DMA5TSEL2              (0x0400)       /* DMA channel 5 transfer select bit 2 */
1172 
#define DMA5TSEL3              (0x0800)       /* DMA channel 5 transfer select bit 3 */
1173 
#define DMA5TSEL4              (0x1000)       /* DMA channel 5 transfer select bit 4 */
1174 
 
1175 
/* DMACTL0 Control Bits */
1176 
#define DMA4TSEL0_L            (0x0001)       /* DMA channel 4 transfer select bit 0 */
1177 
#define DMA4TSEL1_L            (0x0002)       /* DMA channel 4 transfer select bit 1 */
1178 
#define DMA4TSEL2_L            (0x0004)       /* DMA channel 4 transfer select bit 2 */
1179 
#define DMA4TSEL3_L            (0x0008)       /* DMA channel 4 transfer select bit 3 */
1180 
#define DMA4TSEL4_L            (0x0010)       /* DMA channel 4 transfer select bit 4 */
1181 
 
1182 
/* DMACTL0 Control Bits */
1183 
#define DMA5TSEL0_H            (0x0001)       /* DMA channel 5 transfer select bit 0 */
1184 
#define DMA5TSEL1_H            (0x0002)       /* DMA channel 5 transfer select bit 1 */
1185 
#define DMA5TSEL2_H            (0x0004)       /* DMA channel 5 transfer select bit 2 */
1186 
#define DMA5TSEL3_H            (0x0008)       /* DMA channel 5 transfer select bit 3 */
1187 
#define DMA5TSEL4_H            (0x0010)       /* DMA channel 5 transfer select bit 4 */
1188 
 
1189 
/* DMACTL4 Control Bits */
1190 
#define ENNMI                  (0x0001)       /* Enable NMI interruption of DMA */
1191 
#define ROUNDROBIN             (0x0002)       /* Round-Robin DMA channel priorities */
1192 
#define DMARMWDIS              (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
1193 
 
1194 
/* DMACTL4 Control Bits */
1195 
#define ENNMI_L                (0x0001)       /* Enable NMI interruption of DMA */
1196 
#define ROUNDROBIN_L           (0x0002)       /* Round-Robin DMA channel priorities */
1197 
#define DMARMWDIS_L            (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
1198 
 
1199 
/* DMACTL4 Control Bits */
1200 
 
1201 
/* DMAxCTL Control Bits */
1202 
#define DMAREQ                 (0x0001)       /* Initiate DMA transfer with DMATSEL */
1203 
#define DMAABORT               (0x0002)       /* DMA transfer aborted by NMI */
1204 
#define DMAIE                  (0x0004)       /* DMA interrupt enable */
1205 
#define DMAIFG                 (0x0008)       /* DMA interrupt flag */
1206 
#define DMAEN                  (0x0010)       /* DMA enable */
1207 
#define DMALEVEL               (0x0020)       /* DMA level sensitive trigger select */
1208 
#define DMASRCBYTE             (0x0040)       /* DMA source byte */
1209 
#define DMADSTBYTE             (0x0080)       /* DMA destination byte */
1210 
#define DMASRCINCR0            (0x0100)       /* DMA source increment bit 0 */
1211 
#define DMASRCINCR1            (0x0200)       /* DMA source increment bit 1 */
1212 
#define DMADSTINCR0            (0x0400)       /* DMA destination increment bit 0 */
1213 
#define DMADSTINCR1            (0x0800)       /* DMA destination increment bit 1 */
1214 
#define DMADT0                 (0x1000)       /* DMA transfer mode bit 0 */
1215 
#define DMADT1                 (0x2000)       /* DMA transfer mode bit 1 */
1216 
#define DMADT2                 (0x4000)       /* DMA transfer mode bit 2 */
1217 
 
1218 
/* DMAxCTL Control Bits */
1219 
#define DMAREQ_L               (0x0001)       /* Initiate DMA transfer with DMATSEL */
1220 
#define DMAABORT_L             (0x0002)       /* DMA transfer aborted by NMI */
1221 
#define DMAIE_L                (0x0004)       /* DMA interrupt enable */
1222 
#define DMAIFG_L               (0x0008)       /* DMA interrupt flag */
1223 
#define DMAEN_L                (0x0010)       /* DMA enable */
1224 
#define DMALEVEL_L             (0x0020)       /* DMA level sensitive trigger select */
1225 
#define DMASRCBYTE_L           (0x0040)       /* DMA source byte */
1226 
#define DMADSTBYTE_L           (0x0080)       /* DMA destination byte */
1227 
 
1228 
/* DMAxCTL Control Bits */
1229 
#define DMASRCINCR0_H          (0x0001)       /* DMA source increment bit 0 */
1230 
#define DMASRCINCR1_H          (0x0002)       /* DMA source increment bit 1 */
1231 
#define DMADSTINCR0_H          (0x0004)       /* DMA destination increment bit 0 */
1232 
#define DMADSTINCR1_H          (0x0008)       /* DMA destination increment bit 1 */
1233 
#define DMADT0_H               (0x0010)       /* DMA transfer mode bit 0 */
1234 
#define DMADT1_H               (0x0020)       /* DMA transfer mode bit 1 */
1235 
#define DMADT2_H               (0x0040)       /* DMA transfer mode bit 2 */
1236 
 
1237 
#define DMASWDW                (0*0x0040u)    /* DMA transfer: source word to destination word */
1238 
#define DMASBDW                (1*0x0040u)    /* DMA transfer: source byte to destination word */
1239 
#define DMASWDB                (2*0x0040u)    /* DMA transfer: source word to destination byte */
1240 
#define DMASBDB                (3*0x0040u)    /* DMA transfer: source byte to destination byte */
1241 
 
1242 
#define DMASRCINCR_0           (0*0x0100u)    /* DMA source increment 0: source address unchanged */
1243 
#define DMASRCINCR_1           (1*0x0100u)    /* DMA source increment 1: source address unchanged */
1244 
#define DMASRCINCR_2           (2*0x0100u)    /* DMA source increment 2: source address decremented */
1245 
#define DMASRCINCR_3           (3*0x0100u)    /* DMA source increment 3: source address incremented */
1246 
 
1247 
#define DMADSTINCR_0           (0*0x0400u)    /* DMA destination increment 0: destination address unchanged */
1248 
#define DMADSTINCR_1           (1*0x0400u)    /* DMA destination increment 1: destination address unchanged */
1249 
#define DMADSTINCR_2           (2*0x0400u)    /* DMA destination increment 2: destination address decremented */
1250 
#define DMADSTINCR_3           (3*0x0400u)    /* DMA destination increment 3: destination address incremented */
1251 
 
1252 
#define DMADT_0                (0*0x1000u)    /* DMA transfer mode 0: Single transfer */
1253 
#define DMADT_1                (1*0x1000u)    /* DMA transfer mode 1: Block transfer */
1254 
#define DMADT_2                (2*0x1000u)    /* DMA transfer mode 2: Burst-Block transfer */
1255 
#define DMADT_3                (3*0x1000u)    /* DMA transfer mode 3: Burst-Block transfer */
1256 
#define DMADT_4                (4*0x1000u)    /* DMA transfer mode 4: Repeated Single transfer */
1257 
#define DMADT_5                (5*0x1000u)    /* DMA transfer mode 5: Repeated Block transfer */
1258 
#define DMADT_6                (6*0x1000u)    /* DMA transfer mode 6: Repeated Burst-Block transfer */
1259 
#define DMADT_7                (7*0x1000u)    /* DMA transfer mode 7: Repeated Burst-Block transfer */
1260 
 
1261 
/* DMAIV Definitions */
1262 
#define DMAIV_NONE             (0x0000)       /* No Interrupt pending */
1263 
#define DMAIV_DMA0IFG          (0x0002)       /* DMA0IFG*/
1264 
#define DMAIV_DMA1IFG          (0x0004)       /* DMA1IFG*/
1265 
#define DMAIV_DMA2IFG          (0x0006)       /* DMA2IFG*/
1266 
#define DMAIV_DMA3IFG          (0x0008)       /* DMA3IFG*/
1267 
#define DMAIV_DMA4IFG          (0x000A)       /* DMA4IFG*/
1268 
#define DMAIV_DMA5IFG          (0x000C)       /* DMA5IFG*/
1269 
 
1270 
#define DMA0TSEL_0             (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
1271 
#define DMA0TSEL_1             (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1272 
#define DMA0TSEL_2             (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1273 
#define DMA0TSEL_3             (3*0x0001u)    /* DMA channel 0 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1274 
#define DMA0TSEL_4             (4*0x0001u)    /* DMA channel 0 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1275 
#define DMA0TSEL_5             (5*0x0001u)    /* DMA channel 0 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1276 
#define DMA0TSEL_6             (6*0x0001u)    /* DMA channel 0 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1277 
#define DMA0TSEL_7             (7*0x0001u)    /* DMA channel 0 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1278 
#define DMA0TSEL_8             (8*0x0001u)    /* DMA channel 0 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1279 
#define DMA0TSEL_9             (9*0x0001u)    /* DMA channel 0 transfer select 9:  Reserved */
1280 
#define DMA0TSEL_10            (10*0x0001u)   /* DMA channel 0 transfer select 10: Reserved */
1281 
#define DMA0TSEL_11            (11*0x0001u)   /* DMA channel 0 transfer select 11: Reserved */
1282 
#define DMA0TSEL_12            (12*0x0001u)   /* DMA channel 0 transfer select 12: Reserved */
1283 
#define DMA0TSEL_13            (13*0x0001u)   /* DMA channel 0 transfer select 13: Reserved */
1284 
#define DMA0TSEL_14            (14*0x0001u)   /* DMA channel 0 transfer select 14: Reserved */
1285 
#define DMA0TSEL_15            (15*0x0001u)   /* DMA channel 0 transfer select 15: Reserved */
1286 
#define DMA0TSEL_16            (16*0x0001u)   /* DMA channel 0 transfer select 16: USCIA0 receive */
1287 
#define DMA0TSEL_17            (17*0x0001u)   /* DMA channel 0 transfer select 17: USCIA0 transmit */
1288 
#define DMA0TSEL_18            (18*0x0001u)   /* DMA channel 0 transfer select 18: USCIB0 receive */
1289 
#define DMA0TSEL_19            (19*0x0001u)   /* DMA channel 0 transfer select 19: USCIB0 transmit */
1290 
#define DMA0TSEL_20            (20*0x0001u)   /* DMA channel 0 transfer select 20: USCIA1 receive */
1291 
#define DMA0TSEL_21            (21*0x0001u)   /* DMA channel 0 transfer select 21: USCIA1 transmit */
1292 
#define DMA0TSEL_22            (22*0x0001u)   /* DMA channel 0 transfer select 22: USCIB1 receive */
1293 
#define DMA0TSEL_23            (23*0x0001u)   /* DMA channel 0 transfer select 23: USCIB1 transmit */
1294 
#define DMA0TSEL_24            (24*0x0001u)   /* DMA channel 0 transfer select 24: ADC12IFGx */
1295 
#define DMA0TSEL_25            (25*0x0001u)   /* DMA channel 0 transfer select 25: DAC12_0IFG */
1296 
#define DMA0TSEL_26            (26*0x0001u)   /* DMA channel 0 transfer select 26: DAC12_1IFG */
1297 
#define DMA0TSEL_27            (27*0x0001u)   /* DMA channel 0 transfer select 27: USB FNRXD */
1298 
#define DMA0TSEL_28            (28*0x0001u)   /* DMA channel 0 transfer select 28: USB ready */
1299 
#define DMA0TSEL_29            (29*0x0001u)   /* DMA channel 0 transfer select 29: Multiplier ready */
1300 
#define DMA0TSEL_30            (30*0x0001u)   /* DMA channel 0 transfer select 30: previous DMA channel DMA5IFG */
1301 
#define DMA0TSEL_31            (31*0x0001u)   /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
1302 
 
1303 
#define DMA1TSEL_0             (0*0x0100u)    /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
1304 
#define DMA1TSEL_1             (1*0x0100u)    /* DMA channel 1 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1305 
#define DMA1TSEL_2             (2*0x0100u)    /* DMA channel 1 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1306 
#define DMA1TSEL_3             (3*0x0100u)    /* DMA channel 1 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1307 
#define DMA1TSEL_4             (4*0x0100u)    /* DMA channel 1 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1308 
#define DMA1TSEL_5             (5*0x0100u)    /* DMA channel 1 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1309 
#define DMA1TSEL_6             (6*0x0100u)    /* DMA channel 1 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1310 
#define DMA1TSEL_7             (7*0x0001u)    /* DMA channel 1 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1311 
#define DMA1TSEL_8             (8*0x0001u)    /* DMA channel 1 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1312 
#define DMA1TSEL_9             (9*0x0100u)    /* DMA channel 1 transfer select 9:  Reserved */
1313 
#define DMA1TSEL_10            (10*0x0100u)   /* DMA channel 1 transfer select 10: Reserved */
1314 
#define DMA1TSEL_11            (11*0x0100u)   /* DMA channel 1 transfer select 11: Reserved */
1315 
#define DMA1TSEL_12            (12*0x0100u)   /* DMA channel 1 transfer select 12: Reserved */
1316 
#define DMA1TSEL_13            (13*0x0100u)   /* DMA channel 1 transfer select 13: Reserved */
1317 
#define DMA1TSEL_14            (14*0x0100u)   /* DMA channel 1 transfer select 14: Reserved */
1318 
#define DMA1TSEL_15            (15*0x0100u)   /* DMA channel 1 transfer select 15: Reserved */
1319 
#define DMA1TSEL_16            (16*0x0100u)   /* DMA channel 1 transfer select 16: USCIA0 receive */
1320 
#define DMA1TSEL_17            (17*0x0100u)   /* DMA channel 1 transfer select 17: USCIA0 transmit */
1321 
#define DMA1TSEL_18            (18*0x0100u)   /* DMA channel 1 transfer select 18: USCIB0 receive */
1322 
#define DMA1TSEL_19            (19*0x0100u)   /* DMA channel 1 transfer select 19: USCIB0 transmit */
1323 
#define DMA1TSEL_20            (20*0x0100u)   /* DMA channel 1 transfer select 20: USCIA1 receive */
1324 
#define DMA1TSEL_21            (21*0x0100u)   /* DMA channel 1 transfer select 21: USCIA1 transmit */
1325 
#define DMA1TSEL_22            (22*0x0100u)   /* DMA channel 1 transfer select 22: USCIB1 receive */
1326 
#define DMA1TSEL_23            (23*0x0100u)   /* DMA channel 1 transfer select 23: USCIB1 transmit */
1327 
#define DMA1TSEL_24            (24*0x0100u)   /* DMA channel 1 transfer select 24: ADC12IFGx */
1328 
#define DMA1TSEL_25            (25*0x0100u)   /* DMA channel 1 transfer select 25: DAC12_0IFG */
1329 
#define DMA1TSEL_26            (26*0x0100u)   /* DMA channel 1 transfer select 26: DAC12_1IFG */
1330 
#define DMA1TSEL_27            (27*0x0100u)   /* DMA channel 1 transfer select 27: USB FNRXD */
1331 
#define DMA1TSEL_28            (28*0x0100u)   /* DMA channel 1 transfer select 28: USB ready */
1332 
#define DMA1TSEL_29            (29*0x0100u)   /* DMA channel 1 transfer select 29: Multiplier ready */
1333 
#define DMA1TSEL_30            (30*0x0100u)   /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
1334 
#define DMA1TSEL_31            (31*0x0100u)   /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
1335 
 
1336 
#define DMA2TSEL_0             (0*0x0001u)    /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
1337 
#define DMA2TSEL_1             (1*0x0001u)    /* DMA channel 2 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1338 
#define DMA2TSEL_2             (2*0x0001u)    /* DMA channel 2 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1339 
#define DMA2TSEL_3             (3*0x0001u)    /* DMA channel 2 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1340 
#define DMA2TSEL_4             (4*0x0001u)    /* DMA channel 2 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1341 
#define DMA2TSEL_5             (5*0x0001u)    /* DMA channel 2 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1342 
#define DMA2TSEL_6             (6*0x0001u)    /* DMA channel 2 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1343 
#define DMA2TSEL_7             (7*0x0001u)    /* DMA channel 2 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1344 
#define DMA2TSEL_8             (8*0x0001u)    /* DMA channel 2 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1345 
#define DMA2TSEL_9             (9*0x0001u)    /* DMA channel 2 transfer select 9:  Reserved */
1346 
#define DMA2TSEL_10            (10*0x0001u)   /* DMA channel 2 transfer select 10: Reserved */
1347 
#define DMA2TSEL_11            (11*0x0001u)   /* DMA channel 2 transfer select 11: Reserved */
1348 
#define DMA2TSEL_12            (12*0x0001u)   /* DMA channel 2 transfer select 12: Reserved */
1349 
#define DMA2TSEL_13            (13*0x0001u)   /* DMA channel 2 transfer select 13: Reserved */
1350 
#define DMA2TSEL_14            (14*0x0001u)   /* DMA channel 2 transfer select 14: Reserved */
1351 
#define DMA2TSEL_15            (15*0x0001u)   /* DMA channel 2 transfer select 15: Reserved */
1352 
#define DMA2TSEL_16            (16*0x0001u)   /* DMA channel 2 transfer select 16: USCIA0 receive */
1353 
#define DMA2TSEL_17            (17*0x0001u)   /* DMA channel 2 transfer select 17: USCIA0 transmit */
1354 
#define DMA2TSEL_18            (18*0x0001u)   /* DMA channel 2 transfer select 18: USCIB0 receive */
1355 
#define DMA2TSEL_19            (19*0x0001u)   /* DMA channel 2 transfer select 19: USCIB0 transmit */
1356 
#define DMA2TSEL_20            (20*0x0001u)   /* DMA channel 2 transfer select 20: USCIA1 receive */
1357 
#define DMA2TSEL_21            (21*0x0001u)   /* DMA channel 2 transfer select 21: USCIA1 transmit */
1358 
#define DMA2TSEL_22            (22*0x0001u)   /* DMA channel 2 transfer select 22: USCIB1 receive */
1359 
#define DMA2TSEL_23            (23*0x0001u)   /* DMA channel 2 transfer select 23: USCIB1 transmit */
1360 
#define DMA2TSEL_24            (24*0x0001u)   /* DMA channel 2 transfer select 24: ADC12IFGx */
1361 
#define DMA2TSEL_25            (25*0x0001u)   /* DMA channel 2 transfer select 25: DAC12_0IFG */
1362 
#define DMA2TSEL_26            (26*0x0001u)   /* DMA channel 2 transfer select 26: DAC12_1IFG */
1363 
#define DMA2TSEL_27            (27*0x0001u)   /* DMA channel 2 transfer select 27: USB FNRXD */
1364 
#define DMA2TSEL_28            (28*0x0001u)   /* DMA channel 2 transfer select 28: USB ready */
1365 
#define DMA2TSEL_29            (29*0x0001u)   /* DMA channel 2 transfer select 29: Multiplier ready */
1366 
#define DMA2TSEL_30            (30*0x0001u)   /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
1367 
#define DMA2TSEL_31            (31*0x0001u)   /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
1368 
 
1369 
#define DMA3TSEL_0             (0*0x0100u)    /* DMA channel 3 transfer select 0:  DMA_REQ (sw) */
1370 
#define DMA3TSEL_1             (1*0x0100u)    /* DMA channel 3 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1371 
#define DMA3TSEL_2             (2*0x0100u)    /* DMA channel 3 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1372 
#define DMA3TSEL_3             (3*0x0100u)    /* DMA channel 3 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1373 
#define DMA3TSEL_4             (4*0x0100u)    /* DMA channel 3 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1374 
#define DMA3TSEL_5             (5*0x0100u)    /* DMA channel 3 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1375 
#define DMA3TSEL_6             (6*0x0100u)    /* DMA channel 3 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1376 
#define DMA3TSEL_7             (7*0x0001u)    /* DMA channel 3 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1377 
#define DMA3TSEL_8             (8*0x0001u)    /* DMA channel 3 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1378 
#define DMA3TSEL_9             (9*0x0100u)    /* DMA channel 3 transfer select 9:  Reserved */
1379 
#define DMA3TSEL_10            (10*0x0100u)   /* DMA channel 3 transfer select 10: Reserved */
1380 
#define DMA3TSEL_11            (11*0x0100u)   /* DMA channel 3 transfer select 11: Reserved */
1381 
#define DMA3TSEL_12            (12*0x0100u)   /* DMA channel 3 transfer select 12: Reserved */
1382 
#define DMA3TSEL_13            (13*0x0100u)   /* DMA channel 3 transfer select 13: Reserved */
1383 
#define DMA3TSEL_14            (14*0x0100u)   /* DMA channel 3 transfer select 14: Reserved */
1384 
#define DMA3TSEL_15            (15*0x0100u)   /* DMA channel 3 transfer select 15: Reserved */
1385 
#define DMA3TSEL_16            (16*0x0100u)   /* DMA channel 3 transfer select 16: USCIA0 receive */
1386 
#define DMA3TSEL_17            (17*0x0100u)   /* DMA channel 3 transfer select 17: USCIA0 transmit */
1387 
#define DMA3TSEL_18            (18*0x0100u)   /* DMA channel 3 transfer select 18: USCIB0 receive */
1388 
#define DMA3TSEL_19            (19*0x0100u)   /* DMA channel 3 transfer select 19: USCIB0 transmit */
1389 
#define DMA3TSEL_20            (20*0x0100u)   /* DMA channel 3 transfer select 20: USCIA1 receive */
1390 
#define DMA3TSEL_21            (21*0x0100u)   /* DMA channel 3 transfer select 21: USCIA1 transmit */
1391 
#define DMA3TSEL_22            (22*0x0100u)   /* DMA channel 3 transfer select 22: USCIB1 receive */
1392 
#define DMA3TSEL_23            (23*0x0100u)   /* DMA channel 3 transfer select 23: USCIB1 transmit */
1393 
#define DMA3TSEL_24            (24*0x0100u)   /* DMA channel 3 transfer select 24: ADC12IFGx */
1394 
#define DMA3TSEL_25            (25*0x0100u)   /* DMA channel 3 transfer select 25: DAC12_0IFG */
1395 
#define DMA3TSEL_26            (26*0x0100u)   /* DMA channel 3 transfer select 26: DAC12_1IFG */
1396 
#define DMA3TSEL_27            (27*0x0100u)   /* DMA channel 3 transfer select 27: USB FNRXD */
1397 
#define DMA3TSEL_28            (28*0x0100u)   /* DMA channel 3 transfer select 28: USB ready */
1398 
#define DMA3TSEL_29            (29*0x0100u)   /* DMA channel 3 transfer select 29: Multiplier ready */
1399 
#define DMA3TSEL_30            (30*0x0100u)   /* DMA channel 3 transfer select 30: previous DMA channel DMA2IFG */
1400 
#define DMA3TSEL_31            (31*0x0100u)   /* DMA channel 3 transfer select 31: ext. Trigger (DMAE0) */
1401 
 
1402 
#define DMA4TSEL_0             (0*0x0001u)    /* DMA channel 4 transfer select 0:  DMA_REQ (sw) */
1403 
#define DMA4TSEL_1             (1*0x0001u)    /* DMA channel 4 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1404 
#define DMA4TSEL_2             (2*0x0001u)    /* DMA channel 4 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1405 
#define DMA4TSEL_3             (3*0x0001u)    /* DMA channel 4 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1406 
#define DMA4TSEL_4             (4*0x0001u)    /* DMA channel 4 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1407 
#define DMA4TSEL_5             (5*0x0001u)    /* DMA channel 4 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1408 
#define DMA4TSEL_6             (6*0x0001u)    /* DMA channel 4 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1409 
#define DMA4TSEL_7             (7*0x0001u)    /* DMA channel 4 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1410 
#define DMA4TSEL_8             (8*0x0001u)    /* DMA channel 4 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1411 
#define DMA4TSEL_9             (9*0x0001u)    /* DMA channel 4 transfer select 9:  Reserved */
1412 
#define DMA4TSEL_10            (10*0x0001u)   /* DMA channel 4 transfer select 10: Reserved */
1413 
#define DMA4TSEL_11            (11*0x0001u)   /* DMA channel 4 transfer select 11: Reserved */
1414 
#define DMA4TSEL_12            (12*0x0001u)   /* DMA channel 4 transfer select 12: Reserved */
1415 
#define DMA4TSEL_13            (13*0x0001u)   /* DMA channel 4 transfer select 13: Reserved */
1416 
#define DMA4TSEL_14            (14*0x0001u)   /* DMA channel 4 transfer select 14: Reserved */
1417 
#define DMA4TSEL_15            (15*0x0001u)   /* DMA channel 4 transfer select 15: Reserved */
1418 
#define DMA4TSEL_16            (16*0x0001u)   /* DMA channel 4 transfer select 16: USCIA0 receive */
1419 
#define DMA4TSEL_17            (17*0x0001u)   /* DMA channel 4 transfer select 17: USCIA0 transmit */
1420 
#define DMA4TSEL_18            (18*0x0001u)   /* DMA channel 4 transfer select 18: USCIB0 receive */
1421 
#define DMA4TSEL_19            (19*0x0001u)   /* DMA channel 4 transfer select 19: USCIB0 transmit */
1422 
#define DMA4TSEL_20            (20*0x0001u)   /* DMA channel 4 transfer select 20: USCIA1 receive */
1423 
#define DMA4TSEL_21            (21*0x0001u)   /* DMA channel 4 transfer select 21: USCIA1 transmit */
1424 
#define DMA4TSEL_22            (22*0x0001u)   /* DMA channel 4 transfer select 22: USCIB1 receive */
1425 
#define DMA4TSEL_23            (23*0x0001u)   /* DMA channel 4 transfer select 23: USCIB1 transmit */
1426 
#define DMA4TSEL_24            (24*0x0001u)   /* DMA channel 4 transfer select 24: ADC12IFGx */
1427 
#define DMA4TSEL_25            (25*0x0001u)   /* DMA channel 4 transfer select 25: DAC12_0IFG */
1428 
#define DMA4TSEL_26            (26*0x0001u)   /* DMA channel 4 transfer select 26: DAC12_1IFG */
1429 
#define DMA4TSEL_27            (27*0x0001u)   /* DMA channel 4 transfer select 27: USB FNRXD */
1430 
#define DMA4TSEL_28            (28*0x0001u)   /* DMA channel 4 transfer select 28: USB ready */
1431 
#define DMA4TSEL_29            (29*0x0001u)   /* DMA channel 4 transfer select 29: Multiplier ready */
1432 
#define DMA4TSEL_30            (30*0x0001u)   /* DMA channel 4 transfer select 30: previous DMA channel DMA3IFG */
1433 
#define DMA4TSEL_31            (31*0x0001u)   /* DMA channel 4 transfer select 31: ext. Trigger (DMAE0) */
1434 
 
1435 
#define DMA5TSEL_0             (0*0x0100u)    /* DMA channel 5 transfer select 0:  DMA_REQ (sw) */
1436 
#define DMA5TSEL_1             (1*0x0100u)    /* DMA channel 5 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1437 
#define DMA5TSEL_2             (2*0x0100u)    /* DMA channel 5 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1438 
#define DMA5TSEL_3             (3*0x0100u)    /* DMA channel 5 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1439 
#define DMA5TSEL_4             (4*0x0100u)    /* DMA channel 5 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1440 
#define DMA5TSEL_5             (5*0x0100u)    /* DMA channel 5 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1441 
#define DMA5TSEL_6             (6*0x0100u)    /* DMA channel 5 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1442 
#define DMA5TSEL_7             (7*0x0001u)    /* DMA channel 5 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1443 
#define DMA5TSEL_8             (8*0x0001u)    /* DMA channel 5 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1444 
#define DMA5TSEL_9             (9*0x0100u)    /* DMA channel 5 transfer select 9:  Reserved */
1445 
#define DMA5TSEL_10            (10*0x0100u)   /* DMA channel 5 transfer select 10: Reserved */
1446 
#define DMA5TSEL_11            (11*0x0100u)   /* DMA channel 5 transfer select 11: Reserved */
1447 
#define DMA5TSEL_12            (12*0x0100u)   /* DMA channel 5 transfer select 12: Reserved */
1448 
#define DMA5TSEL_13            (13*0x0100u)   /* DMA channel 5 transfer select 13: Reserved */
1449 
#define DMA5TSEL_14            (14*0x0100u)   /* DMA channel 5 transfer select 14: Reserved */
1450 
#define DMA5TSEL_15            (15*0x0100u)   /* DMA channel 5 transfer select 15: Reserved */
1451 
#define DMA5TSEL_16            (16*0x0100u)   /* DMA channel 5 transfer select 16: USCIA0 receive */
1452 
#define DMA5TSEL_17            (17*0x0100u)   /* DMA channel 5 transfer select 17: USCIA0 transmit */
1453 
#define DMA5TSEL_18            (18*0x0100u)   /* DMA channel 5 transfer select 18: USCIB0 receive */
1454 
#define DMA5TSEL_19            (19*0x0100u)   /* DMA channel 5 transfer select 19: USCIB0 transmit */
1455 
#define DMA5TSEL_20            (20*0x0100u)   /* DMA channel 5 transfer select 20: USCIA1 receive */
1456 
#define DMA5TSEL_21            (21*0x0100u)   /* DMA channel 5 transfer select 21: USCIA1 transmit */
1457 
#define DMA5TSEL_22            (22*0x0100u)   /* DMA channel 5 transfer select 22: USCIB1 receive */
1458 
#define DMA5TSEL_23            (23*0x0100u)   /* DMA channel 5 transfer select 23: USCIB1 transmit */
1459 
#define DMA5TSEL_24            (24*0x0100u)   /* DMA channel 5 transfer select 24: ADC12IFGx */
1460 
#define DMA5TSEL_25            (25*0x0100u)   /* DMA channel 5 transfer select 25: DAC12_0IFG */
1461 
#define DMA5TSEL_26            (26*0x0100u)   /* DMA channel 5 transfer select 26: DAC12_1IFG */
1462 
#define DMA5TSEL_27            (27*0x0100u)   /* DMA channel 5 transfer select 27: USB FNRXD */
1463 
#define DMA5TSEL_28            (28*0x0100u)   /* DMA channel 5 transfer select 28: USB ready */
1464 
#define DMA5TSEL_29            (29*0x0100u)   /* DMA channel 5 transfer select 29: Multiplier ready */
1465 
#define DMA5TSEL_30            (30*0x0100u)   /* DMA channel 5 transfer select 30: previous DMA channel DMA4IFG */
1466 
#define DMA5TSEL_31            (31*0x0100u)   /* DMA channel 5 transfer select 31: ext. Trigger (DMAE0) */
1467 
 
1468 
#define DMA0TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
1469 
#define DMA0TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1470 
#define DMA0TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1471 
#define DMA0TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 0 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1472 
#define DMA0TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 0 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1473 
#define DMA0TSEL__TA2CCR0      (5*0x0001u)    /* DMA channel 0 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1474 
#define DMA0TSEL__TA2CCR2      (6*0x0001u)    /* DMA channel 0 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1475 
#define DMA0TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 0 transfer select 7:  TimerB0  (TB0CCR0.IFG) */
1476 
#define DMA0TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 0 transfer select 8:  TimerB0  (TB0CCR2.IFG) */
1477 
#define DMA0TSEL__RES9         (9*0x0001u)    /* DMA channel 0 transfer select 9:  Reserved */
1478 
#define DMA0TSEL__RES10        (10*0x0001u)   /* DMA channel 0 transfer select 10: Reserved */
1479 
#define DMA0TSEL__RES11        (11*0x0001u)   /* DMA channel 0 transfer select 11: Reserved */
1480 
#define DMA0TSEL__RES12        (12*0x0001u)   /* DMA channel 0 transfer select 12: Reserved */
1481 
#define DMA0TSEL__RES13        (13*0x0001u)   /* DMA channel 0 transfer select 13: Reserved */
1482 
#define DMA0TSEL__RES14        (14*0x0001u)   /* DMA channel 0 transfer select 14: Reserved */
1483 
#define DMA0TSEL__RES15        (15*0x0001u)   /* DMA channel 0 transfer select 15: Reserved */
1484 
#define DMA0TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 0 transfer select 16: USCIA0 receive */
1485 
#define DMA0TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 0 transfer select 17: USCIA0 transmit */
1486 
#define DMA0TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 0 transfer select 18: USCIB0 receive */
1487 
#define DMA0TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 0 transfer select 19: USCIB0 transmit */
1488 
#define DMA0TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 0 transfer select 20: USCIA1 receive */
1489 
#define DMA0TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 0 transfer select 21: USCIA1 transmit */
1490 
#define DMA0TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 0 transfer select 22: USCIB1 receive */
1491 
#define DMA0TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 0 transfer select 23: USCIB1 transmit */
1492 
#define DMA0TSEL__ADC12IFG     (24*0x0001u)   /* DMA channel 0 transfer select 24: ADC12IFGx */
1493 
#define DMA0TSEL__DAC12_0IFG   (25*0x0001u)   /* DMA channel 0 transfer select 25: DAC12_0IFG */
1494 
#define DMA0TSEL__DAC12_1IFG   (26*0x0001u)   /* DMA channel 0 transfer select 26: DAC12_1IFG */
1495 
#define DMA0TSEL__USB_FNRXD    (27*0x0001u)   /* DMA channel 0 transfer select 27: USB FNRXD */
1496 
#define DMA0TSEL__USB_READY    (28*0x0001u)   /* DMA channel 0 transfer select 28: USB ready */
1497 
#define DMA0TSEL__MPY          (29*0x0001u)   /* DMA channel 0 transfer select 29: Multiplier ready */
1498 
#define DMA0TSEL__DMA5IFG      (30*0x0001u)   /* DMA channel 0 transfer select 30: previous DMA channel DMA5IFG */
1499 
#define DMA0TSEL__DMAE0        (31*0x0001u)   /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
1500 
 
1501 
#define DMA1TSEL__DMA_REQ      (0*0x0100u)    /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
1502 
#define DMA1TSEL__TA0CCR0      (1*0x0100u)    /* DMA channel 1 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1503 
#define DMA1TSEL__TA0CCR2      (2*0x0100u)    /* DMA channel 1 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1504 
#define DMA1TSEL__TA1CCR0      (3*0x0100u)    /* DMA channel 1 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1505 
#define DMA1TSEL__TA1CCR2      (4*0x0100u)    /* DMA channel 1 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1506 
#define DMA1TSEL__TA2CCR0      (5*0x0100u)    /* DMA channel 1 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1507 
#define DMA1TSEL__TA2CCR2      (6*0x0100u)    /* DMA channel 1 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1508 
#define DMA1TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 1 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1509 
#define DMA1TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 1 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1510 
#define DMA1TSEL__RES9         (9*0x0100u)    /* DMA channel 1 transfer select 9:  Reserved */
1511 
#define DMA1TSEL__RES10        (10*0x0100u)   /* DMA channel 1 transfer select 10: Reserved */
1512 
#define DMA1TSEL__RES11        (11*0x0100u)   /* DMA channel 1 transfer select 11: Reserved */
1513 
#define DMA1TSEL__RES12        (12*0x0100u)   /* DMA channel 1 transfer select 12: Reserved */
1514 
#define DMA1TSEL__RES13        (13*0x0100u)   /* DMA channel 1 transfer select 13: Reserved */
1515 
#define DMA1TSEL__RES14        (14*0x0100u)   /* DMA channel 1 transfer select 14: Reserved */
1516 
#define DMA1TSEL__RES15        (15*0x0100u)   /* DMA channel 1 transfer select 15: Reserved */
1517 
#define DMA1TSEL__USCIA0RX     (16*0x0100u)   /* DMA channel 1 transfer select 16: USCIA0 receive */
1518 
#define DMA1TSEL__USCIA0TX     (17*0x0100u)   /* DMA channel 1 transfer select 17: USCIA0 transmit */
1519 
#define DMA1TSEL__USCIB0RX     (18*0x0100u)   /* DMA channel 1 transfer select 18: USCIB0 receive */
1520 
#define DMA1TSEL__USCIB0TX     (19*0x0100u)   /* DMA channel 1 transfer select 19: USCIB0 transmit */
1521 
#define DMA1TSEL__USCIA1RX     (20*0x0100u)   /* DMA channel 1 transfer select 20: USCIA1 receive */
1522 
#define DMA1TSEL__USCIA1TX     (21*0x0100u)   /* DMA channel 1 transfer select 21: USCIA1 transmit */
1523 
#define DMA1TSEL__USCIB1RX     (22*0x0100u)   /* DMA channel 1 transfer select 22: USCIB1 receive */
1524 
#define DMA1TSEL__USCIB1TX     (23*0x0100u)   /* DMA channel 1 transfer select 23: USCIB1 transmit */
1525 
#define DMA1TSEL__ADC12IFG     (24*0x0100u)   /* DMA channel 1 transfer select 24: ADC12IFGx */
1526 
#define DMA1TSEL__DAC12_0IFG   (25*0x0100u)   /* DMA channel 1 transfer select 25: DAC12_0IFG */
1527 
#define DMA1TSEL__DAC12_1IFG   (26*0x0100u)   /* DMA channel 1 transfer select 26: DAC12_1IFG */
1528 
#define DMA1TSEL__USB_FNRXD    (27*0x0100u)   /* DMA channel 1 transfer select 27: USB FNRXD */
1529 
#define DMA1TSEL__USB_READY    (28*0x0100u)   /* DMA channel 1 transfer select 28: USB ready */
1530 
#define DMA1TSEL__MPY          (29*0x0100u)   /* DMA channel 1 transfer select 29: Multiplier ready */
1531 
#define DMA1TSEL__DMA0IFG      (30*0x0100u)   /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
1532 
#define DMA1TSEL__DMAE0        (31*0x0100u)   /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
1533 
 
1534 
#define DMA2TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
1535 
#define DMA2TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 2 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1536 
#define DMA2TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 2 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1537 
#define DMA2TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 2 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1538 
#define DMA2TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 2 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1539 
#define DMA2TSEL__TA2CCR0      (5*0x0001u)    /* DMA channel 2 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1540 
#define DMA2TSEL__TA2CCR2      (6*0x0001u)    /* DMA channel 2 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1541 
#define DMA2TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 2 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1542 
#define DMA2TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 2 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1543 
#define DMA2TSEL__RES9         (9*0x0001u)    /* DMA channel 2 transfer select 9:  Reserved */
1544 
#define DMA2TSEL__RES10        (10*0x0001u)   /* DMA channel 2 transfer select 10: Reserved */
1545 
#define DMA2TSEL__RES11        (11*0x0001u)   /* DMA channel 2 transfer select 11: Reserved */
1546 
#define DMA2TSEL__RES12        (12*0x0001u)   /* DMA channel 2 transfer select 12: Reserved */
1547 
#define DMA2TSEL__RES13        (13*0x0001u)   /* DMA channel 2 transfer select 13: Reserved */
1548 
#define DMA2TSEL__RES14        (14*0x0001u)   /* DMA channel 2 transfer select 14: Reserved */
1549 
#define DMA2TSEL__RES15        (15*0x0001u)   /* DMA channel 2 transfer select 15: Reserved */
1550 
#define DMA2TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 2 transfer select 16: USCIA0 receive */
1551 
#define DMA2TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 2 transfer select 17: USCIA0 transmit */
1552 
#define DMA2TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 2 transfer select 18: USCIB0 receive */
1553 
#define DMA2TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 2 transfer select 19: USCIB0 transmit */
1554 
#define DMA2TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 2 transfer select 20: USCIA1 receive */
1555 
#define DMA2TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 2 transfer select 21: USCIA1 transmit */
1556 
#define DMA2TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 2 transfer select 22: USCIB1 receive */
1557 
#define DMA2TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 2 transfer select 23: USCIB1 transmit */
1558 
#define DMA2TSEL__ADC12IFG     (24*0x0001u)   /* DMA channel 2 transfer select 24: ADC12IFGx */
1559 
#define DMA2TSEL__DAC12_0IFG   (25*0x0001u)   /* DMA channel 2 transfer select 25: DAC12_0IFG */
1560 
#define DMA2TSEL__DAC12_1IFG   (26*0x0001u)   /* DMA channel 2 transfer select 26: DAC12_1IFG */
1561 
#define DMA2TSEL__USB_FNRXD    (27*0x0001u)   /* DMA channel 2 transfer select 27: USB FNRXD */
1562 
#define DMA2TSEL__USB_READY    (28*0x0001u)   /* DMA channel 2 transfer select 28: USB ready */
1563 
#define DMA2TSEL__MPY          (29*0x0001u)   /* DMA channel 2 transfer select 29: Multiplier ready */
1564 
#define DMA2TSEL__DMA1IFG      (30*0x0001u)   /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
1565 
#define DMA2TSEL__DMAE0        (31*0x0001u)   /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
1566 
 
1567 
#define DMA3TSEL__DMA_REQ      (0*0x0100u)    /* DMA channel 3 transfer select 0:  DMA_REQ (sw) */
1568 
#define DMA3TSEL__TA0CCR0      (1*0x0100u)    /* DMA channel 3 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1569 
#define DMA3TSEL__TA0CCR2      (2*0x0100u)    /* DMA channel 3 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1570 
#define DMA3TSEL__TA1CCR0      (3*0x0100u)    /* DMA channel 3 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1571 
#define DMA3TSEL__TA1CCR2      (4*0x0100u)    /* DMA channel 3 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1572 
#define DMA3TSEL__TA2CCR0      (5*0x0100u)    /* DMA channel 3 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1573 
#define DMA3TSEL__TA2CCR2      (6*0x0100u)    /* DMA channel 3 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1574 
#define DMA3TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 3 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1575 
#define DMA3TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 3 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1576 
#define DMA3TSEL__RES9         (9*0x0100u)    /* DMA channel 3 transfer select 9:  Reserved */
1577 
#define DMA3TSEL__RES10        (10*0x0100u)   /* DMA channel 3 transfer select 10: Reserved */
1578 
#define DMA3TSEL__RES11        (11*0x0100u)   /* DMA channel 3 transfer select 11: Reserved */
1579 
#define DMA3TSEL__RES12        (12*0x0100u)   /* DMA channel 3 transfer select 12: Reserved */
1580 
#define DMA3TSEL__RES13        (13*0x0100u)   /* DMA channel 3 transfer select 13: Reserved */
1581 
#define DMA3TSEL__RES14        (14*0x0100u)   /* DMA channel 3 transfer select 14: Reserved */
1582 
#define DMA3TSEL__RES15        (15*0x0100u)   /* DMA channel 3 transfer select 15: Reserved */
1583 
#define DMA3TSEL__USCIA0RX     (16*0x0100u)   /* DMA channel 3 transfer select 16: USCIA0 receive */
1584 
#define DMA3TSEL__USCIA0TX     (17*0x0100u)   /* DMA channel 3 transfer select 17: USCIA0 transmit */
1585 
#define DMA3TSEL__USCIB0RX     (18*0x0100u)   /* DMA channel 3 transfer select 18: USCIB0 receive */
1586 
#define DMA3TSEL__USCIB0TX     (19*0x0100u)   /* DMA channel 3 transfer select 19: USCIB0 transmit */
1587 
#define DMA3TSEL__USCIA1RX     (20*0x0100u)   /* DMA channel 3 transfer select 20: USCIA1 receive */
1588 
#define DMA3TSEL__USCIA1TX     (21*0x0100u)   /* DMA channel 3 transfer select 21: USCIA1 transmit */
1589 
#define DMA3TSEL__USCIB1RX     (22*0x0100u)   /* DMA channel 3 transfer select 22: USCIB1 receive */
1590 
#define DMA3TSEL__USCIB1TX     (23*0x0100u)   /* DMA channel 3 transfer select 23: USCIB1 transmit */
1591 
#define DMA3TSEL__ADC12IFG     (24*0x0100u)   /* DMA channel 3 transfer select 24: ADC12IFGx */
1592 
#define DMA3TSEL__DAC12_0IFG   (25*0x0100u)   /* DMA channel 3 transfer select 25: DAC12_0IFG */
1593 
#define DMA3TSEL__DAC12_1IFG   (26*0x0100u)   /* DMA channel 3 transfer select 26: DAC12_1IFG */
1594 
#define DMA3TSEL__USB_FNRXD    (27*0x0100u)   /* DMA channel 3 transfer select 27: USB FNRXD */
1595 
#define DMA3TSEL__USB_READY    (28*0x0100u)   /* DMA channel 3 transfer select 28: USB ready */
1596 
#define DMA3TSEL__MPY          (29*0x0100u)   /* DMA channel 3 transfer select 29: Multiplier ready */
1597 
#define DMA3TSEL__DMA2IFG      (30*0x0100u)   /* DMA channel 3 transfer select 30: previous DMA channel DMA2IFG */
1598 
#define DMA3TSEL__DMAE0        (31*0x0100u)   /* DMA channel 3 transfer select 31: ext. Trigger (DMAE0) */
1599 
 
1600 
#define DMA4TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 4 transfer select 0:  DMA_REQ (sw) */
1601 
#define DMA4TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 4 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1602 
#define DMA4TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 4 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1603 
#define DMA4TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 4 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1604 
#define DMA4TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 4 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1605 
#define DMA4TSEL__TA2CCR0      (5*0x0001u)    /* DMA channel 4 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1606 
#define DMA4TSEL__TA2CCR2      (6*0x0001u)    /* DMA channel 4 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1607 
#define DMA4TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 4 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1608 
#define DMA4TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 4 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1609 
#define DMA4TSEL__RES9         (9*0x0001u)    /* DMA channel 4 transfer select 9:  Reserved */
1610 
#define DMA4TSEL__RES10        (10*0x0001u)   /* DMA channel 4 transfer select 10: Reserved */
1611 
#define DMA4TSEL__RES11        (11*0x0001u)   /* DMA channel 4 transfer select 11: Reserved */
1612 
#define DMA4TSEL__RES12        (12*0x0001u)   /* DMA channel 4 transfer select 12: Reserved */
1613 
#define DMA4TSEL__RES13        (13*0x0001u)   /* DMA channel 4 transfer select 13: Reserved */
1614 
#define DMA4TSEL__RES14        (14*0x0001u)   /* DMA channel 4 transfer select 14: Reserved */
1615 
#define DMA4TSEL__RES15        (15*0x0001u)   /* DMA channel 4 transfer select 15: Reserved */
1616 
#define DMA4TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 4 transfer select 16: USCIA0 receive */
1617 
#define DMA4TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 4 transfer select 17: USCIA0 transmit */
1618 
#define DMA4TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 4 transfer select 18: USCIB0 receive */
1619 
#define DMA4TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 4 transfer select 19: USCIB0 transmit */
1620 
#define DMA4TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 4 transfer select 20: USCIA1 receive */
1621 
#define DMA4TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 4 transfer select 21: USCIA1 transmit */
1622 
#define DMA4TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 4 transfer select 22: USCIB1 receive */
1623 
#define DMA4TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 4 transfer select 23: USCIB1 transmit */
1624 
#define DMA4TSEL__ADC12IFG     (24*0x0001u)   /* DMA channel 4 transfer select 24: ADC12IFGx */
1625 
#define DMA4TSEL__DAC12_0IFG   (25*0x0001u)   /* DMA channel 4 transfer select 25: DAC12_0IFG */
1626 
#define DMA4TSEL__DAC12_1IFG   (26*0x0001u)   /* DMA channel 4 transfer select 26: DAC12_1IFG */
1627 
#define DMA4TSEL__USB_FNRXD    (27*0x0001u)   /* DMA channel 4 transfer select 27: USB FNRXD */
1628 
#define DMA4TSEL__USB_READY    (28*0x0001u)   /* DMA channel 4 transfer select 28: USB ready */
1629 
#define DMA4TSEL__MPY          (29*0x0001u)   /* DMA channel 4 transfer select 29: Multiplier ready */
1630 
#define DMA4TSEL__DMA3IFG      (30*0x0001u)   /* DMA channel 4 transfer select 30: previous DMA channel DMA3IFG */
1631 
#define DMA4TSEL__DMAE0        (31*0x0001u)   /* DMA channel 4 transfer select 31: ext. Trigger (DMAE0) */
1632 
 
1633 
#define DMA5TSEL__DMA_REQ      (0*0x0100u)    /* DMA channel 5 transfer select 0:  DMA_REQ (sw) */
1634 
#define DMA5TSEL__TA0CCR0      (1*0x0100u)    /* DMA channel 5 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1635 
#define DMA5TSEL__TA0CCR2      (2*0x0100u)    /* DMA channel 5 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1636 
#define DMA5TSEL__TA1CCR0      (3*0x0100u)    /* DMA channel 5 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1637 
#define DMA5TSEL__TA1CCR2      (4*0x0100u)    /* DMA channel 5 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1638 
#define DMA5TSEL__TA2CCR0      (5*0x0100u)    /* DMA channel 5 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1639 
#define DMA5TSEL__TA2CCR2      (6*0x0100u)    /* DMA channel 5 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1640 
#define DMA5TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 5 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1641 
#define DMA5TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 5 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1642 
#define DMA5TSEL__RES9         (9*0x0100u)    /* DMA channel 5 transfer select 9:  Reserved */
1643 
#define DMA5TSEL__RES10        (10*0x0100u)   /* DMA channel 5 transfer select 10: Reserved */
1644 
#define DMA5TSEL__RES11        (11*0x0100u)   /* DMA channel 5 transfer select 11: Reserved */
1645 
#define DMA5TSEL__RES12        (12*0x0100u)   /* DMA channel 5 transfer select 12: Reserved */
1646 
#define DMA5TSEL__RES13        (13*0x0100u)   /* DMA channel 5 transfer select 13: Reserved */
1647 
#define DMA5TSEL__RES14        (14*0x0100u)   /* DMA channel 5 transfer select 14: Reserved */
1648 
#define DMA5TSEL__RES15        (15*0x0100u)   /* DMA channel 5 transfer select 15: Reserved */
1649 
#define DMA5TSEL__USCIA0RX     (16*0x0100u)   /* DMA channel 5 transfer select 16: USCIA0 receive */
1650 
#define DMA5TSEL__USCIA0TX     (17*0x0100u)   /* DMA channel 5 transfer select 17: USCIA0 transmit */
1651 
#define DMA5TSEL__USCIB0RX     (18*0x0100u)   /* DMA channel 5 transfer select 18: USCIB0 receive */
1652 
#define DMA5TSEL__USCIB0TX     (19*0x0100u)   /* DMA channel 5 transfer select 19: USCIB0 transmit */
1653 
#define DMA5TSEL__USCIA1RX     (20*0x0100u)   /* DMA channel 5 transfer select 20: USCIA1 receive */
1654 
#define DMA5TSEL__USCIA1TX     (21*0x0100u)   /* DMA channel 5 transfer select 21: USCIA1 transmit */
1655 
#define DMA5TSEL__USCIB1RX     (22*0x0100u)   /* DMA channel 5 transfer select 22: USCIB1 receive */
1656 
#define DMA5TSEL__USCIB1TX     (23*0x0100u)   /* DMA channel 5 transfer select 23: USCIB1 transmit */
1657 
#define DMA5TSEL__ADC12IFG     (24*0x0100u)   /* DMA channel 5 transfer select 24: ADC12IFGx */
1658 
#define DMA5TSEL__DAC12_0IFG   (25*0x0100u)   /* DMA channel 5 transfer select 25: DAC12_0IFG */
1659 
#define DMA5TSEL__DAC12_1IFG   (26*0x0100u)   /* DMA channel 5 transfer select 26: DAC12_1IFG */
1660 
#define DMA5TSEL__USB_FNRXD    (27*0x0100u)   /* DMA channel 5 transfer select 27: USB FNRXD */
1661 
#define DMA5TSEL__USB_READY    (28*0x0100u)   /* DMA channel 5 transfer select 28: USB ready */
1662 
#define DMA5TSEL__MPY          (29*0x0100u)   /* DMA channel 5 transfer select 29: Multiplier ready */
1663 
#define DMA5TSEL__DMA4IFG      (30*0x0100u)   /* DMA channel 5 transfer select 30: previous DMA channel DMA4IFG */
1664 
#define DMA5TSEL__DMAE0        (31*0x0100u)   /* DMA channel 5 transfer select 31: ext. Trigger (DMAE0) */
1665 
 
1666 
/*************************************************************
1667 
* Flash Memory
1668 
*************************************************************/
1669 
#define __MSP430_HAS_FLASH__                  /* Definition to show that Module is available */
1670 
#define __MSP430_BASEADDRESS_FLASH__ 0x0140
1671 
 
1672 
SFR_16BIT(FCTL1);                             /* FLASH Control 1 */
1673 
SFR_8BIT(FCTL1_L);                            /* FLASH Control 1 */
1674 
SFR_8BIT(FCTL1_H);                            /* FLASH Control 1 */
1675 
//sfrbw    FCTL2               (0x0142)  /* FLASH Control 2 */
1676 
SFR_16BIT(FCTL3);                             /* FLASH Control 3 */
1677 
SFR_8BIT(FCTL3_L);                            /* FLASH Control 3 */
1678 
SFR_8BIT(FCTL3_H);                            /* FLASH Control 3 */
1679 
SFR_16BIT(FCTL4);                             /* FLASH Control 4 */
1680 
SFR_8BIT(FCTL4_L);                            /* FLASH Control 4 */
1681 
SFR_8BIT(FCTL4_H);                            /* FLASH Control 4 */
1682 
 
1683 
#define FRPW                   (0x9600)       /* Flash password returned by read */
1684 
#define FWPW                   (0xA500)       /* Flash password for write */
1685 
#define FXPW                   (0x3300)       /* for use with XOR instruction */
1686 
#define FRKEY                  (0x9600)       /* (legacy definition) Flash key returned by read */
1687 
#define FWKEY                  (0xA500)       /* (legacy definition) Flash key for write */
1688 
#define FXKEY                  (0x3300)       /* (legacy definition) for use with XOR instruction */
1689 
 
1690 
/* FCTL1 Control Bits */
1691 
//#define RESERVED            (0x0001)  /* Reserved */
1692 
#define ERASE                  (0x0002)       /* Enable bit for Flash segment erase */
1693 
#define MERAS                  (0x0004)       /* Enable bit for Flash mass erase */
1694 
//#define RESERVED            (0x0008)  /* Reserved */
1695 
//#define RESERVED            (0x0010)  /* Reserved */
1696 
#define SWRT                   (0x0020)       /* Smart Write enable */
1697 
#define WRT                    (0x0040)       /* Enable bit for Flash write */
1698 
#define BLKWRT                 (0x0080)       /* Enable bit for Flash segment write */
1699 
 
1700 
/* FCTL1 Control Bits */
1701 
//#define RESERVED            (0x0001)  /* Reserved */
1702 
#define ERASE_L                (0x0002)       /* Enable bit for Flash segment erase */
1703 
#define MERAS_L                (0x0004)       /* Enable bit for Flash mass erase */
1704 
//#define RESERVED            (0x0008)  /* Reserved */
1705 
//#define RESERVED            (0x0010)  /* Reserved */
1706 
#define SWRT_L                 (0x0020)       /* Smart Write enable */
1707 
#define WRT_L                  (0x0040)       /* Enable bit for Flash write */
1708 
#define BLKWRT_L               (0x0080)       /* Enable bit for Flash segment write */
1709 
 
1710 
/* FCTL1 Control Bits */
1711 
//#define RESERVED            (0x0001)  /* Reserved */
1712 
//#define RESERVED            (0x0008)  /* Reserved */
1713 
//#define RESERVED            (0x0010)  /* Reserved */
1714 
 
1715 
/* FCTL3 Control Bits */
1716 
#define BUSY                   (0x0001)       /* Flash busy: 1 */
1717 
#define KEYV                   (0x0002)       /* Flash Key violation flag */
1718 
#define ACCVIFG                (0x0004)       /* Flash Access violation flag */
1719 
#define WAIT                   (0x0008)       /* Wait flag for segment write */
1720 
#define LOCK                   (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
1721 
#define EMEX                   (0x0020)       /* Flash Emergency Exit */
1722 
#define LOCKA                  (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
1723 
//#define RESERVED            (0x0080)  /* Reserved */
1724 
 
1725 
/* FCTL3 Control Bits */
1726 
#define BUSY_L                 (0x0001)       /* Flash busy: 1 */
1727 
#define KEYV_L                 (0x0002)       /* Flash Key violation flag */
1728 
#define ACCVIFG_L              (0x0004)       /* Flash Access violation flag */
1729 
#define WAIT_L                 (0x0008)       /* Wait flag for segment write */
1730 
#define LOCK_L                 (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
1731 
#define EMEX_L                 (0x0020)       /* Flash Emergency Exit */
1732 
#define LOCKA_L                (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
1733 
//#define RESERVED            (0x0080)  /* Reserved */
1734 
 
1735 
/* FCTL3 Control Bits */
1736 
//#define RESERVED            (0x0080)  /* Reserved */
1737 
 
1738 
/* FCTL4 Control Bits */
1739 
#define VPE                    (0x0001)       /* Voltage Changed during Program Error Flag */
1740 
#define MGR0                   (0x0010)       /* Marginal read 0 mode. */
1741 
#define MGR1                   (0x0020)       /* Marginal read 1 mode. */
1742 
#define LOCKINFO               (0x0080)       /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
1743 
 
1744 
/* FCTL4 Control Bits */
1745 
#define VPE_L                  (0x0001)       /* Voltage Changed during Program Error Flag */
1746 
#define MGR0_L                 (0x0010)       /* Marginal read 0 mode. */
1747 
#define MGR1_L                 (0x0020)       /* Marginal read 1 mode. */
1748 
#define LOCKINFO_L             (0x0080)       /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
1749 
 
1750 
/* FCTL4 Control Bits */
1751 
 
1752 
/************************************************************
1753 
* HARDWARE MULTIPLIER 32Bit
1754 
************************************************************/
1755 
#define __MSP430_HAS_MPY32__                  /* Definition to show that Module is available */
1756 
#define __MSP430_BASEADDRESS_MPY32__ 0x04C0
1757 
 
1758 
SFR_16BIT(MPY);                               /* Multiply Unsigned/Operand 1 */
1759 
SFR_8BIT(MPY_L);                              /* Multiply Unsigned/Operand 1 */
1760 
SFR_8BIT(MPY_H);                              /* Multiply Unsigned/Operand 1 */
1761 
SFR_16BIT(MPYS);                              /* Multiply Signed/Operand 1 */
1762 
SFR_8BIT(MPYS_L);                             /* Multiply Signed/Operand 1 */
1763 
SFR_8BIT(MPYS_H);                             /* Multiply Signed/Operand 1 */
1764 
SFR_16BIT(MAC);                               /* Multiply Unsigned and Accumulate/Operand 1 */
1765 
SFR_8BIT(MAC_L);                              /* Multiply Unsigned and Accumulate/Operand 1 */
1766 
SFR_8BIT(MAC_H);                              /* Multiply Unsigned and Accumulate/Operand 1 */
1767 
SFR_16BIT(MACS);                              /* Multiply Signed and Accumulate/Operand 1 */
1768 
SFR_8BIT(MACS_L);                             /* Multiply Signed and Accumulate/Operand 1 */
1769 
SFR_8BIT(MACS_H);                             /* Multiply Signed and Accumulate/Operand 1 */
1770 
SFR_16BIT(OP2);                               /* Operand 2 */
1771 
SFR_8BIT(OP2_L);                              /* Operand 2 */
1772 
SFR_8BIT(OP2_H);                              /* Operand 2 */
1773 
SFR_16BIT(RESLO);                             /* Result Low Word */
1774 
SFR_8BIT(RESLO_L);                            /* Result Low Word */
1775 
SFR_8BIT(RESLO_H);                            /* Result Low Word */
1776 
SFR_16BIT(RESHI);                             /* Result High Word */
1777 
SFR_8BIT(RESHI_L);                            /* Result High Word */
1778 
SFR_8BIT(RESHI_H);                            /* Result High Word */
1779 
SFR_16BIT(SUMEXT);                            /* Sum Extend */
1780 
SFR_8BIT(SUMEXT_L);                           /* Sum Extend */
1781 
SFR_8BIT(SUMEXT_H);                           /* Sum Extend */
1782 
 
1783 
SFR_16BIT(MPY32L);                            /* 32-bit operand 1 - multiply - low word */
1784 
SFR_8BIT(MPY32L_L);                           /* 32-bit operand 1 - multiply - low word */
1785 
SFR_8BIT(MPY32L_H);                           /* 32-bit operand 1 - multiply - low word */
1786 
SFR_16BIT(MPY32H);                            /* 32-bit operand 1 - multiply - high word */
1787 
SFR_8BIT(MPY32H_L);                           /* 32-bit operand 1 - multiply - high word */
1788 
SFR_8BIT(MPY32H_H);                           /* 32-bit operand 1 - multiply - high word */
1789 
SFR_16BIT(MPYS32L);                           /* 32-bit operand 1 - signed multiply - low word */
1790 
SFR_8BIT(MPYS32L_L);                          /* 32-bit operand 1 - signed multiply - low word */
1791 
SFR_8BIT(MPYS32L_H);                          /* 32-bit operand 1 - signed multiply - low word */
1792 
SFR_16BIT(MPYS32H);                           /* 32-bit operand 1 - signed multiply - high word */
1793 
SFR_8BIT(MPYS32H_L);                          /* 32-bit operand 1 - signed multiply - high word */
1794 
SFR_8BIT(MPYS32H_H);                          /* 32-bit operand 1 - signed multiply - high word */
1795 
SFR_16BIT(MAC32L);                            /* 32-bit operand 1 - multiply accumulate - low word */
1796 
SFR_8BIT(MAC32L_L);                           /* 32-bit operand 1 - multiply accumulate - low word */
1797 
SFR_8BIT(MAC32L_H);                           /* 32-bit operand 1 - multiply accumulate - low word */
1798 
SFR_16BIT(MAC32H);                            /* 32-bit operand 1 - multiply accumulate - high word */
1799 
SFR_8BIT(MAC32H_L);                           /* 32-bit operand 1 - multiply accumulate - high word */
1800 
SFR_8BIT(MAC32H_H);                           /* 32-bit operand 1 - multiply accumulate - high word */
1801 
SFR_16BIT(MACS32L);                           /* 32-bit operand 1 - signed multiply accumulate - low word */
1802 
SFR_8BIT(MACS32L_L);                          /* 32-bit operand 1 - signed multiply accumulate - low word */
1803 
SFR_8BIT(MACS32L_H);                          /* 32-bit operand 1 - signed multiply accumulate - low word */
1804 
SFR_16BIT(MACS32H);                           /* 32-bit operand 1 - signed multiply accumulate - high word */
1805 
SFR_8BIT(MACS32H_L);                          /* 32-bit operand 1 - signed multiply accumulate - high word */
1806 
SFR_8BIT(MACS32H_H);                          /* 32-bit operand 1 - signed multiply accumulate - high word */
1807 
SFR_16BIT(OP2L);                              /* 32-bit operand 2 - low word */
1808 
SFR_8BIT(OP2L_L);                             /* 32-bit operand 2 - low word */
1809 
SFR_8BIT(OP2L_H);                             /* 32-bit operand 2 - low word */
1810 
SFR_16BIT(OP2H);                              /* 32-bit operand 2 - high word */
1811 
SFR_8BIT(OP2H_L);                             /* 32-bit operand 2 - high word */
1812 
SFR_8BIT(OP2H_H);                             /* 32-bit operand 2 - high word */
1813 
SFR_16BIT(RES0);                              /* 32x32-bit result 0 - least significant word */
1814 
SFR_8BIT(RES0_L);                             /* 32x32-bit result 0 - least significant word */
1815 
SFR_8BIT(RES0_H);                             /* 32x32-bit result 0 - least significant word */
1816 
SFR_16BIT(RES1);                              /* 32x32-bit result 1 */
1817 
SFR_8BIT(RES1_L);                             /* 32x32-bit result 1 */
1818 
SFR_8BIT(RES1_H);                             /* 32x32-bit result 1 */
1819 
SFR_16BIT(RES2);                              /* 32x32-bit result 2 */
1820 
SFR_8BIT(RES2_L);                             /* 32x32-bit result 2 */
1821 
SFR_8BIT(RES2_H);                             /* 32x32-bit result 2 */
1822 
SFR_16BIT(RES3);                              /* 32x32-bit result 3 - most significant word */
1823 
SFR_8BIT(RES3_L);                             /* 32x32-bit result 3 - most significant word */
1824 
SFR_8BIT(RES3_H);                             /* 32x32-bit result 3 - most significant word */
1825 
SFR_16BIT(MPY32CTL0);                         /* MPY32 Control Register 0 */
1826 
SFR_8BIT(MPY32CTL0_L);                        /* MPY32 Control Register 0 */
1827 
SFR_8BIT(MPY32CTL0_H);                        /* MPY32 Control Register 0 */
1828 
 
1829 
#define MPY_B                  MPY_L          /* Multiply Unsigned/Operand 1 (Byte Access) */
1830 
#define MPYS_B                 MPYS_L         /* Multiply Signed/Operand 1 (Byte Access) */
1831 
#define MAC_B                  MAC_L          /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
1832 
#define MACS_B                 MACS_L         /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
1833 
#define OP2_B                  OP2_L          /* Operand 2 (Byte Access) */
1834 
#define MPY32L_B               MPY32L_L       /* 32-bit operand 1 - multiply - low word (Byte Access) */
1835 
#define MPY32H_B               MPY32H_L       /* 32-bit operand 1 - multiply - high word (Byte Access) */
1836 
#define MPYS32L_B              MPYS32L_L      /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
1837 
#define MPYS32H_B              MPYS32H_L      /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
1838 
#define MAC32L_B               MAC32L_L       /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
1839 
#define MAC32H_B               MAC32H_L       /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
1840 
#define MACS32L_B              MACS32L_L      /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
1841 
#define MACS32H_B              MACS32H_L      /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
1842 
#define OP2L_B                 OP2L_L         /* 32-bit operand 2 - low word (Byte Access) */
1843 
#define OP2H_B                 OP2H_L         /* 32-bit operand 2 - high word (Byte Access) */
1844 
 
1845 
/* MPY32CTL0 Control Bits */
1846 
#define MPYC                   (0x0001)       /* Carry of the multiplier */
1847 
//#define RESERVED            (0x0002)  /* Reserved */
1848 
#define MPYFRAC                (0x0004)       /* Fractional mode */
1849 
#define MPYSAT                 (0x0008)       /* Saturation mode */
1850 
#define MPYM0                  (0x0010)       /* Multiplier mode Bit:0 */
1851 
#define MPYM1                  (0x0020)       /* Multiplier mode Bit:1 */
1852 
#define OP1_32                 (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
1853 
#define OP2_32                 (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
1854 
#define MPYDLYWRTEN            (0x0100)       /* Delayed write enable */
1855 
#define MPYDLY32               (0x0200)       /* Delayed write mode */
1856 
 
1857 
/* MPY32CTL0 Control Bits */
1858 
#define MPYC_L                 (0x0001)       /* Carry of the multiplier */
1859 
//#define RESERVED            (0x0002)  /* Reserved */
1860 
#define MPYFRAC_L              (0x0004)       /* Fractional mode */
1861 
#define MPYSAT_L               (0x0008)       /* Saturation mode */
1862 
#define MPYM0_L                (0x0010)       /* Multiplier mode Bit:0 */
1863 
#define MPYM1_L                (0x0020)       /* Multiplier mode Bit:1 */
1864 
#define OP1_32_L               (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
1865 
#define OP2_32_L               (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
1866 
 
1867 
/* MPY32CTL0 Control Bits */
1868 
//#define RESERVED            (0x0002)  /* Reserved */
1869 
#define MPYDLYWRTEN_H          (0x0001)       /* Delayed write enable */
1870 
#define MPYDLY32_H             (0x0002)       /* Delayed write mode */
1871 
 
1872 
#define MPYM_0                 (0x0000)       /* Multiplier mode: MPY */
1873 
#define MPYM_1                 (0x0010)       /* Multiplier mode: MPYS */
1874 
#define MPYM_2                 (0x0020)       /* Multiplier mode: MAC */
1875 
#define MPYM_3                 (0x0030)       /* Multiplier mode: MACS */
1876 
#define MPYM__MPY              (0x0000)       /* Multiplier mode: MPY */
1877 
#define MPYM__MPYS             (0x0010)       /* Multiplier mode: MPYS */
1878 
#define MPYM__MAC              (0x0020)       /* Multiplier mode: MAC */
1879 
#define MPYM__MACS             (0x0030)       /* Multiplier mode: MACS */
1880 
 
1881 
/************************************************************
1882 
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
1883 
************************************************************/
1884 
#define __MSP430_HAS_PORT1_R__                /* Definition to show that Module is available */
1885 
#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
1886 
#define __MSP430_HAS_PORT2_R__                /* Definition to show that Module is available */
1887 
#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
1888 
#define __MSP430_HAS_PORTA_R__                /* Definition to show that Module is available */
1889 
#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
1890 
 
1891 
SFR_16BIT(PAIN);                              /* Port A Input */
1892 
SFR_8BIT(PAIN_L);                             /* Port A Input */
1893 
SFR_8BIT(PAIN_H);                             /* Port A Input */
1894 
SFR_16BIT(PAOUT);                             /* Port A Output */
1895 
SFR_8BIT(PAOUT_L);                            /* Port A Output */
1896 
SFR_8BIT(PAOUT_H);                            /* Port A Output */
1897 
SFR_16BIT(PADIR);                             /* Port A Direction */
1898 
SFR_8BIT(PADIR_L);                            /* Port A Direction */
1899 
SFR_8BIT(PADIR_H);                            /* Port A Direction */
1900 
SFR_16BIT(PAREN);                             /* Port A Resistor Enable */
1901 
SFR_8BIT(PAREN_L);                            /* Port A Resistor Enable */
1902 
SFR_8BIT(PAREN_H);                            /* Port A Resistor Enable */
1903 
SFR_16BIT(PADS);                              /* Port A Resistor Drive Strenght */
1904 
SFR_8BIT(PADS_L);                             /* Port A Resistor Drive Strenght */
1905 
SFR_8BIT(PADS_H);                             /* Port A Resistor Drive Strenght */
1906 
SFR_16BIT(PASEL);                             /* Port A Selection */
1907 
SFR_8BIT(PASEL_L);                            /* Port A Selection */
1908 
SFR_8BIT(PASEL_H);                            /* Port A Selection */
1909 
SFR_16BIT(PAIES);                             /* Port A Interrupt Edge Select */
1910 
SFR_8BIT(PAIES_L);                            /* Port A Interrupt Edge Select */
1911 
SFR_8BIT(PAIES_H);                            /* Port A Interrupt Edge Select */
1912 
SFR_16BIT(PAIE);                              /* Port A Interrupt Enable */
1913 
SFR_8BIT(PAIE_L);                             /* Port A Interrupt Enable */
1914 
SFR_8BIT(PAIE_H);                             /* Port A Interrupt Enable */
1915 
SFR_16BIT(PAIFG);                             /* Port A Interrupt Flag */
1916 
SFR_8BIT(PAIFG_L);                            /* Port A Interrupt Flag */
1917 
SFR_8BIT(PAIFG_H);                            /* Port A Interrupt Flag */
1918 
 
1919 
 
1920 
SFR_16BIT(P1IV);                              /* Port 1 Interrupt Vector Word */
1921 
SFR_16BIT(P2IV);                              /* Port 2 Interrupt Vector Word */
1922 
#define P1IN                   (PAIN_L)       /* Port 1 Input */
1923 
#define P1OUT                  (PAOUT_L)      /* Port 1 Output */
1924 
#define P1DIR                  (PADIR_L)      /* Port 1 Direction */
1925 
#define P1REN                  (PAREN_L)      /* Port 1 Resistor Enable */
1926 
#define P1DS                   (PADS_L)       /* Port 1 Resistor Drive Strenght */
1927 
#define P1SEL                  (PASEL_L)      /* Port 1 Selection */
1928 
#define P1IES                  (PAIES_L)      /* Port 1 Interrupt Edge Select */
1929 
#define P1IE                   (PAIE_L)       /* Port 1 Interrupt Enable */
1930 
#define P1IFG                  (PAIFG_L)      /* Port 1 Interrupt Flag */
1931 
 
1932 
//Definitions for P1IV
1933 
#define P1IV_NONE              (0x0000)       /* No Interrupt pending */
1934 
#define P1IV_P1IFG0            (0x0002)       /* P1IV P1IFG.0 */
1935 
#define P1IV_P1IFG1            (0x0004)       /* P1IV P1IFG.1 */
1936 
#define P1IV_P1IFG2            (0x0006)       /* P1IV P1IFG.2 */
1937 
#define P1IV_P1IFG3            (0x0008)       /* P1IV P1IFG.3 */
1938 
#define P1IV_P1IFG4            (0x000A)       /* P1IV P1IFG.4 */
1939 
#define P1IV_P1IFG5            (0x000C)       /* P1IV P1IFG.5 */
1940 
#define P1IV_P1IFG6            (0x000E)       /* P1IV P1IFG.6 */
1941 
#define P1IV_P1IFG7            (0x0010)       /* P1IV P1IFG.7 */
1942 
 
1943 
#define P2IN                   (PAIN_H)       /* Port 2 Input */
1944 
#define P2OUT                  (PAOUT_H)      /* Port 2 Output */
1945 
#define P2DIR                  (PADIR_H)      /* Port 2 Direction */
1946 
#define P2REN                  (PAREN_H)      /* Port 2 Resistor Enable */
1947 
#define P2DS                   (PADS_H)       /* Port 2 Resistor Drive Strenght */
1948 
#define P2SEL                  (PASEL_H)      /* Port 2 Selection */
1949 
#define P2IES                  (PAIES_H)      /* Port 2 Interrupt Edge Select */
1950 
#define P2IE                   (PAIE_H)       /* Port 2 Interrupt Enable */
1951 
#define P2IFG                  (PAIFG_H)      /* Port 2 Interrupt Flag */
1952 
 
1953 
//Definitions for P2IV
1954 
#define P2IV_NONE              (0x0000)       /* No Interrupt pending */
1955 
#define P2IV_P2IFG0            (0x0002)       /* P2IV P2IFG.0 */
1956 
#define P2IV_P2IFG1            (0x0004)       /* P2IV P2IFG.1 */
1957 
#define P2IV_P2IFG2            (0x0006)       /* P2IV P2IFG.2 */
1958 
#define P2IV_P2IFG3            (0x0008)       /* P2IV P2IFG.3 */
1959 
#define P2IV_P2IFG4            (0x000A)       /* P2IV P2IFG.4 */
1960 
#define P2IV_P2IFG5            (0x000C)       /* P2IV P2IFG.5 */
1961 
#define P2IV_P2IFG6            (0x000E)       /* P2IV P2IFG.6 */
1962 
#define P2IV_P2IFG7            (0x0010)       /* P2IV P2IFG.7 */
1963 
 
1964 
 
1965 
/************************************************************
1966 
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
1967 
************************************************************/
1968 
#define __MSP430_HAS_PORT3_R__                /* Definition to show that Module is available */
1969 
#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220
1970 
#define __MSP430_HAS_PORT4_R__                /* Definition to show that Module is available */
1971 
#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220
1972 
#define __MSP430_HAS_PORTB_R__                /* Definition to show that Module is available */
1973 
#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220
1974 
 
1975 
SFR_16BIT(PBIN);                              /* Port B Input */
1976 
SFR_8BIT(PBIN_L);                             /* Port B Input */
1977 
SFR_8BIT(PBIN_H);                             /* Port B Input */
1978 
SFR_16BIT(PBOUT);                             /* Port B Output */
1979 
SFR_8BIT(PBOUT_L);                            /* Port B Output */
1980 
SFR_8BIT(PBOUT_H);                            /* Port B Output */
1981 
SFR_16BIT(PBDIR);                             /* Port B Direction */
1982 
SFR_8BIT(PBDIR_L);                            /* Port B Direction */
1983 
SFR_8BIT(PBDIR_H);                            /* Port B Direction */
1984 
SFR_16BIT(PBREN);                             /* Port B Resistor Enable */
1985 
SFR_8BIT(PBREN_L);                            /* Port B Resistor Enable */
1986 
SFR_8BIT(PBREN_H);                            /* Port B Resistor Enable */
1987 
SFR_16BIT(PBDS);                              /* Port B Resistor Drive Strenght */
1988 
SFR_8BIT(PBDS_L);                             /* Port B Resistor Drive Strenght */
1989 
SFR_8BIT(PBDS_H);                             /* Port B Resistor Drive Strenght */
1990 
SFR_16BIT(PBSEL);                             /* Port B Selection */
1991 
SFR_8BIT(PBSEL_L);                            /* Port B Selection */
1992 
SFR_8BIT(PBSEL_H);                            /* Port B Selection */
1993 
SFR_16BIT(PBIES);                             /* Port B Interrupt Edge Select */
1994 
SFR_8BIT(PBIES_L);                            /* Port B Interrupt Edge Select */
1995 
SFR_8BIT(PBIES_H);                            /* Port B Interrupt Edge Select */
1996 
SFR_16BIT(PBIE);                              /* Port B Interrupt Enable */
1997 
SFR_8BIT(PBIE_L);                             /* Port B Interrupt Enable */
1998 
SFR_8BIT(PBIE_H);                             /* Port B Interrupt Enable */
1999 
SFR_16BIT(PBIFG);                             /* Port B Interrupt Flag */
2000 
SFR_8BIT(PBIFG_L);                            /* Port B Interrupt Flag */
2001 
SFR_8BIT(PBIFG_H);                            /* Port B Interrupt Flag */
2002 
 
2003 
 
2004 
SFR_16BIT(P3IV);                              /* Port 3 Interrupt Vector Word */
2005 
SFR_16BIT(P4IV);                              /* Port 4 Interrupt Vector Word */
2006 
#define P3IN                   (PBIN_L)       /* Port 3 Input */
2007 
#define P3OUT                  (PBOUT_L)      /* Port 3 Output */
2008 
#define P3DIR                  (PBDIR_L)      /* Port 3 Direction */
2009 
#define P3REN                  (PBREN_L)      /* Port 3 Resistor Enable */
2010 
#define P3DS                   (PBDS_L)       /* Port 3 Resistor Drive Strenght */
2011 
#define P3SEL                  (PBSEL_L)      /* Port 3 Selection */
2012 
#define P3IES                  (PBIES_L)      /* Port 3 Interrupt Edge Select */
2013 
#define P3IE                   (PBIE_L)       /* Port 3 Interrupt Enable */
2014 
#define P3IFG                  (PBIFG_L)      /* Port 3 Interrupt Flag */
2015 
 
2016 
//Definitions for P3IV
2017 
#define P3IV_NONE              (0x0000)       /* No Interrupt pending */
2018 
#define P3IV_P3IFG0            (0x0002)       /* P3IV P3IFG.0 */
2019 
#define P3IV_P3IFG1            (0x0004)       /* P3IV P3IFG.1 */
2020 
#define P3IV_P3IFG2            (0x0006)       /* P3IV P3IFG.2 */
2021 
#define P3IV_P3IFG3            (0x0008)       /* P3IV P3IFG.3 */
2022 
#define P3IV_P3IFG4            (0x000A)       /* P3IV P3IFG.4 */
2023 
#define P3IV_P3IFG5            (0x000C)       /* P3IV P3IFG.5 */
2024 
#define P3IV_P3IFG6            (0x000E)       /* P3IV P3IFG.6 */
2025 
#define P3IV_P3IFG7            (0x0010)       /* P3IV P3IFG.7 */
2026 
 
2027 
#define P4IN                   (PBIN_H)       /* Port 4 Input */
2028 
#define P4OUT                  (PBOUT_H)      /* Port 4 Output */
2029 
#define P4DIR                  (PBDIR_H)      /* Port 4 Direction */
2030 
#define P4REN                  (PBREN_H)      /* Port 4 Resistor Enable */
2031 
#define P4DS                   (PBDS_H)       /* Port 4 Resistor Drive Strenght */
2032 
#define P4SEL                  (PBSEL_H)      /* Port 4 Selection */
2033 
#define P4IES                  (PBIES_H)      /* Port 4 Interrupt Edge Select */
2034 
#define P4IE                   (PBIE_H)       /* Port 4 Interrupt Enable */
2035 
#define P4IFG                  (PBIFG_H)      /* Port 4 Interrupt Flag */
2036 
 
2037 
//Definitions for P4IV
2038 
#define P4IV_NONE              (0x0000)       /* No Interrupt pending */
2039 
#define P4IV_P4IFG0            (0x0002)       /* P4IV P4IFG.0 */
2040 
#define P4IV_P4IFG1            (0x0004)       /* P4IV P4IFG.1 */
2041 
#define P4IV_P4IFG2            (0x0006)       /* P4IV P4IFG.2 */
2042 
#define P4IV_P4IFG3            (0x0008)       /* P4IV P4IFG.3 */
2043 
#define P4IV_P4IFG4            (0x000A)       /* P4IV P4IFG.4 */
2044 
#define P4IV_P4IFG5            (0x000C)       /* P4IV P4IFG.5 */
2045 
#define P4IV_P4IFG6            (0x000E)       /* P4IV P4IFG.6 */
2046 
#define P4IV_P4IFG7            (0x0010)       /* P4IV P4IFG.7 */
2047 
 
2048 
 
2049 
/************************************************************
2050 
* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
2051 
************************************************************/
2052 
#define __MSP430_HAS_PORT5_R__                /* Definition to show that Module is available */
2053 
#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240
2054 
#define __MSP430_HAS_PORT6_R__                /* Definition to show that Module is available */
2055 
#define __MSP430_BASEADDRESS_PORT6_R__ 0x0240
2056 
#define __MSP430_HAS_PORTC_R__                /* Definition to show that Module is available */
2057 
#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240
2058 
 
2059 
SFR_16BIT(PCIN);                              /* Port C Input */
2060 
SFR_8BIT(PCIN_L);                             /* Port C Input */
2061 
SFR_8BIT(PCIN_H);                             /* Port C Input */
2062 
SFR_16BIT(PCOUT);                             /* Port C Output */
2063 
SFR_8BIT(PCOUT_L);                            /* Port C Output */
2064 
SFR_8BIT(PCOUT_H);                            /* Port C Output */
2065 
SFR_16BIT(PCDIR);                             /* Port C Direction */
2066 
SFR_8BIT(PCDIR_L);                            /* Port C Direction */
2067 
SFR_8BIT(PCDIR_H);                            /* Port C Direction */
2068 
SFR_16BIT(PCREN);                             /* Port C Resistor Enable */
2069 
SFR_8BIT(PCREN_L);                            /* Port C Resistor Enable */
2070 
SFR_8BIT(PCREN_H);                            /* Port C Resistor Enable */
2071 
SFR_16BIT(PCDS);                              /* Port C Resistor Drive Strenght */
2072 
SFR_8BIT(PCDS_L);                             /* Port C Resistor Drive Strenght */
2073 
SFR_8BIT(PCDS_H);                             /* Port C Resistor Drive Strenght */
2074 
SFR_16BIT(PCSEL);                             /* Port C Selection */
2075 
SFR_8BIT(PCSEL_L);                            /* Port C Selection */
2076 
SFR_8BIT(PCSEL_H);                            /* Port C Selection */
2077 
 
2078 
 
2079 
#define P5IN                   (PCIN_L)       /* Port 5 Input */
2080 
#define P5OUT                  (PCOUT_L)      /* Port 5 Output */
2081 
#define P5DIR                  (PCDIR_L)      /* Port 5 Direction */
2082 
#define P5REN                  (PCREN_L)      /* Port 5 Resistor Enable */
2083 
#define P5DS                   (PCDS_L)       /* Port 5 Resistor Drive Strenght */
2084 
#define P5SEL                  (PCSEL_L)      /* Port 5 Selection */
2085 
 
2086 
#define P6IN                   (PCIN_H)       /* Port 6 Input */
2087 
#define P6OUT                  (PCOUT_H)      /* Port 6 Output */
2088 
#define P6DIR                  (PCDIR_H)      /* Port 6 Direction */
2089 
#define P6REN                  (PCREN_H)      /* Port 6 Resistor Enable */
2090 
#define P6DS                   (PCDS_H)       /* Port 6 Resistor Drive Strenght */
2091 
#define P6SEL                  (PCSEL_H)      /* Port 6 Selection */
2092 
 
2093 
 
2094 
/************************************************************
2095 
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
2096 
************************************************************/
2097 
#define __MSP430_HAS_PORT7_R__                /* Definition to show that Module is available */
2098 
#define __MSP430_BASEADDRESS_PORT7_R__ 0x0260
2099 
#define __MSP430_HAS_PORT8_R__                /* Definition to show that Module is available */
2100 
#define __MSP430_BASEADDRESS_PORT8_R__ 0x0260
2101 
#define __MSP430_HAS_PORTD_R__                /* Definition to show that Module is available */
2102 
#define __MSP430_BASEADDRESS_PORTD_R__ 0x0260
2103 
 
2104 
SFR_16BIT(PDIN);                              /* Port D Input */
2105 
SFR_8BIT(PDIN_L);                             /* Port D Input */
2106 
SFR_8BIT(PDIN_H);                             /* Port D Input */
2107 
SFR_16BIT(PDOUT);                             /* Port D Output */
2108 
SFR_8BIT(PDOUT_L);                            /* Port D Output */
2109 
SFR_8BIT(PDOUT_H);                            /* Port D Output */
2110 
SFR_16BIT(PDDIR);                             /* Port D Direction */
2111 
SFR_8BIT(PDDIR_L);                            /* Port D Direction */
2112 
SFR_8BIT(PDDIR_H);                            /* Port D Direction */
2113 
SFR_16BIT(PDREN);                             /* Port D Resistor Enable */
2114 
SFR_8BIT(PDREN_L);                            /* Port D Resistor Enable */
2115 
SFR_8BIT(PDREN_H);                            /* Port D Resistor Enable */
2116 
SFR_16BIT(PDDS);                              /* Port D Resistor Drive Strenght */
2117 
SFR_8BIT(PDDS_L);                             /* Port D Resistor Drive Strenght */
2118 
SFR_8BIT(PDDS_H);                             /* Port D Resistor Drive Strenght */
2119 
SFR_16BIT(PDSEL);                             /* Port D Selection */
2120 
SFR_8BIT(PDSEL_L);                            /* Port D Selection */
2121 
SFR_8BIT(PDSEL_H);                            /* Port D Selection */
2122 
 
2123 
 
2124 
#define P7IN                   (PDIN_L)       /* Port 7 Input */
2125 
#define P7OUT                  (PDOUT_L)      /* Port 7 Output */
2126 
#define P7DIR                  (PDDIR_L)      /* Port 7 Direction */
2127 
#define P7REN                  (PDREN_L)      /* Port 7 Resistor Enable */
2128 
#define P7DS                   (PDDS_L)       /* Port 7 Resistor Drive Strenght */
2129 
#define P7SEL                  (PDSEL_L)      /* Port 7 Selection */
2130 
 
2131 
#define P8IN                   (PDIN_H)       /* Port 8 Input */
2132 
#define P8OUT                  (PDOUT_H)      /* Port 8 Output */
2133 
#define P8DIR                  (PDDIR_H)      /* Port 8 Direction */
2134 
#define P8REN                  (PDREN_H)      /* Port 8 Resistor Enable */
2135 
#define P8DS                   (PDDS_H)       /* Port 8 Resistor Drive Strenght */
2136 
#define P8SEL                  (PDSEL_H)      /* Port 8 Selection */
2137 
 
2138 
 
2139 
/************************************************************
2140 
* DIGITAL I/O Port9 Pull up / Pull down Resistors
2141 
************************************************************/
2142 
#define __MSP430_HAS_PORT9_R__                /* Definition to show that Module is available */
2143 
#define __MSP430_BASEADDRESS_PORT9_R__ 0x0280
2144 
#define __MSP430_HAS_PORTE_R__                /* Definition to show that Module is available */
2145 
#define __MSP430_BASEADDRESS_PORTE_R__ 0x0280
2146 
 
2147 
SFR_16BIT(PEIN);                              /* Port E Input */
2148 
SFR_8BIT(PEIN_L);                             /* Port E Input */
2149 
SFR_8BIT(PEIN_H);                             /* Port E Input */
2150 
SFR_16BIT(PEOUT);                             /* Port E Output */
2151 
SFR_8BIT(PEOUT_L);                            /* Port E Output */
2152 
SFR_8BIT(PEOUT_H);                            /* Port E Output */
2153 
SFR_16BIT(PEDIR);                             /* Port E Direction */
2154 
SFR_8BIT(PEDIR_L);                            /* Port E Direction */
2155 
SFR_8BIT(PEDIR_H);                            /* Port E Direction */
2156 
SFR_16BIT(PEREN);                             /* Port E Resistor Enable */
2157 
SFR_8BIT(PEREN_L);                            /* Port E Resistor Enable */
2158 
SFR_8BIT(PEREN_H);                            /* Port E Resistor Enable */
2159 
SFR_16BIT(PEDS);                              /* Port E Resistor Drive Strenght */
2160 
SFR_8BIT(PEDS_L);                             /* Port E Resistor Drive Strenght */
2161 
SFR_8BIT(PEDS_H);                             /* Port E Resistor Drive Strenght */
2162 
SFR_16BIT(PESEL);                             /* Port E Selection */
2163 
SFR_8BIT(PESEL_L);                            /* Port E Selection */
2164 
SFR_8BIT(PESEL_H);                            /* Port E Selection */
2165 
 
2166 
 
2167 
#define P9IN                   (PEIN_L)       /* Port 9 Input */
2168 
#define P9OUT                  (PEOUT_L)      /* Port 9 Output */
2169 
#define P9DIR                  (PEDIR_L)      /* Port 9 Direction */
2170 
#define P9REN                  (PEREN_L)      /* Port 9 Resistor Enable */
2171 
#define P9DS                   (PEDS_L)       /* Port 9 Resistor Drive Strenght */
2172 
#define P9SEL                  (PESEL_L)      /* Port 9 Selection */
2173 
 
2174 
 
2175 
/************************************************************
2176 
* DIGITAL I/O PortJ Pull up / Pull down Resistors
2177 
************************************************************/
2178 
#define __MSP430_HAS_PORTJ_R__                /* Definition to show that Module is available */
2179 
#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320
2180 
 
2181 
SFR_16BIT(PJIN);                              /* Port J Input */
2182 
SFR_8BIT(PJIN_L);                             /* Port J Input */
2183 
SFR_8BIT(PJIN_H);                             /* Port J Input */
2184 
SFR_16BIT(PJOUT);                             /* Port J Output */
2185 
SFR_8BIT(PJOUT_L);                            /* Port J Output */
2186 
SFR_8BIT(PJOUT_H);                            /* Port J Output */
2187 
SFR_16BIT(PJDIR);                             /* Port J Direction */
2188 
SFR_8BIT(PJDIR_L);                            /* Port J Direction */
2189 
SFR_8BIT(PJDIR_H);                            /* Port J Direction */
2190 
SFR_16BIT(PJREN);                             /* Port J Resistor Enable */
2191 
SFR_8BIT(PJREN_L);                            /* Port J Resistor Enable */
2192 
SFR_8BIT(PJREN_H);                            /* Port J Resistor Enable */
2193 
SFR_16BIT(PJDS);                              /* Port J Resistor Drive Strenght */
2194 
SFR_8BIT(PJDS_L);                             /* Port J Resistor Drive Strenght */
2195 
SFR_8BIT(PJDS_H);                             /* Port J Resistor Drive Strenght */
2196 
 
2197 
/************************************************************
2198 
* PORT MAPPING CONTROLLER
2199 
************************************************************/
2200 
#define __MSP430_HAS_PORT_MAPPING__                /* Definition to show that Module is available */
2201 
#define __MSP430_BASEADDRESS_PORT_MAPPING__ 0x01C0
2202 
 
2203 
SFR_16BIT(PMAPKEYID);                         /* Port Mapping Key register */
2204 
SFR_8BIT(PMAPKEYID_L);                        /* Port Mapping Key register */
2205 
SFR_8BIT(PMAPKEYID_H);                        /* Port Mapping Key register */
2206 
SFR_16BIT(PMAPCTL);                           /* Port Mapping control register */
2207 
SFR_8BIT(PMAPCTL_L);                          /* Port Mapping control register */
2208 
SFR_8BIT(PMAPCTL_H);                          /* Port Mapping control register */
2209 
 
2210 
#define  PMAPKEY               (0x2D52)       /* Port Mapping Key */
2211 
#define  PMAPPWD               PMAPKEYID      /* Legacy Definition: Mapping Key register */
2212 
#define  PMAPPW                (0x2D52)       /* Legacy Definition: Port Mapping Password */
2213 
 
2214 
/* PMAPCTL Control Bits */
2215 
#define PMAPLOCKED             (0x0001)       /* Port Mapping Lock bit. Read only */
2216 
#define PMAPRECFG              (0x0002)       /* Port Mapping re-configuration control bit */
2217 
 
2218 
/* PMAPCTL Control Bits */
2219 
#define PMAPLOCKED_L           (0x0001)       /* Port Mapping Lock bit. Read only */
2220 
#define PMAPRECFG_L            (0x0002)       /* Port Mapping re-configuration control bit */
2221 
 
2222 
/* PMAPCTL Control Bits */
2223 
 
2224 
/************************************************************
2225 
* PORT 2 MAPPING CONTROLLER
2226 
************************************************************/
2227 
#define __MSP430_HAS_PORT2_MAPPING__                /* Definition to show that Module is available */
2228 
#define __MSP430_BASEADDRESS_PORT2_MAPPING__ 0x01D0
2229 
 
2230 
SFR_16BIT(P2MAP01);                           /* Port P2.0/1 mapping register */
2231 
SFR_8BIT(P2MAP01_L);                          /* Port P2.0/1 mapping register */
2232 
SFR_8BIT(P2MAP01_H);                          /* Port P2.0/1 mapping register */
2233 
SFR_16BIT(P2MAP23);                           /* Port P2.2/3 mapping register */
2234 
SFR_8BIT(P2MAP23_L);                          /* Port P2.2/3 mapping register */
2235 
SFR_8BIT(P2MAP23_H);                          /* Port P2.2/3 mapping register */
2236 
SFR_16BIT(P2MAP45);                           /* Port P2.4/5 mapping register */
2237 
SFR_8BIT(P2MAP45_L);                          /* Port P2.4/5 mapping register */
2238 
SFR_8BIT(P2MAP45_H);                          /* Port P2.4/5 mapping register */
2239 
SFR_16BIT(P2MAP67);                           /* Port P2.6/7 mapping register */
2240 
SFR_8BIT(P2MAP67_L);                          /* Port P2.6/7 mapping register */
2241 
SFR_8BIT(P2MAP67_H);                          /* Port P2.6/7 mapping register */
2242 
 
2243 
#define  P2MAP0                P2MAP01_L      /* Port P2.0 mapping register */
2244 
#define  P2MAP1                P2MAP01_H      /* Port P2.1 mapping register */
2245 
#define  P2MAP2                P2MAP23_L      /* Port P2.2 mapping register */
2246 
#define  P2MAP3                P2MAP23_H      /* Port P2.3 mapping register */
2247 
#define  P2MAP4                P2MAP45_L      /* Port P2.4 mapping register */
2248 
#define  P2MAP5                P2MAP45_H      /* Port P2.5 mapping register */
2249 
#define  P2MAP6                P2MAP67_L      /* Port P2.6 mapping register */
2250 
#define  P2MAP7                P2MAP67_H      /* Port P2.7 mapping register */
2251 
 
2252 
#define PM_NONE                0
2253 
#define PM_CBOUT               1
2254 
#define PM_TB0CLK              1
2255 
#define PM_ADC12CLK            2
2256 
#define PM_DMAE0               2
2257 
#define PM_SVMOUT              3
2258 
#define PM_TB0OUTH             3
2259 
#define PM_TB0CCR0B            4
2260 
#define PM_TB0CCR1B            5
2261 
#define PM_TB0CCR2B            6
2262 
#define PM_TB0CCR3B            7
2263 
#define PM_TB0CCR4B            8
2264 
#define PM_TB0CCR5B            9
2265 
#define PM_TB0CCR6B            10
2266 
#define PM_UCA0RXD             11
2267 
#define PM_UCA0SOMI            11
2268 
#define PM_UCA0TXD             12
2269 
#define PM_UCA0SIMO            12
2270 
#define PM_UCA0CLK             13
2271 
#define PM_UCB0STE             13
2272 
#define PM_UCB0SOMI            14
2273 
#define PM_UCB0SCL             14
2274 
#define PM_UCB0SIMO            15
2275 
#define PM_UCB0SDA             15
2276 
#define PM_UCB0CLK             16
2277 
#define PM_UCA0STE             16
2278 
#define PM_MCLK                17
2279 
#define PM_PM_E0               18
2280 
#define PM_PM_E1               19
2281 
#define PM_ANALOG              31
2282 
 
2283 
/************************************************************
2284 
* PMM - Power Management System
2285 
************************************************************/
2286 
#define __MSP430_HAS_PMM__                    /* Definition to show that Module is available */
2287 
#define __MSP430_BASEADDRESS_PMM__ 0x0120
2288 
 
2289 
SFR_16BIT(PMMCTL0);                           /* PMM Control 0 */
2290 
SFR_8BIT(PMMCTL0_L);                          /* PMM Control 0 */
2291 
SFR_8BIT(PMMCTL0_H);                          /* PMM Control 0 */
2292 
SFR_16BIT(PMMCTL1);                           /* PMM Control 1 */
2293 
SFR_8BIT(PMMCTL1_L);                          /* PMM Control 1 */
2294 
SFR_8BIT(PMMCTL1_H);                          /* PMM Control 1 */
2295 
SFR_16BIT(SVSMHCTL);                          /* SVS and SVM high side control register */
2296 
SFR_8BIT(SVSMHCTL_L);                         /* SVS and SVM high side control register */
2297 
SFR_8BIT(SVSMHCTL_H);                         /* SVS and SVM high side control register */
2298 
SFR_16BIT(SVSMLCTL);                          /* SVS and SVM low side control register */
2299 
SFR_8BIT(SVSMLCTL_L);                         /* SVS and SVM low side control register */
2300 
SFR_8BIT(SVSMLCTL_H);                         /* SVS and SVM low side control register */
2301 
SFR_16BIT(SVSMIO);                            /* SVSIN and SVSOUT control register */
2302 
SFR_8BIT(SVSMIO_L);                           /* SVSIN and SVSOUT control register */
2303 
SFR_8BIT(SVSMIO_H);                           /* SVSIN and SVSOUT control register */
2304 
SFR_16BIT(PMMIFG);                            /* PMM Interrupt Flag */
2305 
SFR_8BIT(PMMIFG_L);                           /* PMM Interrupt Flag */
2306 
SFR_8BIT(PMMIFG_H);                           /* PMM Interrupt Flag */
2307 
SFR_16BIT(PMMRIE);                            /* PMM and RESET Interrupt Enable */
2308 
SFR_8BIT(PMMRIE_L);                           /* PMM and RESET Interrupt Enable */
2309 
SFR_8BIT(PMMRIE_H);                           /* PMM and RESET Interrupt Enable */
2310 
SFR_16BIT(PM5CTL0);                           /* PMM Power Mode 5 Control Register 0 */
2311 
SFR_8BIT(PM5CTL0_L);                          /* PMM Power Mode 5 Control Register 0 */
2312 
SFR_8BIT(PM5CTL0_H);                          /* PMM Power Mode 5 Control Register 0 */
2313 
 
2314 
#define PMMPW                  (0xA500)       /* PMM Register Write Password */
2315 
#define PMMPW_H                (0xA5)         /* PMM Register Write Password for high word access */
2316 
 
2317 
/* PMMCTL0 Control Bits */
2318 
#define PMMCOREV0              (0x0001)       /* PMM Core Voltage Bit: 0 */
2319 
#define PMMCOREV1              (0x0002)       /* PMM Core Voltage Bit: 1 */
2320 
#define PMMSWBOR               (0x0004)       /* PMM Software BOR */
2321 
#define PMMSWPOR               (0x0008)       /* PMM Software POR */
2322 
#define PMMREGOFF              (0x0010)       /* PMM Turn Regulator off */
2323 
#define PMMHPMRE               (0x0080)       /* PMM Global High Power Module Request Enable */
2324 
 
2325 
/* PMMCTL0 Control Bits */
2326 
#define PMMCOREV0_L            (0x0001)       /* PMM Core Voltage Bit: 0 */
2327 
#define PMMCOREV1_L            (0x0002)       /* PMM Core Voltage Bit: 1 */
2328 
#define PMMSWBOR_L             (0x0004)       /* PMM Software BOR */
2329 
#define PMMSWPOR_L             (0x0008)       /* PMM Software POR */
2330 
#define PMMREGOFF_L            (0x0010)       /* PMM Turn Regulator off */
2331 
#define PMMHPMRE_L             (0x0080)       /* PMM Global High Power Module Request Enable */
2332 
 
2333 
/* PMMCTL0 Control Bits */
2334 
 
2335 
#define PMMCOREV_0             (0x0000)       /* PMM Core Voltage 0 (1.35V) */
2336 
#define PMMCOREV_1             (0x0001)       /* PMM Core Voltage 1 (1.55V) */
2337 
#define PMMCOREV_2             (0x0002)       /* PMM Core Voltage 2 (1.75V) */
2338 
#define PMMCOREV_3             (0x0003)       /* PMM Core Voltage 3 (1.85V) */
2339 
 
2340 
/* PMMCTL1 Control Bits */
2341 
#define PMMREFMD               (0x0001)       /* PMM Reference Mode */
2342 
#define PMMCMD0                (0x0010)       /* PMM Voltage Regulator Current Mode Bit: 0 */
2343 
#define PMMCMD1                (0x0020)       /* PMM Voltage Regulator Current Mode Bit: 1 */
2344 
 
2345 
/* PMMCTL1 Control Bits */
2346 
#define PMMREFMD_L             (0x0001)       /* PMM Reference Mode */
2347 
#define PMMCMD0_L              (0x0010)       /* PMM Voltage Regulator Current Mode Bit: 0 */
2348 
#define PMMCMD1_L              (0x0020)       /* PMM Voltage Regulator Current Mode Bit: 1 */
2349 
 
2350 
/* PMMCTL1 Control Bits */
2351 
 
2352 
/* SVSMHCTL Control Bits */
2353 
#define SVSMHRRL0              (0x0001)       /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
2354 
#define SVSMHRRL1              (0x0002)       /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
2355 
#define SVSMHRRL2              (0x0004)       /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
2356 
#define SVSMHDLYST             (0x0008)       /* SVS and SVM high side delay status */
2357 
#define SVSHMD                 (0x0010)       /* SVS high side mode */
2358 
#define SVSMHEVM               (0x0040)       /* SVS and SVM high side event mask */
2359 
#define SVSMHACE               (0x0080)       /* SVS and SVM high side auto control enable */
2360 
#define SVSHRVL0               (0x0100)       /* SVS high side reset voltage level Bit: 0 */
2361 
#define SVSHRVL1               (0x0200)       /* SVS high side reset voltage level Bit: 1 */
2362 
#define SVSHE                  (0x0400)       /* SVS high side enable */
2363 
#define SVSHFP                 (0x0800)       /* SVS high side full performace mode */
2364 
#define SVMHOVPE               (0x1000)       /* SVM high side over-voltage enable */
2365 
#define SVMHE                  (0x4000)       /* SVM high side enable */
2366 
#define SVMHFP                 (0x8000)       /* SVM high side full performace mode */
2367 
 
2368 
/* SVSMHCTL Control Bits */
2369 
#define SVSMHRRL0_L            (0x0001)       /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
2370 
#define SVSMHRRL1_L            (0x0002)       /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
2371 
#define SVSMHRRL2_L            (0x0004)       /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
2372 
#define SVSMHDLYST_L           (0x0008)       /* SVS and SVM high side delay status */
2373 
#define SVSHMD_L               (0x0010)       /* SVS high side mode */
2374 
#define SVSMHEVM_L             (0x0040)       /* SVS and SVM high side event mask */
2375 
#define SVSMHACE_L             (0x0080)       /* SVS and SVM high side auto control enable */
2376 
 
2377 
/* SVSMHCTL Control Bits */
2378 
#define SVSHRVL0_H             (0x0001)       /* SVS high side reset voltage level Bit: 0 */
2379 
#define SVSHRVL1_H             (0x0002)       /* SVS high side reset voltage level Bit: 1 */
2380 
#define SVSHE_H                (0x0004)       /* SVS high side enable */
2381 
#define SVSHFP_H               (0x0008)       /* SVS high side full performace mode */
2382 
#define SVMHOVPE_H             (0x0010)       /* SVM high side over-voltage enable */
2383 
#define SVMHE_H                (0x0040)       /* SVM high side enable */
2384 
#define SVMHFP_H               (0x0080)       /* SVM high side full performace mode */
2385 
 
2386 
#define SVSMHRRL_0             (0x0000)       /* SVS and SVM high side Reset Release Voltage Level 0 */
2387 
#define SVSMHRRL_1             (0x0001)       /* SVS and SVM high side Reset Release Voltage Level 1 */
2388 
#define SVSMHRRL_2             (0x0002)       /* SVS and SVM high side Reset Release Voltage Level 2 */
2389 
#define SVSMHRRL_3             (0x0003)       /* SVS and SVM high side Reset Release Voltage Level 3 */
2390 
#define SVSMHRRL_4             (0x0004)       /* SVS and SVM high side Reset Release Voltage Level 4 */
2391 
#define SVSMHRRL_5             (0x0005)       /* SVS and SVM high side Reset Release Voltage Level 5 */
2392 
#define SVSMHRRL_6             (0x0006)       /* SVS and SVM high side Reset Release Voltage Level 6 */
2393 
#define SVSMHRRL_7             (0x0007)       /* SVS and SVM high side Reset Release Voltage Level 7 */
2394 
 
2395 
#define SVSHRVL_0              (0x0000)       /* SVS high side Reset Release Voltage Level 0 */
2396 
#define SVSHRVL_1              (0x0100)       /* SVS high side Reset Release Voltage Level 1 */
2397 
#define SVSHRVL_2              (0x0200)       /* SVS high side Reset Release Voltage Level 2 */
2398 
#define SVSHRVL_3              (0x0300)       /* SVS high side Reset Release Voltage Level 3 */
2399 
 
2400 
/* SVSMLCTL Control Bits */
2401 
#define SVSMLRRL0              (0x0001)       /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
2402 
#define SVSMLRRL1              (0x0002)       /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
2403 
#define SVSMLRRL2              (0x0004)       /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
2404 
#define SVSMLDLYST             (0x0008)       /* SVS and SVM low side delay status */
2405 
#define SVSLMD                 (0x0010)       /* SVS low side mode */
2406 
#define SVSMLEVM               (0x0040)       /* SVS and SVM low side event mask */
2407 
#define SVSMLACE               (0x0080)       /* SVS and SVM low side auto control enable */
2408 
#define SVSLRVL0               (0x0100)       /* SVS low side reset voltage level Bit: 0 */
2409 
#define SVSLRVL1               (0x0200)       /* SVS low side reset voltage level Bit: 1 */
2410 
#define SVSLE                  (0x0400)       /* SVS low side enable */
2411 
#define SVSLFP                 (0x0800)       /* SVS low side full performace mode */
2412 
#define SVMLOVPE               (0x1000)       /* SVM low side over-voltage enable */
2413 
#define SVMLE                  (0x4000)       /* SVM low side enable */
2414 
#define SVMLFP                 (0x8000)       /* SVM low side full performace mode */
2415 
 
2416 
/* SVSMLCTL Control Bits */
2417 
#define SVSMLRRL0_L            (0x0001)       /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
2418 
#define SVSMLRRL1_L            (0x0002)       /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
2419 
#define SVSMLRRL2_L            (0x0004)       /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
2420 
#define SVSMLDLYST_L           (0x0008)       /* SVS and SVM low side delay status */
2421 
#define SVSLMD_L               (0x0010)       /* SVS low side mode */
2422 
#define SVSMLEVM_L             (0x0040)       /* SVS and SVM low side event mask */
2423 
#define SVSMLACE_L             (0x0080)       /* SVS and SVM low side auto control enable */
2424 
 
2425 
/* SVSMLCTL Control Bits */
2426 
#define SVSLRVL0_H             (0x0001)       /* SVS low side reset voltage level Bit: 0 */
2427 
#define SVSLRVL1_H             (0x0002)       /* SVS low side reset voltage level Bit: 1 */
2428 
#define SVSLE_H                (0x0004)       /* SVS low side enable */
2429 
#define SVSLFP_H               (0x0008)       /* SVS low side full performace mode */
2430 
#define SVMLOVPE_H             (0x0010)       /* SVM low side over-voltage enable */
2431 
#define SVMLE_H                (0x0040)       /* SVM low side enable */
2432 
#define SVMLFP_H               (0x0080)       /* SVM low side full performace mode */
2433 
 
2434 
#define SVSMLRRL_0             (0x0000)       /* SVS and SVM low side Reset Release Voltage Level 0 */
2435 
#define SVSMLRRL_1             (0x0001)       /* SVS and SVM low side Reset Release Voltage Level 1 */
2436 
#define SVSMLRRL_2             (0x0002)       /* SVS and SVM low side Reset Release Voltage Level 2 */
2437 
#define SVSMLRRL_3             (0x0003)       /* SVS and SVM low side Reset Release Voltage Level 3 */
2438 
#define SVSMLRRL_4             (0x0004)       /* SVS and SVM low side Reset Release Voltage Level 4 */
2439 
#define SVSMLRRL_5             (0x0005)       /* SVS and SVM low side Reset Release Voltage Level 5 */
2440 
#define SVSMLRRL_6             (0x0006)       /* SVS and SVM low side Reset Release Voltage Level 6 */
2441 
#define SVSMLRRL_7             (0x0007)       /* SVS and SVM low side Reset Release Voltage Level 7 */
2442 
 
2443 
#define SVSLRVL_0              (0x0000)       /* SVS low side Reset Release Voltage Level 0 */
2444 
#define SVSLRVL_1              (0x0100)       /* SVS low side Reset Release Voltage Level 1 */
2445 
#define SVSLRVL_2              (0x0200)       /* SVS low side Reset Release Voltage Level 2 */
2446 
#define SVSLRVL_3              (0x0300)       /* SVS low side Reset Release Voltage Level 3 */
2447 
 
2448 
/* SVSMIO Control Bits */
2449 
#define SVMLOE                 (0x0008)       /* SVM low side output enable */
2450 
#define SVMLVLROE              (0x0010)       /* SVM low side voltage level reached output enable */
2451 
#define SVMOUTPOL              (0x0020)       /* SVMOUT pin polarity */
2452 
#define SVMHOE                 (0x0800)       /* SVM high side output enable */
2453 
#define SVMHVLROE              (0x1000)       /* SVM high side voltage level reached output enable */
2454 
 
2455 
/* SVSMIO Control Bits */
2456 
#define SVMLOE_L               (0x0008)       /* SVM low side output enable */
2457 
#define SVMLVLROE_L            (0x0010)       /* SVM low side voltage level reached output enable */
2458 
#define SVMOUTPOL_L            (0x0020)       /* SVMOUT pin polarity */
2459 
 
2460 
/* SVSMIO Control Bits */
2461 
#define SVMHOE_H               (0x0008)       /* SVM high side output enable */
2462 
#define SVMHVLROE_H            (0x0010)       /* SVM high side voltage level reached output enable */
2463 
 
2464 
/* PMMIFG Control Bits */
2465 
#define SVSMLDLYIFG            (0x0001)       /* SVS and SVM low side Delay expired interrupt flag */
2466 
#define SVMLIFG                (0x0002)       /* SVM low side interrupt flag */
2467 
#define SVMLVLRIFG             (0x0004)       /* SVM low side Voltage Level Reached interrupt flag */
2468 
#define SVSMHDLYIFG            (0x0010)       /* SVS and SVM high side Delay expired interrupt flag */
2469 
#define SVMHIFG                (0x0020)       /* SVM high side interrupt flag */
2470 
#define SVMHVLRIFG             (0x0040)       /* SVM high side Voltage Level Reached interrupt flag */
2471 
#define PMMBORIFG              (0x0100)       /* PMM Software BOR interrupt flag */
2472 
#define PMMRSTIFG              (0x0200)       /* PMM RESET pin interrupt flag */
2473 
#define PMMPORIFG              (0x0400)       /* PMM Software POR interrupt flag */
2474 
#define SVSHIFG                (0x1000)       /* SVS low side interrupt flag */
2475 
#define SVSLIFG                (0x2000)       /* SVS high side interrupt flag */
2476 
#define PMMLPM5IFG             (0x8000)       /* LPM5 indication Flag */
2477 
 
2478 
/* PMMIFG Control Bits */
2479 
#define SVSMLDLYIFG_L          (0x0001)       /* SVS and SVM low side Delay expired interrupt flag */
2480 
#define SVMLIFG_L              (0x0002)       /* SVM low side interrupt flag */
2481 
#define SVMLVLRIFG_L           (0x0004)       /* SVM low side Voltage Level Reached interrupt flag */
2482 
#define SVSMHDLYIFG_L          (0x0010)       /* SVS and SVM high side Delay expired interrupt flag */
2483 
#define SVMHIFG_L              (0x0020)       /* SVM high side interrupt flag */
2484 
#define SVMHVLRIFG_L           (0x0040)       /* SVM high side Voltage Level Reached interrupt flag */
2485 
 
2486 
/* PMMIFG Control Bits */
2487 
#define PMMBORIFG_H            (0x0001)       /* PMM Software BOR interrupt flag */
2488 
#define PMMRSTIFG_H            (0x0002)       /* PMM RESET pin interrupt flag */
2489 
#define PMMPORIFG_H            (0x0004)       /* PMM Software POR interrupt flag */
2490 
#define SVSHIFG_H              (0x0010)       /* SVS low side interrupt flag */
2491 
#define SVSLIFG_H              (0x0020)       /* SVS high side interrupt flag */
2492 
#define PMMLPM5IFG_H           (0x0080)       /* LPM5 indication Flag */
2493 
 
2494 
#define PMMRSTLPM5IFG          PMMLPM5IFG     /* LPM5 indication Flag */
2495 
 
2496 
/* PMMIE and RESET Control Bits */
2497 
#define SVSMLDLYIE             (0x0001)       /* SVS and SVM low side Delay expired interrupt enable */
2498 
#define SVMLIE                 (0x0002)       /* SVM low side interrupt enable */
2499 
#define SVMLVLRIE              (0x0004)       /* SVM low side Voltage Level Reached interrupt enable */
2500 
#define SVSMHDLYIE             (0x0010)       /* SVS and SVM high side Delay expired interrupt enable */
2501 
#define SVMHIE                 (0x0020)       /* SVM high side interrupt enable */
2502 
#define SVMHVLRIE              (0x0040)       /* SVM high side Voltage Level Reached interrupt enable */
2503 
#define SVSLPE                 (0x0100)       /* SVS low side POR enable */
2504 
#define SVMLVLRPE              (0x0200)       /* SVM low side Voltage Level reached POR enable */
2505 
#define SVSHPE                 (0x1000)       /* SVS high side POR enable */
2506 
#define SVMHVLRPE              (0x2000)       /* SVM high side Voltage Level reached POR enable */
2507 
 
2508 
/* PMMIE and RESET Control Bits */
2509 
#define SVSMLDLYIE_L           (0x0001)       /* SVS and SVM low side Delay expired interrupt enable */
2510 
#define SVMLIE_L               (0x0002)       /* SVM low side interrupt enable */
2511 
#define SVMLVLRIE_L            (0x0004)       /* SVM low side Voltage Level Reached interrupt enable */
2512 
#define SVSMHDLYIE_L           (0x0010)       /* SVS and SVM high side Delay expired interrupt enable */
2513 
#define SVMHIE_L               (0x0020)       /* SVM high side interrupt enable */
2514 
#define SVMHVLRIE_L            (0x0040)       /* SVM high side Voltage Level Reached interrupt enable */
2515 
 
2516 
/* PMMIE and RESET Control Bits */
2517 
#define SVSLPE_H               (0x0001)       /* SVS low side POR enable */
2518 
#define SVMLVLRPE_H            (0x0002)       /* SVM low side Voltage Level reached POR enable */
2519 
#define SVSHPE_H               (0x0010)       /* SVS high side POR enable */
2520 
#define SVMHVLRPE_H            (0x0020)       /* SVM high side Voltage Level reached POR enable */
2521 
 
2522 
/* PM5CTL0 Power Mode 5 Control Bits */
2523 
#define LOCKLPM5               (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
2524 
 
2525 
/* PM5CTL0 Power Mode 5 Control Bits */
2526 
#define LOCKLPM5_L             (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
2527 
 
2528 
/* PM5CTL0 Power Mode 5 Control Bits */
2529 
#define LOCKIO                 LOCKLPM5       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
2530 
 
2531 
/*************************************************************
2532 
* RAM Control Module
2533 
*************************************************************/
2534 
#define __MSP430_HAS_RC__                     /* Definition to show that Module is available */
2535 
#define __MSP430_BASEADDRESS_RC__ 0x0158
2536 
 
2537 
SFR_16BIT(RCCTL0);                            /* Ram Controller Control Register */
2538 
SFR_8BIT(RCCTL0_L);                           /* Ram Controller Control Register */
2539 
SFR_8BIT(RCCTL0_H);                           /* Ram Controller Control Register */
2540 
 
2541 
/* RCCTL0 Control Bits */
2542 
#define RCRS0OFF               (0x0001)       /* RAM Controller RAM Sector 0 Off */
2543 
#define RCRS1OFF               (0x0002)       /* RAM Controller RAM Sector 1 Off */
2544 
#define RCRS2OFF               (0x0004)       /* RAM Controller RAM Sector 2 Off */
2545 
#define RCRS3OFF               (0x0008)       /* RAM Controller RAM Sector 3 Off */
2546 
#define RCRS7OFF               (0x0080)       /* RAM Controller RAM Sector 7 (USB) Off */
2547 
 
2548 
/* RCCTL0 Control Bits */
2549 
#define RCRS0OFF_L             (0x0001)       /* RAM Controller RAM Sector 0 Off */
2550 
#define RCRS1OFF_L             (0x0002)       /* RAM Controller RAM Sector 1 Off */
2551 
#define RCRS2OFF_L             (0x0004)       /* RAM Controller RAM Sector 2 Off */
2552 
#define RCRS3OFF_L             (0x0008)       /* RAM Controller RAM Sector 3 Off */
2553 
#define RCRS7OFF_L             (0x0080)       /* RAM Controller RAM Sector 7 (USB) Off */
2554 
 
2555 
/* RCCTL0 Control Bits */
2556 
 
2557 
#define RCKEY                  (0x5A00)
2558 
 
2559 
/************************************************************
2560 
* Shared Reference
2561 
************************************************************/
2562 
#define __MSP430_HAS_REF__                    /* Definition to show that Module is available */
2563 
#define __MSP430_BASEADDRESS_REF__ 0x01B0
2564 
 
2565 
SFR_16BIT(REFCTL0);                           /* REF Shared Reference control register 0 */
2566 
SFR_8BIT(REFCTL0_L);                          /* REF Shared Reference control register 0 */
2567 
SFR_8BIT(REFCTL0_H);                          /* REF Shared Reference control register 0 */
2568 
 
2569 
/* REFCTL0 Control Bits */
2570 
#define REFON                  (0x0001)       /* REF Reference On */
2571 
#define REFOUT                 (0x0002)       /* REF Reference output Buffer On */
2572 
//#define RESERVED            (0x0004)  /* Reserved */
2573 
#define REFTCOFF               (0x0008)       /* REF Temp.Sensor off */
2574 
#define REFVSEL0               (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
2575 
#define REFVSEL1               (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
2576 
//#define RESERVED            (0x0040)  /* Reserved */
2577 
#define REFMSTR                (0x0080)       /* REF Master Control */
2578 
#define REFGENACT              (0x0100)       /* REF Reference generator active */
2579 
#define REFBGACT               (0x0200)       /* REF Reference bandgap active */
2580 
#define REFGENBUSY             (0x0400)       /* REF Reference generator busy */
2581 
#define BGMODE                 (0x0800)       /* REF Bandgap mode */
2582 
//#define RESERVED            (0x1000)  /* Reserved */
2583 
//#define RESERVED            (0x2000)  /* Reserved */
2584 
//#define RESERVED            (0x4000)  /* Reserved */
2585 
//#define RESERVED            (0x8000)  /* Reserved */
2586 
 
2587 
/* REFCTL0 Control Bits */
2588 
#define REFON_L                (0x0001)       /* REF Reference On */
2589 
#define REFOUT_L               (0x0002)       /* REF Reference output Buffer On */
2590 
//#define RESERVED            (0x0004)  /* Reserved */
2591 
#define REFTCOFF_L             (0x0008)       /* REF Temp.Sensor off */
2592 
#define REFVSEL0_L             (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
2593 
#define REFVSEL1_L             (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
2594 
//#define RESERVED            (0x0040)  /* Reserved */
2595 
#define REFMSTR_L              (0x0080)       /* REF Master Control */
2596 
//#define RESERVED            (0x1000)  /* Reserved */
2597 
//#define RESERVED            (0x2000)  /* Reserved */
2598 
//#define RESERVED            (0x4000)  /* Reserved */
2599 
//#define RESERVED            (0x8000)  /* Reserved */
2600 
 
2601 
/* REFCTL0 Control Bits */
2602 
//#define RESERVED            (0x0004)  /* Reserved */
2603 
//#define RESERVED            (0x0040)  /* Reserved */
2604 
#define REFGENACT_H            (0x0001)       /* REF Reference generator active */
2605 
#define REFBGACT_H             (0x0002)       /* REF Reference bandgap active */
2606 
#define REFGENBUSY_H           (0x0004)       /* REF Reference generator busy */
2607 
#define BGMODE_H               (0x0008)       /* REF Bandgap mode */
2608 
//#define RESERVED            (0x1000)  /* Reserved */
2609 
//#define RESERVED            (0x2000)  /* Reserved */
2610 
//#define RESERVED            (0x4000)  /* Reserved */
2611 
//#define RESERVED            (0x8000)  /* Reserved */
2612 
 
2613 
#define REFVSEL_0              (0x0000)       /* REF Reference Voltage Level Select 1.5V */
2614 
#define REFVSEL_1              (0x0010)       /* REF Reference Voltage Level Select 2.0V */
2615 
#define REFVSEL_2              (0x0020)       /* REF Reference Voltage Level Select 2.5V */
2616 
#define REFVSEL_3              (0x0030)       /* REF Reference Voltage Level Select 2.5V */
2617 
 
2618 
/************************************************************
2619 
* Real Time Clock
2620 
************************************************************/
2621 
#define __MSP430_HAS_RTC_B__                  /* Definition to show that Module is available */
2622 
#define __MSP430_BASEADDRESS_RTC_B__ 0x04A0
2623 
 
2624 
SFR_16BIT(RTCCTL01);                          /* Real Timer Control 0/1 */
2625 
SFR_8BIT(RTCCTL01_L);                         /* Real Timer Control 0/1 */
2626 
SFR_8BIT(RTCCTL01_H);                         /* Real Timer Control 0/1 */
2627 
SFR_16BIT(RTCCTL23);                          /* Real Timer Control 2/3 */
2628 
SFR_8BIT(RTCCTL23_L);                         /* Real Timer Control 2/3 */
2629 
SFR_8BIT(RTCCTL23_H);                         /* Real Timer Control 2/3 */
2630 
SFR_16BIT(RTCPS0CTL);                         /* Real Timer Prescale Timer 0 Control */
2631 
SFR_8BIT(RTCPS0CTL_L);                        /* Real Timer Prescale Timer 0 Control */
2632 
SFR_8BIT(RTCPS0CTL_H);                        /* Real Timer Prescale Timer 0 Control */
2633 
SFR_16BIT(RTCPS1CTL);                         /* Real Timer Prescale Timer 1 Control */
2634 
SFR_8BIT(RTCPS1CTL_L);                        /* Real Timer Prescale Timer 1 Control */
2635 
SFR_8BIT(RTCPS1CTL_H);                        /* Real Timer Prescale Timer 1 Control */
2636 
SFR_16BIT(RTCPS);                             /* Real Timer Prescale Timer Control */
2637 
SFR_8BIT(RTCPS_L);                            /* Real Timer Prescale Timer Control */
2638 
SFR_8BIT(RTCPS_H);                            /* Real Timer Prescale Timer Control */
2639 
SFR_16BIT(RTCIV);                             /* Real Time Clock Interrupt Vector */
2640 
SFR_16BIT(RTCTIM0);                           /* Real Time Clock Time 0 */
2641 
SFR_8BIT(RTCTIM0_L);                          /* Real Time Clock Time 0 */
2642 
SFR_8BIT(RTCTIM0_H);                          /* Real Time Clock Time 0 */
2643 
SFR_16BIT(RTCTIM1);                           /* Real Time Clock Time 1 */
2644 
SFR_8BIT(RTCTIM1_L);                          /* Real Time Clock Time 1 */
2645 
SFR_8BIT(RTCTIM1_H);                          /* Real Time Clock Time 1 */
2646 
SFR_16BIT(RTCDATE);                           /* Real Time Clock Date */
2647 
SFR_8BIT(RTCDATE_L);                          /* Real Time Clock Date */
2648 
SFR_8BIT(RTCDATE_H);                          /* Real Time Clock Date */
2649 
SFR_16BIT(RTCYEAR);                           /* Real Time Clock Year */
2650 
SFR_8BIT(RTCYEAR_L);                          /* Real Time Clock Year */
2651 
SFR_8BIT(RTCYEAR_H);                          /* Real Time Clock Year */
2652 
SFR_16BIT(RTCAMINHR);                         /* Real Time Clock Alarm Min/Hour */
2653 
SFR_8BIT(RTCAMINHR_L);                        /* Real Time Clock Alarm Min/Hour */
2654 
SFR_8BIT(RTCAMINHR_H);                        /* Real Time Clock Alarm Min/Hour */
2655 
SFR_16BIT(RTCADOWDAY);                        /* Real Time Clock Alarm day of week/day */
2656 
SFR_8BIT(RTCADOWDAY_L);                       /* Real Time Clock Alarm day of week/day */
2657 
SFR_8BIT(RTCADOWDAY_H);                       /* Real Time Clock Alarm day of week/day */
2658 
SFR_16BIT(BIN2BCD);                           /* Real Time Binary-to-BCD conversion register */
2659 
SFR_16BIT(BCD2BIN);                           /* Real Time BCD-to-binary conversion register */
2660 
 
2661 
#define RTCCTL0                RTCCTL01_L     /* Real Time Clock Control 0 */
2662 
#define RTCCTL1                RTCCTL01_H     /* Real Time Clock Control 1 */
2663 
#define RTCCTL2                RTCCTL23_L     /* Real Time Clock Control 2 */
2664 
#define RTCCTL3                RTCCTL23_H     /* Real Time Clock Control 3 */
2665 
#define RTCNT12                RTCTIM0
2666 
#define RTCNT34                RTCTIM1
2667 
#define RTCNT1                 RTCTIM0_L
2668 
#define RTCNT2                 RTCTIM0_H
2669 
#define RTCNT3                 RTCTIM1_L
2670 
#define RTCNT4                 RTCTIM1_H
2671 
#define RTCSEC                 RTCTIM0_L
2672 
#define RTCMIN                 RTCTIM0_H
2673 
#define RTCHOUR                RTCTIM1_L
2674 
#define RTCDOW                 RTCTIM1_H
2675 
#define RTCDAY                 RTCDATE_L
2676 
#define RTCMON                 RTCDATE_H
2677 
#define RTCYEARL               RTCYEAR_L
2678 
#define RTCYEARH               RTCYEAR_H
2679 
#define RT0PS                  RTCPS_L
2680 
#define RT1PS                  RTCPS_H
2681 
#define RTCAMIN                RTCAMINHR_L    /* Real Time Clock Alarm Min */
2682 
#define RTCAHOUR               RTCAMINHR_H    /* Real Time Clock Alarm Hour */
2683 
#define RTCADOW                RTCADOWDAY_L   /* Real Time Clock Alarm day of week */
2684 
#define RTCADAY                RTCADOWDAY_H   /* Real Time Clock Alarm day */
2685 
 
2686 
/* RTCCTL01 Control Bits */
2687 
#define RTCBCD                 (0x8000)       /* RTC BCD  0:Binary / 1:BCD */
2688 
#define RTCHOLD                (0x4000)       /* RTC Hold */
2689 
//#define RESERVED            (0x2000)     /* RESERVED */
2690 
#define RTCRDY                 (0x1000)       /* RTC Ready */
2691 
//#define RESERVED            (0x0800)     /* RESERVED */
2692 
//#define RESERVED            (0x0400)     /* RESERVED */
2693 
#define RTCTEV1                (0x0200)       /* RTC Time Event 1 */
2694 
#define RTCTEV0                (0x0100)       /* RTC Time Event 0 */
2695 
#define RTCOFIE                (0x0080)       /* RTC 32kHz cyrstal oscillator fault interrupt enable */
2696 
#define RTCTEVIE               (0x0040)       /* RTC Time Event Interrupt Enable Flag */
2697 
#define RTCAIE                 (0x0020)       /* RTC Alarm Interrupt Enable Flag */
2698 
#define RTCRDYIE               (0x0010)       /* RTC Ready Interrupt Enable Flag */
2699 
#define RTCOFIFG               (0x0008)       /* RTC 32kHz cyrstal oscillator fault interrupt flag */
2700 
#define RTCTEVIFG              (0x0004)       /* RTC Time Event Interrupt Flag */
2701 
#define RTCAIFG                (0x0002)       /* RTC Alarm Interrupt Flag */
2702 
#define RTCRDYIFG              (0x0001)       /* RTC Ready Interrupt Flag */
2703 
 
2704 
/* RTCCTL01 Control Bits */
2705 
//#define RESERVED            (0x2000)     /* RESERVED */
2706 
//#define RESERVED            (0x0800)     /* RESERVED */
2707 
//#define RESERVED            (0x0400)     /* RESERVED */
2708 
#define RTCOFIE_L              (0x0080)       /* RTC 32kHz cyrstal oscillator fault interrupt enable */
2709 
#define RTCTEVIE_L             (0x0040)       /* RTC Time Event Interrupt Enable Flag */
2710 
#define RTCAIE_L               (0x0020)       /* RTC Alarm Interrupt Enable Flag */
2711 
#define RTCRDYIE_L             (0x0010)       /* RTC Ready Interrupt Enable Flag */
2712 
#define RTCOFIFG_L             (0x0008)       /* RTC 32kHz cyrstal oscillator fault interrupt flag */
2713 
#define RTCTEVIFG_L            (0x0004)       /* RTC Time Event Interrupt Flag */
2714 
#define RTCAIFG_L              (0x0002)       /* RTC Alarm Interrupt Flag */
2715 
#define RTCRDYIFG_L            (0x0001)       /* RTC Ready Interrupt Flag */
2716 
 
2717 
/* RTCCTL01 Control Bits */
2718 
#define RTCBCD_H               (0x0080)       /* RTC BCD  0:Binary / 1:BCD */
2719 
#define RTCHOLD_H              (0x0040)       /* RTC Hold */
2720 
//#define RESERVED            (0x2000)     /* RESERVED */
2721 
#define RTCRDY_H               (0x0010)       /* RTC Ready */
2722 
//#define RESERVED            (0x0800)     /* RESERVED */
2723 
//#define RESERVED            (0x0400)     /* RESERVED */
2724 
#define RTCTEV1_H              (0x0002)       /* RTC Time Event 1 */
2725 
#define RTCTEV0_H              (0x0001)       /* RTC Time Event 0 */
2726 
 
2727 
#define RTCTEV_0               (0x0000)       /* RTC Time Event: 0 (Min. changed) */
2728 
#define RTCTEV_1               (0x0100)       /* RTC Time Event: 1 (Hour changed) */
2729 
#define RTCTEV_2               (0x0200)       /* RTC Time Event: 2 (12:00 changed) */
2730 
#define RTCTEV_3               (0x0300)       /* RTC Time Event: 3 (00:00 changed) */
2731 
#define RTCTEV__MIN            (0x0000)       /* RTC Time Event: 0 (Min. changed) */
2732 
#define RTCTEV__HOUR           (0x0100)       /* RTC Time Event: 1 (Hour changed) */
2733 
#define RTCTEV__0000           (0x0200)       /* RTC Time Event: 3 (00:00 changed) */
2734 
#define RTCTEV__1200           (0x0300)       /* RTC Time Event: 2 (12:00 changed) */
2735 
 
2736 
/* RTCCTL23 Control Bits */
2737 
#define RTCCALF1               (0x0200)       /* RTC Calibration Frequency Bit 1 */
2738 
#define RTCCALF0               (0x0100)       /* RTC Calibration Frequency Bit 0 */
2739 
#define RTCCALS                (0x0080)       /* RTC Calibration Sign */
2740 
//#define Reserved          (0x0040)
2741 
#define RTCCAL5                (0x0020)       /* RTC Calibration Bit 5 */
2742 
#define RTCCAL4                (0x0010)       /* RTC Calibration Bit 4 */
2743 
#define RTCCAL3                (0x0008)       /* RTC Calibration Bit 3 */
2744 
#define RTCCAL2                (0x0004)       /* RTC Calibration Bit 2 */
2745 
#define RTCCAL1                (0x0002)       /* RTC Calibration Bit 1 */
2746 
#define RTCCAL0                (0x0001)       /* RTC Calibration Bit 0 */
2747 
 
2748 
/* RTCCTL23 Control Bits */
2749 
#define RTCCALS_L              (0x0080)       /* RTC Calibration Sign */
2750 
//#define Reserved          (0x0040)
2751 
#define RTCCAL5_L              (0x0020)       /* RTC Calibration Bit 5 */
2752 
#define RTCCAL4_L              (0x0010)       /* RTC Calibration Bit 4 */
2753 
#define RTCCAL3_L              (0x0008)       /* RTC Calibration Bit 3 */
2754 
#define RTCCAL2_L              (0x0004)       /* RTC Calibration Bit 2 */
2755 
#define RTCCAL1_L              (0x0002)       /* RTC Calibration Bit 1 */
2756 
#define RTCCAL0_L              (0x0001)       /* RTC Calibration Bit 0 */
2757 
 
2758 
/* RTCCTL23 Control Bits */
2759 
#define RTCCALF1_H             (0x0002)       /* RTC Calibration Frequency Bit 1 */
2760 
#define RTCCALF0_H             (0x0001)       /* RTC Calibration Frequency Bit 0 */
2761 
//#define Reserved          (0x0040)
2762 
 
2763 
#define RTCCALF_0              (0x0000)       /* RTC Calibration Frequency: No Output */
2764 
#define RTCCALF_1              (0x0100)       /* RTC Calibration Frequency: 512 Hz */
2765 
#define RTCCALF_2              (0x0200)       /* RTC Calibration Frequency: 256 Hz */
2766 
#define RTCCALF_3              (0x0300)       /* RTC Calibration Frequency: 1 Hz */
2767 
 
2768 
/* RTCPS0CTL Control Bits */
2769 
//#define Reserved          (0x0080)
2770 
//#define Reserved          (0x0040)
2771 
//#define Reserved          (0x0020)
2772 
#define RT0IP2                 (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
2773 
#define RT0IP1                 (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
2774 
#define RT0IP0                 (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
2775 
#define RT0PSIE                (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
2776 
#define RT0PSIFG               (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
2777 
 
2778 
/* RTCPS0CTL Control Bits */
2779 
//#define Reserved          (0x0080)
2780 
//#define Reserved          (0x0040)
2781 
//#define Reserved          (0x0020)
2782 
#define RT0IP2_L               (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
2783 
#define RT0IP1_L               (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
2784 
#define RT0IP0_L               (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
2785 
#define RT0PSIE_L              (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
2786 
#define RT0PSIFG_L             (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
2787 
 
2788 
/* RTCPS0CTL Control Bits */
2789 
//#define Reserved          (0x0080)
2790 
//#define Reserved          (0x0040)
2791 
//#define Reserved          (0x0020)
2792 
 
2793 
#define RT0IP_0                (0x0000)       /* RTC Prescale Timer 0 Interrupt Interval /2 */
2794 
#define RT0IP_1                (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval /4 */
2795 
#define RT0IP_2                (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval /8 */
2796 
#define RT0IP_3                (0x000C)       /* RTC Prescale Timer 0 Interrupt Interval /16 */
2797 
#define RT0IP_4                (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval /32 */
2798 
#define RT0IP_5                (0x0014)       /* RTC Prescale Timer 0 Interrupt Interval /64 */
2799 
#define RT0IP_6                (0x0018)       /* RTC Prescale Timer 0 Interrupt Interval /128 */
2800 
#define RT0IP_7                (0x001C)       /* RTC Prescale Timer 0 Interrupt Interval /256 */
2801 
 
2802 
#define RT0IP__2               (0x0000)       /* RTC Prescale Timer 0 Interrupt Interval /2 */
2803 
#define RT0IP__4               (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval /4 */
2804 
#define RT0IP__8               (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval /8 */
2805 
#define RT0IP__16              (0x000C)       /* RTC Prescale Timer 0 Interrupt Interval /16 */
2806 
#define RT0IP__32              (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval /32 */
2807 
#define RT0IP__64              (0x0014)       /* RTC Prescale Timer 0 Interrupt Interval /64 */
2808 
#define RT0IP__128             (0x0018)       /* RTC Prescale Timer 0 Interrupt Interval /128 */
2809 
#define RT0IP__256             (0x001C)       /* RTC Prescale Timer 0 Interrupt Interval /256 */
2810 
 
2811 
/* RTCPS1CTL Control Bits */
2812 
//#define Reserved          (0x0080)
2813 
//#define Reserved          (0x0040)
2814 
//#define Reserved          (0x0020)
2815 
#define RT1IP2                 (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
2816 
#define RT1IP1                 (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
2817 
#define RT1IP0                 (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
2818 
#define RT1PSIE                (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
2819 
#define RT1PSIFG               (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
2820 
 
2821 
/* RTCPS1CTL Control Bits */
2822 
//#define Reserved          (0x0080)
2823 
//#define Reserved          (0x0040)
2824 
//#define Reserved          (0x0020)
2825 
#define RT1IP2_L               (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
2826 
#define RT1IP1_L               (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
2827 
#define RT1IP0_L               (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
2828 
#define RT1PSIE_L              (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
2829 
#define RT1PSIFG_L             (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
2830 
 
2831 
/* RTCPS1CTL Control Bits */
2832 
//#define Reserved          (0x0080)
2833 
//#define Reserved          (0x0040)
2834 
//#define Reserved          (0x0020)
2835 
 
2836 
#define RT1IP_0                (0x0000)       /* RTC Prescale Timer 1 Interrupt Interval /2 */
2837 
#define RT1IP_1                (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval /4 */
2838 
#define RT1IP_2                (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval /8 */
2839 
#define RT1IP_3                (0x000C)       /* RTC Prescale Timer 1 Interrupt Interval /16 */
2840 
#define RT1IP_4                (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval /32 */
2841 
#define RT1IP_5                (0x0014)       /* RTC Prescale Timer 1 Interrupt Interval /64 */
2842 
#define RT1IP_6                (0x0018)       /* RTC Prescale Timer 1 Interrupt Interval /128 */
2843 
#define RT1IP_7                (0x001C)       /* RTC Prescale Timer 1 Interrupt Interval /256 */
2844 
 
2845 
#define RT1IP__2               (0x0000)       /* RTC Prescale Timer 1 Interrupt Interval /2 */
2846 
#define RT1IP__4               (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval /4 */
2847 
#define RT1IP__8               (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval /8 */
2848 
#define RT1IP__16              (0x000C)       /* RTC Prescale Timer 1 Interrupt Interval /16 */
2849 
#define RT1IP__32              (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval /32 */
2850 
#define RT1IP__64              (0x0014)       /* RTC Prescale Timer 1 Interrupt Interval /64 */
2851 
#define RT1IP__128             (0x0018)       /* RTC Prescale Timer 1 Interrupt Interval /128 */
2852 
#define RT1IP__256             (0x001C)       /* RTC Prescale Timer 1 Interrupt Interval /256 */
2853 
 
2854 
/* RTC Definitions */
2855 
#define RTCIV_NONE             (0x0000)       /* No Interrupt pending */
2856 
#define RTCIV_RTCRDYIFG        (0x0002)       /* RTC ready: RTCRDYIFG */
2857 
#define RTCIV_RTCTEVIFG        (0x0004)       /* RTC interval timer: RTCTEVIFG */
2858 
#define RTCIV_RTCAIFG          (0x0006)       /* RTC user alarm: RTCAIFG */
2859 
#define RTCIV_RT0PSIFG         (0x0008)       /* RTC prescaler 0: RT0PSIFG */
2860 
#define RTCIV_RT1PSIFG         (0x000A)       /* RTC prescaler 1: RT1PSIFG */
2861 
#define RTCIV_RTCOFIFG         (0x000C)       /* RTC Oscillator fault */
2862 
 
2863 
/* Legacy Definitions */
2864 
#define RTC_NONE               (0x0000)       /* No Interrupt pending */
2865 
#define RTC_RTCRDYIFG          (0x0002)       /* RTC ready: RTCRDYIFG */
2866 
#define RTC_RTCTEVIFG          (0x0004)       /* RTC interval timer: RTCTEVIFG */
2867 
#define RTC_RTCAIFG            (0x0006)       /* RTC user alarm: RTCAIFG */
2868 
#define RTC_RT0PSIFG           (0x0008)       /* RTC prescaler 0: RT0PSIFG */
2869 
#define RTC_RT1PSIFG           (0x000A)       /* RTC prescaler 1: RT1PSIFG */
2870 
#define RTC_RTCOFIFG           (0x000C)       /* RTC Oscillator fault */
2871 
 
2872 
/************************************************************
2873 
* SFR - Special Function Register Module
2874 
************************************************************/
2875 
#define __MSP430_HAS_SFR__                    /* Definition to show that Module is available */
2876 
#define __MSP430_BASEADDRESS_SFR__ 0x0100
2877 
 
2878 
SFR_16BIT(SFRIE1);                            /* Interrupt Enable 1 */
2879 
SFR_8BIT(SFRIE1_L);                           /* Interrupt Enable 1 */
2880 
SFR_8BIT(SFRIE1_H);                           /* Interrupt Enable 1 */
2881 
 
2882 
/* SFRIE1 Control Bits */
2883 
#define WDTIE                  (0x0001)       /* WDT Interrupt Enable */
2884 
#define OFIE                   (0x0002)       /* Osc Fault Enable */
2885 
//#define Reserved          (0x0004)
2886 
#define VMAIE                  (0x0008)       /* Vacant Memory Interrupt Enable */
2887 
#define NMIIE                  (0x0010)       /* NMI Interrupt Enable */
2888 
#define ACCVIE                 (0x0020)       /* Flash Access Violation Interrupt Enable */
2889 
#define JMBINIE                (0x0040)       /* JTAG Mail Box input Interrupt Enable */
2890 
#define JMBOUTIE               (0x0080)       /* JTAG Mail Box output Interrupt Enable */
2891 
 
2892 
#define WDTIE_L                (0x0001)       /* WDT Interrupt Enable */
2893 
#define OFIE_L                 (0x0002)       /* Osc Fault Enable */
2894 
//#define Reserved          (0x0004)
2895 
#define VMAIE_L                (0x0008)       /* Vacant Memory Interrupt Enable */
2896 
#define NMIIE_L                (0x0010)       /* NMI Interrupt Enable */
2897 
#define ACCVIE_L               (0x0020)       /* Flash Access Violation Interrupt Enable */
2898 
#define JMBINIE_L              (0x0040)       /* JTAG Mail Box input Interrupt Enable */
2899 
#define JMBOUTIE_L             (0x0080)       /* JTAG Mail Box output Interrupt Enable */
2900 
 
2901 
//#define Reserved          (0x0004)
2902 
 
2903 
SFR_16BIT(SFRIFG1);                           /* Interrupt Flag 1 */
2904 
SFR_8BIT(SFRIFG1_L);                          /* Interrupt Flag 1 */
2905 
SFR_8BIT(SFRIFG1_H);                          /* Interrupt Flag 1 */
2906 
/* SFRIFG1 Control Bits */
2907 
#define WDTIFG                 (0x0001)       /* WDT Interrupt Flag */
2908 
#define OFIFG                  (0x0002)       /* Osc Fault Flag */
2909 
//#define Reserved          (0x0004)
2910 
#define VMAIFG                 (0x0008)       /* Vacant Memory Interrupt Flag */
2911 
#define NMIIFG                 (0x0010)       /* NMI Interrupt Flag */
2912 
//#define Reserved          (0x0020)
2913 
#define JMBINIFG               (0x0040)       /* JTAG Mail Box input Interrupt Flag */
2914 
#define JMBOUTIFG              (0x0080)       /* JTAG Mail Box output Interrupt Flag */
2915 
 
2916 
#define WDTIFG_L               (0x0001)       /* WDT Interrupt Flag */
2917 
#define OFIFG_L                (0x0002)       /* Osc Fault Flag */
2918 
//#define Reserved          (0x0004)
2919 
#define VMAIFG_L               (0x0008)       /* Vacant Memory Interrupt Flag */
2920 
#define NMIIFG_L               (0x0010)       /* NMI Interrupt Flag */
2921 
//#define Reserved          (0x0020)
2922 
#define JMBINIFG_L             (0x0040)       /* JTAG Mail Box input Interrupt Flag */
2923 
#define JMBOUTIFG_L            (0x0080)       /* JTAG Mail Box output Interrupt Flag */
2924 
 
2925 
//#define Reserved          (0x0004)
2926 
//#define Reserved          (0x0020)
2927 
 
2928 
SFR_16BIT(SFRRPCR);                           /* RESET Pin Control Register */
2929 
SFR_8BIT(SFRRPCR_L);                          /* RESET Pin Control Register */
2930 
SFR_8BIT(SFRRPCR_H);                          /* RESET Pin Control Register */
2931 
/* SFRRPCR Control Bits */
2932 
#define SYSNMI                 (0x0001)       /* NMI select */
2933 
#define SYSNMIIES              (0x0002)       /* NMI edge select */
2934 
#define SYSRSTUP               (0x0004)       /* RESET Pin pull down/up select */
2935 
#define SYSRSTRE               (0x0008)       /* RESET Pin Resistor enable */
2936 
 
2937 
#define SYSNMI_L               (0x0001)       /* NMI select */
2938 
#define SYSNMIIES_L            (0x0002)       /* NMI edge select */
2939 
#define SYSRSTUP_L             (0x0004)       /* RESET Pin pull down/up select */
2940 
#define SYSRSTRE_L             (0x0008)       /* RESET Pin Resistor enable */
2941 
 
2942 
/************************************************************
2943 
* SYS - System Module
2944 
************************************************************/
2945 
#define __MSP430_HAS_SYS__                    /* Definition to show that Module is available */
2946 
#define __MSP430_BASEADDRESS_SYS__ 0x0180
2947 
 
2948 
SFR_16BIT(SYSCTL);                            /* System control */
2949 
SFR_8BIT(SYSCTL_L);                           /* System control */
2950 
SFR_8BIT(SYSCTL_H);                           /* System control */
2951 
SFR_16BIT(SYSBSLC);                           /* Boot strap configuration area */
2952 
SFR_8BIT(SYSBSLC_L);                          /* Boot strap configuration area */
2953 
SFR_8BIT(SYSBSLC_H);                          /* Boot strap configuration area */
2954 
SFR_16BIT(SYSJMBC);                           /* JTAG mailbox control */
2955 
SFR_8BIT(SYSJMBC_L);                          /* JTAG mailbox control */
2956 
SFR_8BIT(SYSJMBC_H);                          /* JTAG mailbox control */
2957 
SFR_16BIT(SYSJMBI0);                          /* JTAG mailbox input 0 */
2958 
SFR_8BIT(SYSJMBI0_L);                         /* JTAG mailbox input 0 */
2959 
SFR_8BIT(SYSJMBI0_H);                         /* JTAG mailbox input 0 */
2960 
SFR_16BIT(SYSJMBI1);                          /* JTAG mailbox input 1 */
2961 
SFR_8BIT(SYSJMBI1_L);                         /* JTAG mailbox input 1 */
2962 
SFR_8BIT(SYSJMBI1_H);                         /* JTAG mailbox input 1 */
2963 
SFR_16BIT(SYSJMBO0);                          /* JTAG mailbox output 0 */
2964 
SFR_8BIT(SYSJMBO0_L);                         /* JTAG mailbox output 0 */
2965 
SFR_8BIT(SYSJMBO0_H);                         /* JTAG mailbox output 0 */
2966 
SFR_16BIT(SYSJMBO1);                          /* JTAG mailbox output 1 */
2967 
SFR_8BIT(SYSJMBO1_L);                         /* JTAG mailbox output 1 */
2968 
SFR_8BIT(SYSJMBO1_H);                         /* JTAG mailbox output 1 */
2969 
 
2970 
SFR_16BIT(SYSBERRIV);                         /* Bus Error vector generator */
2971 
SFR_8BIT(SYSBERRIV_L);                        /* Bus Error vector generator */
2972 
SFR_8BIT(SYSBERRIV_H);                        /* Bus Error vector generator */
2973 
SFR_16BIT(SYSUNIV);                           /* User NMI vector generator */
2974 
SFR_8BIT(SYSUNIV_L);                          /* User NMI vector generator */
2975 
SFR_8BIT(SYSUNIV_H);                          /* User NMI vector generator */
2976 
SFR_16BIT(SYSSNIV);                           /* System NMI vector generator */
2977 
SFR_8BIT(SYSSNIV_L);                          /* System NMI vector generator */
2978 
SFR_8BIT(SYSSNIV_H);                          /* System NMI vector generator */
2979 
SFR_16BIT(SYSRSTIV);                          /* Reset vector generator */
2980 
SFR_8BIT(SYSRSTIV_L);                         /* Reset vector generator */
2981 
SFR_8BIT(SYSRSTIV_H);                         /* Reset vector generator */
2982 
 
2983 
/* SYSCTL Control Bits */
2984 
#define SYSRIVECT              (0x0001)       /* SYS - RAM based interrupt vectors */
2985 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2986 
#define SYSPMMPE               (0x0004)       /* SYS - PMM access protect */
2987 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2988 
#define SYSBSLIND              (0x0010)       /* SYS - TCK/RST indication detected */
2989 
#define SYSJTAGPIN             (0x0020)       /* SYS - Dedicated JTAG pins enabled */
2990 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2991 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2992 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2993 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2994 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2995 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2996 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2997 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2998 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2999 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
3000 
 
3001 
/* SYSCTL Control Bits */
3002 
#define SYSRIVECT_L            (0x0001)       /* SYS - RAM based interrupt vectors */
3003 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
3004 
#define SYSPMMPE_L             (0x0004)       /* SYS - PMM access protect */
3005 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
3006 
#define SYSBSLIND_L            (0x0010)       /* SYS - TCK/RST indication detected */
3007 
#define SYSJTAGPIN_L           (0x0020)       /* SYS - Dedicated JTAG pins enabled */
3008 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
3009 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
3010 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
3011 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
3012 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
3013 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
3014 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
3015 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
3016 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
3017 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
3018 
 
3019 
/* SYSCTL Control Bits */
3020 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
3021 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
3022 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
3023 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
3024 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
3025 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
3026 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
3027 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
3028 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
3029 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
3030 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
3031 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
3032 
 
3033 
/* SYSBSLC Control Bits */
3034 
#define SYSBSLSIZE0            (0x0001)       /* SYS - BSL Protection Size 0 */
3035 
#define SYSBSLSIZE1            (0x0002)       /* SYS - BSL Protection Size 1 */
3036 
#define SYSBSLR                (0x0004)       /* SYS - RAM assigned to BSL */
3037 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
3038 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
3039 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
3040 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
3041 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
3042 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
3043 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
3044 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
3045 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
3046 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
3047 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
3048 
#define SYSBSLOFF              (0x4000)       /* SYS - BSL Memeory disabled */
3049 
#define SYSBSLPE               (0x8000)       /* SYS - BSL Memory protection enabled */
3050 
 
3051 
/* SYSBSLC Control Bits */
3052 
#define SYSBSLSIZE0_L          (0x0001)       /* SYS - BSL Protection Size 0 */
3053 
#define SYSBSLSIZE1_L          (0x0002)       /* SYS - BSL Protection Size 1 */
3054 
#define SYSBSLR_L              (0x0004)       /* SYS - RAM assigned to BSL */
3055 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
3056 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
3057 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
3058 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
3059 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
3060 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
3061 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
3062 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
3063 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
3064 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
3065 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
3066 
 
3067 
/* SYSBSLC Control Bits */
3068 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
3069 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
3070 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
3071 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
3072 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
3073 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
3074 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
3075 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
3076 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
3077 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
3078 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
3079 
#define SYSBSLOFF_H            (0x0040)       /* SYS - BSL Memeory disabled */
3080 
#define SYSBSLPE_H             (0x0080)       /* SYS - BSL Memory protection enabled */
3081 
 
3082 
/* SYSJMBC Control Bits */
3083 
#define JMBIN0FG               (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
3084 
#define JMBIN1FG               (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
3085 
#define JMBOUT0FG              (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
3086 
#define JMBOUT1FG              (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
3087 
#define JMBMODE                (0x0010)       /* SYS - JMB 16/32 Bit Mode */
3088 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
3089 
#define JMBCLR0OFF             (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
3090 
#define JMBCLR1OFF             (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
3091 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
3092 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
3093 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
3094 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
3095 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
3096 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
3097 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
3098 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
3099 
 
3100 
/* SYSJMBC Control Bits */
3101 
#define JMBIN0FG_L             (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
3102 
#define JMBIN1FG_L             (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
3103 
#define JMBOUT0FG_L            (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
3104 
#define JMBOUT1FG_L            (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
3105 
#define JMBMODE_L              (0x0010)       /* SYS - JMB 16/32 Bit Mode */
3106 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
3107 
#define JMBCLR0OFF_L           (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
3108 
#define JMBCLR1OFF_L           (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
3109 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
3110 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
3111 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
3112 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
3113 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
3114 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
3115 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
3116 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
3117 
 
3118 
/* SYSJMBC Control Bits */
3119 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
3120 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
3121 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
3122 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
3123 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
3124 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
3125 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
3126 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
3127 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
3128 
 
3129 
/* SYSUNIV Definitions */
3130 
#define SYSUNIV_NONE           (0x0000)       /* No Interrupt pending */
3131 
#define SYSUNIV_NMIIFG         (0x0002)       /* SYSUNIV : NMIIFG */
3132 
#define SYSUNIV_OFIFG          (0x0004)       /* SYSUNIV : Osc. Fail - OFIFG */
3133 
#define SYSUNIV_ACCVIFG        (0x0006)       /* SYSUNIV : Access Violation - ACCVIFG */
3134 
#define SYSUNIV_BUSIFG         (0x0008)       /* SYSUNIV : Bus Error */
3135 
 
3136 
/* SYSBERRIV Definitions */
3137 
#define SYSBERRIV_NONE         (0x0000)       /* No Interrupt pending */
3138 
#define SYSBERRIV_USB          (0x0002)       /* SYSBERRIV : USB Waitstate Error */
3139 
 
3140 
/* SYSSNIV Definitions */
3141 
#define SYSSNIV_NONE           (0x0000)       /* No Interrupt pending */
3142 
#define SYSSNIV_SVMLIFG        (0x0002)       /* SYSSNIV : SVMLIFG */
3143 
#define SYSSNIV_SVMHIFG        (0x0004)       /* SYSSNIV : SVMHIFG */
3144 
#define SYSSNIV_DLYLIFG        (0x0006)       /* SYSSNIV : DLYLIFG */
3145 
#define SYSSNIV_DLYHIFG        (0x0008)       /* SYSSNIV : DLYHIFG */
3146 
#define SYSSNIV_VMAIFG         (0x000A)       /* SYSSNIV : VMAIFG */
3147 
#define SYSSNIV_JMBINIFG       (0x000C)       /* SYSSNIV : JMBINIFG */
3148 
#define SYSSNIV_JMBOUTIFG      (0x000E)       /* SYSSNIV : JMBOUTIFG */
3149 
#define SYSSNIV_VLRLIFG        (0x0010)       /* SYSSNIV : VLRLIFG */
3150 
#define SYSSNIV_VLRHIFG        (0x0012)       /* SYSSNIV : VLRHIFG */
3151 
 
3152 
/* SYSRSTIV Definitions */
3153 
#define SYSRSTIV_NONE          (0x0000)       /* No Interrupt pending */
3154 
#define SYSRSTIV_BOR           (0x0002)       /* SYSRSTIV : BOR */
3155 
#define SYSRSTIV_RSTNMI        (0x0004)       /* SYSRSTIV : RST/NMI */
3156 
#define SYSRSTIV_DOBOR         (0x0006)       /* SYSRSTIV : Do BOR */
3157 
#define SYSRSTIV_LPM5WU        (0x0008)       /* SYSRSTIV : Port LPM5 Wake Up */
3158 
#define SYSRSTIV_SECYV         (0x000A)       /* SYSRSTIV : Security violation */
3159 
#define SYSRSTIV_SVSL          (0x000C)       /* SYSRSTIV : SVSL */
3160 
#define SYSRSTIV_SVSH          (0x000E)       /* SYSRSTIV : SVSH */
3161 
#define SYSRSTIV_SVML_OVP      (0x0010)       /* SYSRSTIV : SVML_OVP */
3162 
#define SYSRSTIV_SVMH_OVP      (0x0012)       /* SYSRSTIV : SVMH_OVP */
3163 
#define SYSRSTIV_DOPOR         (0x0014)       /* SYSRSTIV : Do POR */
3164 
#define SYSRSTIV_WDTTO         (0x0016)       /* SYSRSTIV : WDT Time out */
3165 
#define SYSRSTIV_WDTKEY        (0x0018)       /* SYSRSTIV : WDTKEY violation */
3166 
#define SYSRSTIV_KEYV          (0x001A)       /* SYSRSTIV : Flash Key violation */
3167 
#define SYSRSTIV_FLLUL         (0x001C)       /* SYSRSTIV : FLL unlock */
3168 
#define SYSRSTIV_PERF          (0x001E)       /* SYSRSTIV : peripheral/config area fetch */
3169 
#define SYSRSTIV_PMMKEY        (0x0020)       /* SYSRSTIV : PMMKEY violation */
3170 
 
3171 
/************************************************************
3172 
* Timer0_A5
3173 
************************************************************/
3174 
#define __MSP430_HAS_T0A5__                   /* Definition to show that Module is available */
3175 
#define __MSP430_BASEADDRESS_T0A5__ 0x0340
3176 
 
3177 
SFR_16BIT(TA0CTL);                            /* Timer0_A5 Control */
3178 
SFR_16BIT(TA0CCTL0);                          /* Timer0_A5 Capture/Compare Control 0 */
3179 
SFR_16BIT(TA0CCTL1);                          /* Timer0_A5 Capture/Compare Control 1 */
3180 
SFR_16BIT(TA0CCTL2);                          /* Timer0_A5 Capture/Compare Control 2 */
3181 
SFR_16BIT(TA0CCTL3);                          /* Timer0_A5 Capture/Compare Control 3 */
3182 
SFR_16BIT(TA0CCTL4);                          /* Timer0_A5 Capture/Compare Control 4 */
3183 
SFR_16BIT(TA0R);                              /* Timer0_A5 */
3184 
SFR_16BIT(TA0CCR0);                           /* Timer0_A5 Capture/Compare 0 */
3185 
SFR_16BIT(TA0CCR1);                           /* Timer0_A5 Capture/Compare 1 */
3186 
SFR_16BIT(TA0CCR2);                           /* Timer0_A5 Capture/Compare 2 */
3187 
SFR_16BIT(TA0CCR3);                           /* Timer0_A5 Capture/Compare 3 */
3188 
SFR_16BIT(TA0CCR4);                           /* Timer0_A5 Capture/Compare 4 */
3189 
SFR_16BIT(TA0IV);                             /* Timer0_A5 Interrupt Vector Word */
3190 
SFR_16BIT(TA0EX0);                            /* Timer0_A5 Expansion Register 0 */
3191 
 
3192 
/* TAxCTL Control Bits */
3193 
#define TASSEL1                (0x0200)       /* Timer A clock source select 0 */
3194 
#define TASSEL0                (0x0100)       /* Timer A clock source select 1 */
3195 
#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
3196 
#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
3197 
#define MC1                    (0x0020)       /* Timer A mode control 1 */
3198 
#define MC0                    (0x0010)       /* Timer A mode control 0 */
3199 
#define TACLR                  (0x0004)       /* Timer A counter clear */
3200 
#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
3201 
#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
3202 
 
3203 
#define MC_0                   (0*0x10u)      /* Timer A mode control: 0 - Stop */
3204 
#define MC_1                   (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
3205 
#define MC_2                   (2*0x10u)      /* Timer A mode control: 2 - Continous up */
3206 
#define MC_3                   (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
3207 
#define ID_0                   (0*0x40u)      /* Timer A input divider: 0 - /1 */
3208 
#define ID_1                   (1*0x40u)      /* Timer A input divider: 1 - /2 */
3209 
#define ID_2                   (2*0x40u)      /* Timer A input divider: 2 - /4 */
3210 
#define ID_3                   (3*0x40u)      /* Timer A input divider: 3 - /8 */
3211 
#define TASSEL_0               (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
3212 
#define TASSEL_1               (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
3213 
#define TASSEL_2               (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
3214 
#define TASSEL_3               (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
3215 
#define MC__STOP               (0*0x10u)      /* Timer A mode control: 0 - Stop */
3216 
#define MC__UP                 (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
3217 
#define MC__CONTINOUS          (2*0x10u)      /* Timer A mode control: 2 - Continous up */
3218 
#define MC__UPDOWN             (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
3219 
#define ID__1                  (0*0x40u)      /* Timer A input divider: 0 - /1 */
3220 
#define ID__2                  (1*0x40u)      /* Timer A input divider: 1 - /2 */
3221 
#define ID__4                  (2*0x40u)      /* Timer A input divider: 2 - /4 */
3222 
#define ID__8                  (3*0x40u)      /* Timer A input divider: 3 - /8 */
3223 
#define TASSEL__TACLK          (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
3224 
#define TASSEL__ACLK           (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
3225 
#define TASSEL__SMCLK          (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
3226 
#define TASSEL__INCLK          (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
3227 
 
3228 
/* TAxCCTLx Control Bits */
3229 
#define CM1                    (0x8000)       /* Capture mode 1 */
3230 
#define CM0                    (0x4000)       /* Capture mode 0 */
3231 
#define CCIS1                  (0x2000)       /* Capture input select 1 */
3232 
#define CCIS0                  (0x1000)       /* Capture input select 0 */
3233 
#define SCS                    (0x0800)       /* Capture sychronize */
3234 
#define SCCI                   (0x0400)       /* Latched capture signal (read) */
3235 
#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
3236 
#define OUTMOD2                (0x0080)       /* Output mode 2 */
3237 
#define OUTMOD1                (0x0040)       /* Output mode 1 */
3238 
#define OUTMOD0                (0x0020)       /* Output mode 0 */
3239 
#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
3240 
#define CCI                    (0x0008)       /* Capture input signal (read) */
3241 
#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
3242 
#define COV                    (0x0002)       /* Capture/compare overflow flag */
3243 
#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
3244 
 
3245 
#define OUTMOD_0               (0*0x20u)      /* PWM output mode: 0 - output only */
3246 
#define OUTMOD_1               (1*0x20u)      /* PWM output mode: 1 - set */
3247 
#define OUTMOD_2               (2*0x20u)      /* PWM output mode: 2 - PWM toggle/reset */
3248 
#define OUTMOD_3               (3*0x20u)      /* PWM output mode: 3 - PWM set/reset */
3249 
#define OUTMOD_4               (4*0x20u)      /* PWM output mode: 4 - toggle */
3250 
#define OUTMOD_5               (5*0x20u)      /* PWM output mode: 5 - Reset */
3251 
#define OUTMOD_6               (6*0x20u)      /* PWM output mode: 6 - PWM toggle/set */
3252 
#define OUTMOD_7               (7*0x20u)      /* PWM output mode: 7 - PWM reset/set */
3253 
#define CCIS_0                 (0*0x1000u)    /* Capture input select: 0 - CCIxA */
3254 
#define CCIS_1                 (1*0x1000u)    /* Capture input select: 1 - CCIxB */
3255 
#define CCIS_2                 (2*0x1000u)    /* Capture input select: 2 - GND */
3256 
#define CCIS_3                 (3*0x1000u)    /* Capture input select: 3 - Vcc */
3257 
#define CM_0                   (0*0x4000u)    /* Capture mode: 0 - disabled */
3258 
#define CM_1                   (1*0x4000u)    /* Capture mode: 1 - pos. edge */
3259 
#define CM_2                   (2*0x4000u)    /* Capture mode: 1 - neg. edge */
3260 
#define CM_3                   (3*0x4000u)    /* Capture mode: 1 - both edges */
3261 
 
3262 
/* TAxEX0 Control Bits */
3263 
#define TAIDEX0                (0x0001)       /* Timer A Input divider expansion Bit: 0 */
3264 
#define TAIDEX1                (0x0002)       /* Timer A Input divider expansion Bit: 1 */
3265 
#define TAIDEX2                (0x0004)       /* Timer A Input divider expansion Bit: 2 */
3266 
 
3267 
#define TAIDEX_0               (0*0x0001u)    /* Timer A Input divider expansion : /1 */
3268 
#define TAIDEX_1               (1*0x0001u)    /* Timer A Input divider expansion : /2 */
3269 
#define TAIDEX_2               (2*0x0001u)    /* Timer A Input divider expansion : /3 */
3270 
#define TAIDEX_3               (3*0x0001u)    /* Timer A Input divider expansion : /4 */
3271 
#define TAIDEX_4               (4*0x0001u)    /* Timer A Input divider expansion : /5 */
3272 
#define TAIDEX_5               (5*0x0001u)    /* Timer A Input divider expansion : /6 */
3273 
#define TAIDEX_6               (6*0x0001u)    /* Timer A Input divider expansion : /7 */
3274 
#define TAIDEX_7               (7*0x0001u)    /* Timer A Input divider expansion : /8 */
3275 
 
3276 
/* T0A5IV Definitions */
3277 
#define TA0IV_NONE             (0x0000)       /* No Interrupt pending */
3278 
#define TA0IV_TA0CCR1          (0x0002)       /* TA0CCR1_CCIFG */
3279 
#define TA0IV_TA0CCR2          (0x0004)       /* TA0CCR2_CCIFG */
3280 
#define TA0IV_TA0CCR3          (0x0006)       /* TA0CCR3_CCIFG */
3281 
#define TA0IV_TA0CCR4          (0x0008)       /* TA0CCR4_CCIFG */
3282 
#define TA0IV_5                (0x000A)       /* Reserved */
3283 
#define TA0IV_6                (0x000C)       /* Reserved */
3284 
#define TA0IV_TA0IFG           (0x000E)       /* TA0IFG */
3285 
 
3286 
/************************************************************
3287 
* Timer1_A3
3288 
************************************************************/
3289 
#define __MSP430_HAS_T1A3__                   /* Definition to show that Module is available */
3290 
#define __MSP430_BASEADDRESS_T1A3__ 0x0380
3291 
 
3292 
SFR_16BIT(TA1CTL);                            /* Timer1_A3 Control */
3293 
SFR_16BIT(TA1CCTL0);                          /* Timer1_A3 Capture/Compare Control 0 */
3294 
SFR_16BIT(TA1CCTL1);                          /* Timer1_A3 Capture/Compare Control 1 */
3295 
SFR_16BIT(TA1CCTL2);                          /* Timer1_A3 Capture/Compare Control 2 */
3296 
SFR_16BIT(TA1R);                              /* Timer1_A3 */
3297 
SFR_16BIT(TA1CCR0);                           /* Timer1_A3 Capture/Compare 0 */
3298 
SFR_16BIT(TA1CCR1);                           /* Timer1_A3 Capture/Compare 1 */
3299 
SFR_16BIT(TA1CCR2);                           /* Timer1_A3 Capture/Compare 2 */
3300 
SFR_16BIT(TA1IV);                             /* Timer1_A3 Interrupt Vector Word */
3301 
SFR_16BIT(TA1EX0);                            /* Timer1_A3 Expansion Register 0 */
3302 
 
3303 
/* Bits are already defined within the Timer0_Ax */
3304 
 
3305 
/* TA1IV Definitions */
3306 
#define TA1IV_NONE             (0x0000)       /* No Interrupt pending */
3307 
#define TA1IV_TA1CCR1          (0x0002)       /* TA1CCR1_CCIFG */
3308 
#define TA1IV_TA1CCR2          (0x0004)       /* TA1CCR2_CCIFG */
3309 
#define TA1IV_3                (0x0006)       /* Reserved */
3310 
#define TA1IV_4                (0x0008)       /* Reserved */
3311 
#define TA1IV_5                (0x000A)       /* Reserved */
3312 
#define TA1IV_6                (0x000C)       /* Reserved */
3313 
#define TA1IV_TA1IFG           (0x000E)       /* TA1IFG */
3314 
 
3315 
/************************************************************
3316 
* Timer2_A3
3317 
************************************************************/
3318 
#define __MSP430_HAS_T2A3__                   /* Definition to show that Module is available */
3319 
#define __MSP430_BASEADDRESS_T2A3__ 0x0400
3320 
 
3321 
SFR_16BIT(TA2CTL);                            /* Timer2_A3 Control */
3322 
SFR_16BIT(TA2CCTL0);                          /* Timer2_A3 Capture/Compare Control 0 */
3323 
SFR_16BIT(TA2CCTL1);                          /* Timer2_A3 Capture/Compare Control 1 */
3324 
SFR_16BIT(TA2CCTL2);                          /* Timer2_A3 Capture/Compare Control 2 */
3325 
SFR_16BIT(TA2R);                              /* Timer2_A3 */
3326 
SFR_16BIT(TA2CCR0);                           /* Timer2_A3 Capture/Compare 0 */
3327 
SFR_16BIT(TA2CCR1);                           /* Timer2_A3 Capture/Compare 1 */
3328 
SFR_16BIT(TA2CCR2);                           /* Timer2_A3 Capture/Compare 2 */
3329 
SFR_16BIT(TA2IV);                             /* Timer2_A3 Interrupt Vector Word */
3330 
SFR_16BIT(TA2EX0);                            /* Timer2_A3 Expansion Register 0 */
3331 
 
3332 
/* Bits are already defined within the Timer0_Ax */
3333 
 
3334 
/* TA2IV Definitions */
3335 
#define TA2IV_NONE             (0x0000)       /* No Interrupt pending */
3336 
#define TA2IV_TA1CCR1          (0x0002)       /* TA2CCR1_CCIFG */
3337 
#define TA2IV_TA1CCR2          (0x0004)       /* TA2CCR2_CCIFG */
3338 
#define TA2IV_3                (0x0006)       /* Reserved */
3339 
#define TA2IV_4                (0x0008)       /* Reserved */
3340 
#define TA2IV_5                (0x000A)       /* Reserved */
3341 
#define TA2IV_6                (0x000C)       /* Reserved */
3342 
#define TA2IV_TA2IFG           (0x000E)       /* TA2IFG */
3343 
 
3344 
/************************************************************
3345 
* Timer0_B7
3346 
************************************************************/
3347 
#define __MSP430_HAS_T0B7__                   /* Definition to show that Module is available */
3348 
#define __MSP430_BASEADDRESS_T0B7__ 0x03C0
3349 
 
3350 
SFR_16BIT(TB0CTL);                            /* Timer0_B7 Control */
3351 
SFR_16BIT(TB0CCTL0);                          /* Timer0_B7 Capture/Compare Control 0 */
3352 
SFR_16BIT(TB0CCTL1);                          /* Timer0_B7 Capture/Compare Control 1 */
3353 
SFR_16BIT(TB0CCTL2);                          /* Timer0_B7 Capture/Compare Control 2 */
3354 
SFR_16BIT(TB0CCTL3);                          /* Timer0_B7 Capture/Compare Control 3 */
3355 
SFR_16BIT(TB0CCTL4);                          /* Timer0_B7 Capture/Compare Control 4 */
3356 
SFR_16BIT(TB0CCTL5);                          /* Timer0_B7 Capture/Compare Control 5 */
3357 
SFR_16BIT(TB0CCTL6);                          /* Timer0_B7 Capture/Compare Control 6 */
3358 
SFR_16BIT(TB0R);                              /* Timer0_B7 */
3359 
SFR_16BIT(TB0CCR0);                           /* Timer0_B7 Capture/Compare 0 */
3360 
SFR_16BIT(TB0CCR1);                           /* Timer0_B7 Capture/Compare 1 */
3361 
SFR_16BIT(TB0CCR2);                           /* Timer0_B7 Capture/Compare 2 */
3362 
SFR_16BIT(TB0CCR3);                           /* Timer0_B7 Capture/Compare 3 */
3363 
SFR_16BIT(TB0CCR4);                           /* Timer0_B7 Capture/Compare 4 */
3364 
SFR_16BIT(TB0CCR5);                           /* Timer0_B7 Capture/Compare 5 */
3365 
SFR_16BIT(TB0CCR6);                           /* Timer0_B7 Capture/Compare 6 */
3366 
SFR_16BIT(TB0EX0);                            /* Timer0_B7 Expansion Register 0 */
3367 
SFR_16BIT(TB0IV);                             /* Timer0_B7 Interrupt Vector Word */
3368 
 
3369 
/* Legacy Type Definitions for TimerB */
3370 
#define TBCTL                  TB0CTL         /* Timer0_B7 Control */
3371 
#define TBCCTL0                TB0CCTL0       /* Timer0_B7 Capture/Compare Control 0 */
3372 
#define TBCCTL1                TB0CCTL1       /* Timer0_B7 Capture/Compare Control 1 */
3373 
#define TBCCTL2                TB0CCTL2       /* Timer0_B7 Capture/Compare Control 2 */
3374 
#define TBCCTL3                TB0CCTL3       /* Timer0_B7 Capture/Compare Control 3 */
3375 
#define TBCCTL4                TB0CCTL4       /* Timer0_B7 Capture/Compare Control 4 */
3376 
#define TBCCTL5                TB0CCTL5       /* Timer0_B7 Capture/Compare Control 5 */
3377 
#define TBCCTL6                TB0CCTL6       /* Timer0_B7 Capture/Compare Control 6 */
3378 
#define TBR                    TB0R           /* Timer0_B7 */
3379 
#define TBCCR0                 TB0CCR0        /* Timer0_B7 Capture/Compare 0 */
3380 
#define TBCCR1                 TB0CCR1        /* Timer0_B7 Capture/Compare 1 */
3381 
#define TBCCR2                 TB0CCR2        /* Timer0_B7 Capture/Compare 2 */
3382 
#define TBCCR3                 TB0CCR3        /* Timer0_B7 Capture/Compare 3 */
3383 
#define TBCCR4                 TB0CCR4        /* Timer0_B7 Capture/Compare 4 */
3384 
#define TBCCR5                 TB0CCR5        /* Timer0_B7 Capture/Compare 5 */
3385 
#define TBCCR6                 TB0CCR6        /* Timer0_B7 Capture/Compare 6 */
3386 
#define TBEX0                  TB0EX0         /* Timer0_B7 Expansion Register 0 */
3387 
#define TBIV                   TB0IV          /* Timer0_B7 Interrupt Vector Word */
3388 
#define TIMERB1_VECTOR       TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
3389 
#define TIMERB0_VECTOR       TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
3390 
 
3391 
/* TBxCTL Control Bits */
3392 
#define TBCLGRP1               (0x4000)       /* Timer0_B7 Compare latch load group 1 */
3393 
#define TBCLGRP0               (0x2000)       /* Timer0_B7 Compare latch load group 0 */
3394 
#define CNTL1                  (0x1000)       /* Counter lenght 1 */
3395 
#define CNTL0                  (0x0800)       /* Counter lenght 0 */
3396 
#define TBSSEL1                (0x0200)       /* Clock source 1 */
3397 
#define TBSSEL0                (0x0100)       /* Clock source 0 */
3398 
#define TBCLR                  (0x0004)       /* Timer0_B7 counter clear */
3399 
#define TBIE                   (0x0002)       /* Timer0_B7 interrupt enable */
3400 
#define TBIFG                  (0x0001)       /* Timer0_B7 interrupt flag */
3401 
 
3402 
#define SHR1                   (0x4000)       /* Timer0_B7 Compare latch load group 1 */
3403 
#define SHR0                   (0x2000)       /* Timer0_B7 Compare latch load group 0 */
3404 
 
3405 
#define TBSSEL_0               (0*0x0100u)    /* Clock Source: TBCLK */
3406 
#define TBSSEL_1               (1*0x0100u)    /* Clock Source: ACLK  */
3407 
#define TBSSEL_2               (2*0x0100u)    /* Clock Source: SMCLK */
3408 
#define TBSSEL_3               (3*0x0100u)    /* Clock Source: INCLK */
3409 
#define CNTL_0                 (0*0x0800u)    /* Counter lenght: 16 bit */
3410 
#define CNTL_1                 (1*0x0800u)    /* Counter lenght: 12 bit */
3411 
#define CNTL_2                 (2*0x0800u)    /* Counter lenght: 10 bit */
3412 
#define CNTL_3                 (3*0x0800u)    /* Counter lenght:  8 bit */
3413 
#define SHR_0                  (0*0x2000u)    /* Timer0_B7 Group: 0 - individually */
3414 
#define SHR_1                  (1*0x2000u)    /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
3415 
#define SHR_2                  (2*0x2000u)    /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
3416 
#define SHR_3                  (3*0x2000u)    /* Timer0_B7 Group: 3 - 1 group (all) */
3417 
#define TBCLGRP_0              (0*0x2000u)    /* Timer0_B7 Group: 0 - individually */
3418 
#define TBCLGRP_1              (1*0x2000u)    /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
3419 
#define TBCLGRP_2              (2*0x2000u)    /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
3420 
#define TBCLGRP_3              (3*0x2000u)    /* Timer0_B7 Group: 3 - 1 group (all) */
3421 
#define TBSSEL__TACLK          (0*0x100u)     /* Timer0_B7 clock source select: 0 - TACLK */
3422 
#define TBSSEL__ACLK           (1*0x100u)     /* Timer0_B7 clock source select: 1 - ACLK  */
3423 
#define TBSSEL__SMCLK          (2*0x100u)     /* Timer0_B7 clock source select: 2 - SMCLK */
3424 
#define TBSSEL__INCLK          (3*0x100u)     /* Timer0_B7 clock source select: 3 - INCLK */
3425 
#define CNTL__16               (0*0x0800u)    /* Counter lenght: 16 bit */
3426 
#define CNTL__12               (1*0x0800u)    /* Counter lenght: 12 bit */
3427 
#define CNTL__10               (2*0x0800u)    /* Counter lenght: 10 bit */
3428 
#define CNTL__8                (3*0x0800u)    /* Counter lenght:  8 bit */
3429 
 
3430 
/* Additional Timer B Control Register bits are defined in Timer A */
3431 
/* TBxCCTLx Control Bits */
3432 
#define CLLD1                  (0x0400)       /* Compare latch load source 1 */
3433 
#define CLLD0                  (0x0200)       /* Compare latch load source 0 */
3434 
 
3435 
#define SLSHR1                 (0x0400)       /* Compare latch load source 1 */
3436 
#define SLSHR0                 (0x0200)       /* Compare latch load source 0 */
3437 
 
3438 
#define SLSHR_0                (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
3439 
#define SLSHR_1                (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
3440 
#define SLSHR_2                (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
3441 
#define SLSHR_3                (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
3442 
 
3443 
#define CLLD_0                 (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
3444 
#define CLLD_1                 (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
3445 
#define CLLD_2                 (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
3446 
#define CLLD_3                 (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
3447 
 
3448 
/* TBxEX0 Control Bits */
3449 
#define TBIDEX0                (0x0001)       /* Timer0_B7 Input divider expansion Bit: 0 */
3450 
#define TBIDEX1                (0x0002)       /* Timer0_B7 Input divider expansion Bit: 1 */
3451 
#define TBIDEX2                (0x0004)       /* Timer0_B7 Input divider expansion Bit: 2 */
3452 
 
3453 
#define TBIDEX_0               (0*0x0001u)    /* Timer0_B7 Input divider expansion : /1 */
3454 
#define TBIDEX_1               (1*0x0001u)    /* Timer0_B7 Input divider expansion : /2 */
3455 
#define TBIDEX_2               (2*0x0001u)    /* Timer0_B7 Input divider expansion : /3 */
3456 
#define TBIDEX_3               (3*0x0001u)    /* Timer0_B7 Input divider expansion : /4 */
3457 
#define TBIDEX_4               (4*0x0001u)    /* Timer0_B7 Input divider expansion : /5 */
3458 
#define TBIDEX_5               (5*0x0001u)    /* Timer0_B7 Input divider expansion : /6 */
3459 
#define TBIDEX_6               (6*0x0001u)    /* Timer0_B7 Input divider expansion : /7 */
3460 
#define TBIDEX_7               (7*0x0001u)    /* Timer0_B7 Input divider expansion : /8 */
3461 
#define TBIDEX__1              (0*0x0001u)    /* Timer0_B7 Input divider expansion : /1 */
3462 
#define TBIDEX__2              (1*0x0001u)    /* Timer0_B7 Input divider expansion : /2 */
3463 
#define TBIDEX__3              (2*0x0001u)    /* Timer0_B7 Input divider expansion : /3 */
3464 
#define TBIDEX__4              (3*0x0001u)    /* Timer0_B7 Input divider expansion : /4 */
3465 
#define TBIDEX__5              (4*0x0001u)    /* Timer0_B7 Input divider expansion : /5 */
3466 
#define TBIDEX__6              (5*0x0001u)    /* Timer0_B7 Input divider expansion : /6 */
3467 
#define TBIDEX__7              (6*0x0001u)    /* Timer0_B7 Input divider expansion : /7 */
3468 
#define TBIDEX__8              (7*0x0001u)    /* Timer0_B7 Input divider expansion : /8 */
3469 
 
3470 
/* TB0IV Definitions */
3471 
#define TB0IV_NONE             (0x0000)       /* No Interrupt pending */
3472 
#define TB0IV_TB1CCR1          (0x0002)       /* TBCCR1_CCIFG */
3473 
#define TB0IV_TB1CCR2          (0x0004)       /* TBCCR2_CCIFG */
3474 
#define TB0IV_3                (0x0006)       /* Reserved */
3475 
#define TB0IV_4                (0x0008)       /* Reserved */
3476 
#define TB0IV_5                (0x000A)       /* Reserved */
3477 
#define TB0IV_6                (0x000C)       /* Reserved */
3478 
#define TB0IV_TB0IFG           (0x000E)       /* TBIFG */
3479 
 
3480 
 
3481 
/************************************************************
3482 
* USB
3483 
************************************************************/
3484 
#define __MSP430_HAS_USB__                    /* Definition to show that Module is available */
3485 
#define __MSP430_BASEADDRESS_USB__ 0x0900
3486 
 
3487 
/* ========================================================================= */
3488 
/* USB Configuration Registers */
3489 
/* ========================================================================= */
3490 
SFR_16BIT(USBKEYID);                          /* USB Controller key register */
3491 
SFR_8BIT(USBKEYID_L);                         /* USB Controller key register */
3492 
SFR_8BIT(USBKEYID_H);                         /* USB Controller key register */
3493 
SFR_16BIT(USBCNF);                            /* USB Module  configuration register */
3494 
SFR_8BIT(USBCNF_L);                           /* USB Module  configuration register */
3495 
SFR_8BIT(USBCNF_H);                           /* USB Module  configuration register */
3496 
SFR_16BIT(USBPHYCTL);                         /* USB PHY control register */
3497 
SFR_8BIT(USBPHYCTL_L);                        /* USB PHY control register */
3498 
SFR_8BIT(USBPHYCTL_H);                        /* USB PHY control register */
3499 
SFR_16BIT(USBPWRCTL);                         /* USB Power control register */
3500 
SFR_8BIT(USBPWRCTL_L);                        /* USB Power control register */
3501 
SFR_8BIT(USBPWRCTL_H);                        /* USB Power control register */
3502 
SFR_16BIT(USBPLLCTL);                         /* USB PLL control register */
3503 
SFR_8BIT(USBPLLCTL_L);                        /* USB PLL control register */
3504 
SFR_8BIT(USBPLLCTL_H);                        /* USB PLL control register */
3505 
SFR_16BIT(USBPLLDIVB);                        /* USB PLL Clock Divider Buffer control register */
3506 
SFR_8BIT(USBPLLDIVB_L);                       /* USB PLL Clock Divider Buffer control register */
3507 
SFR_8BIT(USBPLLDIVB_H);                       /* USB PLL Clock Divider Buffer control register */
3508 
SFR_16BIT(USBPLLIR);                          /* USB PLL Interrupt control register */
3509 
SFR_8BIT(USBPLLIR_L);                         /* USB PLL Interrupt control register */
3510 
SFR_8BIT(USBPLLIR_H);                         /* USB PLL Interrupt control register */
3511 
 
3512 
#define USBKEYPID              USBKEYID       /* Legacy Definition: USB Controller key register */
3513 
#define USBKEY                 (0x9628)       /* USB Control Register key */
3514 
 
3515 
/* USBCNF Control Bits */
3516 
#define USB_EN                 (0x0001)       /* USB - Module enable */
3517 
#define PUR_EN                 (0x0002)       /* USB - PUR pin enable */
3518 
#define PUR_IN                 (0x0004)       /* USB - PUR pin input value */
3519 
#define BLKRDY                 (0x0008)       /* USB - Block ready signal for DMA */
3520 
#define FNTEN                  (0x0010)       /* USB - Frame Number receive Trigger enable for DMA */
3521 
//#define RESERVED            (0x0020)  /* USB -  */
3522 
//#define RESERVED            (0x0040)  /* USB -  */
3523 
//#define RESERVED            (0x0080)  /* USB -  */
3524 
//#define RESERVED            (0x0100)  /* USB -  */
3525 
//#define RESERVED            (0x0200)  /* USB -  */
3526 
//#define RESERVED            (0x0400)  /* USB -  */
3527 
//#define RESERVED            (0x0800)  /* USB -  */
3528 
//#define RESERVED            (0x1000)  /* USB -  */
3529 
//#define RESERVED            (0x2000)  /* USB -  */
3530 
//#define RESERVED            (0x4000)  /* USB -  */
3531 
//#define RESERVED            (0x8000)  /* USB -  */
3532 
 
3533 
/* USBCNF Control Bits */
3534 
#define USB_EN_L               (0x0001)       /* USB - Module enable */
3535 
#define PUR_EN_L               (0x0002)       /* USB - PUR pin enable */
3536 
#define PUR_IN_L               (0x0004)       /* USB - PUR pin input value */
3537 
#define BLKRDY_L               (0x0008)       /* USB - Block ready signal for DMA */
3538 
#define FNTEN_L                (0x0010)       /* USB - Frame Number receive Trigger enable for DMA */
3539 
//#define RESERVED            (0x0020)  /* USB -  */
3540 
//#define RESERVED            (0x0040)  /* USB -  */
3541 
//#define RESERVED            (0x0080)  /* USB -  */
3542 
//#define RESERVED            (0x0100)  /* USB -  */
3543 
//#define RESERVED            (0x0200)  /* USB -  */
3544 
//#define RESERVED            (0x0400)  /* USB -  */
3545 
//#define RESERVED            (0x0800)  /* USB -  */
3546 
//#define RESERVED            (0x1000)  /* USB -  */
3547 
//#define RESERVED            (0x2000)  /* USB -  */
3548 
//#define RESERVED            (0x4000)  /* USB -  */
3549 
//#define RESERVED            (0x8000)  /* USB -  */
3550 
 
3551 
/* USBCNF Control Bits */
3552 
//#define RESERVED            (0x0020)  /* USB -  */
3553 
//#define RESERVED            (0x0040)  /* USB -  */
3554 
//#define RESERVED            (0x0080)  /* USB -  */
3555 
//#define RESERVED            (0x0100)  /* USB -  */
3556 
//#define RESERVED            (0x0200)  /* USB -  */
3557 
//#define RESERVED            (0x0400)  /* USB -  */
3558 
//#define RESERVED            (0x0800)  /* USB -  */
3559 
//#define RESERVED            (0x1000)  /* USB -  */
3560 
//#define RESERVED            (0x2000)  /* USB -  */
3561 
//#define RESERVED            (0x4000)  /* USB -  */
3562 
//#define RESERVED            (0x8000)  /* USB -  */
3563 
 
3564 
/* USBPHYCTL Control Bits */
3565 
#define PUOUT0                 (0x0001)       /* USB - USB Port Output Signal Bit 0 */
3566 
#define PUOUT1                 (0x0002)       /* USB - USB Port Output Signal Bit 1 */
3567 
#define PUIN0                  (0x0004)       /* USB - PU0/DP Input Data */
3568 
#define PUIN1                  (0x0008)       /* USB - PU1/DM Input Data */
3569 
//#define RESERVED            (0x0010)  /* USB -  */
3570 
#define PUOPE                  (0x0020)       /* USB - USB Port Output Enable */
3571 
//#define RESERVED            (0x0040)  /* USB -  */
3572 
#define PUSEL                  (0x0080)       /* USB - USB Port Function Select */
3573 
#define PUIPE                  (0x0100)       /* USB - PHY Single Ended Input enable */
3574 
//#define RESERVED            (0x0200)  /* USB -  */
3575 
//#define RESERVED            (0x0100)  /* USB -  */
3576 
//#define RESERVED            (0x0200)  /* USB -  */
3577 
//#define RESERVED            (0x0400)  /* USB -  */
3578 
//#define RESERVED            (0x0800)  /* USB -  */
3579 
//#define RESERVED            (0x1000)  /* USB -  */
3580 
//#define RESERVED            (0x2000)  /* USB -  */
3581 
//#define RESERVED            (0x4000)  /* USB -  */
3582 
//#define RESERVED            (0x8000)  /* USB -  */
3583 
 
3584 
/* USBPHYCTL Control Bits */
3585 
#define PUOUT0_L               (0x0001)       /* USB - USB Port Output Signal Bit 0 */
3586 
#define PUOUT1_L               (0x0002)       /* USB - USB Port Output Signal Bit 1 */
3587 
#define PUIN0_L                (0x0004)       /* USB - PU0/DP Input Data */
3588 
#define PUIN1_L                (0x0008)       /* USB - PU1/DM Input Data */
3589 
//#define RESERVED            (0x0010)  /* USB -  */
3590 
#define PUOPE_L                (0x0020)       /* USB - USB Port Output Enable */
3591 
//#define RESERVED            (0x0040)  /* USB -  */
3592 
#define PUSEL_L                (0x0080)       /* USB - USB Port Function Select */
3593 
//#define RESERVED            (0x0200)  /* USB -  */
3594 
//#define RESERVED            (0x0100)  /* USB -  */
3595 
//#define RESERVED            (0x0200)  /* USB -  */
3596 
//#define RESERVED            (0x0400)  /* USB -  */
3597 
//#define RESERVED            (0x0800)  /* USB -  */
3598 
//#define RESERVED            (0x1000)  /* USB -  */
3599 
//#define RESERVED            (0x2000)  /* USB -  */
3600 
//#define RESERVED            (0x4000)  /* USB -  */
3601 
//#define RESERVED            (0x8000)  /* USB -  */
3602 
 
3603 
/* USBPHYCTL Control Bits */
3604 
//#define RESERVED            (0x0010)  /* USB -  */
3605 
//#define RESERVED            (0x0040)  /* USB -  */
3606 
#define PUIPE_H                (0x0001)       /* USB - PHY Single Ended Input enable */
3607 
//#define RESERVED            (0x0200)  /* USB -  */
3608 
//#define RESERVED            (0x0100)  /* USB -  */
3609 
//#define RESERVED            (0x0200)  /* USB -  */
3610 
//#define RESERVED            (0x0400)  /* USB -  */
3611 
//#define RESERVED            (0x0800)  /* USB -  */
3612 
//#define RESERVED            (0x1000)  /* USB -  */
3613 
//#define RESERVED            (0x2000)  /* USB -  */
3614 
//#define RESERVED            (0x4000)  /* USB -  */
3615 
//#define RESERVED            (0x8000)  /* USB -  */
3616 
 
3617 
#define PUDIR                  (0x0020)       /* USB - Legacy Definition: USB Port Output Enable */
3618 
#define PSEIEN                 (0x0100)       /* USB - Legacy Definition: PHY Single Ended Input enable */
3619 
 
3620 
/* USBPWRCTL Control Bits */
3621 
#define VUOVLIFG               (0x0001)       /* USB - VUSB Overload Interrupt Flag */
3622 
#define VBONIFG                (0x0002)       /* USB - VBUS "Coming ON" Interrupt Flag */
3623 
#define VBOFFIFG               (0x0004)       /* USB - VBUS "Going OFF" Interrupt Flag */
3624 
#define USBBGVBV               (0x0008)       /* USB - USB Bandgap and VBUS valid */
3625 
#define USBDETEN               (0x0010)       /* USB - VBUS on/off events enable */
3626 
#define OVLAOFF                (0x0020)       /* USB - LDO overload auto off enable */
3627 
#define SLDOAON                (0x0040)       /* USB - Secondary LDO auto on enable */
3628 
//#define RESERVED            (0x0080)  /* USB -  */
3629 
#define VUOVLIE                (0x0100)       /* USB - Overload indication Interrupt Enable */
3630 
#define VBONIE                 (0x0200)       /* USB - VBUS "Coming ON" Interrupt Enable */
3631 
#define VBOFFIE                (0x0400)       /* USB - VBUS "Going OFF" Interrupt Enable */
3632 
#define VUSBEN                 (0x0800)       /* USB - LDO Enable (3.3V) */
3633 
#define SLDOEN                 (0x1000)       /* USB - Secondary LDO Enable (1.8V) */
3634 
//#define RESERVED            (0x2000)  /* USB -  */
3635 
//#define RESERVED            (0x4000)  /* USB -  */
3636 
//#define RESERVED            (0x8000)  /* USB -  */
3637 
 
3638 
/* USBPWRCTL Control Bits */
3639 
#define VUOVLIFG_L             (0x0001)       /* USB - VUSB Overload Interrupt Flag */
3640 
#define VBONIFG_L              (0x0002)       /* USB - VBUS "Coming ON" Interrupt Flag */
3641 
#define VBOFFIFG_L             (0x0004)       /* USB - VBUS "Going OFF" Interrupt Flag */
3642 
#define USBBGVBV_L             (0x0008)       /* USB - USB Bandgap and VBUS valid */
3643 
#define USBDETEN_L             (0x0010)       /* USB - VBUS on/off events enable */
3644 
#define OVLAOFF_L              (0x0020)       /* USB - LDO overload auto off enable */
3645 
#define SLDOAON_L              (0x0040)       /* USB - Secondary LDO auto on enable */
3646 
//#define RESERVED            (0x0080)  /* USB -  */
3647 
//#define RESERVED            (0x2000)  /* USB -  */
3648 
//#define RESERVED            (0x4000)  /* USB -  */
3649 
//#define RESERVED            (0x8000)  /* USB -  */
3650 
 
3651 
/* USBPWRCTL Control Bits */
3652 
//#define RESERVED            (0x0080)  /* USB -  */
3653 
#define VUOVLIE_H              (0x0001)       /* USB - Overload indication Interrupt Enable */
3654 
#define VBONIE_H               (0x0002)       /* USB - VBUS "Coming ON" Interrupt Enable */
3655 
#define VBOFFIE_H              (0x0004)       /* USB - VBUS "Going OFF" Interrupt Enable */
3656 
#define VUSBEN_H               (0x0008)       /* USB - LDO Enable (3.3V) */
3657 
#define SLDOEN_H               (0x0010)       /* USB - Secondary LDO Enable (1.8V) */
3658 
//#define RESERVED            (0x2000)  /* USB -  */
3659 
//#define RESERVED            (0x4000)  /* USB -  */
3660 
//#define RESERVED            (0x8000)  /* USB -  */
3661 
 
3662 
/* USBPLLCTL Control Bits */
3663 
//#define RESERVED            (0x0001)  /* USB -  */
3664 
//#define RESERVED            (0x0002)  /* USB -  */
3665 
//#define RESERVED            (0x0004)  /* USB -  */
3666 
//#define RESERVED            (0x0008)  /* USB -  */
3667 
//#define RESERVED            (0x0010)  /* USB -  */
3668 
//#define RESERVED            (0x0020)  /* USB -  */
3669 
#define UCLKSEL0               (0x0040)       /* USB - Module Clock Select Bit 0 */
3670 
#define UCLKSEL1               (0x0080)       /* USB - Module Clock Select Bit 1 */
3671 
#define UPLLEN                 (0x0100)       /* USB - PLL enable */
3672 
#define UPFDEN                 (0x0200)       /* USB - Phase Freq. Discriminator enable */
3673 
//#define RESERVED            (0x0400)  /* USB -  */
3674 
//#define RESERVED            (0x0800)  /* USB -  */
3675 
#define UPCS0                  (0x1000)       /* USB - PLL Clock Select Bit 0 */
3676 
//#define RESERVED            (0x2000)  /* USB -  */
3677 
//#define RESERVED            (0x4000)  /* USB -  */
3678 
//#define RESERVED            (0x8000)  /* USB -  */
3679 
 
3680 
/* USBPLLCTL Control Bits */
3681 
//#define RESERVED            (0x0001)  /* USB -  */
3682 
//#define RESERVED            (0x0002)  /* USB -  */
3683 
//#define RESERVED            (0x0004)  /* USB -  */
3684 
//#define RESERVED            (0x0008)  /* USB -  */
3685 
//#define RESERVED            (0x0010)  /* USB -  */
3686 
//#define RESERVED            (0x0020)  /* USB -  */
3687 
#define UCLKSEL0_L             (0x0040)       /* USB - Module Clock Select Bit 0 */
3688 
#define UCLKSEL1_L             (0x0080)       /* USB - Module Clock Select Bit 1 */
3689 
//#define RESERVED            (0x0400)  /* USB -  */
3690 
//#define RESERVED            (0x0800)  /* USB -  */
3691 
//#define RESERVED            (0x2000)  /* USB -  */
3692 
//#define RESERVED            (0x4000)  /* USB -  */
3693 
//#define RESERVED            (0x8000)  /* USB -  */
3694 
 
3695 
/* USBPLLCTL Control Bits */
3696 
//#define RESERVED            (0x0001)  /* USB -  */
3697 
//#define RESERVED            (0x0002)  /* USB -  */
3698 
//#define RESERVED            (0x0004)  /* USB -  */
3699 
//#define RESERVED            (0x0008)  /* USB -  */
3700 
//#define RESERVED            (0x0010)  /* USB -  */
3701 
//#define RESERVED            (0x0020)  /* USB -  */
3702 
#define UPLLEN_H               (0x0001)       /* USB - PLL enable */
3703 
#define UPFDEN_H               (0x0002)       /* USB - Phase Freq. Discriminator enable */
3704 
//#define RESERVED            (0x0400)  /* USB -  */
3705 
//#define RESERVED            (0x0800)  /* USB -  */
3706 
#define UPCS0_H                (0x0010)       /* USB - PLL Clock Select Bit 0 */
3707 
//#define RESERVED            (0x2000)  /* USB -  */
3708 
//#define RESERVED            (0x4000)  /* USB -  */
3709 
//#define RESERVED            (0x8000)  /* USB -  */
3710 
 
3711 
#define UCLKSEL_0              (0x0000)       /* USB - Module Clock Select: 0 */
3712 
#define UCLKSEL_1              (0x0040)       /* USB - Module Clock Select: 1 */
3713 
#define UCLKSEL_2              (0x0080)       /* USB - Module Clock Select: 2 */
3714 
#define UCLKSEL_3              (0x00C0)       /* USB - Module Clock Select: 3 (Reserved) */
3715 
 
3716 
#define UCLKSEL__PLLCLK        (0x0000)       /* USB - Module Clock Select: PLLCLK */
3717 
#define UCLKSEL__XT1CLK        (0x0040)       /* USB - Module Clock Select: XT1CLK */
3718 
#define UCLKSEL__XT2CLK        (0x0080)       /* USB - Module Clock Select: XT2CLK */
3719 
 
3720 
/* USBPLLDIVB Control Bits */
3721 
#define UPMB0                  (0x0001)       /* USB - PLL feedback divider buffer Bit 0 */
3722 
#define UPMB1                  (0x0002)       /* USB - PLL feedback divider buffer Bit 1 */
3723 
#define UPMB2                  (0x0004)       /* USB - PLL feedback divider buffer Bit 2 */
3724 
#define UPMB3                  (0x0008)       /* USB - PLL feedback divider buffer Bit 3 */
3725 
#define UPMB4                  (0x0010)       /* USB - PLL feedback divider buffer Bit 4 */
3726 
#define UPMB5                  (0x0020)       /* USB - PLL feedback divider buffer Bit 5 */
3727 
//#define RESERVED            (0x0040)  /* USB -  */
3728 
//#define RESERVED            (0x0080)  /* USB -  */
3729 
#define UPQB0                  (0x0100)       /* USB - PLL prescale divider buffer Bit 0 */
3730 
#define UPQB1                  (0x0200)       /* USB - PLL prescale divider buffer Bit 1 */
3731 
#define UPQB2                  (0x0400)       /* USB - PLL prescale divider buffer Bit 2 */
3732 
//#define RESERVED            (0x0800)  /* USB -  */
3733 
//#define RESERVED            (0x1000)  /* USB -  */
3734 
//#define RESERVED            (0x2000)  /* USB -  */
3735 
//#define RESERVED            (0x4000)  /* USB -  */
3736 
//#define RESERVED            (0x8000)  /* USB -  */
3737 
 
3738 
/* USBPLLDIVB Control Bits */
3739 
#define UPMB0_L                (0x0001)       /* USB - PLL feedback divider buffer Bit 0 */
3740 
#define UPMB1_L                (0x0002)       /* USB - PLL feedback divider buffer Bit 1 */
3741 
#define UPMB2_L                (0x0004)       /* USB - PLL feedback divider buffer Bit 2 */
3742 
#define UPMB3_L                (0x0008)       /* USB - PLL feedback divider buffer Bit 3 */
3743 
#define UPMB4_L                (0x0010)       /* USB - PLL feedback divider buffer Bit 4 */
3744 
#define UPMB5_L                (0x0020)       /* USB - PLL feedback divider buffer Bit 5 */
3745 
//#define RESERVED            (0x0040)  /* USB -  */
3746 
//#define RESERVED            (0x0080)  /* USB -  */
3747 
//#define RESERVED            (0x0800)  /* USB -  */
3748 
//#define RESERVED            (0x1000)  /* USB -  */
3749 
//#define RESERVED            (0x2000)  /* USB -  */
3750 
//#define RESERVED            (0x4000)  /* USB -  */
3751 
//#define RESERVED            (0x8000)  /* USB -  */
3752 
 
3753 
/* USBPLLDIVB Control Bits */
3754 
//#define RESERVED            (0x0040)  /* USB -  */
3755 
//#define RESERVED            (0x0080)  /* USB -  */
3756 
#define UPQB0_H                (0x0001)       /* USB - PLL prescale divider buffer Bit 0 */
3757 
#define UPQB1_H                (0x0002)       /* USB - PLL prescale divider buffer Bit 1 */
3758 
#define UPQB2_H                (0x0004)       /* USB - PLL prescale divider buffer Bit 2 */
3759 
//#define RESERVED            (0x0800)  /* USB -  */
3760 
//#define RESERVED            (0x1000)  /* USB -  */
3761 
//#define RESERVED            (0x2000)  /* USB -  */
3762 
//#define RESERVED            (0x4000)  /* USB -  */
3763 
//#define RESERVED            (0x8000)  /* USB -  */
3764 
 
3765 
#define USBPLL_SETCLK_1_5      (UPMB0*31      | UPQB0*0)  /* USB - PLL Set for 1.5 MHz input clock */
3766 
#define USBPLL_SETCLK_1_6      (UPMB0*29      | UPQB0*0)  /* USB - PLL Set for 1.6 MHz input clock */
3767 
#define USBPLL_SETCLK_1_7778   (UPMB0*26      | UPQB0*0)  /* USB - PLL Set for 1.7778 MHz input clock */
3768 
#define USBPLL_SETCLK_1_8432   (UPMB0*25      | UPQB0*0)  /* USB - PLL Set for 1.8432 MHz input clock */
3769 
#define USBPLL_SETCLK_1_8461   (UPMB0*25      | UPQB0*0)  /* USB - PLL Set for 1.8461 MHz input clock */
3770 
#define USBPLL_SETCLK_1_92     (UPMB0*24      | UPQB0*0)  /* USB - PLL Set for 1.92 MHz input clock */
3771 
#define USBPLL_SETCLK_2_0      (UPMB0*23      | UPQB0*0)  /* USB - PLL Set for 2.0 MHz input clock */
3772 
#define USBPLL_SETCLK_2_4      (UPMB0*19      | UPQB0*0)  /* USB - PLL Set for 2.4 MHz input clock */
3773 
#define USBPLL_SETCLK_2_6667   (UPMB0*17      | UPQB0*0)  /* USB - PLL Set for 2.6667 MHz input clock */
3774 
#define USBPLL_SETCLK_3_0      (UPMB0*15      | UPQB0*0)  /* USB - PLL Set for 3.0 MHz input clock */
3775 
#define USBPLL_SETCLK_3_2      (UPMB0*29      | UPQB0*1)  /* USB - PLL Set for 3.2 MHz input clock */
3776 
#define USBPLL_SETCLK_3_5556   (UPMB0*26      | UPQB0*1)  /* USB - PLL Set for 3.5556 MHz input clock */
3777 
#define USBPLL_SETCLK_3_579545 (UPMB0*26      | UPQB0*1)  /* USB - PLL Set for 3.579546 MHz input clock */
3778 
#define USBPLL_SETCLK_3_84     (UPMB0*24      | UPQB0*1)  /* USB - PLL Set for 3.84 MHz input clock */
3779 
#define USBPLL_SETCLK_4_0      (UPMB0*23      | UPQB0*1)  /* USB - PLL Set for 4.0 MHz input clock */
3780 
#define USBPLL_SETCLK_4_1739   (UPMB0*22      | UPQB0*1)  /* USB - PLL Set for 4.1739 MHz input clock */
3781 
#define USBPLL_SETCLK_4_1943   (UPMB0*22      | UPQB0*1)  /* USB - PLL Set for 4.1943 MHz input clock */
3782 
#define USBPLL_SETCLK_4_332    (UPMB0*21      | UPQB0*1)  /* USB - PLL Set for 4.332 MHz input clock */
3783 
#define USBPLL_SETCLK_4_3636   (UPMB0*21      | UPQB0*1)  /* USB - PLL Set for 4.3636 MHz input clock */
3784 
#define USBPLL_SETCLK_4_5      (UPMB0*31      | UPQB0*2)  /* USB - PLL Set for 4.5 MHz input clock */
3785 
#define USBPLL_SETCLK_4_8      (UPMB0*19      | UPQB0*1)  /* USB - PLL Set for 4.8 MHz input clock */
3786 
#define USBPLL_SETCLK_5_33     (UPMB0*17      | UPQB0*1)  /* USB - PLL Set for 5.33 MHz input clock */
3787 
#define USBPLL_SETCLK_5_76     (UPMB0*24      | UPQB0*2)  /* USB - PLL Set for 5.76 MHz input clock */
3788 
#define USBPLL_SETCLK_6_0      (UPMB0*23      | UPQB0*2)  /* USB - PLL Set for 6.0 MHz input clock */
3789 
#define USBPLL_SETCLK_6_4      (UPMB0*29      | UPQB0*3)  /* USB - PLL Set for 6.4 MHz input clock */
3790 
#define USBPLL_SETCLK_7_2      (UPMB0*19      | UPQB0*2)  /* USB - PLL Set for 7.2 MHz input clock */
3791 
#define USBPLL_SETCLK_7_68     (UPMB0*24      | UPQB0*3)  /* USB - PLL Set for 7.68 MHz input clock */
3792 
#define USBPLL_SETCLK_8_0      (UPMB0*17      | UPQB0*2)  /* USB - PLL Set for 8.0 MHz input clock */
3793 
#define USBPLL_SETCLK_9_0      (UPMB0*15      | UPQB0*2)  /* USB - PLL Set for 9.0 MHz input clock */
3794 
#define USBPLL_SETCLK_9_6      (UPMB0*19      | UPQB0*3)  /* USB - PLL Set for 9.6 MHz input clock */
3795 
#define USBPLL_SETCLK_10_66    (UPMB0*17      | UPQB0*3)  /* USB - PLL Set for 10.66 MHz input clock */
3796 
#define USBPLL_SETCLK_12_0     (UPMB0*15      | UPQB0*3)  /* USB - PLL Set for 12.0 MHz input clock */
3797 
#define USBPLL_SETCLK_12_8     (UPMB0*29      | UPQB0*5)  /* USB - PLL Set for 12.8 MHz input clock */
3798 
#define USBPLL_SETCLK_14_4     (UPMB0*19      | UPQB0*4)  /* USB - PLL Set for 14.4 MHz input clock */
3799 
#define USBPLL_SETCLK_16_0     (UPMB0*17      | UPQB0*4)  /* USB - PLL Set for 16.0 MHz input clock */
3800 
#define USBPLL_SETCLK_16_9344  (UPMB0*16      | UPQB0*4)  /* USB - PLL Set for 16.9344 MHz input clock */
3801 
#define USBPLL_SETCLK_16_94118 (UPMB0*16      | UPQB0*4)  /* USB - PLL Set for 16.94118 MHz input clock */
3802 
#define USBPLL_SETCLK_18_0     (UPMB0*15      | UPQB0*4)  /* USB - PLL Set for 18.0 MHz input clock */
3803 
#define USBPLL_SETCLK_19_2     (UPMB0*19      | UPQB0*5)  /* USB - PLL Set for 19.2 MHz input clock */
3804 
#define USBPLL_SETCLK_24_0     (UPMB0*15      | UPQB0*5)  /* USB - PLL Set for 24.0 MHz input clock */
3805 
#define USBPLL_SETCLK_25_6     (UPMB0*29      | UPQB0*7)  /* USB - PLL Set for 25.6 MHz input clock */
3806 
#define USBPLL_SETCLK_26_0     (UPMB0*23      | UPQB0*6)  /* USB - PLL Set for 26.0 MHz input clock */
3807 
#define USBPLL_SETCLK_32_0     (UPMB0*23      | UPQB0*7)  /* USB - PLL Set for 32.0 MHz input clock */
3808 
 
3809 
/* USBPLLIR Control Bits */
3810 
#define USBOOLIFG              (0x0001)       /* USB - PLL out of lock Interrupt Flag */
3811 
#define USBLOSIFG              (0x0002)       /* USB - PLL loss of signal Interrupt Flag */
3812 
#define USBOORIFG              (0x0004)       /* USB - PLL out of range Interrupt Flag */
3813 
//#define RESERVED            (0x0008)  /* USB -  */
3814 
//#define RESERVED            (0x0010)  /* USB -  */
3815 
//#define RESERVED            (0x0020)  /* USB -  */
3816 
//#define RESERVED            (0x0040)  /* USB -  */
3817 
//#define RESERVED            (0x0080)  /* USB -  */
3818 
#define USBOOLIE               (0x0100)       /* USB - PLL out of lock Interrupt enable */
3819 
#define USBLOSIE               (0x0200)       /* USB - PLL loss of signal Interrupt enable */
3820 
#define USBOORIE               (0x0400)       /* USB - PLL out of range Interrupt enable */
3821 
//#define RESERVED            (0x0800)  /* USB -  */
3822 
//#define RESERVED            (0x1000)  /* USB -  */
3823 
//#define RESERVED            (0x2000)  /* USB -  */
3824 
//#define RESERVED            (0x4000)  /* USB -  */
3825 
//#define RESERVED            (0x8000)  /* USB -  */
3826 
 
3827 
/* USBPLLIR Control Bits */
3828 
#define USBOOLIFG_L            (0x0001)       /* USB - PLL out of lock Interrupt Flag */
3829 
#define USBLOSIFG_L            (0x0002)       /* USB - PLL loss of signal Interrupt Flag */
3830 
#define USBOORIFG_L            (0x0004)       /* USB - PLL out of range Interrupt Flag */
3831 
//#define RESERVED            (0x0008)  /* USB -  */
3832 
//#define RESERVED            (0x0010)  /* USB -  */
3833 
//#define RESERVED            (0x0020)  /* USB -  */
3834 
//#define RESERVED            (0x0040)  /* USB -  */
3835 
//#define RESERVED            (0x0080)  /* USB -  */
3836 
//#define RESERVED            (0x0800)  /* USB -  */
3837 
//#define RESERVED            (0x1000)  /* USB -  */
3838 
//#define RESERVED            (0x2000)  /* USB -  */
3839 
//#define RESERVED            (0x4000)  /* USB -  */
3840 
//#define RESERVED            (0x8000)  /* USB -  */
3841 
 
3842 
/* USBPLLIR Control Bits */
3843 
//#define RESERVED            (0x0008)  /* USB -  */
3844 
//#define RESERVED            (0x0010)  /* USB -  */
3845 
//#define RESERVED            (0x0020)  /* USB -  */
3846 
//#define RESERVED            (0x0040)  /* USB -  */
3847 
//#define RESERVED            (0x0080)  /* USB -  */
3848 
#define USBOOLIE_H             (0x0001)       /* USB - PLL out of lock Interrupt enable */
3849 
#define USBLOSIE_H             (0x0002)       /* USB - PLL loss of signal Interrupt enable */
3850 
#define USBOORIE_H             (0x0004)       /* USB - PLL out of range Interrupt enable */
3851 
//#define RESERVED            (0x0800)  /* USB -  */
3852 
//#define RESERVED            (0x1000)  /* USB -  */
3853 
//#define RESERVED            (0x2000)  /* USB -  */
3854 
//#define RESERVED            (0x4000)  /* USB -  */
3855 
//#define RESERVED            (0x8000)  /* USB -  */
3856 
 
3857 
/* ========================================================================= */
3858 
/* USB Control Registers */
3859 
/* ========================================================================= */
3860 
SFR_8BIT(USBIEPCNF_0);                        /* USB Input endpoint_0: Configuration */
3861 
SFR_8BIT(USBIEPCNT_0);                        /* USB Input endpoint_0: Byte Count */
3862 
SFR_8BIT(USBOEPCNF_0);                        /* USB Output endpoint_0: Configuration */
3863 
SFR_8BIT(USBOEPCNT_0);                        /* USB Output endpoint_0: byte count */
3864 
SFR_8BIT(USBIEPIE);                           /* USB Input endpoint interrupt enable flags */
3865 
SFR_8BIT(USBOEPIE);                           /* USB Output endpoint interrupt enable flags */
3866 
SFR_8BIT(USBIEPIFG);                          /* USB Input endpoint interrupt flags */
3867 
SFR_8BIT(USBOEPIFG);                          /* USB Output endpoint interrupt flags */
3868 
SFR_16BIT(USBVECINT);                         /* USB Vector interrupt register */
3869 
SFR_8BIT(USBVECINT_L);                        /* USB Vector interrupt register */
3870 
SFR_8BIT(USBVECINT_H);                        /* USB Vector interrupt register */
3871 
SFR_16BIT(USBMAINT);                          /* USB maintenance register */
3872 
SFR_8BIT(USBMAINT_L);                         /* USB maintenance register */
3873 
SFR_8BIT(USBMAINT_H);                         /* USB maintenance register */
3874 
SFR_16BIT(USBTSREG);                          /* USB Time Stamp register */
3875 
SFR_8BIT(USBTSREG_L);                         /* USB Time Stamp register */
3876 
SFR_8BIT(USBTSREG_H);                         /* USB Time Stamp register */
3877 
SFR_16BIT(USBFN);                             /* USB Frame number */
3878 
SFR_8BIT(USBFN_L);                            /* USB Frame number */
3879 
SFR_8BIT(USBFN_H);                            /* USB Frame number */
3880 
SFR_8BIT(USBCTL);                             /* USB control register */
3881 
SFR_8BIT(USBIE);                              /* USB interrupt enable register */
3882 
SFR_8BIT(USBIFG);                             /* USB interrupt flag register */
3883 
SFR_8BIT(USBFUNADR);                          /* USB Function address register */
3884 
 
3885 
#define USBIV                  USBVECINT      /* USB Vector interrupt register (alternate define) */
3886 
 
3887 
/* USBIEPCNF_0 Control Bits */
3888 
/* USBOEPCNF_0 Control Bits */
3889 
//#define RESERVED       (0x0001)  /* USB -  */
3890 
//#define RESERVED       (0x0001)  /* USB -  */
3891 
#define USBIIE                 (0x0004)       /* USB - Transaction Interrupt indication enable */
3892 
#define STALL                  (0x0008)       /* USB - Stall Condition */
3893 
//#define RESERVED       (0x0010)  /* USB -  */
3894 
#define TOGGLE                 (0x0020)       /* USB - Toggle Bit */
3895 
//#define RESERVED       (0x0040)  /* USB -  */
3896 
#define UBME                   (0x0080)       /* USB - UBM In-Endpoint Enable */
3897 
 
3898 
/* USBIEPBCNT_0 Control Bits */
3899 
/* USBOEPBCNT_0 Control Bits */
3900 
#define CNT0                   (0x0001)       /* USB - Byte Count Bit 0 */
3901 
#define CNT1                   (0x0001)       /* USB - Byte Count Bit 1 */
3902 
#define CNT2                   (0x0004)       /* USB - Byte Count Bit 2 */
3903 
#define CNT3                   (0x0008)       /* USB - Byte Count Bit 3 */
3904 
//#define RESERVED       (0x0010)  /* USB -  */
3905 
//#define RESERVED       (0x0020)  /* USB -  */
3906 
//#define RESERVED       (0x0040)  /* USB -  */
3907 
#define NAK                    (0x0080)       /* USB - No Acknowledge Status Bit */
3908 
 
3909 
/* USBMAINT Control Bits */
3910 
#define UTIFG                  (0x0001)       /* USB - Timer Interrupt Flag */
3911 
#define UTIE                   (0x0002)       /* USB - Timer Interrupt Enable */
3912 
//#define RESERVED       (0x0004)  /* USB -  */
3913 
//#define RESERVED       (0x0008)  /* USB -  */
3914 
//#define RESERVED       (0x0010)  /* USB -  */
3915 
//#define RESERVED       (0x0020)  /* USB -  */
3916 
//#define RESERVED       (0x0040)  /* USB -  */
3917 
//#define RESERVED       (0x0080)  /* USB -  */
3918 
#define TSGEN                  (0x0100)       /* USB - Time Stamp Generator Enable */
3919 
#define TSESEL0                (0x0200)       /* USB - Time Stamp Event Select Bit 0 */
3920 
#define TSESEL1                (0x0400)       /* USB - Time Stamp Event Select Bit 1 */
3921 
#define TSE3                   (0x0800)       /* USB - Time Stamp Event #3 Bit */
3922 
//#define RESERVED       (0x1000)  /* USB -  */
3923 
#define UTSEL0                 (0x2000)       /* USB - Timer Select Bit 0 */
3924 
#define UTSEL1                 (0x4000)       /* USB - Timer Select Bit 1 */
3925 
#define UTSEL2                 (0x8000)       /* USB - Timer Select Bit 2 */
3926 
 
3927 
/* USBMAINT Control Bits */
3928 
#define UTIFG_L                (0x0001)       /* USB - Timer Interrupt Flag */
3929 
#define UTIE_L                 (0x0002)       /* USB - Timer Interrupt Enable */
3930 
//#define RESERVED       (0x0004)  /* USB -  */
3931 
//#define RESERVED       (0x0008)  /* USB -  */
3932 
//#define RESERVED       (0x0010)  /* USB -  */
3933 
//#define RESERVED       (0x0020)  /* USB -  */
3934 
//#define RESERVED       (0x0040)  /* USB -  */
3935 
//#define RESERVED       (0x0080)  /* USB -  */
3936 
//#define RESERVED       (0x1000)  /* USB -  */
3937 
 
3938 
/* USBMAINT Control Bits */
3939 
//#define RESERVED       (0x0004)  /* USB -  */
3940 
//#define RESERVED       (0x0008)  /* USB -  */
3941 
//#define RESERVED       (0x0010)  /* USB -  */
3942 
//#define RESERVED       (0x0020)  /* USB -  */
3943 
//#define RESERVED       (0x0040)  /* USB -  */
3944 
//#define RESERVED       (0x0080)  /* USB -  */
3945 
#define TSGEN_H                (0x0001)       /* USB - Time Stamp Generator Enable */
3946 
#define TSESEL0_H              (0x0002)       /* USB - Time Stamp Event Select Bit 0 */
3947 
#define TSESEL1_H              (0x0004)       /* USB - Time Stamp Event Select Bit 1 */
3948 
#define TSE3_H                 (0x0008)       /* USB - Time Stamp Event #3 Bit */
3949 
//#define RESERVED       (0x1000)  /* USB -  */
3950 
#define UTSEL0_H               (0x0020)       /* USB - Timer Select Bit 0 */
3951 
#define UTSEL1_H               (0x0040)       /* USB - Timer Select Bit 1 */
3952 
#define UTSEL2_H               (0x0080)       /* USB - Timer Select Bit 2 */
3953 
 
3954 
#define TSESEL_0               (0x0000)       /* USB - Time Stamp Event Select: 0 */
3955 
#define TSESEL_1               (0x0200)       /* USB - Time Stamp Event Select: 1 */
3956 
#define TSESEL_2               (0x0400)       /* USB - Time Stamp Event Select: 2 */
3957 
#define TSESEL_3               (0x0600)       /* USB - Time Stamp Event Select: 3 */
3958 
 
3959 
#define UTSEL_0                (0x0000)       /* USB - Timer Select: 0 */
3960 
#define UTSEL_1                (0x2000)       /* USB - Timer Select: 1 */
3961 
#define UTSEL_2                (0x4000)       /* USB - Timer Select: 2 */
3962 
#define UTSEL_3                (0x6000)       /* USB - Timer Select: 3 */
3963 
#define UTSEL_4                (0x8000)       /* USB - Timer Select: 4 */
3964 
#define UTSEL_5                (0xA000)       /* USB - Timer Select: 5 */
3965 
#define UTSEL_6                (0xC000)       /* USB - Timer Select: 6 */
3966 
#define UTSEL_7                (0xE000)       /* USB - Timer Select: 7 */
3967 
 
3968 
/* USBCTL Control Bits */
3969 
#define DIR                    (0x0001)       /* USB - Data Response Bit */
3970 
//#define RESERVED       (0x0002)  /* USB -  */
3971 
//#define RESERVED       (0x0004)  /* USB -  */
3972 
//#define RESERVED       (0x0008)  /* USB -  */
3973 
#define FRSTE                  (0x0010)       /* USB - Function Reset Connection Enable */
3974 
#define RWUP                   (0x0020)       /* USB - Device Remote Wakeup Request */
3975 
#define FEN                    (0x0040)       /* USB - Function Enable Bit */
3976 
//#define RESERVED       (0x0080)  /* USB -  */
3977 
 
3978 
/* USBIE Control Bits */
3979 
#define STPOWIE                (0x0001)       /* USB - Setup Overwrite Interrupt Enable */
3980 
//#define RESERVED       (0x0002)  /* USB -  */
3981 
#define SETUPIE                (0x0004)       /* USB - Setup Interrupt Enable */
3982 
//#define RESERVED       (0x0008)  /* USB -  */
3983 
//#define RESERVED       (0x0010)  /* USB -  */
3984 
#define RESRIE                 (0x0020)       /* USB - Function Resume Request Interrupt Enable */
3985 
#define SUSRIE                 (0x0040)       /* USB - Function Suspend Request Interrupt Enable */
3986 
#define RSTRIE                 (0x0080)       /* USB - Function Reset Request Interrupt Enable */
3987 
 
3988 
/* USBIFG Control Bits */
3989 
#define STPOWIFG               (0x0001)       /* USB - Setup Overwrite Interrupt Flag */
3990 
//#define RESERVED       (0x0002)  /* USB -  */
3991 
#define SETUPIFG               (0x0004)       /* USB - Setup Interrupt Flag */
3992 
//#define RESERVED       (0x0008)  /* USB -  */
3993 
//#define RESERVED       (0x0010)  /* USB -  */
3994 
#define RESRIFG                (0x0020)       /* USB - Function Resume Request Interrupt Flag */
3995 
#define SUSRIFG                (0x0040)       /* USB - Function Suspend Request Interrupt Flag */
3996 
#define RSTRIFG                (0x0080)       /* USB - Function Reset Request Interrupt Flag */
3997 
 
3998 
//values of USBVECINT when USB-interrupt occured
3999 
#define     USBVECINT_NONE     0x00
4000 
#define     USBVECINT_PWR_DROP 0x02
4001 
#define     USBVECINT_PLL_LOCK 0x04
4002 
#define     USBVECINT_PLL_SIGNAL 0x06
4003 
#define     USBVECINT_PLL_RANGE 0x08
4004 
#define     USBVECINT_PWR_VBUSOn 0x0A
4005 
#define     USBVECINT_PWR_VBUSOff 0x0C
4006 
#define     USBVECINT_USB_TIMESTAMP 0x10
4007 
#define     USBVECINT_INPUT_ENDPOINT0 0x12
4008 
#define     USBVECINT_OUTPUT_ENDPOINT0 0x14
4009 
#define     USBVECINT_RSTR     0x16
4010 
#define     USBVECINT_SUSR     0x18
4011 
#define     USBVECINT_RESR     0x1A
4012 
#define     USBVECINT_SETUP_PACKET_RECEIVED 0x20
4013 
#define     USBVECINT_STPOW_PACKET_RECEIVED 0x22
4014 
#define     USBVECINT_INPUT_ENDPOINT1 0x24
4015 
#define     USBVECINT_INPUT_ENDPOINT2 0x26
4016 
#define     USBVECINT_INPUT_ENDPOINT3 0x28
4017 
#define     USBVECINT_INPUT_ENDPOINT4 0x2A
4018 
#define     USBVECINT_INPUT_ENDPOINT5 0x2C
4019 
#define     USBVECINT_INPUT_ENDPOINT6 0x2E
4020 
#define     USBVECINT_INPUT_ENDPOINT7 0x30
4021 
#define     USBVECINT_OUTPUT_ENDPOINT1 0x32
4022 
#define     USBVECINT_OUTPUT_ENDPOINT2 0x34
4023 
#define     USBVECINT_OUTPUT_ENDPOINT3 0x36
4024 
#define     USBVECINT_OUTPUT_ENDPOINT4 0x38
4025 
#define     USBVECINT_OUTPUT_ENDPOINT5 0x3A
4026 
#define     USBVECINT_OUTPUT_ENDPOINT6 0x3C
4027 
#define     USBVECINT_OUTPUT_ENDPOINT7 0x3E
4028 
 
4029 
 
4030 
/* ========================================================================= */
4031 
/* USB Operation Registers */
4032 
/* ========================================================================= */
4033 
 
4034 
SFR_8BIT(USBIEPSIZXY_7);                      /* Input Endpoint_7: X/Y-buffer size  */
4035 
SFR_8BIT(USBIEPBCTY_7);                       /* Input Endpoint_7: Y-byte count  */
4036 
SFR_8BIT(USBIEPBBAY_7);                       /* Input Endpoint_7: Y-buffer base addr.  */
4037 
//sfrb    Spare    (0x23FC)   /* Not used  */
4038 
//sfrb    Spare    (0x23FB)   /* Not used  */
4039 
SFR_8BIT(USBIEPBCTX_7);                       /* Input Endpoint_7: X-byte count  */
4040 
SFR_8BIT(USBIEPBBAX_7);                       /* Input Endpoint_7: X-buffer base addr. */
4041 
SFR_8BIT(USBIEPCNF_7);                        /* Input Endpoint_7: Configuration  */
4042 
SFR_8BIT(USBIEPSIZXY_6);                      /* Input Endpoint_6: X/Y-buffer size  */
4043 
SFR_8BIT(USBIEPBCTY_6);                       /* Input Endpoint_6: Y-byte count */
4044 
SFR_8BIT(USBIEPBBAY_6);                       /* Input Endpoint_6: Y-buffer base addr. */
4045 
//sfrb    Spare    (0x23F4)   /* Not used  */
4046 
//sfrb    Spare    (0x23F3)   /* Not used  */
4047 
SFR_8BIT(USBIEPBCTX_6);                       /* Input Endpoint_6: X-byte count */
4048 
SFR_8BIT(USBIEPBBAX_6);                       /* Input Endpoint_6: X-buffer base addr. */
4049 
SFR_8BIT(USBIEPCNF_6);                        /* Input Endpoint_6: Configuration */
4050 
SFR_8BIT(USBIEPSIZXY_5);                      /* Input Endpoint_5: X/Y-buffer size */
4051 
SFR_8BIT(USBIEPBCTY_5);                       /* Input Endpoint_5: Y-byte count */
4052 
SFR_8BIT(USBIEPBBAY_5);                       /* Input Endpoint_5: Y-buffer base addr. */
4053 
//sfrb    Spare    (0x23EC)   /* Not used */
4054 
//sfrb    Spare    (0x23EB)   /* Not used */
4055 
SFR_8BIT(USBIEPBCTX_5);                       /* Input Endpoint_5: X-byte count */
4056 
SFR_8BIT(USBIEPBBAX_5);                       /* Input Endpoint_5: X-buffer base addr. */
4057 
SFR_8BIT(USBIEPCNF_5);                        /* Input Endpoint_5: Configuration */
4058 
SFR_8BIT(USBIEPSIZXY_4);                      /* Input Endpoint_4: X/Y-buffer size */
4059 
SFR_8BIT(USBIEPBCTY_4);                       /* Input Endpoint_4: Y-byte count */
4060 
SFR_8BIT(USBIEPBBAY_4);                       /* Input Endpoint_4: Y-buffer base addr. */
4061 
//sfrb    Spare    (0x23E4)   /* Not used */
4062 
//sfrb    Spare    (0x23E3)   /* Not used */
4063 
SFR_8BIT(USBIEPBCTX_4);                       /* Input Endpoint_4: X-byte count */
4064 
SFR_8BIT(USBIEPBBAX_4);                       /* Input Endpoint_4: X-buffer base addr. */
4065 
SFR_8BIT(USBIEPCNF_4);                        /* Input Endpoint_4: Configuration */
4066 
SFR_8BIT(USBIEPSIZXY_3);                      /* Input Endpoint_3: X/Y-buffer size */
4067 
SFR_8BIT(USBIEPBCTY_3);                       /* Input Endpoint_3: Y-byte count */
4068 
SFR_8BIT(USBIEPBBAY_3);                       /* Input Endpoint_3: Y-buffer base addr. */
4069 
//sfrb    Spare    (0x23DC)   /* Not used */
4070 
//sfrb    Spare    (0x23DB)   /* Not used */
4071 
SFR_8BIT(USBIEPBCTX_3);                       /* Input Endpoint_3: X-byte count */
4072 
SFR_8BIT(USBIEPBBAX_3);                       /* Input Endpoint_3: X-buffer base addr. */
4073 
SFR_8BIT(USBIEPCNF_3);                        /* Input Endpoint_3: Configuration */
4074 
SFR_8BIT(USBIEPSIZXY_2);                      /* Input Endpoint_2: X/Y-buffer size */
4075 
SFR_8BIT(USBIEPBCTY_2);                       /* Input Endpoint_2: Y-byte count */
4076 
SFR_8BIT(USBIEPBBAY_2);                       /* Input Endpoint_2: Y-buffer base addr. */
4077 
//sfrb    Spare    (0x23D4)   /* Not used */
4078 
//sfrb    Spare    (0x23D3)   /* Not used */
4079 
SFR_8BIT(USBIEPBCTX_2);                       /* Input Endpoint_2: X-byte count */
4080 
SFR_8BIT(USBIEPBBAX_2);                       /* Input Endpoint_2: X-buffer base addr. */
4081 
SFR_8BIT(USBIEPCNF_2);                        /* Input Endpoint_2: Configuration */
4082 
SFR_8BIT(USBIEPSIZXY_1);                      /* Input Endpoint_1: X/Y-buffer size */
4083 
SFR_8BIT(USBIEPBCTY_1);                       /* Input Endpoint_1: Y-byte count */
4084 
SFR_8BIT(USBIEPBBAY_1);                       /* Input Endpoint_1: Y-buffer base addr. */
4085 
//sfrb    Spare    (0x23CC)   /* Not used */
4086 
//sfrb    Spare    (0x23CB)   /* Not used */
4087 
SFR_8BIT(USBIEPBCTX_1);                       /* Input Endpoint_1: X-byte count */
4088 
SFR_8BIT(USBIEPBBAX_1);                       /* Input Endpoint_1: X-buffer base addr. */
4089 
SFR_8BIT(USBIEPCNF_1);                        /* Input Endpoint_1: Configuration */
4090 
//sfrb       (0x23C7)   0x0000 */
4091 
//sfrb     RESERVED      (0x1C00)    /* */
4092 
//sfrb       (0x23C0)   0x0000 */
4093 
SFR_8BIT(USBOEPSIZXY_7);                      /* Output Endpoint_7: X/Y-buffer size */
4094 
SFR_8BIT(USBOEPBCTY_7);                       /* Output Endpoint_7: Y-byte count */
4095 
SFR_8BIT(USBOEPBBAY_7);                       /* Output Endpoint_7: Y-buffer base addr. */
4096 
//sfrb    Spare    (0x23BC)   /* Not used */
4097 
//sfrb    Spare    (0x23BB)   /* Not used */
4098 
SFR_8BIT(USBOEPBCTX_7);                       /* Output Endpoint_7: X-byte count */
4099 
SFR_8BIT(USBOEPBBAX_7);                       /* Output Endpoint_7: X-buffer base addr. */
4100 
SFR_8BIT(USBOEPCNF_7);                        /* Output Endpoint_7: Configuration */
4101 
SFR_8BIT(USBOEPSIZXY_6);                      /* Output Endpoint_6: X/Y-buffer size */
4102 
SFR_8BIT(USBOEPBCTY_6);                       /* Output Endpoint_6: Y-byte count */
4103 
SFR_8BIT(USBOEPBBAY_6);                       /* Output Endpoint_6: Y-buffer base addr. */
4104 
//sfrb    Spare    (0x23B4)   /* Not used */
4105 
//sfrb    Spare    (0x23B3)   /* Not used */
4106 
SFR_8BIT(USBOEPBCTX_6);                       /* Output Endpoint_6: X-byte count */
4107 
SFR_8BIT(USBOEPBBAX_6);                       /* Output Endpoint_6: X-buffer base addr. */
4108 
SFR_8BIT(USBOEPCNF_6);                        /* Output Endpoint_6: Configuration */
4109 
SFR_8BIT(USBOEPSIZXY_5);                      /* Output Endpoint_5: X/Y-buffer size */
4110 
SFR_8BIT(USBOEPBCTY_5);                       /* Output Endpoint_5: Y-byte count */
4111 
SFR_8BIT(USBOEPBBAY_5);                       /* Output Endpoint_5: Y-buffer base addr. */
4112 
//sfrb    Spare    (0x23AC)   /* Not used */
4113 
//sfrb    Spare    (0x23AB)   /* Not used */
4114 
SFR_8BIT(USBOEPBCTX_5);                       /* Output Endpoint_5: X-byte count */
4115 
SFR_8BIT(USBOEPBBAX_5);                       /* Output Endpoint_5: X-buffer base addr. */
4116 
SFR_8BIT(USBOEPCNF_5);                        /* Output Endpoint_5: Configuration */
4117 
SFR_8BIT(USBOEPSIZXY_4);                      /* Output Endpoint_4: X/Y-buffer size */
4118 
SFR_8BIT(USBOEPBCTY_4);                       /* Output Endpoint_4: Y-byte count */
4119 
SFR_8BIT(USBOEPBBAY_4);                       /* Output Endpoint_4: Y-buffer base addr. */
4120 
//sfrb    Spare    (0x23A4)   /* Not used */
4121 
//sfrb    Spare    (0x23A3)   /* Not used */
4122 
SFR_8BIT(USBOEPBCTX_4);                       /* Output Endpoint_4: X-byte count */
4123 
SFR_8BIT(USBOEPBBAX_4);                       /* Output Endpoint_4: X-buffer base addr. */
4124 
SFR_8BIT(USBOEPCNF_4);                        /* Output Endpoint_4: Configuration */
4125 
SFR_8BIT(USBOEPSIZXY_3);                      /* Output Endpoint_3: X/Y-buffer size */
4126 
SFR_8BIT(USBOEPBCTY_3);                       /* Output Endpoint_3: Y-byte count */
4127 
SFR_8BIT(USBOEPBBAY_3);                       /* Output Endpoint_3: Y-buffer base addr. */
4128 
//sfrb    Spare    (0x239C)   /* Not used */
4129 
//sfrb    Spare    (0x239B)   /* Not used */
4130 
SFR_8BIT(USBOEPBCTX_3);                       /* Output Endpoint_3: X-byte count */
4131 
SFR_8BIT(USBOEPBBAX_3);                       /* Output Endpoint_3: X-buffer base addr. */
4132 
SFR_8BIT(USBOEPCNF_3);                        /* Output Endpoint_3: Configuration */
4133 
SFR_8BIT(USBOEPSIZXY_2);                      /* Output Endpoint_2: X/Y-buffer size */
4134 
SFR_8BIT(USBOEPBCTY_2);                       /* Output Endpoint_2: Y-byte count */
4135 
SFR_8BIT(USBOEPBBAY_2);                       /* Output Endpoint_2: Y-buffer base addr. */
4136 
//sfrb    Spare    (0x2394)   /* Not used */
4137 
//sfrb    Spare    (0x2393)   /* Not used */
4138 
SFR_8BIT(USBOEPBCTX_2);                       /* Output Endpoint_2: X-byte count */
4139 
SFR_8BIT(USBOEPBBAX_2);                       /* Output Endpoint_2: X-buffer base addr. */
4140 
SFR_8BIT(USBOEPCNF_2);                        /* Output Endpoint_2: Configuration */
4141 
SFR_8BIT(USBOEPSIZXY_1);                      /* Output Endpoint_1: X/Y-buffer size */
4142 
SFR_8BIT(USBOEPBCTY_1);                       /* Output Endpoint_1: Y-byte count */
4143 
SFR_8BIT(USBOEPBBAY_1);                       /* Output Endpoint_1: Y-buffer base addr. */
4144 
//sfrb    Spare    (0x238C)   /* Not used */
4145 
//sfrb    Spare    (0x238B)   /* Not used */
4146 
SFR_8BIT(USBOEPBCTX_1);                       /* Output Endpoint_1: X-byte count */
4147 
SFR_8BIT(USBOEPBBAX_1);                       /* Output Endpoint_1: X-buffer base addr. */
4148 
SFR_8BIT(USBOEPCNF_1);                        /* Output Endpoint_1: Configuration */
4149 
SFR_8BIT(USBSUBLK);                           /* Setup Packet Block */
4150 
SFR_8BIT(USBIEP0BUF);                         /* Input endpoint_0 buffer */
4151 
SFR_8BIT(USBOEP0BUF);                         /* Output endpoint_0 buffer */
4152 
SFR_8BIT(USBTOPBUFF);                         /* Top of buffer space */
4153 
//         (1904 Bytes)               /* Buffer space */
4154 
SFR_8BIT(USBSTABUFF);                         /* Start of buffer space */
4155 
 
4156 
/* USBIEPCNF_n Control Bits */
4157 
/* USBOEPCNF_n Control Bits */
4158 
//#define RESERVED       (0x0001)  /* USB -  */
4159 
//#define RESERVED       (0x0001)  /* USB -  */
4160 
#define DBUF                   (0x0010)       /* USB - Double Buffer Enable */
4161 
//#define RESERVED       (0x0040)  /* USB -  */
4162 
 
4163 
/* USBIEPBCNT_n Control Bits */
4164 
/* USBOEPBCNT_n Control Bits */
4165 
#define CNT4                   (0x0010)       /* USB - Byte Count Bit 3 */
4166 
#define CNT5                   (0x0020)       /* USB - Byte Count Bit 3 */
4167 
#define CNT6                   (0x0040)       /* USB - Byte Count Bit 3 */
4168 
/************************************************************
4169 
* UNIFIED CLOCK SYSTEM
4170 
************************************************************/
4171 
#define __MSP430_HAS_UCS__                    /* Definition to show that Module is available */
4172 
#define __MSP430_BASEADDRESS_UCS__ 0x0160
4173 
 
4174 
SFR_16BIT(UCSCTL0);                           /* UCS Control Register 0 */
4175 
SFR_8BIT(UCSCTL0_L);                          /* UCS Control Register 0 */
4176 
SFR_8BIT(UCSCTL0_H);                          /* UCS Control Register 0 */
4177 
SFR_16BIT(UCSCTL1);                           /* UCS Control Register 1 */
4178 
SFR_8BIT(UCSCTL1_L);                          /* UCS Control Register 1 */
4179 
SFR_8BIT(UCSCTL1_H);                          /* UCS Control Register 1 */
4180 
SFR_16BIT(UCSCTL2);                           /* UCS Control Register 2 */
4181 
SFR_8BIT(UCSCTL2_L);                          /* UCS Control Register 2 */
4182 
SFR_8BIT(UCSCTL2_H);                          /* UCS Control Register 2 */
4183 
SFR_16BIT(UCSCTL3);                           /* UCS Control Register 3 */
4184 
SFR_8BIT(UCSCTL3_L);                          /* UCS Control Register 3 */
4185 
SFR_8BIT(UCSCTL3_H);                          /* UCS Control Register 3 */
4186 
SFR_16BIT(UCSCTL4);                           /* UCS Control Register 4 */
4187 
SFR_8BIT(UCSCTL4_L);                          /* UCS Control Register 4 */
4188 
SFR_8BIT(UCSCTL4_H);                          /* UCS Control Register 4 */
4189 
SFR_16BIT(UCSCTL5);                           /* UCS Control Register 5 */
4190 
SFR_8BIT(UCSCTL5_L);                          /* UCS Control Register 5 */
4191 
SFR_8BIT(UCSCTL5_H);                          /* UCS Control Register 5 */
4192 
SFR_16BIT(UCSCTL6);                           /* UCS Control Register 6 */
4193 
SFR_8BIT(UCSCTL6_L);                          /* UCS Control Register 6 */
4194 
SFR_8BIT(UCSCTL6_H);                          /* UCS Control Register 6 */
4195 
SFR_16BIT(UCSCTL7);                           /* UCS Control Register 7 */
4196 
SFR_8BIT(UCSCTL7_L);                          /* UCS Control Register 7 */
4197 
SFR_8BIT(UCSCTL7_H);                          /* UCS Control Register 7 */
4198 
SFR_16BIT(UCSCTL8);                           /* UCS Control Register 8 */
4199 
SFR_8BIT(UCSCTL8_L);                          /* UCS Control Register 8 */
4200 
SFR_8BIT(UCSCTL8_H);                          /* UCS Control Register 8 */
4201 
 
4202 
/* UCSCTL0 Control Bits */
4203 
//#define RESERVED            (0x0001)    /* RESERVED */
4204 
//#define RESERVED            (0x0002)    /* RESERVED */
4205 
//#define RESERVED            (0x0004)    /* RESERVED */
4206 
#define MOD0                   (0x0008)       /* Modulation Bit Counter Bit : 0 */
4207 
#define MOD1                   (0x0010)       /* Modulation Bit Counter Bit : 1 */
4208 
#define MOD2                   (0x0020)       /* Modulation Bit Counter Bit : 2 */
4209 
#define MOD3                   (0x0040)       /* Modulation Bit Counter Bit : 3 */
4210 
#define MOD4                   (0x0080)       /* Modulation Bit Counter Bit : 4 */
4211 
#define DCO0                   (0x0100)       /* DCO TAP Bit : 0 */
4212 
#define DCO1                   (0x0200)       /* DCO TAP Bit : 1 */
4213 
#define DCO2                   (0x0400)       /* DCO TAP Bit : 2 */
4214 
#define DCO3                   (0x0800)       /* DCO TAP Bit : 3 */
4215 
#define DCO4                   (0x1000)       /* DCO TAP Bit : 4 */
4216 
//#define RESERVED            (0x2000)    /* RESERVED */
4217 
//#define RESERVED            (0x4000)    /* RESERVED */
4218 
//#define RESERVED            (0x8000)    /* RESERVED */
4219 
 
4220 
/* UCSCTL0 Control Bits */
4221 
//#define RESERVED            (0x0001)    /* RESERVED */
4222 
//#define RESERVED            (0x0002)    /* RESERVED */
4223 
//#define RESERVED            (0x0004)    /* RESERVED */
4224 
#define MOD0_L                 (0x0008)       /* Modulation Bit Counter Bit : 0 */
4225 
#define MOD1_L                 (0x0010)       /* Modulation Bit Counter Bit : 1 */
4226 
#define MOD2_L                 (0x0020)       /* Modulation Bit Counter Bit : 2 */
4227 
#define MOD3_L                 (0x0040)       /* Modulation Bit Counter Bit : 3 */
4228 
#define MOD4_L                 (0x0080)       /* Modulation Bit Counter Bit : 4 */
4229 
//#define RESERVED            (0x2000)    /* RESERVED */
4230 
//#define RESERVED            (0x4000)    /* RESERVED */
4231 
//#define RESERVED            (0x8000)    /* RESERVED */
4232 
 
4233 
/* UCSCTL0 Control Bits */
4234 
//#define RESERVED            (0x0001)    /* RESERVED */
4235 
//#define RESERVED            (0x0002)    /* RESERVED */
4236 
//#define RESERVED            (0x0004)    /* RESERVED */
4237 
#define DCO0_H                 (0x0001)       /* DCO TAP Bit : 0 */
4238 
#define DCO1_H                 (0x0002)       /* DCO TAP Bit : 1 */
4239 
#define DCO2_H                 (0x0004)       /* DCO TAP Bit : 2 */
4240 
#define DCO3_H                 (0x0008)       /* DCO TAP Bit : 3 */
4241 
#define DCO4_H                 (0x0010)       /* DCO TAP Bit : 4 */
4242 
//#define RESERVED            (0x2000)    /* RESERVED */
4243 
//#define RESERVED            (0x4000)    /* RESERVED */
4244 
//#define RESERVED            (0x8000)    /* RESERVED */
4245 
 
4246 
/* UCSCTL1 Control Bits */
4247 
#define DISMOD                 (0x0001)       /* Disable Modulation */
4248 
//#define RESERVED            (0x0002)    /* RESERVED */
4249 
//#define RESERVED            (0x0004)    /* RESERVED */
4250 
//#define RESERVED            (0x0008)    /* RESERVED */
4251 
#define DCORSEL0               (0x0010)       /* DCO Freq. Range Select Bit : 0 */
4252 
#define DCORSEL1               (0x0020)       /* DCO Freq. Range Select Bit : 1 */
4253 
#define DCORSEL2               (0x0040)       /* DCO Freq. Range Select Bit : 2 */
4254 
//#define RESERVED            (0x0080)    /* RESERVED */
4255 
//#define RESERVED            (0x0100)    /* RESERVED */
4256 
//#define RESERVED            (0x0200)    /* RESERVED */
4257 
//#define RESERVED            (0x0400)    /* RESERVED */
4258 
//#define RESERVED            (0x0800)    /* RESERVED */
4259 
//#define RESERVED            (0x1000)    /* RESERVED */
4260 
//#define RESERVED            (0x2000)    /* RESERVED */
4261 
//#define RESERVED            (0x4000)    /* RESERVED */
4262 
//#define RESERVED            (0x8000)    /* RESERVED */
4263 
 
4264 
/* UCSCTL1 Control Bits */
4265 
#define DISMOD_L               (0x0001)       /* Disable Modulation */
4266 
//#define RESERVED            (0x0002)    /* RESERVED */
4267 
//#define RESERVED            (0x0004)    /* RESERVED */
4268 
//#define RESERVED            (0x0008)    /* RESERVED */
4269 
#define DCORSEL0_L             (0x0010)       /* DCO Freq. Range Select Bit : 0 */
4270 
#define DCORSEL1_L             (0x0020)       /* DCO Freq. Range Select Bit : 1 */
4271 
#define DCORSEL2_L             (0x0040)       /* DCO Freq. Range Select Bit : 2 */
4272 
//#define RESERVED            (0x0080)    /* RESERVED */
4273 
//#define RESERVED            (0x0100)    /* RESERVED */
4274 
//#define RESERVED            (0x0200)    /* RESERVED */
4275 
//#define RESERVED            (0x0400)    /* RESERVED */
4276 
//#define RESERVED            (0x0800)    /* RESERVED */
4277 
//#define RESERVED            (0x1000)    /* RESERVED */
4278 
//#define RESERVED            (0x2000)    /* RESERVED */
4279 
//#define RESERVED            (0x4000)    /* RESERVED */
4280 
//#define RESERVED            (0x8000)    /* RESERVED */
4281 
 
4282 
/* UCSCTL1 Control Bits */
4283 
//#define RESERVED            (0x0002)    /* RESERVED */
4284 
//#define RESERVED            (0x0004)    /* RESERVED */
4285 
//#define RESERVED            (0x0008)    /* RESERVED */
4286 
//#define RESERVED            (0x0080)    /* RESERVED */
4287 
//#define RESERVED            (0x0100)    /* RESERVED */
4288 
//#define RESERVED            (0x0200)    /* RESERVED */
4289 
//#define RESERVED            (0x0400)    /* RESERVED */
4290 
//#define RESERVED            (0x0800)    /* RESERVED */
4291 
//#define RESERVED            (0x1000)    /* RESERVED */
4292 
//#define RESERVED            (0x2000)    /* RESERVED */
4293 
//#define RESERVED            (0x4000)    /* RESERVED */
4294 
//#define RESERVED            (0x8000)    /* RESERVED */
4295 
 
4296 
#define DCORSEL_0              (0x0000)       /* DCO RSEL 0 */
4297 
#define DCORSEL_1              (0x0010)       /* DCO RSEL 1 */
4298 
#define DCORSEL_2              (0x0020)       /* DCO RSEL 2 */
4299 
#define DCORSEL_3              (0x0030)       /* DCO RSEL 3 */
4300 
#define DCORSEL_4              (0x0040)       /* DCO RSEL 4 */
4301 
#define DCORSEL_5              (0x0050)       /* DCO RSEL 5 */
4302 
#define DCORSEL_6              (0x0060)       /* DCO RSEL 6 */
4303 
#define DCORSEL_7              (0x0070)       /* DCO RSEL 7 */
4304 
 
4305 
/* UCSCTL2 Control Bits */
4306 
#define FLLN0                  (0x0001)       /* FLL Multipier Bit : 0 */
4307 
#define FLLN1                  (0x0002)       /* FLL Multipier Bit : 1 */
4308 
#define FLLN2                  (0x0004)       /* FLL Multipier Bit : 2 */
4309 
#define FLLN3                  (0x0008)       /* FLL Multipier Bit : 3 */
4310 
#define FLLN4                  (0x0010)       /* FLL Multipier Bit : 4 */
4311 
#define FLLN5                  (0x0020)       /* FLL Multipier Bit : 5 */
4312 
#define FLLN6                  (0x0040)       /* FLL Multipier Bit : 6 */
4313 
#define FLLN7                  (0x0080)       /* FLL Multipier Bit : 7 */
4314 
#define FLLN8                  (0x0100)       /* FLL Multipier Bit : 8 */
4315 
#define FLLN9                  (0x0200)       /* FLL Multipier Bit : 9 */
4316 
//#define RESERVED            (0x0400)    /* RESERVED */
4317 
//#define RESERVED            (0x0800)    /* RESERVED */
4318 
#define FLLD0                  (0x1000)       /* Loop Divider Bit : 0 */
4319 
#define FLLD1                  (0x2000)       /* Loop Divider Bit : 1 */
4320 
#define FLLD2                  (0x4000)       /* Loop Divider Bit : 1 */
4321 
//#define RESERVED            (0x8000)    /* RESERVED */
4322 
 
4323 
/* UCSCTL2 Control Bits */
4324 
#define FLLN0_L                (0x0001)       /* FLL Multipier Bit : 0 */
4325 
#define FLLN1_L                (0x0002)       /* FLL Multipier Bit : 1 */
4326 
#define FLLN2_L                (0x0004)       /* FLL Multipier Bit : 2 */
4327 
#define FLLN3_L                (0x0008)       /* FLL Multipier Bit : 3 */
4328 
#define FLLN4_L                (0x0010)       /* FLL Multipier Bit : 4 */
4329 
#define FLLN5_L                (0x0020)       /* FLL Multipier Bit : 5 */
4330 
#define FLLN6_L                (0x0040)       /* FLL Multipier Bit : 6 */
4331 
#define FLLN7_L                (0x0080)       /* FLL Multipier Bit : 7 */
4332 
//#define RESERVED            (0x0400)    /* RESERVED */
4333 
//#define RESERVED            (0x0800)    /* RESERVED */
4334 
//#define RESERVED            (0x8000)    /* RESERVED */
4335 
 
4336 
/* UCSCTL2 Control Bits */
4337 
#define FLLN8_H                (0x0001)       /* FLL Multipier Bit : 8 */
4338 
#define FLLN9_H                (0x0002)       /* FLL Multipier Bit : 9 */
4339 
//#define RESERVED            (0x0400)    /* RESERVED */
4340 
//#define RESERVED            (0x0800)    /* RESERVED */
4341 
#define FLLD0_H                (0x0010)       /* Loop Divider Bit : 0 */
4342 
#define FLLD1_H                (0x0020)       /* Loop Divider Bit : 1 */
4343 
#define FLLD2_H                (0x0040)       /* Loop Divider Bit : 1 */
4344 
//#define RESERVED            (0x8000)    /* RESERVED */
4345 
 
4346 
#define FLLD_0                 (0x0000)       /* Multiply Selected Loop Freq. 1 */
4347 
#define FLLD_1                 (0x1000)       /* Multiply Selected Loop Freq. 2 */
4348 
#define FLLD_2                 (0x2000)       /* Multiply Selected Loop Freq. 4 */
4349 
#define FLLD_3                 (0x3000)       /* Multiply Selected Loop Freq. 8 */
4350 
#define FLLD_4                 (0x4000)       /* Multiply Selected Loop Freq. 16 */
4351 
#define FLLD_5                 (0x5000)       /* Multiply Selected Loop Freq. 32 */
4352 
#define FLLD_6                 (0x6000)       /* Multiply Selected Loop Freq. 32 */
4353 
#define FLLD_7                 (0x7000)       /* Multiply Selected Loop Freq. 32 */
4354 
#define FLLD__1                (0x0000)       /* Multiply Selected Loop Freq. By 1 */
4355 
#define FLLD__2                (0x1000)       /* Multiply Selected Loop Freq. By 2 */
4356 
#define FLLD__4                (0x2000)       /* Multiply Selected Loop Freq. By 4 */
4357 
#define FLLD__8                (0x3000)       /* Multiply Selected Loop Freq. By 8 */
4358 
#define FLLD__16               (0x4000)       /* Multiply Selected Loop Freq. By 16 */
4359 
#define FLLD__32               (0x5000)       /* Multiply Selected Loop Freq. By 32 */
4360 
 
4361 
/* UCSCTL3 Control Bits */
4362 
#define FLLREFDIV0             (0x0001)       /* Reference Divider Bit : 0 */
4363 
#define FLLREFDIV1             (0x0002)       /* Reference Divider Bit : 1 */
4364 
#define FLLREFDIV2             (0x0004)       /* Reference Divider Bit : 2 */
4365 
//#define RESERVED            (0x0008)    /* RESERVED */
4366 
#define SELREF0                (0x0010)       /* FLL Reference Clock Select Bit : 0 */
4367 
#define SELREF1                (0x0020)       /* FLL Reference Clock Select Bit : 1 */
4368 
#define SELREF2                (0x0040)       /* FLL Reference Clock Select Bit : 2 */
4369 
//#define RESERVED            (0x0080)    /* RESERVED */
4370 
//#define RESERVED            (0x0100)    /* RESERVED */
4371 
//#define RESERVED            (0x0200)    /* RESERVED */
4372 
//#define RESERVED            (0x0400)    /* RESERVED */
4373 
//#define RESERVED            (0x0800)    /* RESERVED */
4374 
//#define RESERVED            (0x1000)    /* RESERVED */
4375 
//#define RESERVED            (0x2000)    /* RESERVED */
4376 
//#define RESERVED            (0x4000)    /* RESERVED */
4377 
//#define RESERVED            (0x8000)    /* RESERVED */
4378 
 
4379 
/* UCSCTL3 Control Bits */
4380 
#define FLLREFDIV0_L           (0x0001)       /* Reference Divider Bit : 0 */
4381 
#define FLLREFDIV1_L           (0x0002)       /* Reference Divider Bit : 1 */
4382 
#define FLLREFDIV2_L           (0x0004)       /* Reference Divider Bit : 2 */
4383 
//#define RESERVED            (0x0008)    /* RESERVED */
4384 
#define SELREF0_L              (0x0010)       /* FLL Reference Clock Select Bit : 0 */
4385 
#define SELREF1_L              (0x0020)       /* FLL Reference Clock Select Bit : 1 */
4386 
#define SELREF2_L              (0x0040)       /* FLL Reference Clock Select Bit : 2 */
4387 
//#define RESERVED            (0x0080)    /* RESERVED */
4388 
//#define RESERVED            (0x0100)    /* RESERVED */
4389 
//#define RESERVED            (0x0200)    /* RESERVED */
4390 
//#define RESERVED            (0x0400)    /* RESERVED */
4391 
//#define RESERVED            (0x0800)    /* RESERVED */
4392 
//#define RESERVED            (0x1000)    /* RESERVED */
4393 
//#define RESERVED            (0x2000)    /* RESERVED */
4394 
//#define RESERVED            (0x4000)    /* RESERVED */
4395 
//#define RESERVED            (0x8000)    /* RESERVED */
4396 
 
4397 
/* UCSCTL3 Control Bits */
4398 
//#define RESERVED            (0x0008)    /* RESERVED */
4399 
//#define RESERVED            (0x0080)    /* RESERVED */
4400 
//#define RESERVED            (0x0100)    /* RESERVED */
4401 
//#define RESERVED            (0x0200)    /* RESERVED */
4402 
//#define RESERVED            (0x0400)    /* RESERVED */
4403 
//#define RESERVED            (0x0800)    /* RESERVED */
4404 
//#define RESERVED            (0x1000)    /* RESERVED */
4405 
//#define RESERVED            (0x2000)    /* RESERVED */
4406 
//#define RESERVED            (0x4000)    /* RESERVED */
4407 
//#define RESERVED            (0x8000)    /* RESERVED */
4408 
 
4409 
#define FLLREFDIV_0            (0x0000)       /* Reference Divider: f(LFCLK)/1 */
4410 
#define FLLREFDIV_1            (0x0001)       /* Reference Divider: f(LFCLK)/2 */
4411 
#define FLLREFDIV_2            (0x0002)       /* Reference Divider: f(LFCLK)/4 */
4412 
#define FLLREFDIV_3            (0x0003)       /* Reference Divider: f(LFCLK)/8 */
4413 
#define FLLREFDIV_4            (0x0004)       /* Reference Divider: f(LFCLK)/12 */
4414 
#define FLLREFDIV_5            (0x0005)       /* Reference Divider: f(LFCLK)/16 */
4415 
#define FLLREFDIV_6            (0x0006)       /* Reference Divider: f(LFCLK)/16 */
4416 
#define FLLREFDIV_7            (0x0007)       /* Reference Divider: f(LFCLK)/16 */
4417 
#define FLLREFDIV__1           (0x0000)       /* Reference Divider: f(LFCLK)/1 */
4418 
#define FLLREFDIV__2           (0x0001)       /* Reference Divider: f(LFCLK)/2 */
4419 
#define FLLREFDIV__4           (0x0002)       /* Reference Divider: f(LFCLK)/4 */
4420 
#define FLLREFDIV__8           (0x0003)       /* Reference Divider: f(LFCLK)/8 */
4421 
#define FLLREFDIV__12          (0x0004)       /* Reference Divider: f(LFCLK)/12 */
4422 
#define FLLREFDIV__16          (0x0005)       /* Reference Divider: f(LFCLK)/16 */
4423 
#define SELREF_0               (0x0000)       /* FLL Reference Clock Select 0 */
4424 
#define SELREF_1               (0x0010)       /* FLL Reference Clock Select 1 */
4425 
#define SELREF_2               (0x0020)       /* FLL Reference Clock Select 2 */
4426 
#define SELREF_3               (0x0030)       /* FLL Reference Clock Select 3 */
4427 
#define SELREF_4               (0x0040)       /* FLL Reference Clock Select 4 */
4428 
#define SELREF_5               (0x0050)       /* FLL Reference Clock Select 5 */
4429 
#define SELREF_6               (0x0060)       /* FLL Reference Clock Select 6 */
4430 
#define SELREF_7               (0x0070)       /* FLL Reference Clock Select 7 */
4431 
#define SELREF__XT1CLK         (0x0000)       /* Multiply Selected Loop Freq. By XT1CLK */
4432 
#define SELREF__REFOCLK        (0x0020)       /* Multiply Selected Loop Freq. By REFOCLK */
4433 
#define SELREF__XT2CLK         (0x0050)       /* Multiply Selected Loop Freq. By XT2CLK */
4434 
 
4435 
/* UCSCTL4 Control Bits */
4436 
#define SELM0                  (0x0001)       /* MCLK Source Select Bit: 0 */
4437 
#define SELM1                  (0x0002)       /* MCLK Source Select Bit: 1 */
4438 
#define SELM2                  (0x0004)       /* MCLK Source Select Bit: 2 */
4439 
//#define RESERVED            (0x0008)    /* RESERVED */
4440 
#define SELS0                  (0x0010)       /* SMCLK Source Select Bit: 0 */
4441 
#define SELS1                  (0x0020)       /* SMCLK Source Select Bit: 1 */
4442 
#define SELS2                  (0x0040)       /* SMCLK Source Select Bit: 2 */
4443 
//#define RESERVED            (0x0080)    /* RESERVED */
4444 
#define SELA0                  (0x0100)       /* ACLK Source Select Bit: 0 */
4445 
#define SELA1                  (0x0200)       /* ACLK Source Select Bit: 1 */
4446 
#define SELA2                  (0x0400)       /* ACLK Source Select Bit: 2 */
4447 
//#define RESERVED            (0x0800)    /* RESERVED */
4448 
//#define RESERVED            (0x1000)    /* RESERVED */
4449 
//#define RESERVED            (0x2000)    /* RESERVED */
4450 
//#define RESERVED            (0x4000)    /* RESERVED */
4451 
//#define RESERVED            (0x8000)    /* RESERVED */
4452 
 
4453 
/* UCSCTL4 Control Bits */
4454 
#define SELM0_L                (0x0001)       /* MCLK Source Select Bit: 0 */
4455 
#define SELM1_L                (0x0002)       /* MCLK Source Select Bit: 1 */
4456 
#define SELM2_L                (0x0004)       /* MCLK Source Select Bit: 2 */
4457 
//#define RESERVED            (0x0008)    /* RESERVED */
4458 
#define SELS0_L                (0x0010)       /* SMCLK Source Select Bit: 0 */
4459 
#define SELS1_L                (0x0020)       /* SMCLK Source Select Bit: 1 */
4460 
#define SELS2_L                (0x0040)       /* SMCLK Source Select Bit: 2 */
4461 
//#define RESERVED            (0x0080)    /* RESERVED */
4462 
//#define RESERVED            (0x0800)    /* RESERVED */
4463 
//#define RESERVED            (0x1000)    /* RESERVED */
4464 
//#define RESERVED            (0x2000)    /* RESERVED */
4465 
//#define RESERVED            (0x4000)    /* RESERVED */
4466 
//#define RESERVED            (0x8000)    /* RESERVED */
4467 
 
4468 
/* UCSCTL4 Control Bits */
4469 
//#define RESERVED            (0x0008)    /* RESERVED */
4470 
//#define RESERVED            (0x0080)    /* RESERVED */
4471 
#define SELA0_H                (0x0001)       /* ACLK Source Select Bit: 0 */
4472 
#define SELA1_H                (0x0002)       /* ACLK Source Select Bit: 1 */
4473 
#define SELA2_H                (0x0004)       /* ACLK Source Select Bit: 2 */
4474 
//#define RESERVED            (0x0800)    /* RESERVED */
4475 
//#define RESERVED            (0x1000)    /* RESERVED */
4476 
//#define RESERVED            (0x2000)    /* RESERVED */
4477 
//#define RESERVED            (0x4000)    /* RESERVED */
4478 
//#define RESERVED            (0x8000)    /* RESERVED */
4479 
 
4480 
#define SELM_0                 (0x0000)       /* MCLK Source Select 0 */
4481 
#define SELM_1                 (0x0001)       /* MCLK Source Select 1 */
4482 
#define SELM_2                 (0x0002)       /* MCLK Source Select 2 */
4483 
#define SELM_3                 (0x0003)       /* MCLK Source Select 3 */
4484 
#define SELM_4                 (0x0004)       /* MCLK Source Select 4 */
4485 
#define SELM_5                 (0x0005)       /* MCLK Source Select 5 */
4486 
#define SELM_6                 (0x0006)       /* MCLK Source Select 6 */
4487 
#define SELM_7                 (0x0007)       /* MCLK Source Select 7 */
4488 
#define SELM__XT1CLK           (0x0000)       /* MCLK Source Select XT1CLK */
4489 
#define SELM__VLOCLK           (0x0001)       /* MCLK Source Select VLOCLK */
4490 
#define SELM__REFOCLK          (0x0002)       /* MCLK Source Select REFOCLK */
4491 
#define SELM__DCOCLK           (0x0003)       /* MCLK Source Select DCOCLK */
4492 
#define SELM__DCOCLKDIV        (0x0004)       /* MCLK Source Select DCOCLKDIV */
4493 
#define SELM__XT2CLK           (0x0005)       /* MCLK Source Select XT2CLK */
4494 
 
4495 
#define SELS_0                 (0x0000)       /* SMCLK Source Select 0 */
4496 
#define SELS_1                 (0x0010)       /* SMCLK Source Select 1 */
4497 
#define SELS_2                 (0x0020)       /* SMCLK Source Select 2 */
4498 
#define SELS_3                 (0x0030)       /* SMCLK Source Select 3 */
4499 
#define SELS_4                 (0x0040)       /* SMCLK Source Select 4 */
4500 
#define SELS_5                 (0x0050)       /* SMCLK Source Select 5 */
4501 
#define SELS_6                 (0x0060)       /* SMCLK Source Select 6 */
4502 
#define SELS_7                 (0x0070)       /* SMCLK Source Select 7 */
4503 
#define SELS__XT1CLK           (0x0000)       /* SMCLK Source Select XT1CLK */
4504 
#define SELS__VLOCLK           (0x0010)       /* SMCLK Source Select VLOCLK */
4505 
#define SELS__REFOCLK          (0x0020)       /* SMCLK Source Select REFOCLK */
4506 
#define SELS__DCOCLK           (0x0030)       /* SMCLK Source Select DCOCLK */
4507 
#define SELS__DCOCLKDIV        (0x0040)       /* SMCLK Source Select DCOCLKDIV */
4508 
#define SELS__XT2CLK           (0x0050)       /* SMCLK Source Select XT2CLK */
4509 
 
4510 
#define SELA_0                 (0x0000)       /* ACLK Source Select 0 */
4511 
#define SELA_1                 (0x0100)       /* ACLK Source Select 1 */
4512 
#define SELA_2                 (0x0200)       /* ACLK Source Select 2 */
4513 
#define SELA_3                 (0x0300)       /* ACLK Source Select 3 */
4514 
#define SELA_4                 (0x0400)       /* ACLK Source Select 4 */
4515 
#define SELA_5                 (0x0500)       /* ACLK Source Select 5 */
4516 
#define SELA_6                 (0x0600)       /* ACLK Source Select 6 */
4517 
#define SELA_7                 (0x0700)       /* ACLK Source Select 7 */
4518 
#define SELA__XT1CLK           (0x0000)       /* ACLK Source Select XT1CLK */
4519 
#define SELA__VLOCLK           (0x0100)       /* ACLK Source Select VLOCLK */
4520 
#define SELA__REFOCLK          (0x0200)       /* ACLK Source Select REFOCLK */
4521 
#define SELA__DCOCLK           (0x0300)       /* ACLK Source Select DCOCLK */
4522 
#define SELA__DCOCLKDIV        (0x0400)       /* ACLK Source Select DCOCLKDIV */
4523 
#define SELA__XT2CLK           (0x0500)       /* ACLK Source Select XT2CLK */
4524 
 
4525 
/* UCSCTL5 Control Bits */
4526 
#define DIVM0                  (0x0001)       /* MCLK Divider Bit: 0 */
4527 
#define DIVM1                  (0x0002)       /* MCLK Divider Bit: 1 */
4528 
#define DIVM2                  (0x0004)       /* MCLK Divider Bit: 2 */
4529 
//#define RESERVED            (0x0008)    /* RESERVED */
4530 
#define DIVS0                  (0x0010)       /* SMCLK Divider Bit: 0 */
4531 
#define DIVS1                  (0x0020)       /* SMCLK Divider Bit: 1 */
4532 
#define DIVS2                  (0x0040)       /* SMCLK Divider Bit: 2 */
4533 
//#define RESERVED            (0x0080)    /* RESERVED */
4534 
#define DIVA0                  (0x0100)       /* ACLK Divider Bit: 0 */
4535 
#define DIVA1                  (0x0200)       /* ACLK Divider Bit: 1 */
4536 
#define DIVA2                  (0x0400)       /* ACLK Divider Bit: 2 */
4537 
//#define RESERVED            (0x0800)    /* RESERVED */
4538 
#define DIVPA0                 (0x1000)       /* ACLK from Pin Divider Bit: 0 */
4539 
#define DIVPA1                 (0x2000)       /* ACLK from Pin Divider Bit: 1 */
4540 
#define DIVPA2                 (0x4000)       /* ACLK from Pin Divider Bit: 2 */
4541 
//#define RESERVED            (0x8000)    /* RESERVED */
4542 
 
4543 
/* UCSCTL5 Control Bits */
4544 
#define DIVM0_L                (0x0001)       /* MCLK Divider Bit: 0 */
4545 
#define DIVM1_L                (0x0002)       /* MCLK Divider Bit: 1 */
4546 
#define DIVM2_L                (0x0004)       /* MCLK Divider Bit: 2 */
4547 
//#define RESERVED            (0x0008)    /* RESERVED */
4548 
#define DIVS0_L                (0x0010)       /* SMCLK Divider Bit: 0 */
4549 
#define DIVS1_L                (0x0020)       /* SMCLK Divider Bit: 1 */
4550 
#define DIVS2_L                (0x0040)       /* SMCLK Divider Bit: 2 */
4551 
//#define RESERVED            (0x0080)    /* RESERVED */
4552 
//#define RESERVED            (0x0800)    /* RESERVED */
4553 
//#define RESERVED            (0x8000)    /* RESERVED */
4554 
 
4555 
/* UCSCTL5 Control Bits */
4556 
//#define RESERVED            (0x0008)    /* RESERVED */
4557 
//#define RESERVED            (0x0080)    /* RESERVED */
4558 
#define DIVA0_H                (0x0001)       /* ACLK Divider Bit: 0 */
4559 
#define DIVA1_H                (0x0002)       /* ACLK Divider Bit: 1 */
4560 
#define DIVA2_H                (0x0004)       /* ACLK Divider Bit: 2 */
4561 
//#define RESERVED            (0x0800)    /* RESERVED */
4562 
#define DIVPA0_H               (0x0010)       /* ACLK from Pin Divider Bit: 0 */
4563 
#define DIVPA1_H               (0x0020)       /* ACLK from Pin Divider Bit: 1 */
4564 
#define DIVPA2_H               (0x0040)       /* ACLK from Pin Divider Bit: 2 */
4565 
//#define RESERVED            (0x8000)    /* RESERVED */
4566 
 
4567 
#define DIVM_0                 (0x0000)       /* MCLK Source Divider 0 */
4568 
#define DIVM_1                 (0x0001)       /* MCLK Source Divider 1 */
4569 
#define DIVM_2                 (0x0002)       /* MCLK Source Divider 2 */
4570 
#define DIVM_3                 (0x0003)       /* MCLK Source Divider 3 */
4571 
#define DIVM_4                 (0x0004)       /* MCLK Source Divider 4 */
4572 
#define DIVM_5                 (0x0005)       /* MCLK Source Divider 5 */
4573 
#define DIVM_6                 (0x0006)       /* MCLK Source Divider 6 */
4574 
#define DIVM_7                 (0x0007)       /* MCLK Source Divider 7 */
4575 
#define DIVM__1                (0x0000)       /* MCLK Source Divider f(MCLK)/1 */
4576 
#define DIVM__2                (0x0001)       /* MCLK Source Divider f(MCLK)/2 */
4577 
#define DIVM__4                (0x0002)       /* MCLK Source Divider f(MCLK)/4 */
4578 
#define DIVM__8                (0x0003)       /* MCLK Source Divider f(MCLK)/8 */
4579 
#define DIVM__16               (0x0004)       /* MCLK Source Divider f(MCLK)/16 */
4580 
#define DIVM__32               (0x0005)       /* MCLK Source Divider f(MCLK)/32 */
4581 
 
4582 
#define DIVS_0                 (0x0000)       /* SMCLK Source Divider 0 */
4583 
#define DIVS_1                 (0x0010)       /* SMCLK Source Divider 1 */
4584 
#define DIVS_2                 (0x0020)       /* SMCLK Source Divider 2 */
4585 
#define DIVS_3                 (0x0030)       /* SMCLK Source Divider 3 */
4586 
#define DIVS_4                 (0x0040)       /* SMCLK Source Divider 4 */
4587 
#define DIVS_5                 (0x0050)       /* SMCLK Source Divider 5 */
4588 
#define DIVS_6                 (0x0060)       /* SMCLK Source Divider 6 */
4589 
#define DIVS_7                 (0x0070)       /* SMCLK Source Divider 7 */
4590 
#define DIVS__1                (0x0000)       /* SMCLK Source Divider f(SMCLK)/1 */
4591 
#define DIVS__2                (0x0010)       /* SMCLK Source Divider f(SMCLK)/2 */
4592 
#define DIVS__4                (0x0020)       /* SMCLK Source Divider f(SMCLK)/4 */
4593 
#define DIVS__8                (0x0030)       /* SMCLK Source Divider f(SMCLK)/8 */
4594 
#define DIVS__16               (0x0040)       /* SMCLK Source Divider f(SMCLK)/16 */
4595 
#define DIVS__32               (0x0050)       /* SMCLK Source Divider f(SMCLK)/32 */
4596 
 
4597 
#define DIVA_0                 (0x0000)       /* ACLK Source Divider 0 */
4598 
#define DIVA_1                 (0x0100)       /* ACLK Source Divider 1 */
4599 
#define DIVA_2                 (0x0200)       /* ACLK Source Divider 2 */
4600 
#define DIVA_3                 (0x0300)       /* ACLK Source Divider 3 */
4601 
#define DIVA_4                 (0x0400)       /* ACLK Source Divider 4 */
4602 
#define DIVA_5                 (0x0500)       /* ACLK Source Divider 5 */
4603 
#define DIVA_6                 (0x0600)       /* ACLK Source Divider 6 */
4604 
#define DIVA_7                 (0x0700)       /* ACLK Source Divider 7 */
4605 
#define DIVA__1                (0x0000)       /* ACLK Source Divider f(ACLK)/1 */
4606 
#define DIVA__2                (0x0100)       /* ACLK Source Divider f(ACLK)/2 */
4607 
#define DIVA__4                (0x0200)       /* ACLK Source Divider f(ACLK)/4 */
4608 
#define DIVA__8                (0x0300)       /* ACLK Source Divider f(ACLK)/8 */
4609 
#define DIVA__16               (0x0400)       /* ACLK Source Divider f(ACLK)/16 */
4610 
#define DIVA__32               (0x0500)       /* ACLK Source Divider f(ACLK)/32 */
4611 
 
4612 
#define DIVPA_0                (0x0000)       /* ACLK from Pin Source Divider 0 */
4613 
#define DIVPA_1                (0x1000)       /* ACLK from Pin Source Divider 1 */
4614 
#define DIVPA_2                (0x2000)       /* ACLK from Pin Source Divider 2 */
4615 
#define DIVPA_3                (0x3000)       /* ACLK from Pin Source Divider 3 */
4616 
#define DIVPA_4                (0x4000)       /* ACLK from Pin Source Divider 4 */
4617 
#define DIVPA_5                (0x5000)       /* ACLK from Pin Source Divider 5 */
4618 
#define DIVPA_6                (0x6000)       /* ACLK from Pin Source Divider 6 */
4619 
#define DIVPA_7                (0x7000)       /* ACLK from Pin Source Divider 7 */
4620 
#define DIVPA__1               (0x0000)       /* ACLK from Pin Source Divider f(ACLK)/1 */
4621 
#define DIVPA__2               (0x1000)       /* ACLK from Pin Source Divider f(ACLK)/2 */
4622 
#define DIVPA__4               (0x2000)       /* ACLK from Pin Source Divider f(ACLK)/4 */
4623 
#define DIVPA__8               (0x3000)       /* ACLK from Pin Source Divider f(ACLK)/8 */
4624 
#define DIVPA__16              (0x4000)       /* ACLK from Pin Source Divider f(ACLK)/16 */
4625 
#define DIVPA__32              (0x5000)       /* ACLK from Pin Source Divider f(ACLK)/32 */
4626 
 
4627 
/* UCSCTL6 Control Bits */
4628 
#define XT1OFF                 (0x0001)       /* High Frequency Oscillator 1 (XT1) disable */
4629 
#define SMCLKOFF               (0x0002)       /* SMCLK Off */
4630 
#define XCAP0                  (0x0004)       /* XIN/XOUT Cap Bit: 0 */
4631 
#define XCAP1                  (0x0008)       /* XIN/XOUT Cap Bit: 1 */
4632 
#define XT1BYPASS              (0x0010)       /* XT1 bypass mode : 0: internal 1:sourced from external pin */
4633 
#define XTS                    (0x0020)       /* 1: Selects high-freq. oscillator */
4634 
#define XT1DRIVE0              (0x0040)       /* XT1 Drive Level mode Bit 0 */
4635 
#define XT1DRIVE1              (0x0080)       /* XT1 Drive Level mode Bit 1 */
4636 
#define XT2OFF                 (0x0100)       /* High Frequency Oscillator 2 (XT2) disable */
4637 
//#define RESERVED            (0x0200)    /* RESERVED */
4638 
//#define RESERVED            (0x0400)    /* RESERVED */
4639 
//#define RESERVED            (0x0800)    /* RESERVED */
4640 
#define XT2BYPASS              (0x1000)       /* XT2 bypass mode : 0: internal 1:sourced from external pin */
4641 
//#define RESERVED            (0x2000)    /* RESERVED */
4642 
#define XT2DRIVE0              (0x4000)       /* XT2 Drive Level mode Bit 0 */
4643 
#define XT2DRIVE1              (0x8000)       /* XT2 Drive Level mode Bit 1 */
4644 
 
4645 
/* UCSCTL6 Control Bits */
4646 
#define XT1OFF_L               (0x0001)       /* High Frequency Oscillator 1 (XT1) disable */
4647 
#define SMCLKOFF_L             (0x0002)       /* SMCLK Off */
4648 
#define XCAP0_L                (0x0004)       /* XIN/XOUT Cap Bit: 0 */
4649 
#define XCAP1_L                (0x0008)       /* XIN/XOUT Cap Bit: 1 */
4650 
#define XT1BYPASS_L            (0x0010)       /* XT1 bypass mode : 0: internal 1:sourced from external pin */
4651 
#define XTS_L                  (0x0020)       /* 1: Selects high-freq. oscillator */
4652 
#define XT1DRIVE0_L            (0x0040)       /* XT1 Drive Level mode Bit 0 */
4653 
#define XT1DRIVE1_L            (0x0080)       /* XT1 Drive Level mode Bit 1 */
4654 
//#define RESERVED            (0x0200)    /* RESERVED */
4655 
//#define RESERVED            (0x0400)    /* RESERVED */
4656 
//#define RESERVED            (0x0800)    /* RESERVED */
4657 
//#define RESERVED            (0x2000)    /* RESERVED */
4658 
 
4659 
/* UCSCTL6 Control Bits */
4660 
#define XT2OFF_H               (0x0001)       /* High Frequency Oscillator 2 (XT2) disable */
4661 
//#define RESERVED            (0x0200)    /* RESERVED */
4662 
//#define RESERVED            (0x0400)    /* RESERVED */
4663 
//#define RESERVED            (0x0800)    /* RESERVED */
4664 
#define XT2BYPASS_H            (0x0010)       /* XT2 bypass mode : 0: internal 1:sourced from external pin */
4665 
//#define RESERVED            (0x2000)    /* RESERVED */
4666 
#define XT2DRIVE0_H            (0x0040)       /* XT2 Drive Level mode Bit 0 */
4667 
#define XT2DRIVE1_H            (0x0080)       /* XT2 Drive Level mode Bit 1 */
4668 
 
4669 
#define XCAP_0                 (0x0000)       /* XIN/XOUT Cap 0 */
4670 
#define XCAP_1                 (0x0004)       /* XIN/XOUT Cap 1 */
4671 
#define XCAP_2                 (0x0008)       /* XIN/XOUT Cap 2 */
4672 
#define XCAP_3                 (0x000C)       /* XIN/XOUT Cap 3 */
4673 
#define XT1DRIVE_0             (0x0000)       /* XT1 Drive Level mode: 0 */
4674 
#define XT1DRIVE_1             (0x0040)       /* XT1 Drive Level mode: 1 */
4675 
#define XT1DRIVE_2             (0x0080)       /* XT1 Drive Level mode: 2 */
4676 
#define XT1DRIVE_3             (0x00C0)       /* XT1 Drive Level mode: 3 */
4677 
#define XT2DRIVE_0             (0x0000)       /* XT2 Drive Level mode: 0 */
4678 
#define XT2DRIVE_1             (0x4000)       /* XT2 Drive Level mode: 1 */
4679 
#define XT2DRIVE_2             (0x8000)       /* XT2 Drive Level mode: 2 */
4680 
#define XT2DRIVE_3             (0xC000)       /* XT2 Drive Level mode: 3 */
4681 
 
4682 
/* UCSCTL7 Control Bits */
4683 
#define DCOFFG                 (0x0001)       /* DCO Fault Flag */
4684 
#define XT1LFOFFG              (0x0002)       /* XT1 Low Frequency Oscillator Fault Flag */
4685 
#define XT1HFOFFG              (0x0004)       /* XT1 High Frequency Oscillator 1 Fault Flag */
4686 
#define XT2OFFG                (0x0008)       /* High Frequency Oscillator 2 Fault Flag */
4687 
//#define RESERVED            (0x0010)    /* RESERVED */
4688 
//#define RESERVED            (0x0020)    /* RESERVED */
4689 
//#define RESERVED            (0x0040)    /* RESERVED */
4690 
//#define RESERVED            (0x0080)    /* RESERVED */
4691 
//#define RESERVED            (0x0100)    /* RESERVED */
4692 
//#define RESERVED            (0x0200)    /* RESERVED */
4693 
//#define RESERVED            (0x0400)    /* RESERVED */
4694 
//#define RESERVED            (0x0800)    /* RESERVED */
4695 
//#define RESERVED            (0x1000)    /* RESERVED */
4696 
//#define RESERVED            (0x2000)    /* RESERVED */
4697 
//#define RESERVED            (0x4000)    /* RESERVED */
4698 
//#define RESERVED            (0x8000)    /* RESERVED */
4699 
 
4700 
/* UCSCTL7 Control Bits */
4701 
#define DCOFFG_L               (0x0001)       /* DCO Fault Flag */
4702 
#define XT1LFOFFG_L            (0x0002)       /* XT1 Low Frequency Oscillator Fault Flag */
4703 
#define XT1HFOFFG_L            (0x0004)       /* XT1 High Frequency Oscillator 1 Fault Flag */
4704 
#define XT2OFFG_L              (0x0008)       /* High Frequency Oscillator 2 Fault Flag */
4705 
//#define RESERVED            (0x0010)    /* RESERVED */
4706 
//#define RESERVED            (0x0020)    /* RESERVED */
4707 
//#define RESERVED            (0x0040)    /* RESERVED */
4708 
//#define RESERVED            (0x0080)    /* RESERVED */
4709 
//#define RESERVED            (0x0100)    /* RESERVED */
4710 
//#define RESERVED            (0x0200)    /* RESERVED */
4711 
//#define RESERVED            (0x0400)    /* RESERVED */
4712 
//#define RESERVED            (0x0800)    /* RESERVED */
4713 
//#define RESERVED            (0x1000)    /* RESERVED */
4714 
//#define RESERVED            (0x2000)    /* RESERVED */
4715 
//#define RESERVED            (0x4000)    /* RESERVED */
4716 
//#define RESERVED            (0x8000)    /* RESERVED */
4717 
 
4718 
/* UCSCTL7 Control Bits */
4719 
//#define RESERVED            (0x0010)    /* RESERVED */
4720 
//#define RESERVED            (0x0020)    /* RESERVED */
4721 
//#define RESERVED            (0x0040)    /* RESERVED */
4722 
//#define RESERVED            (0x0080)    /* RESERVED */
4723 
//#define RESERVED            (0x0100)    /* RESERVED */
4724 
//#define RESERVED            (0x0200)    /* RESERVED */
4725 
//#define RESERVED            (0x0400)    /* RESERVED */
4726 
//#define RESERVED            (0x0800)    /* RESERVED */
4727 
//#define RESERVED            (0x1000)    /* RESERVED */
4728 
//#define RESERVED            (0x2000)    /* RESERVED */
4729 
//#define RESERVED            (0x4000)    /* RESERVED */
4730 
//#define RESERVED            (0x8000)    /* RESERVED */
4731 
 
4732 
/* UCSCTL8 Control Bits */
4733 
#define ACLKREQEN              (0x0001)       /* ACLK Clock Request Enable */
4734 
#define MCLKREQEN              (0x0002)       /* MCLK Clock Request Enable */
4735 
#define SMCLKREQEN             (0x0004)       /* SMCLK Clock Request Enable */
4736 
#define MODOSCREQEN            (0x0008)       /* MODOSC Clock Request Enable */
4737 
//#define RESERVED            (0x0010)    /* RESERVED */
4738 
//#define RESERVED            (0x0020)    /* RESERVED */
4739 
//#define RESERVED            (0x0040)    /* RESERVED */
4740 
//#define RESERVED            (0x0080)    /* RESERVED */
4741 
//#define RESERVED            (0x0100)    /* RESERVED */
4742 
//#define RESERVED            (0x0200)    /* RESERVED */
4743 
//#define RESERVED            (0x0400)    /* RESERVED */
4744 
//#define RESERVED            (0x0800)    /* RESERVED */
4745 
//#define RESERVED            (0x1000)    /* RESERVED */
4746 
//#define RESERVED            (0x2000)    /* RESERVED */
4747 
//#define RESERVED            (0x4000)    /* RESERVED */
4748 
//#define RESERVED            (0x8000)    /* RESERVED */
4749 
 
4750 
/* UCSCTL8 Control Bits */
4751 
#define ACLKREQEN_L            (0x0001)       /* ACLK Clock Request Enable */
4752 
#define MCLKREQEN_L            (0x0002)       /* MCLK Clock Request Enable */
4753 
#define SMCLKREQEN_L           (0x0004)       /* SMCLK Clock Request Enable */
4754 
#define MODOSCREQEN_L          (0x0008)       /* MODOSC Clock Request Enable */
4755 
//#define RESERVED            (0x0010)    /* RESERVED */
4756 
//#define RESERVED            (0x0020)    /* RESERVED */
4757 
//#define RESERVED            (0x0040)    /* RESERVED */
4758 
//#define RESERVED            (0x0080)    /* RESERVED */
4759 
//#define RESERVED            (0x0100)    /* RESERVED */
4760 
//#define RESERVED            (0x0200)    /* RESERVED */
4761 
//#define RESERVED            (0x0400)    /* RESERVED */
4762 
//#define RESERVED            (0x0800)    /* RESERVED */
4763 
//#define RESERVED            (0x1000)    /* RESERVED */
4764 
//#define RESERVED            (0x2000)    /* RESERVED */
4765 
//#define RESERVED            (0x4000)    /* RESERVED */
4766 
//#define RESERVED            (0x8000)    /* RESERVED */
4767 
 
4768 
/* UCSCTL8 Control Bits */
4769 
//#define RESERVED            (0x0010)    /* RESERVED */
4770 
//#define RESERVED            (0x0020)    /* RESERVED */
4771 
//#define RESERVED            (0x0040)    /* RESERVED */
4772 
//#define RESERVED            (0x0080)    /* RESERVED */
4773 
//#define RESERVED            (0x0100)    /* RESERVED */
4774 
//#define RESERVED            (0x0200)    /* RESERVED */
4775 
//#define RESERVED            (0x0400)    /* RESERVED */
4776 
//#define RESERVED            (0x0800)    /* RESERVED */
4777 
//#define RESERVED            (0x1000)    /* RESERVED */
4778 
//#define RESERVED            (0x2000)    /* RESERVED */
4779 
//#define RESERVED            (0x4000)    /* RESERVED */
4780 
//#define RESERVED            (0x8000)    /* RESERVED */
4781 
 
4782 
/************************************************************
4783 
* USCI A0
4784 
************************************************************/
4785 
#define __MSP430_HAS_USCI_A0__                /* Definition to show that Module is available */
4786 
#define __MSP430_BASEADDRESS_USCI_A0__ 0x05C0
4787 
 
4788 
SFR_16BIT(UCA0CTLW0);                         /* USCI A0 Control Word Register 0 */
4789 
SFR_8BIT(UCA0CTLW0_L);                        /* USCI A0 Control Word Register 0 */
4790 
SFR_8BIT(UCA0CTLW0_H);                        /* USCI A0 Control Word Register 0 */
4791 
#define UCA0CTL1               UCA0CTLW0_L    /* USCI A0 Control Register 1 */
4792 
#define UCA0CTL0               UCA0CTLW0_H    /* USCI A0 Control Register 0 */
4793 
SFR_16BIT(UCA0BRW);                           /* USCI A0 Baud Word Rate 0 */
4794 
SFR_8BIT(UCA0BRW_L);                          /* USCI A0 Baud Word Rate 0 */
4795 
SFR_8BIT(UCA0BRW_H);                          /* USCI A0 Baud Word Rate 0 */
4796 
#define UCA0BR0                UCA0BRW_L      /* USCI A0 Baud Rate 0 */
4797 
#define UCA0BR1                UCA0BRW_H      /* USCI A0 Baud Rate 1 */
4798 
SFR_8BIT(UCA0MCTL);                           /* USCI A0 Modulation Control */
4799 
SFR_8BIT(UCA0STAT);                           /* USCI A0 Status Register */
4800 
SFR_8BIT(UCA0RXBUF);                          /* USCI A0 Receive Buffer */
4801 
SFR_8BIT(UCA0TXBUF);                          /* USCI A0 Transmit Buffer */
4802 
SFR_8BIT(UCA0ABCTL);                          /* USCI A0 LIN Control */
4803 
SFR_16BIT(UCA0IRCTL);                         /* USCI A0 IrDA Transmit Control */
4804 
SFR_8BIT(UCA0IRCTL_L);                        /* USCI A0 IrDA Transmit Control */
4805 
SFR_8BIT(UCA0IRCTL_H);                        /* USCI A0 IrDA Transmit Control */
4806 
#define UCA0IRTCTL             UCA0IRCTL_L    /* USCI A0 IrDA Transmit Control */
4807 
#define UCA0IRRCTL             UCA0IRCTL_H    /* USCI A0 IrDA Receive Control */
4808 
SFR_16BIT(UCA0ICTL);                          /* USCI A0 Interrupt Enable Register */
4809 
SFR_8BIT(UCA0ICTL_L);                         /* USCI A0 Interrupt Enable Register */
4810 
SFR_8BIT(UCA0ICTL_H);                         /* USCI A0 Interrupt Enable Register */
4811 
#define UCA0IE                 UCA0ICTL_L     /* USCI A0 Interrupt Enable Register */
4812 
#define UCA0IFG                UCA0ICTL_H     /* USCI A0 Interrupt Flags Register */
4813 
SFR_16BIT(UCA0IV);                            /* USCI A0 Interrupt Vector Register */
4814 
 
4815 
 
4816 
/************************************************************
4817 
* USCI B0
4818 
************************************************************/
4819 
#define __MSP430_HAS_USCI_B0__                /* Definition to show that Module is available */
4820 
#define __MSP430_BASEADDRESS_USCI_B0__ 0x05E0
4821 
 
4822 
 
4823 
SFR_16BIT(UCB0CTLW0);                         /* USCI B0 Control Word Register 0 */
4824 
SFR_8BIT(UCB0CTLW0_L);                        /* USCI B0 Control Word Register 0 */
4825 
SFR_8BIT(UCB0CTLW0_H);                        /* USCI B0 Control Word Register 0 */
4826 
#define UCB0CTL1               UCB0CTLW0_L    /* USCI B0 Control Register 1 */
4827 
#define UCB0CTL0               UCB0CTLW0_H    /* USCI B0 Control Register 0 */
4828 
SFR_16BIT(UCB0BRW);                           /* USCI B0 Baud Word Rate 0 */
4829 
SFR_8BIT(UCB0BRW_L);                          /* USCI B0 Baud Word Rate 0 */
4830 
SFR_8BIT(UCB0BRW_H);                          /* USCI B0 Baud Word Rate 0 */
4831 
#define UCB0BR0                UCB0BRW_L      /* USCI B0 Baud Rate 0 */
4832 
#define UCB0BR1                UCB0BRW_H      /* USCI B0 Baud Rate 1 */
4833 
SFR_8BIT(UCB0STAT);                           /* USCI B0 Status Register */
4834 
SFR_8BIT(UCB0RXBUF);                          /* USCI B0 Receive Buffer */
4835 
SFR_8BIT(UCB0TXBUF);                          /* USCI B0 Transmit Buffer */
4836 
SFR_16BIT(UCB0I2COA);                         /* USCI B0 I2C Own Address */
4837 
SFR_8BIT(UCB0I2COA_L);                        /* USCI B0 I2C Own Address */
4838 
SFR_8BIT(UCB0I2COA_H);                        /* USCI B0 I2C Own Address */
4839 
SFR_16BIT(UCB0I2CSA);                         /* USCI B0 I2C Slave Address */
4840 
SFR_8BIT(UCB0I2CSA_L);                        /* USCI B0 I2C Slave Address */
4841 
SFR_8BIT(UCB0I2CSA_H);                        /* USCI B0 I2C Slave Address */
4842 
SFR_16BIT(UCB0ICTL);                          /* USCI B0 Interrupt Enable Register */
4843 
SFR_8BIT(UCB0ICTL_L);                         /* USCI B0 Interrupt Enable Register */
4844 
SFR_8BIT(UCB0ICTL_H);                         /* USCI B0 Interrupt Enable Register */
4845 
#define UCB0IE                 UCB0ICTL_L     /* USCI B0 Interrupt Enable Register */
4846 
#define UCB0IFG                UCB0ICTL_H     /* USCI B0 Interrupt Flags Register */
4847 
SFR_16BIT(UCB0IV);                            /* USCI B0 Interrupt Vector Register */
4848 
 
4849 
// UCAxCTL0 UART-Mode Control Bits
4850 
#define UCPEN                  (0x80)         /* Async. Mode: Parity enable */
4851 
#define UCPAR                  (0x40)         /* Async. Mode: Parity     0:odd / 1:even */
4852 
#define UCMSB                  (0x20)         /* Async. Mode: MSB first  0:LSB / 1:MSB */
4853 
#define UC7BIT                 (0x10)         /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
4854 
#define UCSPB                  (0x08)         /* Async. Mode: Stop Bits  0:one / 1: two */
4855 
#define UCMODE1                (0x04)         /* Async. Mode: USCI Mode 1 */
4856 
#define UCMODE0                (0x02)         /* Async. Mode: USCI Mode 0 */
4857 
#define UCSYNC                 (0x01)         /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
4858 
 
4859 
// UCxxCTL0 SPI-Mode Control Bits
4860 
#define UCCKPH                 (0x80)         /* Sync. Mode: Clock Phase */
4861 
#define UCCKPL                 (0x40)         /* Sync. Mode: Clock Polarity */
4862 
#define UCMST                  (0x08)         /* Sync. Mode: Master Select */
4863 
 
4864 
// UCBxCTL0 I2C-Mode Control Bits
4865 
#define UCA10                  (0x80)         /* 10-bit Address Mode */
4866 
#define UCSLA10                (0x40)         /* 10-bit Slave Address Mode */
4867 
#define UCMM                   (0x20)         /* Multi-Master Environment */
4868 
//#define res               (0x10)    /* reserved */
4869 
#define UCMODE_0               (0x00)         /* Sync. Mode: USCI Mode: 0 */
4870 
#define UCMODE_1               (0x02)         /* Sync. Mode: USCI Mode: 1 */
4871 
#define UCMODE_2               (0x04)         /* Sync. Mode: USCI Mode: 2 */
4872 
#define UCMODE_3               (0x06)         /* Sync. Mode: USCI Mode: 3 */
4873 
 
4874 
// UCAxCTL1 UART-Mode Control Bits
4875 
#define UCSSEL1                (0x80)         /* USCI 0 Clock Source Select 1 */
4876 
#define UCSSEL0                (0x40)         /* USCI 0 Clock Source Select 0 */
4877 
#define UCRXEIE                (0x20)         /* RX Error interrupt enable */
4878 
#define UCBRKIE                (0x10)         /* Break interrupt enable */
4879 
#define UCDORM                 (0x08)         /* Dormant (Sleep) Mode */
4880 
#define UCTXADDR               (0x04)         /* Send next Data as Address */
4881 
#define UCTXBRK                (0x02)         /* Send next Data as Break */
4882 
#define UCSWRST                (0x01)         /* USCI Software Reset */
4883 
 
4884 
// UCxxCTL1 SPI-Mode Control Bits
4885 
//#define res               (0x20)    /* reserved */
4886 
//#define res               (0x10)    /* reserved */
4887 
//#define res               (0x08)    /* reserved */
4888 
//#define res               (0x04)    /* reserved */
4889 
//#define res               (0x02)    /* reserved */
4890 
 
4891 
// UCBxCTL1 I2C-Mode Control Bits
4892 
//#define res               (0x20)    /* reserved */
4893 
#define UCTR                   (0x10)         /* Transmit/Receive Select/Flag */
4894 
#define UCTXNACK               (0x08)         /* Transmit NACK */
4895 
#define UCTXSTP                (0x04)         /* Transmit STOP */
4896 
#define UCTXSTT                (0x02)         /* Transmit START */
4897 
#define UCSSEL_0               (0x00)         /* USCI 0 Clock Source: 0 */
4898 
#define UCSSEL_1               (0x40)         /* USCI 0 Clock Source: 1 */
4899 
#define UCSSEL_2               (0x80)         /* USCI 0 Clock Source: 2 */
4900 
#define UCSSEL_3               (0xC0)         /* USCI 0 Clock Source: 3 */
4901 
#define UCSSEL__UCLK           (0x00)         /* USCI 0 Clock Source: UCLK */
4902 
#define UCSSEL__ACLK           (0x40)         /* USCI 0 Clock Source: ACLK */
4903 
#define UCSSEL__SMCLK          (0x80)         /* USCI 0 Clock Source: SMCLK */
4904 
 
4905 
/* UCAxMCTL Control Bits */
4906 
#define UCBRF3                 (0x80)         /* USCI First Stage Modulation Select 3 */
4907 
#define UCBRF2                 (0x40)         /* USCI First Stage Modulation Select 2 */
4908 
#define UCBRF1                 (0x20)         /* USCI First Stage Modulation Select 1 */
4909 
#define UCBRF0                 (0x10)         /* USCI First Stage Modulation Select 0 */
4910 
#define UCBRS2                 (0x08)         /* USCI Second Stage Modulation Select 2 */
4911 
#define UCBRS1                 (0x04)         /* USCI Second Stage Modulation Select 1 */
4912 
#define UCBRS0                 (0x02)         /* USCI Second Stage Modulation Select 0 */
4913 
#define UCOS16                 (0x01)         /* USCI 16-times Oversampling enable */
4914 
 
4915 
#define UCBRF_0                (0x00)         /* USCI First Stage Modulation: 0 */
4916 
#define UCBRF_1                (0x10)         /* USCI First Stage Modulation: 1 */
4917 
#define UCBRF_2                (0x20)         /* USCI First Stage Modulation: 2 */
4918 
#define UCBRF_3                (0x30)         /* USCI First Stage Modulation: 3 */
4919 
#define UCBRF_4                (0x40)         /* USCI First Stage Modulation: 4 */
4920 
#define UCBRF_5                (0x50)         /* USCI First Stage Modulation: 5 */
4921 
#define UCBRF_6                (0x60)         /* USCI First Stage Modulation: 6 */
4922 
#define UCBRF_7                (0x70)         /* USCI First Stage Modulation: 7 */
4923 
#define UCBRF_8                (0x80)         /* USCI First Stage Modulation: 8 */
4924 
#define UCBRF_9                (0x90)         /* USCI First Stage Modulation: 9 */
4925 
#define UCBRF_10               (0xA0)         /* USCI First Stage Modulation: A */
4926 
#define UCBRF_11               (0xB0)         /* USCI First Stage Modulation: B */
4927 
#define UCBRF_12               (0xC0)         /* USCI First Stage Modulation: C */
4928 
#define UCBRF_13               (0xD0)         /* USCI First Stage Modulation: D */
4929 
#define UCBRF_14               (0xE0)         /* USCI First Stage Modulation: E */
4930 
#define UCBRF_15               (0xF0)         /* USCI First Stage Modulation: F */
4931 
 
4932 
#define UCBRS_0                (0x00)         /* USCI Second Stage Modulation: 0 */
4933 
#define UCBRS_1                (0x02)         /* USCI Second Stage Modulation: 1 */
4934 
#define UCBRS_2                (0x04)         /* USCI Second Stage Modulation: 2 */
4935 
#define UCBRS_3                (0x06)         /* USCI Second Stage Modulation: 3 */
4936 
#define UCBRS_4                (0x08)         /* USCI Second Stage Modulation: 4 */
4937 
#define UCBRS_5                (0x0A)         /* USCI Second Stage Modulation: 5 */
4938 
#define UCBRS_6                (0x0C)         /* USCI Second Stage Modulation: 6 */
4939 
#define UCBRS_7                (0x0E)         /* USCI Second Stage Modulation: 7 */
4940 
 
4941 
/* UCAxSTAT Control Bits */
4942 
#define UCLISTEN               (0x80)         /* USCI Listen mode */
4943 
#define UCFE                   (0x40)         /* USCI Frame Error Flag */
4944 
#define UCOE                   (0x20)         /* USCI Overrun Error Flag */
4945 
#define UCPE                   (0x10)         /* USCI Parity Error Flag */
4946 
#define UCBRK                  (0x08)         /* USCI Break received */
4947 
#define UCRXERR                (0x04)         /* USCI RX Error Flag */
4948 
#define UCADDR                 (0x02)         /* USCI Address received Flag */
4949 
#define UCBUSY                 (0x01)         /* USCI Busy Flag */
4950 
#define UCIDLE                 (0x02)         /* USCI Idle line detected Flag */
4951 
 
4952 
/* UCBxSTAT Control Bits */
4953 
#define UCSCLLOW               (0x40)         /* SCL low */
4954 
#define UCGC                   (0x20)         /* General Call address received Flag */
4955 
#define UCBBUSY                (0x10)         /* Bus Busy Flag */
4956 
 
4957 
/* UCAxIRTCTL Control Bits */
4958 
#define UCIRTXPL5              (0x80)         /* IRDA Transmit Pulse Length 5 */
4959 
#define UCIRTXPL4              (0x40)         /* IRDA Transmit Pulse Length 4 */
4960 
#define UCIRTXPL3              (0x20)         /* IRDA Transmit Pulse Length 3 */
4961 
#define UCIRTXPL2              (0x10)         /* IRDA Transmit Pulse Length 2 */
4962 
#define UCIRTXPL1              (0x08)         /* IRDA Transmit Pulse Length 1 */
4963 
#define UCIRTXPL0              (0x04)         /* IRDA Transmit Pulse Length 0 */
4964 
#define UCIRTXCLK              (0x02)         /* IRDA Transmit Pulse Clock Select */
4965 
#define UCIREN                 (0x01)         /* IRDA Encoder/Decoder enable */
4966 
 
4967 
/* UCAxIRRCTL Control Bits */
4968 
#define UCIRRXFL5              (0x80)         /* IRDA Receive Filter Length 5 */
4969 
#define UCIRRXFL4              (0x40)         /* IRDA Receive Filter Length 4 */
4970 
#define UCIRRXFL3              (0x20)         /* IRDA Receive Filter Length 3 */
4971 
#define UCIRRXFL2              (0x10)         /* IRDA Receive Filter Length 2 */
4972 
#define UCIRRXFL1              (0x08)         /* IRDA Receive Filter Length 1 */
4973 
#define UCIRRXFL0              (0x04)         /* IRDA Receive Filter Length 0 */
4974 
#define UCIRRXPL               (0x02)         /* IRDA Receive Input Polarity */
4975 
#define UCIRRXFE               (0x01)         /* IRDA Receive Filter enable */
4976 
 
4977 
/* UCAxABCTL Control Bits */
4978 
//#define res               (0x80)    /* reserved */
4979 
//#define res               (0x40)    /* reserved */
4980 
#define UCDELIM1               (0x20)         /* Break Sync Delimiter 1 */
4981 
#define UCDELIM0               (0x10)         /* Break Sync Delimiter 0 */
4982 
#define UCSTOE                 (0x08)         /* Sync-Field Timeout error */
4983 
#define UCBTOE                 (0x04)         /* Break Timeout error */
4984 
//#define res               (0x02)    /* reserved */
4985 
#define UCABDEN                (0x01)         /* Auto Baud Rate detect enable */
4986 
 
4987 
/* UCBxI2COA Control Bits */
4988 
#define UCGCEN                 (0x8000)       /* I2C General Call enable */
4989 
#define UCOA9                  (0x0200)       /* I2C Own Address 9 */
4990 
#define UCOA8                  (0x0100)       /* I2C Own Address 8 */
4991 
#define UCOA7                  (0x0080)       /* I2C Own Address 7 */
4992 
#define UCOA6                  (0x0040)       /* I2C Own Address 6 */
4993 
#define UCOA5                  (0x0020)       /* I2C Own Address 5 */
4994 
#define UCOA4                  (0x0010)       /* I2C Own Address 4 */
4995 
#define UCOA3                  (0x0008)       /* I2C Own Address 3 */
4996 
#define UCOA2                  (0x0004)       /* I2C Own Address 2 */
4997 
#define UCOA1                  (0x0002)       /* I2C Own Address 1 */
4998 
#define UCOA0                  (0x0001)       /* I2C Own Address 0 */
4999 
 
5000 
/* UCBxI2COA Control Bits */
5001 
#define UCOA7_L                (0x0080)       /* I2C Own Address 7 */
5002 
#define UCOA6_L                (0x0040)       /* I2C Own Address 6 */
5003 
#define UCOA5_L                (0x0020)       /* I2C Own Address 5 */
5004 
#define UCOA4_L                (0x0010)       /* I2C Own Address 4 */
5005 
#define UCOA3_L                (0x0008)       /* I2C Own Address 3 */
5006 
#define UCOA2_L                (0x0004)       /* I2C Own Address 2 */
5007 
#define UCOA1_L                (0x0002)       /* I2C Own Address 1 */
5008 
#define UCOA0_L                (0x0001)       /* I2C Own Address 0 */
5009 
 
5010 
/* UCBxI2COA Control Bits */
5011 
#define UCGCEN_H               (0x0080)       /* I2C General Call enable */
5012 
#define UCOA9_H                (0x0002)       /* I2C Own Address 9 */
5013 
#define UCOA8_H                (0x0001)       /* I2C Own Address 8 */
5014 
 
5015 
/* UCBxI2CSA Control Bits */
5016 
#define UCSA9                  (0x0200)       /* I2C Slave Address 9 */
5017 
#define UCSA8                  (0x0100)       /* I2C Slave Address 8 */
5018 
#define UCSA7                  (0x0080)       /* I2C Slave Address 7 */
5019 
#define UCSA6                  (0x0040)       /* I2C Slave Address 6 */
5020 
#define UCSA5                  (0x0020)       /* I2C Slave Address 5 */
5021 
#define UCSA4                  (0x0010)       /* I2C Slave Address 4 */
5022 
#define UCSA3                  (0x0008)       /* I2C Slave Address 3 */
5023 
#define UCSA2                  (0x0004)       /* I2C Slave Address 2 */
5024 
#define UCSA1                  (0x0002)       /* I2C Slave Address 1 */
5025 
#define UCSA0                  (0x0001)       /* I2C Slave Address 0 */
5026 
 
5027 
/* UCBxI2CSA Control Bits */
5028 
#define UCSA7_L                (0x0080)       /* I2C Slave Address 7 */
5029 
#define UCSA6_L                (0x0040)       /* I2C Slave Address 6 */
5030 
#define UCSA5_L                (0x0020)       /* I2C Slave Address 5 */
5031 
#define UCSA4_L                (0x0010)       /* I2C Slave Address 4 */
5032 
#define UCSA3_L                (0x0008)       /* I2C Slave Address 3 */
5033 
#define UCSA2_L                (0x0004)       /* I2C Slave Address 2 */
5034 
#define UCSA1_L                (0x0002)       /* I2C Slave Address 1 */
5035 
#define UCSA0_L                (0x0001)       /* I2C Slave Address 0 */
5036 
 
5037 
/* UCBxI2CSA Control Bits */
5038 
#define UCSA9_H                (0x0002)       /* I2C Slave Address 9 */
5039 
#define UCSA8_H                (0x0001)       /* I2C Slave Address 8 */
5040 
 
5041 
/* UCAxIE Control Bits */
5042 
#define UCTXIE                 (0x0002)       /* USCI Transmit Interrupt Enable */
5043 
#define UCRXIE                 (0x0001)       /* USCI Receive Interrupt Enable */
5044 
 
5045 
/* UCBxIE Control Bits */
5046 
#define UCNACKIE               (0x0020)       /* NACK Condition interrupt enable */
5047 
#define UCALIE                 (0x0010)       /* Arbitration Lost interrupt enable */
5048 
#define UCSTPIE                (0x0008)       /* STOP Condition interrupt enable */
5049 
#define UCSTTIE                (0x0004)       /* START Condition interrupt enable */
5050 
#define UCTXIE                 (0x0002)       /* USCI Transmit Interrupt Enable */
5051 
#define UCRXIE                 (0x0001)       /* USCI Receive Interrupt Enable */
5052 
 
5053 
/* UCAxIFG Control Bits */
5054 
#define UCTXIFG                (0x0002)       /* USCI Transmit Interrupt Flag */
5055 
#define UCRXIFG                (0x0001)       /* USCI Receive Interrupt Flag */
5056 
 
5057 
/* UCBxIFG Control Bits */
5058 
#define UCNACKIFG              (0x0020)       /* NAK Condition interrupt Flag */
5059 
#define UCALIFG                (0x0010)       /* Arbitration Lost interrupt Flag */
5060 
#define UCSTPIFG               (0x0008)       /* STOP Condition interrupt Flag */
5061 
#define UCSTTIFG               (0x0004)       /* START Condition interrupt Flag */
5062 
#define UCTXIFG                (0x0002)       /* USCI Transmit Interrupt Flag */
5063 
#define UCRXIFG                (0x0001)       /* USCI Receive Interrupt Flag */
5064 
 
5065 
/* USCI Definitions */
5066 
#define USCI_NONE              (0x0000)       /* No Interrupt pending */
5067 
#define USCI_UCRXIFG           (0x0002)       /* USCI UCRXIFG */
5068 
#define USCI_UCTXIFG           (0x0004)       /* USCI UCTXIFG */
5069 
#define USCI_I2C_UCALIFG       (0x0002)       /* USCI I2C Mode: UCALIFG */
5070 
#define USCI_I2C_UCNACKIFG     (0x0004)       /* USCI I2C Mode: UCNACKIFG */
5071 
#define USCI_I2C_UCSTTIFG      (0x0006)       /* USCI I2C Mode: UCSTTIFG*/
5072 
#define USCI_I2C_UCSTPIFG      (0x0008)       /* USCI I2C Mode: UCSTPIFG*/
5073 
#define USCI_I2C_UCRXIFG       (0x000A)       /* USCI I2C Mode: UCRXIFG */
5074 
#define USCI_I2C_UCTXIFG       (0x000C)       /* USCI I2C Mode: UCTXIFG */
5075 
 
5076 
/************************************************************
5077 
* USCI A1
5078 
************************************************************/
5079 
#define __MSP430_HAS_USCI_A1__                /* Definition to show that Module is available */
5080 
#define __MSP430_BASEADDRESS_USCI_A1__ 0x0600
5081 
 
5082 
SFR_16BIT(UCA1CTLW0);                         /* USCI A1 Control Word Register 0 */
5083 
SFR_8BIT(UCA1CTLW0_L);                        /* USCI A1 Control Word Register 0 */
5084 
SFR_8BIT(UCA1CTLW0_H);                        /* USCI A1 Control Word Register 0 */
5085 
#define UCA1CTL1               UCA1CTLW0_L    /* USCI A1 Control Register 1 */
5086 
#define UCA1CTL0               UCA1CTLW0_H    /* USCI A1 Control Register 0 */
5087 
SFR_16BIT(UCA1BRW);                           /* USCI A1 Baud Word Rate 0 */
5088 
SFR_8BIT(UCA1BRW_L);                          /* USCI A1 Baud Word Rate 0 */
5089 
SFR_8BIT(UCA1BRW_H);                          /* USCI A1 Baud Word Rate 0 */
5090 
#define UCA1BR0                UCA1BRW_L      /* USCI A1 Baud Rate 0 */
5091 
#define UCA1BR1                UCA1BRW_H      /* USCI A1 Baud Rate 1 */
5092 
SFR_8BIT(UCA1MCTL);                           /* USCI A1 Modulation Control */
5093 
SFR_8BIT(UCA1STAT);                           /* USCI A1 Status Register */
5094 
SFR_8BIT(UCA1RXBUF);                          /* USCI A1 Receive Buffer */
5095 
SFR_8BIT(UCA1TXBUF);                          /* USCI A1 Transmit Buffer */
5096 
SFR_8BIT(UCA1ABCTL);                          /* USCI A1 LIN Control */
5097 
SFR_16BIT(UCA1IRCTL);                         /* USCI A1 IrDA Transmit Control */
5098 
SFR_8BIT(UCA1IRCTL_L);                        /* USCI A1 IrDA Transmit Control */
5099 
SFR_8BIT(UCA1IRCTL_H);                        /* USCI A1 IrDA Transmit Control */
5100 
#define UCA1IRTCTL             UCA1IRCTL_L    /* USCI A1 IrDA Transmit Control */
5101 
#define UCA1IRRCTL             UCA1IRCTL_H    /* USCI A1 IrDA Receive Control */
5102 
SFR_16BIT(UCA1ICTL);                          /* USCI A1 Interrupt Enable Register */
5103 
SFR_8BIT(UCA1ICTL_L);                         /* USCI A1 Interrupt Enable Register */
5104 
SFR_8BIT(UCA1ICTL_H);                         /* USCI A1 Interrupt Enable Register */
5105 
#define UCA1IE                 UCA1ICTL_L     /* USCI A1 Interrupt Enable Register */
5106 
#define UCA1IFG                UCA1ICTL_H     /* USCI A1 Interrupt Flags Register */
5107 
SFR_16BIT(UCA1IV);                            /* USCI A1 Interrupt Vector Register */
5108 
 
5109 
 
5110 
/************************************************************
5111 
* USCI B1
5112 
************************************************************/
5113 
#define __MSP430_HAS_USCI_B1__                /* Definition to show that Module is available */
5114 
#define __MSP430_BASEADDRESS_USCI_B1__ 0x0620
5115 
 
5116 
 
5117 
SFR_16BIT(UCB1CTLW0);                         /* USCI B1 Control Word Register 0 */
5118 
SFR_8BIT(UCB1CTLW0_L);                        /* USCI B1 Control Word Register 0 */
5119 
SFR_8BIT(UCB1CTLW0_H);                        /* USCI B1 Control Word Register 0 */
5120 
#define UCB1CTL1               UCB1CTLW0_L    /* USCI B1 Control Register 1 */
5121 
#define UCB1CTL0               UCB1CTLW0_H    /* USCI B1 Control Register 0 */
5122 
SFR_16BIT(UCB1BRW);                           /* USCI B1 Baud Word Rate 0 */
5123 
SFR_8BIT(UCB1BRW_L);                          /* USCI B1 Baud Word Rate 0 */
5124 
SFR_8BIT(UCB1BRW_H);                          /* USCI B1 Baud Word Rate 0 */
5125 
#define UCB1BR0                UCB1BRW_L      /* USCI B1 Baud Rate 0 */
5126 
#define UCB1BR1                UCB1BRW_H      /* USCI B1 Baud Rate 1 */
5127 
SFR_8BIT(UCB1STAT);                           /* USCI B1 Status Register */
5128 
SFR_8BIT(UCB1RXBUF);                          /* USCI B1 Receive Buffer */
5129 
SFR_8BIT(UCB1TXBUF);                          /* USCI B1 Transmit Buffer */
5130 
SFR_16BIT(UCB1I2COA);                         /* USCI B1 I2C Own Address */
5131 
SFR_8BIT(UCB1I2COA_L);                        /* USCI B1 I2C Own Address */
5132 
SFR_8BIT(UCB1I2COA_H);                        /* USCI B1 I2C Own Address */
5133 
SFR_16BIT(UCB1I2CSA);                         /* USCI B1 I2C Slave Address */
5134 
SFR_8BIT(UCB1I2CSA_L);                        /* USCI B1 I2C Slave Address */
5135 
SFR_8BIT(UCB1I2CSA_H);                        /* USCI B1 I2C Slave Address */
5136 
SFR_16BIT(UCB1ICTL);                          /* USCI B1 Interrupt Enable Register */
5137 
SFR_8BIT(UCB1ICTL_L);                         /* USCI B1 Interrupt Enable Register */
5138 
SFR_8BIT(UCB1ICTL_H);                         /* USCI B1 Interrupt Enable Register */
5139 
#define UCB1IE                 UCB1ICTL_L     /* USCI B1 Interrupt Enable Register */
5140 
#define UCB1IFG                UCB1ICTL_H     /* USCI B1 Interrupt Flags Register */
5141 
SFR_16BIT(UCB1IV);                            /* USCI B1 Interrupt Vector Register */
5142 
 
5143 
/************************************************************
5144 
* WATCHDOG TIMER A
5145 
************************************************************/
5146 
#define __MSP430_HAS_WDT_A__                  /* Definition to show that Module is available */
5147 
#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
5148 
 
5149 
SFR_16BIT(WDTCTL);                            /* Watchdog Timer Control */
5150 
SFR_8BIT(WDTCTL_L);                           /* Watchdog Timer Control */
5151 
SFR_8BIT(WDTCTL_H);                           /* Watchdog Timer Control */
5152 
/* The bit names have been prefixed with "WDT" */
5153 
/* WDTCTL Control Bits */
5154 
#define WDTIS0                 (0x0001)       /* WDT - Timer Interval Select 0 */
5155 
#define WDTIS1                 (0x0002)       /* WDT - Timer Interval Select 1 */
5156 
#define WDTIS2                 (0x0004)       /* WDT - Timer Interval Select 2 */
5157 
#define WDTCNTCL               (0x0008)       /* WDT - Timer Clear */
5158 
#define WDTTMSEL               (0x0010)       /* WDT - Timer Mode Select */
5159 
#define WDTSSEL0               (0x0020)       /* WDT - Timer Clock Source Select 0 */
5160 
#define WDTSSEL1               (0x0040)       /* WDT - Timer Clock Source Select 1 */
5161 
#define WDTHOLD                (0x0080)       /* WDT - Timer hold */
5162 
 
5163 
/* WDTCTL Control Bits */
5164 
#define WDTIS0_L               (0x0001)       /* WDT - Timer Interval Select 0 */
5165 
#define WDTIS1_L               (0x0002)       /* WDT - Timer Interval Select 1 */
5166 
#define WDTIS2_L               (0x0004)       /* WDT - Timer Interval Select 2 */
5167 
#define WDTCNTCL_L             (0x0008)       /* WDT - Timer Clear */
5168 
#define WDTTMSEL_L             (0x0010)       /* WDT - Timer Mode Select */
5169 
#define WDTSSEL0_L             (0x0020)       /* WDT - Timer Clock Source Select 0 */
5170 
#define WDTSSEL1_L             (0x0040)       /* WDT - Timer Clock Source Select 1 */
5171 
#define WDTHOLD_L              (0x0080)       /* WDT - Timer hold */
5172 
 
5173 
/* WDTCTL Control Bits */
5174 
 
5175 
#define WDTPW                  (0x5A00)
5176 
 
5177 
#define WDTIS_0                (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
5178 
#define WDTIS_1                (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
5179 
#define WDTIS_2                (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
5180 
#define WDTIS_3                (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
5181 
#define WDTIS_4                (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
5182 
#define WDTIS_5                (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
5183 
#define WDTIS_6                (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
5184 
#define WDTIS_7                (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
5185 
#define WDTIS__2G              (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
5186 
#define WDTIS__128M            (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
5187 
#define WDTIS__8192K           (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
5188 
#define WDTIS__512K            (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
5189 
#define WDTIS__32K             (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
5190 
#define WDTIS__8192            (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
5191 
#define WDTIS__512             (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
5192 
#define WDTIS__64              (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
5193 
 
5194 
#define WDTSSEL_0              (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
5195 
#define WDTSSEL_1              (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
5196 
#define WDTSSEL_2              (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
5197 
#define WDTSSEL_3              (3*0x0020u)    /* WDT - Timer Clock Source Select: reserved */
5198 
#define WDTSSEL__SMCLK         (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
5199 
#define WDTSSEL__ACLK          (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
5200 
#define WDTSSEL__VLO           (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
5201 
 
5202 
/* WDT-interval times [1ms] coded with Bits 0-2 */
5203 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
5204 
#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2)                         /* 32ms interval (default) */
5205 
#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0)                  /* 8ms     " */
5206 
#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1)                  /* 0.5ms   " */
5207 
#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)           /* 0.064ms " */
5208 
/* WDT is clocked by fACLK (assumed 32KHz) */
5209 
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)                /* 1000ms  " */
5210 
#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0)         /* 250ms   " */
5211 
#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1)         /* 16ms    " */
5212 
#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0)  /* 1.9ms   " */
5213 
/* Watchdog mode -> reset after expired time */
5214 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
5215 
#define WDT_MRST_32         (WDTPW+WDTCNTCL+WDTIS2)                                  /* 32ms interval (default) */
5216 
#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS2+WDTIS0)                           /* 8ms     " */
5217 
#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS2+WDTIS1)                           /* 0.5ms   " */
5218 
#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)                    /* 0.064ms " */
5219 
/* WDT is clocked by fACLK (assumed 32KHz) */
5220 
#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2)                         /* 1000ms  " */
5221 
#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0)                  /* 250ms   " */
5222 
#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1)                  /* 16ms    " */
5223 
#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0)           /* 1.9ms   " */
5224 
 
5225 
 
5226 
/************************************************************
5227 
* TLV Descriptors
5228 
************************************************************/
5229 
#define __MSP430_HAS_TLV__                    /* Definition to show that Module is available */
5230 
 
5231 
#define TLV_START              (0x1A08)       /* Start Address of the TLV structure */
5232 
#define TLV_END                (0x1AFF)       /* End Address of the TLV structure */
5233 
 
5234 
#define TLV_LDTAG              (0x01)         /*  Legacy descriptor (1xx, 2xx, 4xx families) */
5235 
#define TLV_PDTAG              (0x02)         /*  Peripheral discovery descriptor */
5236 
#define TLV_Reserved3          (0x03)         /*  Future usage */
5237 
#define TLV_Reserved4          (0x04)         /*  Future usage */
5238 
#define TLV_BLANK              (0x05)         /*  Blank descriptor */
5239 
#define TLV_Reserved6          (0x06)         /*  Future usage */
5240 
#define TLV_Reserved7          (0x07)         /*  Serial Number */
5241 
#define TLV_DIERECORD          (0x08)         /*  Die Record  */
5242 
#define TLV_ADCCAL             (0x11)         /*  ADC12 calibration */
5243 
#define TLV_ADC12CAL           (0x11)         /*  ADC12 calibration */
5244 
#define TLV_ADC10CAL           (0x13)         /*  ADC10 calibration */
5245 
#define TLV_REFCAL             (0x12)         /*  REF calibration */
5246 
#define TLV_TAGEXT             (0xFE)         /*  Tag extender */
5247 
#define TLV_TAGEND             (0xFF)         //  Tag End of Table
5248 
 
5249 
/************************************************************
5250 
* Interrupt Vectors (offset from 0xFF80)
5251 
************************************************************/
5252 
 
5253 
#pragma diag_suppress 1107
5254 
#define VECTOR_NAME(name)             name##_ptr
5255 
#define EMIT_PRAGMA(x)                _Pragma(#x)
5256 
#define CREATE_VECTOR(name)           void * const VECTOR_NAME(name) = (void *)(long)&name
5257 
#define PLACE_VECTOR(vector,section)  EMIT_PRAGMA(DATA_SECTION(vector,section))
5258 
#define PLACE_INTERRUPT(func)         EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
5259 
#define ISR_VECTOR(func,offset)       CREATE_VECTOR(func); \
5260 
                                      PLACE_VECTOR(VECTOR_NAME(func), offset) \
5261 
                                      PLACE_INTERRUPT(func)
5262 
 
5263 
 
5264 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5265 
#define PORT4_VECTOR            ".int37"                    /* 0xFFCA Port 4 */
5266 
#else
5267 
#define PORT4_VECTOR            (37 * 1u)                    /* 0xFFCA Port 4 */
5268 
/*#define PORT4_ISR(func)         ISR_VECTOR(func, ".int37")  */ /* 0xFFCA Port 4 */ /* CCE V2 Style */
5269 
#endif
5270 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5271 
#define PORT3_VECTOR            ".int38"                    /* 0xFFCC Port 3 */
5272 
#else
5273 
#define PORT3_VECTOR            (38 * 1u)                    /* 0xFFCC Port 3 */
5274 
/*#define PORT3_ISR(func)         ISR_VECTOR(func, ".int38")  */ /* 0xFFCC Port 3 */ /* CCE V2 Style */
5275 
#endif
5276 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5277 
#define TIMER2_A1_VECTOR        ".int39"                    /* 0xFFCE Timer0_A5 CC1-4, TA */
5278 
#else
5279 
#define TIMER2_A1_VECTOR        (39 * 1u)                    /* 0xFFCE Timer0_A5 CC1-4, TA */
5280 
/*#define TIMER2_A1_ISR(func)     ISR_VECTOR(func, ".int39")  */ /* 0xFFCE Timer0_A5 CC1-4, TA */ /* CCE V2 Style */
5281 
#endif
5282 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5283 
#define TIMER2_A0_VECTOR        ".int40"                    /* 0xFFD0 Timer0_A5 CC0 */
5284 
#else
5285 
#define TIMER2_A0_VECTOR        (40 * 1u)                    /* 0xFFD0 Timer0_A5 CC0 */
5286 
/*#define TIMER2_A0_ISR(func)     ISR_VECTOR(func, ".int40")  */ /* 0xFFD0 Timer0_A5 CC0 */ /* CCE V2 Style */
5287 
#endif
5288 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5289 
#define DAC12_VECTOR            ".int41"                    /* 0xFFD3 DAC12 */
5290 
#else
5291 
#define DAC12_VECTOR            (41 * 1u)                    /* 0xFFD3 DAC12 */
5292 
/*#define DAC12_ISR(func)         ISR_VECTOR(func, ".int41")  */ /* 0xFFD3 DAC12 */ /* CCE V2 Style */
5293 
#endif
5294 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5295 
#define RTC_VECTOR              ".int42"                    /* 0xFFD4 RTC */
5296 
#else
5297 
#define RTC_VECTOR              (42 * 1u)                    /* 0xFFD4 RTC */
5298 
/*#define RTC_ISR(func)           ISR_VECTOR(func, ".int42")  */ /* 0xFFD4 RTC */ /* CCE V2 Style */
5299 
#endif
5300 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5301 
#define PORT2_VECTOR            ".int44"                    /* 0xFFD8 Port 2 */
5302 
#else
5303 
#define PORT2_VECTOR            (44 * 1u)                    /* 0xFFD8 Port 2 */
5304 
/*#define PORT2_ISR(func)         ISR_VECTOR(func, ".int44")  */ /* 0xFFD8 Port 2 */ /* CCE V2 Style */
5305 
#endif
5306 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5307 
#define USCI_B1_VECTOR          ".int45"                    /* 0xFFDA USCI B1 Receive/Transmit */
5308 
#else
5309 
#define USCI_B1_VECTOR          (45 * 1u)                    /* 0xFFDA USCI B1 Receive/Transmit */
5310 
/*#define USCI_B1_ISR(func)       ISR_VECTOR(func, ".int45")  */ /* 0xFFDA USCI B1 Receive/Transmit */ /* CCE V2 Style */
5311 
#endif
5312 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5313 
#define USCI_A1_VECTOR          ".int46"                    /* 0xFFDC USCI A1 Receive/Transmit */
5314 
#else
5315 
#define USCI_A1_VECTOR          (46 * 1u)                    /* 0xFFDC USCI A1 Receive/Transmit */
5316 
/*#define USCI_A1_ISR(func)       ISR_VECTOR(func, ".int46")  */ /* 0xFFDC USCI A1 Receive/Transmit */ /* CCE V2 Style */
5317 
#endif
5318 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5319 
#define PORT1_VECTOR            ".int47"                    /* 0xFFDE Port 1 */
5320 
#else
5321 
#define PORT1_VECTOR            (47 * 1u)                    /* 0xFFDE Port 1 */
5322 
/*#define PORT1_ISR(func)         ISR_VECTOR(func, ".int47")  */ /* 0xFFDE Port 1 */ /* CCE V2 Style */
5323 
#endif
5324 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5325 
#define TIMER1_A1_VECTOR        ".int48"                    /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
5326 
#else
5327 
#define TIMER1_A1_VECTOR        (48 * 1u)                    /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
5328 
/*#define TIMER1_A1_ISR(func)     ISR_VECTOR(func, ".int48")  */ /* 0xFFE0 Timer1_A3 CC1-2, TA1 */ /* CCE V2 Style */
5329 
#endif
5330 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5331 
#define TIMER1_A0_VECTOR        ".int49"                    /* 0xFFE2 Timer1_A3 CC0 */
5332 
#else
5333 
#define TIMER1_A0_VECTOR        (49 * 1u)                    /* 0xFFE2 Timer1_A3 CC0 */
5334 
/*#define TIMER1_A0_ISR(func)     ISR_VECTOR(func, ".int49")  */ /* 0xFFE2 Timer1_A3 CC0 */ /* CCE V2 Style */
5335 
#endif
5336 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5337 
#define DMA_VECTOR              ".int50"                    /* 0xFFE4 DMA */
5338 
#else
5339 
#define DMA_VECTOR              (50 * 1u)                    /* 0xFFE4 DMA */
5340 
/*#define DMA_ISR(func)           ISR_VECTOR(func, ".int50")  */ /* 0xFFE4 DMA */ /* CCE V2 Style */
5341 
#endif
5342 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5343 
#define USB_UBM_VECTOR          ".int51"                    /* 0xFFE6 USB Timer / cable event / USB reset */
5344 
#else
5345 
#define USB_UBM_VECTOR          (51 * 1u)                    /* 0xFFE6 USB Timer / cable event / USB reset */
5346 
/*#define USB_UBM_ISR(func)       ISR_VECTOR(func, ".int51")  */ /* 0xFFE6 USB Timer / cable event / USB reset */ /* CCE V2 Style */
5347 
#endif
5348 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5349 
#define TIMER0_A1_VECTOR        ".int52"                    /* 0xFFE8 Timer0_A5 CC1-4, TA */
5350 
#else
5351 
#define TIMER0_A1_VECTOR        (52 * 1u)                    /* 0xFFE8 Timer0_A5 CC1-4, TA */
5352 
/*#define TIMER0_A1_ISR(func)     ISR_VECTOR(func, ".int52")  */ /* 0xFFE8 Timer0_A5 CC1-4, TA */ /* CCE V2 Style */
5353 
#endif
5354 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5355 
#define TIMER0_A0_VECTOR        ".int53"                    /* 0xFFEA Timer0_A5 CC0 */
5356 
#else
5357 
#define TIMER0_A0_VECTOR        (53 * 1u)                    /* 0xFFEA Timer0_A5 CC0 */
5358 
/*#define TIMER0_A0_ISR(func)     ISR_VECTOR(func, ".int53")  */ /* 0xFFEA Timer0_A5 CC0 */ /* CCE V2 Style */
5359 
#endif
5360 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5361 
#define ADC12_VECTOR            ".int54"                    /* 0xFFEC ADC */
5362 
#else
5363 
#define ADC12_VECTOR            (54 * 1u)                    /* 0xFFEC ADC */
5364 
/*#define ADC12_ISR(func)         ISR_VECTOR(func, ".int54")  */ /* 0xFFEC ADC */ /* CCE V2 Style */
5365 
#endif
5366 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5367 
#define USCI_B0_VECTOR          ".int55"                    /* 0xFFEE USCI B0 Receive/Transmit */
5368 
#else
5369 
#define USCI_B0_VECTOR          (55 * 1u)                    /* 0xFFEE USCI B0 Receive/Transmit */
5370 
/*#define USCI_B0_ISR(func)       ISR_VECTOR(func, ".int55")  */ /* 0xFFEE USCI B0 Receive/Transmit */ /* CCE V2 Style */
5371 
#endif
5372 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5373 
#define USCI_A0_VECTOR          ".int56"                    /* 0xFFF0 USCI A0 Receive/Transmit */
5374 
#else
5375 
#define USCI_A0_VECTOR          (56 * 1u)                    /* 0xFFF0 USCI A0 Receive/Transmit */
5376 
/*#define USCI_A0_ISR(func)       ISR_VECTOR(func, ".int56")  */ /* 0xFFF0 USCI A0 Receive/Transmit */ /* CCE V2 Style */
5377 
#endif
5378 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5379 
#define WDT_VECTOR              ".int57"                    /* 0xFFF2 Watchdog Timer */
5380 
#else
5381 
#define WDT_VECTOR              (57 * 1u)                    /* 0xFFF2 Watchdog Timer */
5382 
/*#define WDT_ISR(func)           ISR_VECTOR(func, ".int57")  */ /* 0xFFF2 Watchdog Timer */ /* CCE V2 Style */
5383 
#endif
5384 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5385 
#define TIMER0_B1_VECTOR        ".int58"                    /* 0xFFF4 Timer0_B7 CC1-6, TB */
5386 
#else
5387 
#define TIMER0_B1_VECTOR        (58 * 1u)                    /* 0xFFF4 Timer0_B7 CC1-6, TB */
5388 
/*#define TIMER0_B1_ISR(func)     ISR_VECTOR(func, ".int58")  */ /* 0xFFF4 Timer0_B7 CC1-6, TB */ /* CCE V2 Style */
5389 
#endif
5390 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5391 
#define TIMER0_B0_VECTOR        ".int59"                    /* 0xFFF6 Timer0_B7 CC0 */
5392 
#else
5393 
#define TIMER0_B0_VECTOR        (59 * 1u)                    /* 0xFFF6 Timer0_B7 CC0 */
5394 
/*#define TIMER0_B0_ISR(func)     ISR_VECTOR(func, ".int59")  */ /* 0xFFF6 Timer0_B7 CC0 */ /* CCE V2 Style */
5395 
#endif
5396 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5397 
#define COMP_B_VECTOR           ".int60"                    /* 0xFFF8 Comparator B */
5398 
#else
5399 
#define COMP_B_VECTOR           (60 * 1u)                    /* 0xFFF8 Comparator B */
5400 
/*#define COMP_B_ISR(func)        ISR_VECTOR(func, ".int60")  */ /* 0xFFF8 Comparator B */ /* CCE V2 Style */
5401 
#endif
5402 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5403 
#define UNMI_VECTOR             ".int61"                    /* 0xFFFA User Non-maskable */
5404 
#else
5405 
#define UNMI_VECTOR             (61 * 1u)                    /* 0xFFFA User Non-maskable */
5406 
/*#define UNMI_ISR(func)          ISR_VECTOR(func, ".int61")  */ /* 0xFFFA User Non-maskable */ /* CCE V2 Style */
5407 
#endif
5408 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5409 
#define SYSNMI_VECTOR           ".int62"                    /* 0xFFFC System Non-maskable */
5410 
#else
5411 
#define SYSNMI_VECTOR           (62 * 1u)                    /* 0xFFFC System Non-maskable */
5412 
/*#define SYSNMI_ISR(func)        ISR_VECTOR(func, ".int62")  */ /* 0xFFFC System Non-maskable */ /* CCE V2 Style */
5413 
#endif
5414 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
5415 
#define RESET_VECTOR            ".reset"                    /* 0xFFFE Reset [Highest Priority] */
5416 
#else
5417 
#define RESET_VECTOR            (63 * 1u)                    /* 0xFFFE Reset [Highest Priority] */
5418 
/*#define RESET_ISR(func)         ISR_VECTOR(func, ".int63")  */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
5419 
#endif
5420 
 
5421 
/************************************************************
5422 
* End of Modules
5423 
************************************************************/
5424 
 
5425 
#ifdef __cplusplus
5426 
}
5427 
#endif /* extern "C" */
5428 
 
5429 
#endif /* #ifndef __MSP430F5637 */
5430