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2850 dpurdie 1 
/********************************************************************
2 
*
3 
* Standard register and bit definitions for the Texas Instruments
4 
* MSP430 microcontroller.
5 
*
6 
* This file supports assembler and C development for
7 
* MSP430F5632 devices.
8 
*
9 
* Texas Instruments, Version 1.2
10 
*
11 
* Rev. 1.0, Setup
12 
* Rev. 1.1  Changed access type of TimerA/B registers to word only
13 
* Rev. 1.2  Fixed definition of RTCTEV__0000 and RTCTEV__1200
14 
*           Removed not availabe bits RTCMODE and RTCSSELx
15 
*
16 
*
17 
********************************************************************/
18 
 
19 
#ifndef __MSP430F5632
20 
#define __MSP430F5632
21 
 
22 
#ifdef __cplusplus
23 
extern "C" {
24 
#endif
25 
 
26 
 
27 
/*----------------------------------------------------------------------------*/
28 
/* PERIPHERAL FILE MAP                                                        */
29 
/*----------------------------------------------------------------------------*/
30 
 
31 
/* External references resolved by a device-specific linker command file */
32 
#define SFR_8BIT(address)   extern volatile unsigned char address
33 
#define SFR_16BIT(address)  extern volatile unsigned int address
34 
//#define SFR_20BIT(address)  extern volatile unsigned int address
35 
typedef void (* __SFR_FARPTR)();
36 
#define SFR_20BIT(address) extern __SFR_FARPTR address
37 
#define SFR_32BIT(address)  extern volatile unsigned long address
38 
 
39 
 
40 
 
41 
/************************************************************
42 
* STANDARD BITS
43 
************************************************************/
44 
 
45 
#define BIT0                   (0x0001)
46 
#define BIT1                   (0x0002)
47 
#define BIT2                   (0x0004)
48 
#define BIT3                   (0x0008)
49 
#define BIT4                   (0x0010)
50 
#define BIT5                   (0x0020)
51 
#define BIT6                   (0x0040)
52 
#define BIT7                   (0x0080)
53 
#define BIT8                   (0x0100)
54 
#define BIT9                   (0x0200)
55 
#define BITA                   (0x0400)
56 
#define BITB                   (0x0800)
57 
#define BITC                   (0x1000)
58 
#define BITD                   (0x2000)
59 
#define BITE                   (0x4000)
60 
#define BITF                   (0x8000)
61 
 
62 
/************************************************************
63 
* STATUS REGISTER BITS
64 
************************************************************/
65 
 
66 
#define C                      (0x0001)
67 
#define Z                      (0x0002)
68 
#define N                      (0x0004)
69 
#define V                      (0x0100)
70 
#define GIE                    (0x0008)
71 
#define CPUOFF                 (0x0010)
72 
#define OSCOFF                 (0x0020)
73 
#define SCG0                   (0x0040)
74 
#define SCG1                   (0x0080)
75 
 
76 
/* Low Power Modes coded with Bits 4-7 in SR */
77 
 
78 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
79 
#define LPM0                   (CPUOFF)
80 
#define LPM1                   (SCG0+CPUOFF)
81 
#define LPM2                   (SCG1+CPUOFF)
82 
#define LPM3                   (SCG1+SCG0+CPUOFF)
83 
#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
84 
/* End #defines for assembler */
85 
 
86 
#else /* Begin #defines for C */
87 
#define LPM0_bits              (CPUOFF)
88 
#define LPM1_bits              (SCG0+CPUOFF)
89 
#define LPM2_bits              (SCG1+CPUOFF)
90 
#define LPM3_bits              (SCG1+SCG0+CPUOFF)
91 
#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
92 
 
93 
#include "in430.h"
94 
 
95 
#define LPM0         _bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
96 
#define LPM0_EXIT    _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
97 
#define LPM1         _bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
98 
#define LPM1_EXIT    _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
99 
#define LPM2         _bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
100 
#define LPM2_EXIT    _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
101 
#define LPM3         _bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
102 
#define LPM3_EXIT    _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
103 
#define LPM4         _bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
104 
#define LPM4_EXIT    _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
105 
#endif /* End #defines for C */
106 
 
107 
/************************************************************
108 
* CPU
109 
************************************************************/
110 
#define __MSP430_HAS_MSP430XV2_CPU__                /* Definition to show that it has MSP430XV2 CPU */
111 
 
112 
/************************************************************
113 
* PERIPHERAL FILE MAP
114 
************************************************************/
115 
 
116 
/*************************************************************
117 
* Backup RAM Module
118 
*************************************************************/
119 
#define __MSP430_HAS_BACKUP_RAM__                /* Definition to show that Module is available */
120 
#define __MSP430_BASEADDRESS_BACKUP_RAM__ 0x0480
121 
 
122 
SFR_16BIT(BAKMEM0);                           /* Battery Backup Memory 0 */
123 
SFR_8BIT(BAKMEM0_L);                          /* Battery Backup Memory 0 */
124 
SFR_8BIT(BAKMEM0_H);                          /* Battery Backup Memory 0 */
125 
SFR_16BIT(BAKMEM1);                           /* Battery Backup Memory 0 */
126 
SFR_8BIT(BAKMEM1_L);                          /* Battery Backup Memory 0 */
127 
SFR_8BIT(BAKMEM1_H);                          /* Battery Backup Memory 0 */
128 
SFR_16BIT(BAKMEM2);                           /* Battery Backup Memory 0 */
129 
SFR_8BIT(BAKMEM2_L);                          /* Battery Backup Memory 0 */
130 
SFR_8BIT(BAKMEM2_H);                          /* Battery Backup Memory 0 */
131 
SFR_16BIT(BAKMEM3);                           /* Battery Backup Memory 0 */
132 
SFR_8BIT(BAKMEM3_L);                          /* Battery Backup Memory 0 */
133 
SFR_8BIT(BAKMEM3_H);                          /* Battery Backup Memory 0 */
134 
 
135 
/*************************************************************
136 
* Battery Charger Module
137 
*************************************************************/
138 
#define __MSP430_HAS_BATTERY_CHARGER__                /* Definition to show that Module is available */
139 
#define __MSP430_BASEADDRESS_BATTERY_CHARGER__ 0x049C
140 
 
141 
SFR_16BIT(BAKCTL);                            /* Battery Backup Control */
142 
SFR_8BIT(BAKCTL_L);                           /* Battery Backup Control */
143 
SFR_8BIT(BAKCTL_H);                           /* Battery Backup Control */
144 
SFR_16BIT(BAKCHCTL);                          /* Battery Charger Control */
145 
SFR_8BIT(BAKCHCTL_L);                         /* Battery Charger Control */
146 
SFR_8BIT(BAKCHCTL_H);                         /* Battery Charger Control */
147 
 
148 
/* BAKCTL Control Bits */
149 
#define LOCKBAK                (0x0001)       /* Lock backup sub-system */
150 
#define BAKSW                  (0x0002)       /* Manual switch to battery backup supply */
151 
#define BAKADC                 (0x0004)       /* Battery backup supply to ADC. */
152 
#define BAKDIS                 (0x0008)       /* Disable backup supply switching. */
153 
 
154 
/* BAKCTL Control Bits */
155 
#define LOCKBAK_L              (0x0001)       /* Lock backup sub-system */
156 
#define BAKSW_L                (0x0002)       /* Manual switch to battery backup supply */
157 
#define BAKADC_L               (0x0004)       /* Battery backup supply to ADC. */
158 
#define BAKDIS_L               (0x0008)       /* Disable backup supply switching. */
159 
 
160 
/* BAKCTL Control Bits */
161 
 
162 
/* BAKCHCTL Control Bits */
163 
#define CHEN                   (0x0001)       /* Charger enable */
164 
#define CHC0                   (0x0002)       /* Charger charge current Bit 0 */
165 
#define CHC1                   (0x0004)       /* Charger charge current Bit 1 */
166 
#define CHV0                   (0x0010)       /* Charger end voltage Bit 0 */
167 
#define CHV1                   (0x0020)       /* Charger end voltage Bit 1 */
168 
 
169 
/* BAKCHCTL Control Bits */
170 
#define CHEN_L                 (0x0001)       /* Charger enable */
171 
#define CHC0_L                 (0x0002)       /* Charger charge current Bit 0 */
172 
#define CHC1_L                 (0x0004)       /* Charger charge current Bit 1 */
173 
#define CHV0_L                 (0x0010)       /* Charger end voltage Bit 0 */
174 
#define CHV1_L                 (0x0020)       /* Charger end voltage Bit 1 */
175 
 
176 
/* BAKCHCTL Control Bits */
177 
 
178 
#define CHPWD                  (0x6900)       /* Charger write password. */
179 
 
180 
/************************************************************
181 
* Comparator B
182 
************************************************************/
183 
#define __MSP430_HAS_COMPB__                  /* Definition to show that Module is available */
184 
#define __MSP430_BASEADDRESS_COMPB__ 0x08C0
185 
 
186 
SFR_16BIT(CBCTL0);                            /* Comparator B Control Register 0 */
187 
SFR_8BIT(CBCTL0_L);                           /* Comparator B Control Register 0 */
188 
SFR_8BIT(CBCTL0_H);                           /* Comparator B Control Register 0 */
189 
SFR_16BIT(CBCTL1);                            /* Comparator B Control Register 1 */
190 
SFR_8BIT(CBCTL1_L);                           /* Comparator B Control Register 1 */
191 
SFR_8BIT(CBCTL1_H);                           /* Comparator B Control Register 1 */
192 
SFR_16BIT(CBCTL2);                            /* Comparator B Control Register 2 */
193 
SFR_8BIT(CBCTL2_L);                           /* Comparator B Control Register 2 */
194 
SFR_8BIT(CBCTL2_H);                           /* Comparator B Control Register 2 */
195 
SFR_16BIT(CBCTL3);                            /* Comparator B Control Register 3 */
196 
SFR_8BIT(CBCTL3_L);                           /* Comparator B Control Register 3 */
197 
SFR_8BIT(CBCTL3_H);                           /* Comparator B Control Register 3 */
198 
SFR_16BIT(CBINT);                             /* Comparator B Interrupt Register */
199 
SFR_8BIT(CBINT_L);                            /* Comparator B Interrupt Register */
200 
SFR_8BIT(CBINT_H);                            /* Comparator B Interrupt Register */
201 
SFR_16BIT(CBIV);                              /* Comparator B Interrupt Vector Word */
202 
 
203 
/* CBCTL0 Control Bits */
204 
#define CBIPSEL0               (0x0001)       /* Comp. B Pos. Channel Input Select 0 */
205 
#define CBIPSEL1               (0x0002)       /* Comp. B Pos. Channel Input Select 1 */
206 
#define CBIPSEL2               (0x0004)       /* Comp. B Pos. Channel Input Select 2 */
207 
#define CBIPSEL3               (0x0008)       /* Comp. B Pos. Channel Input Select 3 */
208 
//#define RESERVED            (0x0010)  /* Comp. B */
209 
//#define RESERVED            (0x0020)  /* Comp. B */
210 
//#define RESERVED            (0x0040)  /* Comp. B */
211 
#define CBIPEN                 (0x0080)       /* Comp. B Pos. Channel Input Enable */
212 
#define CBIMSEL0               (0x0100)       /* Comp. B Neg. Channel Input Select 0 */
213 
#define CBIMSEL1               (0x0200)       /* Comp. B Neg. Channel Input Select 1 */
214 
#define CBIMSEL2               (0x0400)       /* Comp. B Neg. Channel Input Select 2 */
215 
#define CBIMSEL3               (0x0800)       /* Comp. B Neg. Channel Input Select 3 */
216 
//#define RESERVED            (0x1000)  /* Comp. B */
217 
//#define RESERVED            (0x2000)  /* Comp. B */
218 
//#define RESERVED            (0x4000)  /* Comp. B */
219 
#define CBIMEN                 (0x8000)       /* Comp. B Neg. Channel Input Enable */
220 
 
221 
/* CBCTL0 Control Bits */
222 
#define CBIPSEL0_L             (0x0001)       /* Comp. B Pos. Channel Input Select 0 */
223 
#define CBIPSEL1_L             (0x0002)       /* Comp. B Pos. Channel Input Select 1 */
224 
#define CBIPSEL2_L             (0x0004)       /* Comp. B Pos. Channel Input Select 2 */
225 
#define CBIPSEL3_L             (0x0008)       /* Comp. B Pos. Channel Input Select 3 */
226 
//#define RESERVED            (0x0010)  /* Comp. B */
227 
//#define RESERVED            (0x0020)  /* Comp. B */
228 
//#define RESERVED            (0x0040)  /* Comp. B */
229 
#define CBIPEN_L               (0x0080)       /* Comp. B Pos. Channel Input Enable */
230 
//#define RESERVED            (0x1000)  /* Comp. B */
231 
//#define RESERVED            (0x2000)  /* Comp. B */
232 
//#define RESERVED            (0x4000)  /* Comp. B */
233 
 
234 
/* CBCTL0 Control Bits */
235 
//#define RESERVED            (0x0010)  /* Comp. B */
236 
//#define RESERVED            (0x0020)  /* Comp. B */
237 
//#define RESERVED            (0x0040)  /* Comp. B */
238 
#define CBIMSEL0_H             (0x0001)       /* Comp. B Neg. Channel Input Select 0 */
239 
#define CBIMSEL1_H             (0x0002)       /* Comp. B Neg. Channel Input Select 1 */
240 
#define CBIMSEL2_H             (0x0004)       /* Comp. B Neg. Channel Input Select 2 */
241 
#define CBIMSEL3_H             (0x0008)       /* Comp. B Neg. Channel Input Select 3 */
242 
//#define RESERVED            (0x1000)  /* Comp. B */
243 
//#define RESERVED            (0x2000)  /* Comp. B */
244 
//#define RESERVED            (0x4000)  /* Comp. B */
245 
#define CBIMEN_H               (0x0080)       /* Comp. B Neg. Channel Input Enable */
246 
 
247 
#define CBIPSEL_0              (0x0000)       /* Comp. B V+ terminal Input Select: Channel 0 */
248 
#define CBIPSEL_1              (0x0001)       /* Comp. B V+ terminal Input Select: Channel 1 */
249 
#define CBIPSEL_2              (0x0002)       /* Comp. B V+ terminal Input Select: Channel 2 */
250 
#define CBIPSEL_3              (0x0003)       /* Comp. B V+ terminal Input Select: Channel 3 */
251 
#define CBIPSEL_4              (0x0004)       /* Comp. B V+ terminal Input Select: Channel 4 */
252 
#define CBIPSEL_5              (0x0005)       /* Comp. B V+ terminal Input Select: Channel 5 */
253 
#define CBIPSEL_6              (0x0006)       /* Comp. B V+ terminal Input Select: Channel 6 */
254 
#define CBIPSEL_7              (0x0007)       /* Comp. B V+ terminal Input Select: Channel 7 */
255 
#define CBIPSEL_8              (0x0008)       /* Comp. B V+ terminal Input Select: Channel 8 */
256 
#define CBIPSEL_9              (0x0009)       /* Comp. B V+ terminal Input Select: Channel 9 */
257 
#define CBIPSEL_10             (0x000A)       /* Comp. B V+ terminal Input Select: Channel 10 */
258 
#define CBIPSEL_11             (0x000B)       /* Comp. B V+ terminal Input Select: Channel 11 */
259 
#define CBIPSEL_12             (0x000C)       /* Comp. B V+ terminal Input Select: Channel 12 */
260 
#define CBIPSEL_13             (0x000D)       /* Comp. B V+ terminal Input Select: Channel 13 */
261 
#define CBIPSEL_14             (0x000E)       /* Comp. B V+ terminal Input Select: Channel 14 */
262 
#define CBIPSEL_15             (0x000F)       /* Comp. B V+ terminal Input Select: Channel 15 */
263 
 
264 
#define CBIMSEL_0              (0x0000)       /* Comp. B V- Terminal Input Select: Channel 0 */
265 
#define CBIMSEL_1              (0x0100)       /* Comp. B V- Terminal Input Select: Channel 1 */
266 
#define CBIMSEL_2              (0x0200)       /* Comp. B V- Terminal Input Select: Channel 2 */
267 
#define CBIMSEL_3              (0x0300)       /* Comp. B V- Terminal Input Select: Channel 3 */
268 
#define CBIMSEL_4              (0x0400)       /* Comp. B V- Terminal Input Select: Channel 4 */
269 
#define CBIMSEL_5              (0x0500)       /* Comp. B V- Terminal Input Select: Channel 5 */
270 
#define CBIMSEL_6              (0x0600)       /* Comp. B V- Terminal Input Select: Channel 6 */
271 
#define CBIMSEL_7              (0x0700)       /* Comp. B V- Terminal Input Select: Channel 7 */
272 
#define CBIMSEL_8              (0x0800)       /* Comp. B V- terminal Input Select: Channel 8 */
273 
#define CBIMSEL_9              (0x0900)       /* Comp. B V- terminal Input Select: Channel 9 */
274 
#define CBIMSEL_10             (0x0A00)       /* Comp. B V- terminal Input Select: Channel 10 */
275 
#define CBIMSEL_11             (0x0B00)       /* Comp. B V- terminal Input Select: Channel 11 */
276 
#define CBIMSEL_12             (0x0C00)       /* Comp. B V- terminal Input Select: Channel 12 */
277 
#define CBIMSEL_13             (0x0D00)       /* Comp. B V- terminal Input Select: Channel 13 */
278 
#define CBIMSEL_14             (0x0E00)       /* Comp. B V- terminal Input Select: Channel 14 */
279 
#define CBIMSEL_15             (0x0F00)       /* Comp. B V- terminal Input Select: Channel 15 */
280 
 
281 
/* CBCTL1 Control Bits */
282 
#define CBOUT                  (0x0001)       /* Comp. B Output */
283 
#define CBOUTPOL               (0x0002)       /* Comp. B Output Polarity */
284 
#define CBF                    (0x0004)       /* Comp. B Enable Output Filter */
285 
#define CBIES                  (0x0008)       /* Comp. B Interrupt Edge Select */
286 
#define CBSHORT                (0x0010)       /* Comp. B Input Short */
287 
#define CBEX                   (0x0020)       /* Comp. B Exchange Inputs */
288 
#define CBFDLY0                (0x0040)       /* Comp. B Filter delay Bit 0 */
289 
#define CBFDLY1                (0x0080)       /* Comp. B Filter delay Bit 1 */
290 
#define CBPWRMD0               (0x0100)       /* Comp. B Power Mode Bit 0 */
291 
#define CBPWRMD1               (0x0200)       /* Comp. B Power Mode Bit 1 */
292 
#define CBON                   (0x0400)       /* Comp. B enable */
293 
#define CBMRVL                 (0x0800)       /* Comp. B CBMRV Level */
294 
#define CBMRVS                 (0x1000)       /* Comp. B Output selects between VREF0 or VREF1*/
295 
//#define RESERVED            (0x2000)  /* Comp. B */
296 
//#define RESERVED            (0x4000)  /* Comp. B */
297 
//#define RESERVED            (0x8000)  /* Comp. B */
298 
 
299 
/* CBCTL1 Control Bits */
300 
#define CBOUT_L                (0x0001)       /* Comp. B Output */
301 
#define CBOUTPOL_L             (0x0002)       /* Comp. B Output Polarity */
302 
#define CBF_L                  (0x0004)       /* Comp. B Enable Output Filter */
303 
#define CBIES_L                (0x0008)       /* Comp. B Interrupt Edge Select */
304 
#define CBSHORT_L              (0x0010)       /* Comp. B Input Short */
305 
#define CBEX_L                 (0x0020)       /* Comp. B Exchange Inputs */
306 
#define CBFDLY0_L              (0x0040)       /* Comp. B Filter delay Bit 0 */
307 
#define CBFDLY1_L              (0x0080)       /* Comp. B Filter delay Bit 1 */
308 
//#define RESERVED            (0x2000)  /* Comp. B */
309 
//#define RESERVED            (0x4000)  /* Comp. B */
310 
//#define RESERVED            (0x8000)  /* Comp. B */
311 
 
312 
/* CBCTL1 Control Bits */
313 
#define CBPWRMD0_H             (0x0001)       /* Comp. B Power Mode Bit 0 */
314 
#define CBPWRMD1_H             (0x0002)       /* Comp. B Power Mode Bit 1 */
315 
#define CBON_H                 (0x0004)       /* Comp. B enable */
316 
#define CBMRVL_H               (0x0008)       /* Comp. B CBMRV Level */
317 
#define CBMRVS_H               (0x0010)       /* Comp. B Output selects between VREF0 or VREF1*/
318 
//#define RESERVED            (0x2000)  /* Comp. B */
319 
//#define RESERVED            (0x4000)  /* Comp. B */
320 
//#define RESERVED            (0x8000)  /* Comp. B */
321 
 
322 
#define CBFDLY_0               (0x0000)       /* Comp. B Filter delay 0 : 450ns */
323 
#define CBFDLY_1               (0x0040)       /* Comp. B Filter delay 1 : 900ns */
324 
#define CBFDLY_2               (0x0080)       /* Comp. B Filter delay 2 : 1800ns */
325 
#define CBFDLY_3               (0x00C0)       /* Comp. B Filter delay 3 : 3600ns */
326 
 
327 
#define CBPWRMD_0              (0x0000)       /* Comp. B Power Mode 0 : High speed */
328 
#define CBPWRMD_1              (0x0100)       /* Comp. B Power Mode 1 : Normal */
329 
#define CBPWRMD_2              (0x0200)       /* Comp. B Power Mode 2 : Ultra-Low*/
330 
#define CBPWRMD_3              (0x0300)       /* Comp. B Power Mode 3 : Reserved */
331 
 
332 
/* CBCTL2 Control Bits */
333 
#define CBREF00                (0x0001)       /* Comp. B Reference 0 Resistor Select Bit : 0 */
334 
#define CBREF01                (0x0002)       /* Comp. B Reference 0 Resistor Select Bit : 1 */
335 
#define CBREF02                (0x0004)       /* Comp. B Reference 0 Resistor Select Bit : 2 */
336 
#define CBREF03                (0x0008)       /* Comp. B Reference 0 Resistor Select Bit : 3 */
337 
#define CBREF04                (0x0010)       /* Comp. B Reference 0 Resistor Select Bit : 4 */
338 
#define CBRSEL                 (0x0020)       /* Comp. B Reference select */
339 
#define CBRS0                  (0x0040)       /* Comp. B Reference Source Bit : 0 */
340 
#define CBRS1                  (0x0080)       /* Comp. B Reference Source Bit : 1 */
341 
#define CBREF10                (0x0100)       /* Comp. B Reference 1 Resistor Select Bit : 0 */
342 
#define CBREF11                (0x0200)       /* Comp. B Reference 1 Resistor Select Bit : 1 */
343 
#define CBREF12                (0x0400)       /* Comp. B Reference 1 Resistor Select Bit : 2 */
344 
#define CBREF13                (0x0800)       /* Comp. B Reference 1 Resistor Select Bit : 3 */
345 
#define CBREF14                (0x1000)       /* Comp. B Reference 1 Resistor Select Bit : 4 */
346 
#define CBREFL0                (0x2000)       /* Comp. B Reference voltage level Bit : 0 */
347 
#define CBREFL1                (0x4000)       /* Comp. B Reference voltage level Bit : 1 */
348 
#define CBREFACC               (0x8000)       /* Comp. B Reference Accuracy */
349 
 
350 
/* CBCTL2 Control Bits */
351 
#define CBREF00_L              (0x0001)       /* Comp. B Reference 0 Resistor Select Bit : 0 */
352 
#define CBREF01_L              (0x0002)       /* Comp. B Reference 0 Resistor Select Bit : 1 */
353 
#define CBREF02_L              (0x0004)       /* Comp. B Reference 0 Resistor Select Bit : 2 */
354 
#define CBREF03_L              (0x0008)       /* Comp. B Reference 0 Resistor Select Bit : 3 */
355 
#define CBREF04_L              (0x0010)       /* Comp. B Reference 0 Resistor Select Bit : 4 */
356 
#define CBRSEL_L               (0x0020)       /* Comp. B Reference select */
357 
#define CBRS0_L                (0x0040)       /* Comp. B Reference Source Bit : 0 */
358 
#define CBRS1_L                (0x0080)       /* Comp. B Reference Source Bit : 1 */
359 
 
360 
/* CBCTL2 Control Bits */
361 
#define CBREF10_H              (0x0001)       /* Comp. B Reference 1 Resistor Select Bit : 0 */
362 
#define CBREF11_H              (0x0002)       /* Comp. B Reference 1 Resistor Select Bit : 1 */
363 
#define CBREF12_H              (0x0004)       /* Comp. B Reference 1 Resistor Select Bit : 2 */
364 
#define CBREF13_H              (0x0008)       /* Comp. B Reference 1 Resistor Select Bit : 3 */
365 
#define CBREF14_H              (0x0010)       /* Comp. B Reference 1 Resistor Select Bit : 4 */
366 
#define CBREFL0_H              (0x0020)       /* Comp. B Reference voltage level Bit : 0 */
367 
#define CBREFL1_H              (0x0040)       /* Comp. B Reference voltage level Bit : 1 */
368 
#define CBREFACC_H             (0x0080)       /* Comp. B Reference Accuracy */
369 
 
370 
#define CBREF0_0               (0x0000)       /* Comp. B Int. Ref.0 Select 0 : 1/32 */
371 
#define CBREF0_1               (0x0001)       /* Comp. B Int. Ref.0 Select 1 : 2/32 */
372 
#define CBREF0_2               (0x0002)       /* Comp. B Int. Ref.0 Select 2 : 3/32 */
373 
#define CBREF0_3               (0x0003)       /* Comp. B Int. Ref.0 Select 3 : 4/32 */
374 
#define CBREF0_4               (0x0004)       /* Comp. B Int. Ref.0 Select 4 : 5/32 */
375 
#define CBREF0_5               (0x0005)       /* Comp. B Int. Ref.0 Select 5 : 6/32 */
376 
#define CBREF0_6               (0x0006)       /* Comp. B Int. Ref.0 Select 6 : 7/32 */
377 
#define CBREF0_7               (0x0007)       /* Comp. B Int. Ref.0 Select 7 : 8/32 */
378 
#define CBREF0_8               (0x0008)       /* Comp. B Int. Ref.0 Select 0 : 9/32 */
379 
#define CBREF0_9               (0x0009)       /* Comp. B Int. Ref.0 Select 1 : 10/32 */
380 
#define CBREF0_10              (0x000A)       /* Comp. B Int. Ref.0 Select 2 : 11/32 */
381 
#define CBREF0_11              (0x000B)       /* Comp. B Int. Ref.0 Select 3 : 12/32 */
382 
#define CBREF0_12              (0x000C)       /* Comp. B Int. Ref.0 Select 4 : 13/32 */
383 
#define CBREF0_13              (0x000D)       /* Comp. B Int. Ref.0 Select 5 : 14/32 */
384 
#define CBREF0_14              (0x000E)       /* Comp. B Int. Ref.0 Select 6 : 15/32 */
385 
#define CBREF0_15              (0x000F)       /* Comp. B Int. Ref.0 Select 7 : 16/32 */
386 
#define CBREF0_16              (0x0010)       /* Comp. B Int. Ref.0 Select 0 : 17/32 */
387 
#define CBREF0_17              (0x0011)       /* Comp. B Int. Ref.0 Select 1 : 18/32 */
388 
#define CBREF0_18              (0x0012)       /* Comp. B Int. Ref.0 Select 2 : 19/32 */
389 
#define CBREF0_19              (0x0013)       /* Comp. B Int. Ref.0 Select 3 : 20/32 */
390 
#define CBREF0_20              (0x0014)       /* Comp. B Int. Ref.0 Select 4 : 21/32 */
391 
#define CBREF0_21              (0x0015)       /* Comp. B Int. Ref.0 Select 5 : 22/32 */
392 
#define CBREF0_22              (0x0016)       /* Comp. B Int. Ref.0 Select 6 : 23/32 */
393 
#define CBREF0_23              (0x0017)       /* Comp. B Int. Ref.0 Select 7 : 24/32 */
394 
#define CBREF0_24              (0x0018)       /* Comp. B Int. Ref.0 Select 0 : 25/32 */
395 
#define CBREF0_25              (0x0019)       /* Comp. B Int. Ref.0 Select 1 : 26/32 */
396 
#define CBREF0_26              (0x001A)       /* Comp. B Int. Ref.0 Select 2 : 27/32 */
397 
#define CBREF0_27              (0x001B)       /* Comp. B Int. Ref.0 Select 3 : 28/32 */
398 
#define CBREF0_28              (0x001C)       /* Comp. B Int. Ref.0 Select 4 : 29/32 */
399 
#define CBREF0_29              (0x001D)       /* Comp. B Int. Ref.0 Select 5 : 30/32 */
400 
#define CBREF0_30              (0x001E)       /* Comp. B Int. Ref.0 Select 6 : 31/32 */
401 
#define CBREF0_31              (0x001F)       /* Comp. B Int. Ref.0 Select 7 : 32/32 */
402 
 
403 
#define CBRS_0                 (0x0000)       /* Comp. B Reference Source 0 : Off */
404 
#define CBRS_1                 (0x0040)       /* Comp. B Reference Source 1 : Vcc */
405 
#define CBRS_2                 (0x0080)       /* Comp. B Reference Source 2 : Shared Ref. */
406 
#define CBRS_3                 (0x00C0)       /* Comp. B Reference Source 3 : Shared Ref. / Off */
407 
 
408 
#define CBREF1_0               (0x0000)       /* Comp. B Int. Ref.1 Select 0 : 1/32 */
409 
#define CBREF1_1               (0x0100)       /* Comp. B Int. Ref.1 Select 1 : 2/32 */
410 
#define CBREF1_2               (0x0200)       /* Comp. B Int. Ref.1 Select 2 : 3/32 */
411 
#define CBREF1_3               (0x0300)       /* Comp. B Int. Ref.1 Select 3 : 4/32 */
412 
#define CBREF1_4               (0x0400)       /* Comp. B Int. Ref.1 Select 4 : 5/32 */
413 
#define CBREF1_5               (0x0500)       /* Comp. B Int. Ref.1 Select 5 : 6/32 */
414 
#define CBREF1_6               (0x0600)       /* Comp. B Int. Ref.1 Select 6 : 7/32 */
415 
#define CBREF1_7               (0x0700)       /* Comp. B Int. Ref.1 Select 7 : 8/32 */
416 
#define CBREF1_8               (0x0800)       /* Comp. B Int. Ref.1 Select 0 : 9/32 */
417 
#define CBREF1_9               (0x0900)       /* Comp. B Int. Ref.1 Select 1 : 10/32 */
418 
#define CBREF1_10              (0x0A00)       /* Comp. B Int. Ref.1 Select 2 : 11/32 */
419 
#define CBREF1_11              (0x0B00)       /* Comp. B Int. Ref.1 Select 3 : 12/32 */
420 
#define CBREF1_12              (0x0C00)       /* Comp. B Int. Ref.1 Select 4 : 13/32 */
421 
#define CBREF1_13              (0x0D00)       /* Comp. B Int. Ref.1 Select 5 : 14/32 */
422 
#define CBREF1_14              (0x0E00)       /* Comp. B Int. Ref.1 Select 6 : 15/32 */
423 
#define CBREF1_15              (0x0F00)       /* Comp. B Int. Ref.1 Select 7 : 16/32 */
424 
#define CBREF1_16              (0x1000)       /* Comp. B Int. Ref.1 Select 0 : 17/32 */
425 
#define CBREF1_17              (0x1100)       /* Comp. B Int. Ref.1 Select 1 : 18/32 */
426 
#define CBREF1_18              (0x1200)       /* Comp. B Int. Ref.1 Select 2 : 19/32 */
427 
#define CBREF1_19              (0x1300)       /* Comp. B Int. Ref.1 Select 3 : 20/32 */
428 
#define CBREF1_20              (0x1400)       /* Comp. B Int. Ref.1 Select 4 : 21/32 */
429 
#define CBREF1_21              (0x1500)       /* Comp. B Int. Ref.1 Select 5 : 22/32 */
430 
#define CBREF1_22              (0x1600)       /* Comp. B Int. Ref.1 Select 6 : 23/32 */
431 
#define CBREF1_23              (0x1700)       /* Comp. B Int. Ref.1 Select 7 : 24/32 */
432 
#define CBREF1_24              (0x1800)       /* Comp. B Int. Ref.1 Select 0 : 25/32 */
433 
#define CBREF1_25              (0x1900)       /* Comp. B Int. Ref.1 Select 1 : 26/32 */
434 
#define CBREF1_26              (0x1A00)       /* Comp. B Int. Ref.1 Select 2 : 27/32 */
435 
#define CBREF1_27              (0x1B00)       /* Comp. B Int. Ref.1 Select 3 : 28/32 */
436 
#define CBREF1_28              (0x1C00)       /* Comp. B Int. Ref.1 Select 4 : 29/32 */
437 
#define CBREF1_29              (0x1D00)       /* Comp. B Int. Ref.1 Select 5 : 30/32 */
438 
#define CBREF1_30              (0x1E00)       /* Comp. B Int. Ref.1 Select 6 : 31/32 */
439 
#define CBREF1_31              (0x1F00)       /* Comp. B Int. Ref.1 Select 7 : 32/32 */
440 
 
441 
#define CBREFL_0               (0x0000)       /* Comp. B Reference voltage level 0 : None */
442 
#define CBREFL_1               (0x2000)       /* Comp. B Reference voltage level 1 : 1.5V */
443 
#define CBREFL_2               (0x4000)       /* Comp. B Reference voltage level 2 : 2.0V  */
444 
#define CBREFL_3               (0x6000)       /* Comp. B Reference voltage level 3 : 2.5V  */
445 
 
446 
#define CBPD0                  (0x0001)       /* Comp. B Disable Input Buffer of Port Register .0 */
447 
#define CBPD1                  (0x0002)       /* Comp. B Disable Input Buffer of Port Register .1 */
448 
#define CBPD2                  (0x0004)       /* Comp. B Disable Input Buffer of Port Register .2 */
449 
#define CBPD3                  (0x0008)       /* Comp. B Disable Input Buffer of Port Register .3 */
450 
#define CBPD4                  (0x0010)       /* Comp. B Disable Input Buffer of Port Register .4 */
451 
#define CBPD5                  (0x0020)       /* Comp. B Disable Input Buffer of Port Register .5 */
452 
#define CBPD6                  (0x0040)       /* Comp. B Disable Input Buffer of Port Register .6 */
453 
#define CBPD7                  (0x0080)       /* Comp. B Disable Input Buffer of Port Register .7 */
454 
#define CBPD8                  (0x0100)       /* Comp. B Disable Input Buffer of Port Register .8 */
455 
#define CBPD9                  (0x0200)       /* Comp. B Disable Input Buffer of Port Register .9 */
456 
#define CBPD10                 (0x0400)       /* Comp. B Disable Input Buffer of Port Register .10 */
457 
#define CBPD11                 (0x0800)       /* Comp. B Disable Input Buffer of Port Register .11 */
458 
#define CBPD12                 (0x1000)       /* Comp. B Disable Input Buffer of Port Register .12 */
459 
#define CBPD13                 (0x2000)       /* Comp. B Disable Input Buffer of Port Register .13 */
460 
#define CBPD14                 (0x4000)       /* Comp. B Disable Input Buffer of Port Register .14 */
461 
#define CBPD15                 (0x8000)       /* Comp. B Disable Input Buffer of Port Register .15 */
462 
 
463 
#define CBPD0_L                (0x0001)       /* Comp. B Disable Input Buffer of Port Register .0 */
464 
#define CBPD1_L                (0x0002)       /* Comp. B Disable Input Buffer of Port Register .1 */
465 
#define CBPD2_L                (0x0004)       /* Comp. B Disable Input Buffer of Port Register .2 */
466 
#define CBPD3_L                (0x0008)       /* Comp. B Disable Input Buffer of Port Register .3 */
467 
#define CBPD4_L                (0x0010)       /* Comp. B Disable Input Buffer of Port Register .4 */
468 
#define CBPD5_L                (0x0020)       /* Comp. B Disable Input Buffer of Port Register .5 */
469 
#define CBPD6_L                (0x0040)       /* Comp. B Disable Input Buffer of Port Register .6 */
470 
#define CBPD7_L                (0x0080)       /* Comp. B Disable Input Buffer of Port Register .7 */
471 
 
472 
#define CBPD8_H                (0x0001)       /* Comp. B Disable Input Buffer of Port Register .8 */
473 
#define CBPD9_H                (0x0002)       /* Comp. B Disable Input Buffer of Port Register .9 */
474 
#define CBPD10_H               (0x0004)       /* Comp. B Disable Input Buffer of Port Register .10 */
475 
#define CBPD11_H               (0x0008)       /* Comp. B Disable Input Buffer of Port Register .11 */
476 
#define CBPD12_H               (0x0010)       /* Comp. B Disable Input Buffer of Port Register .12 */
477 
#define CBPD13_H               (0x0020)       /* Comp. B Disable Input Buffer of Port Register .13 */
478 
#define CBPD14_H               (0x0040)       /* Comp. B Disable Input Buffer of Port Register .14 */
479 
#define CBPD15_H               (0x0080)       /* Comp. B Disable Input Buffer of Port Register .15 */
480 
 
481 
/* CBINT Control Bits */
482 
#define CBIFG                  (0x0001)       /* Comp. B Interrupt Flag */
483 
#define CBIIFG                 (0x0002)       /* Comp. B Interrupt Flag Inverted Polarity */
484 
//#define RESERVED             (0x0004)  /* Comp. B */
485 
//#define RESERVED             (0x0008)  /* Comp. B */
486 
//#define RESERVED             (0x0010)  /* Comp. B */
487 
//#define RESERVED             (0x0020)  /* Comp. B */
488 
//#define RESERVED             (0x0040)  /* Comp. B */
489 
//#define RESERVED             (0x0080)  /* Comp. B */
490 
#define CBIE                   (0x0100)       /* Comp. B Interrupt Enable */
491 
#define CBIIE                  (0x0200)       /* Comp. B Interrupt Enable Inverted Polarity */
492 
//#define RESERVED             (0x0400)  /* Comp. B */
493 
//#define RESERVED             (0x0800)  /* Comp. B */
494 
//#define RESERVED             (0x1000)  /* Comp. B */
495 
//#define RESERVED             (0x2000)  /* Comp. B */
496 
//#define RESERVED             (0x4000)  /* Comp. B */
497 
//#define RESERVED             (0x8000)  /* Comp. B */
498 
 
499 
/* CBINT Control Bits */
500 
#define CBIFG_L                (0x0001)       /* Comp. B Interrupt Flag */
501 
#define CBIIFG_L               (0x0002)       /* Comp. B Interrupt Flag Inverted Polarity */
502 
//#define RESERVED             (0x0004)  /* Comp. B */
503 
//#define RESERVED             (0x0008)  /* Comp. B */
504 
//#define RESERVED             (0x0010)  /* Comp. B */
505 
//#define RESERVED             (0x0020)  /* Comp. B */
506 
//#define RESERVED             (0x0040)  /* Comp. B */
507 
//#define RESERVED             (0x0080)  /* Comp. B */
508 
//#define RESERVED             (0x0400)  /* Comp. B */
509 
//#define RESERVED             (0x0800)  /* Comp. B */
510 
//#define RESERVED             (0x1000)  /* Comp. B */
511 
//#define RESERVED             (0x2000)  /* Comp. B */
512 
//#define RESERVED             (0x4000)  /* Comp. B */
513 
//#define RESERVED             (0x8000)  /* Comp. B */
514 
 
515 
/* CBINT Control Bits */
516 
//#define RESERVED             (0x0004)  /* Comp. B */
517 
//#define RESERVED             (0x0008)  /* Comp. B */
518 
//#define RESERVED             (0x0010)  /* Comp. B */
519 
//#define RESERVED             (0x0020)  /* Comp. B */
520 
//#define RESERVED             (0x0040)  /* Comp. B */
521 
//#define RESERVED             (0x0080)  /* Comp. B */
522 
#define CBIE_H                 (0x0001)       /* Comp. B Interrupt Enable */
523 
#define CBIIE_H                (0x0002)       /* Comp. B Interrupt Enable Inverted Polarity */
524 
//#define RESERVED             (0x0400)  /* Comp. B */
525 
//#define RESERVED             (0x0800)  /* Comp. B */
526 
//#define RESERVED             (0x1000)  /* Comp. B */
527 
//#define RESERVED             (0x2000)  /* Comp. B */
528 
//#define RESERVED             (0x4000)  /* Comp. B */
529 
//#define RESERVED             (0x8000)  /* Comp. B */
530 
 
531 
/* CBIV Definitions */
532 
#define CBIV_NONE              (0x0000)       /* No Interrupt pending */
533 
#define CBIV_CBIFG             (0x0002)       /* CBIFG */
534 
#define CBIV_CBIIFG            (0x0004)       /* CBIIFG */
535 
 
536 
/*************************************************************
537 
* CRC Module
538 
*************************************************************/
539 
#define __MSP430_HAS_CRC__                    /* Definition to show that Module is available */
540 
#define __MSP430_BASEADDRESS_CRC__ 0x0150
541 
 
542 
SFR_16BIT(CRCDI);                             /* CRC Data In Register */
543 
SFR_8BIT(CRCDI_L);                            /* CRC Data In Register */
544 
SFR_8BIT(CRCDI_H);                            /* CRC Data In Register */
545 
SFR_16BIT(CRCDIRB);                           /* CRC data in reverse byte Register */
546 
SFR_8BIT(CRCDIRB_L);                          /* CRC data in reverse byte Register */
547 
SFR_8BIT(CRCDIRB_H);                          /* CRC data in reverse byte Register */
548 
SFR_16BIT(CRCINIRES);                         /* CRC Initialisation Register and Result Register */
549 
SFR_8BIT(CRCINIRES_L);                        /* CRC Initialisation Register and Result Register */
550 
SFR_8BIT(CRCINIRES_H);                        /* CRC Initialisation Register and Result Register */
551 
SFR_16BIT(CRCRESR);                           /* CRC reverse result Register */
552 
SFR_8BIT(CRCRESR_L);                          /* CRC reverse result Register */
553 
SFR_8BIT(CRCRESR_H);                          /* CRC reverse result Register */
554 
 
555 
/************************************************************
556 
* DMA_X
557 
************************************************************/
558 
#define __MSP430_HAS_DMAX_6__                 /* Definition to show that Module is available */
559 
#define __MSP430_BASEADDRESS_DMAX_6__ 0x0500
560 
 
561 
SFR_16BIT(DMACTL0);                           /* DMA Module Control 0 */
562 
SFR_8BIT(DMACTL0_L);                          /* DMA Module Control 0 */
563 
SFR_8BIT(DMACTL0_H);                          /* DMA Module Control 0 */
564 
SFR_16BIT(DMACTL1);                           /* DMA Module Control 1 */
565 
SFR_8BIT(DMACTL1_L);                          /* DMA Module Control 1 */
566 
SFR_8BIT(DMACTL1_H);                          /* DMA Module Control 1 */
567 
SFR_16BIT(DMACTL2);                           /* DMA Module Control 2 */
568 
SFR_8BIT(DMACTL2_L);                          /* DMA Module Control 2 */
569 
SFR_8BIT(DMACTL2_H);                          /* DMA Module Control 2 */
570 
SFR_16BIT(DMACTL3);                           /* DMA Module Control 3 */
571 
SFR_8BIT(DMACTL3_L);                          /* DMA Module Control 3 */
572 
SFR_8BIT(DMACTL3_H);                          /* DMA Module Control 3 */
573 
SFR_16BIT(DMACTL4);                           /* DMA Module Control 4 */
574 
SFR_8BIT(DMACTL4_L);                          /* DMA Module Control 4 */
575 
SFR_8BIT(DMACTL4_H);                          /* DMA Module Control 4 */
576 
SFR_16BIT(DMAIV);                             /* DMA Interrupt Vector Word */
577 
SFR_8BIT(DMAIV_L);                            /* DMA Interrupt Vector Word */
578 
SFR_8BIT(DMAIV_H);                            /* DMA Interrupt Vector Word */
579 
 
580 
SFR_16BIT(DMA0CTL);                           /* DMA Channel 0 Control */
581 
SFR_8BIT(DMA0CTL_L);                          /* DMA Channel 0 Control */
582 
SFR_8BIT(DMA0CTL_H);                          /* DMA Channel 0 Control */
583 
SFR_20BIT(DMA0SA);                            /* DMA Channel 0 Source Address */
584 
SFR_16BIT(DMA0SAL);                           /* DMA Channel 0 Source Address */
585 
SFR_20BIT(DMA0DA);                            /* DMA Channel 0 Destination Address */
586 
SFR_16BIT(DMA0DAL);                           /* DMA Channel 0 Destination Address */
587 
SFR_16BIT(DMA0SZ);                            /* DMA Channel 0 Transfer Size */
588 
 
589 
SFR_16BIT(DMA1CTL);                           /* DMA Channel 1 Control */
590 
SFR_8BIT(DMA1CTL_L);                          /* DMA Channel 1 Control */
591 
SFR_8BIT(DMA1CTL_H);                          /* DMA Channel 1 Control */
592 
SFR_20BIT(DMA1SA);                            /* DMA Channel 1 Source Address */
593 
SFR_16BIT(DMA1SAL);                           /* DMA Channel 1 Source Address */
594 
SFR_20BIT(DMA1DA);                            /* DMA Channel 1 Destination Address */
595 
SFR_16BIT(DMA1DAL);                           /* DMA Channel 1 Destination Address */
596 
SFR_16BIT(DMA1SZ);                            /* DMA Channel 1 Transfer Size */
597 
 
598 
SFR_16BIT(DMA2CTL);                           /* DMA Channel 2 Control */
599 
SFR_8BIT(DMA2CTL_L);                          /* DMA Channel 2 Control */
600 
SFR_8BIT(DMA2CTL_H);                          /* DMA Channel 2 Control */
601 
SFR_20BIT(DMA2SA);                            /* DMA Channel 2 Source Address */
602 
SFR_16BIT(DMA2SAL);                           /* DMA Channel 2 Source Address */
603 
SFR_20BIT(DMA2DA);                            /* DMA Channel 2 Destination Address */
604 
SFR_16BIT(DMA2DAL);                           /* DMA Channel 2 Destination Address */
605 
SFR_16BIT(DMA2SZ);                            /* DMA Channel 2 Transfer Size */
606 
 
607 
SFR_16BIT(DMA3CTL);                           /* DMA Channel 3 Control */
608 
SFR_8BIT(DMA3CTL_L);                          /* DMA Channel 3 Control */
609 
SFR_8BIT(DMA3CTL_H);                          /* DMA Channel 3 Control */
610 
SFR_20BIT(DMA3SA);                            /* DMA Channel 3 Source Address */
611 
SFR_16BIT(DMA3SAL);                           /* DMA Channel 3 Source Address */
612 
SFR_20BIT(DMA3DA);                            /* DMA Channel 3 Destination Address */
613 
SFR_16BIT(DMA3DAL);                           /* DMA Channel 3 Destination Address */
614 
SFR_16BIT(DMA3SZ);                            /* DMA Channel 3 Transfer Size */
615 
 
616 
SFR_16BIT(DMA4CTL);                           /* DMA Channel 4 Control */
617 
SFR_8BIT(DMA4CTL_L);                          /* DMA Channel 4 Control */
618 
SFR_8BIT(DMA4CTL_H);                          /* DMA Channel 4 Control */
619 
SFR_20BIT(DMA4SA);                            /* DMA Channel 4 Source Address */
620 
SFR_16BIT(DMA4SAL);                           /* DMA Channel 4 Source Address */
621 
SFR_20BIT(DMA4DA);                            /* DMA Channel 4 Destination Address */
622 
SFR_16BIT(DMA4DAL);                           /* DMA Channel 4 Destination Address */
623 
SFR_16BIT(DMA4SZ);                            /* DMA Channel 4 Transfer Size */
624 
 
625 
SFR_16BIT(DMA5CTL);                           /* DMA Channel 5 Control */
626 
SFR_8BIT(DMA5CTL_L);                          /* DMA Channel 5 Control */
627 
SFR_8BIT(DMA5CTL_H);                          /* DMA Channel 5 Control */
628 
SFR_20BIT(DMA5SA);                            /* DMA Channel 5 Source Address */
629 
SFR_16BIT(DMA5SAL);                           /* DMA Channel 5 Source Address */
630 
SFR_20BIT(DMA5DA);                            /* DMA Channel 5 Destination Address */
631 
SFR_16BIT(DMA5DAL);                           /* DMA Channel 5 Destination Address */
632 
SFR_16BIT(DMA5SZ);                            /* DMA Channel 5 Transfer Size */
633 
 
634 
/* DMACTL0 Control Bits */
635 
#define DMA0TSEL0              (0x0001)       /* DMA channel 0 transfer select bit 0 */
636 
#define DMA0TSEL1              (0x0002)       /* DMA channel 0 transfer select bit 1 */
637 
#define DMA0TSEL2              (0x0004)       /* DMA channel 0 transfer select bit 2 */
638 
#define DMA0TSEL3              (0x0008)       /* DMA channel 0 transfer select bit 3 */
639 
#define DMA0TSEL4              (0x0010)       /* DMA channel 0 transfer select bit 4 */
640 
#define DMA1TSEL0              (0x0100)       /* DMA channel 1 transfer select bit 0 */
641 
#define DMA1TSEL1              (0x0200)       /* DMA channel 1 transfer select bit 1 */
642 
#define DMA1TSEL2              (0x0400)       /* DMA channel 1 transfer select bit 2 */
643 
#define DMA1TSEL3              (0x0800)       /* DMA channel 1 transfer select bit 3 */
644 
#define DMA1TSEL4              (0x1000)       /* DMA channel 1 transfer select bit 4 */
645 
 
646 
/* DMACTL0 Control Bits */
647 
#define DMA0TSEL0_L            (0x0001)       /* DMA channel 0 transfer select bit 0 */
648 
#define DMA0TSEL1_L            (0x0002)       /* DMA channel 0 transfer select bit 1 */
649 
#define DMA0TSEL2_L            (0x0004)       /* DMA channel 0 transfer select bit 2 */
650 
#define DMA0TSEL3_L            (0x0008)       /* DMA channel 0 transfer select bit 3 */
651 
#define DMA0TSEL4_L            (0x0010)       /* DMA channel 0 transfer select bit 4 */
652 
 
653 
/* DMACTL0 Control Bits */
654 
#define DMA1TSEL0_H            (0x0001)       /* DMA channel 1 transfer select bit 0 */
655 
#define DMA1TSEL1_H            (0x0002)       /* DMA channel 1 transfer select bit 1 */
656 
#define DMA1TSEL2_H            (0x0004)       /* DMA channel 1 transfer select bit 2 */
657 
#define DMA1TSEL3_H            (0x0008)       /* DMA channel 1 transfer select bit 3 */
658 
#define DMA1TSEL4_H            (0x0010)       /* DMA channel 1 transfer select bit 4 */
659 
 
660 
/* DMACTL01 Control Bits */
661 
#define DMA2TSEL0              (0x0001)       /* DMA channel 2 transfer select bit 0 */
662 
#define DMA2TSEL1              (0x0002)       /* DMA channel 2 transfer select bit 1 */
663 
#define DMA2TSEL2              (0x0004)       /* DMA channel 2 transfer select bit 2 */
664 
#define DMA2TSEL3              (0x0008)       /* DMA channel 2 transfer select bit 3 */
665 
#define DMA2TSEL4              (0x0010)       /* DMA channel 2 transfer select bit 4 */
666 
#define DMA3TSEL0              (0x0100)       /* DMA channel 3 transfer select bit 0 */
667 
#define DMA3TSEL1              (0x0200)       /* DMA channel 3 transfer select bit 1 */
668 
#define DMA3TSEL2              (0x0400)       /* DMA channel 3 transfer select bit 2 */
669 
#define DMA3TSEL3              (0x0800)       /* DMA channel 3 transfer select bit 3 */
670 
#define DMA3TSEL4              (0x1000)       /* DMA channel 3 transfer select bit 4 */
671 
 
672 
/* DMACTL01 Control Bits */
673 
#define DMA2TSEL0_L            (0x0001)       /* DMA channel 2 transfer select bit 0 */
674 
#define DMA2TSEL1_L            (0x0002)       /* DMA channel 2 transfer select bit 1 */
675 
#define DMA2TSEL2_L            (0x0004)       /* DMA channel 2 transfer select bit 2 */
676 
#define DMA2TSEL3_L            (0x0008)       /* DMA channel 2 transfer select bit 3 */
677 
#define DMA2TSEL4_L            (0x0010)       /* DMA channel 2 transfer select bit 4 */
678 
 
679 
/* DMACTL01 Control Bits */
680 
#define DMA3TSEL0_H            (0x0001)       /* DMA channel 3 transfer select bit 0 */
681 
#define DMA3TSEL1_H            (0x0002)       /* DMA channel 3 transfer select bit 1 */
682 
#define DMA3TSEL2_H            (0x0004)       /* DMA channel 3 transfer select bit 2 */
683 
#define DMA3TSEL3_H            (0x0008)       /* DMA channel 3 transfer select bit 3 */
684 
#define DMA3TSEL4_H            (0x0010)       /* DMA channel 3 transfer select bit 4 */
685 
 
686 
/* DMACTL0 Control Bits */
687 
#define DMA4TSEL0              (0x0001)       /* DMA channel 4 transfer select bit 0 */
688 
#define DMA4TSEL1              (0x0002)       /* DMA channel 4 transfer select bit 1 */
689 
#define DMA4TSEL2              (0x0004)       /* DMA channel 4 transfer select bit 2 */
690 
#define DMA4TSEL3              (0x0008)       /* DMA channel 4 transfer select bit 3 */
691 
#define DMA4TSEL4              (0x0010)       /* DMA channel 4 transfer select bit 4 */
692 
#define DMA5TSEL0              (0x0100)       /* DMA channel 5 transfer select bit 0 */
693 
#define DMA5TSEL1              (0x0200)       /* DMA channel 5 transfer select bit 1 */
694 
#define DMA5TSEL2              (0x0400)       /* DMA channel 5 transfer select bit 2 */
695 
#define DMA5TSEL3              (0x0800)       /* DMA channel 5 transfer select bit 3 */
696 
#define DMA5TSEL4              (0x1000)       /* DMA channel 5 transfer select bit 4 */
697 
 
698 
/* DMACTL0 Control Bits */
699 
#define DMA4TSEL0_L            (0x0001)       /* DMA channel 4 transfer select bit 0 */
700 
#define DMA4TSEL1_L            (0x0002)       /* DMA channel 4 transfer select bit 1 */
701 
#define DMA4TSEL2_L            (0x0004)       /* DMA channel 4 transfer select bit 2 */
702 
#define DMA4TSEL3_L            (0x0008)       /* DMA channel 4 transfer select bit 3 */
703 
#define DMA4TSEL4_L            (0x0010)       /* DMA channel 4 transfer select bit 4 */
704 
 
705 
/* DMACTL0 Control Bits */
706 
#define DMA5TSEL0_H            (0x0001)       /* DMA channel 5 transfer select bit 0 */
707 
#define DMA5TSEL1_H            (0x0002)       /* DMA channel 5 transfer select bit 1 */
708 
#define DMA5TSEL2_H            (0x0004)       /* DMA channel 5 transfer select bit 2 */
709 
#define DMA5TSEL3_H            (0x0008)       /* DMA channel 5 transfer select bit 3 */
710 
#define DMA5TSEL4_H            (0x0010)       /* DMA channel 5 transfer select bit 4 */
711 
 
712 
/* DMACTL4 Control Bits */
713 
#define ENNMI                  (0x0001)       /* Enable NMI interruption of DMA */
714 
#define ROUNDROBIN             (0x0002)       /* Round-Robin DMA channel priorities */
715 
#define DMARMWDIS              (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
716 
 
717 
/* DMACTL4 Control Bits */
718 
#define ENNMI_L                (0x0001)       /* Enable NMI interruption of DMA */
719 
#define ROUNDROBIN_L           (0x0002)       /* Round-Robin DMA channel priorities */
720 
#define DMARMWDIS_L            (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
721 
 
722 
/* DMACTL4 Control Bits */
723 
 
724 
/* DMAxCTL Control Bits */
725 
#define DMAREQ                 (0x0001)       /* Initiate DMA transfer with DMATSEL */
726 
#define DMAABORT               (0x0002)       /* DMA transfer aborted by NMI */
727 
#define DMAIE                  (0x0004)       /* DMA interrupt enable */
728 
#define DMAIFG                 (0x0008)       /* DMA interrupt flag */
729 
#define DMAEN                  (0x0010)       /* DMA enable */
730 
#define DMALEVEL               (0x0020)       /* DMA level sensitive trigger select */
731 
#define DMASRCBYTE             (0x0040)       /* DMA source byte */
732 
#define DMADSTBYTE             (0x0080)       /* DMA destination byte */
733 
#define DMASRCINCR0            (0x0100)       /* DMA source increment bit 0 */
734 
#define DMASRCINCR1            (0x0200)       /* DMA source increment bit 1 */
735 
#define DMADSTINCR0            (0x0400)       /* DMA destination increment bit 0 */
736 
#define DMADSTINCR1            (0x0800)       /* DMA destination increment bit 1 */
737 
#define DMADT0                 (0x1000)       /* DMA transfer mode bit 0 */
738 
#define DMADT1                 (0x2000)       /* DMA transfer mode bit 1 */
739 
#define DMADT2                 (0x4000)       /* DMA transfer mode bit 2 */
740 
 
741 
/* DMAxCTL Control Bits */
742 
#define DMAREQ_L               (0x0001)       /* Initiate DMA transfer with DMATSEL */
743 
#define DMAABORT_L             (0x0002)       /* DMA transfer aborted by NMI */
744 
#define DMAIE_L                (0x0004)       /* DMA interrupt enable */
745 
#define DMAIFG_L               (0x0008)       /* DMA interrupt flag */
746 
#define DMAEN_L                (0x0010)       /* DMA enable */
747 
#define DMALEVEL_L             (0x0020)       /* DMA level sensitive trigger select */
748 
#define DMASRCBYTE_L           (0x0040)       /* DMA source byte */
749 
#define DMADSTBYTE_L           (0x0080)       /* DMA destination byte */
750 
 
751 
/* DMAxCTL Control Bits */
752 
#define DMASRCINCR0_H          (0x0001)       /* DMA source increment bit 0 */
753 
#define DMASRCINCR1_H          (0x0002)       /* DMA source increment bit 1 */
754 
#define DMADSTINCR0_H          (0x0004)       /* DMA destination increment bit 0 */
755 
#define DMADSTINCR1_H          (0x0008)       /* DMA destination increment bit 1 */
756 
#define DMADT0_H               (0x0010)       /* DMA transfer mode bit 0 */
757 
#define DMADT1_H               (0x0020)       /* DMA transfer mode bit 1 */
758 
#define DMADT2_H               (0x0040)       /* DMA transfer mode bit 2 */
759 
 
760 
#define DMASWDW                (0*0x0040u)    /* DMA transfer: source word to destination word */
761 
#define DMASBDW                (1*0x0040u)    /* DMA transfer: source byte to destination word */
762 
#define DMASWDB                (2*0x0040u)    /* DMA transfer: source word to destination byte */
763 
#define DMASBDB                (3*0x0040u)    /* DMA transfer: source byte to destination byte */
764 
 
765 
#define DMASRCINCR_0           (0*0x0100u)    /* DMA source increment 0: source address unchanged */
766 
#define DMASRCINCR_1           (1*0x0100u)    /* DMA source increment 1: source address unchanged */
767 
#define DMASRCINCR_2           (2*0x0100u)    /* DMA source increment 2: source address decremented */
768 
#define DMASRCINCR_3           (3*0x0100u)    /* DMA source increment 3: source address incremented */
769 
 
770 
#define DMADSTINCR_0           (0*0x0400u)    /* DMA destination increment 0: destination address unchanged */
771 
#define DMADSTINCR_1           (1*0x0400u)    /* DMA destination increment 1: destination address unchanged */
772 
#define DMADSTINCR_2           (2*0x0400u)    /* DMA destination increment 2: destination address decremented */
773 
#define DMADSTINCR_3           (3*0x0400u)    /* DMA destination increment 3: destination address incremented */
774 
 
775 
#define DMADT_0                (0*0x1000u)    /* DMA transfer mode 0: Single transfer */
776 
#define DMADT_1                (1*0x1000u)    /* DMA transfer mode 1: Block transfer */
777 
#define DMADT_2                (2*0x1000u)    /* DMA transfer mode 2: Burst-Block transfer */
778 
#define DMADT_3                (3*0x1000u)    /* DMA transfer mode 3: Burst-Block transfer */
779 
#define DMADT_4                (4*0x1000u)    /* DMA transfer mode 4: Repeated Single transfer */
780 
#define DMADT_5                (5*0x1000u)    /* DMA transfer mode 5: Repeated Block transfer */
781 
#define DMADT_6                (6*0x1000u)    /* DMA transfer mode 6: Repeated Burst-Block transfer */
782 
#define DMADT_7                (7*0x1000u)    /* DMA transfer mode 7: Repeated Burst-Block transfer */
783 
 
784 
/* DMAIV Definitions */
785 
#define DMAIV_NONE             (0x0000)       /* No Interrupt pending */
786 
#define DMAIV_DMA0IFG          (0x0002)       /* DMA0IFG*/
787 
#define DMAIV_DMA1IFG          (0x0004)       /* DMA1IFG*/
788 
#define DMAIV_DMA2IFG          (0x0006)       /* DMA2IFG*/
789 
#define DMAIV_DMA3IFG          (0x0008)       /* DMA3IFG*/
790 
#define DMAIV_DMA4IFG          (0x000A)       /* DMA4IFG*/
791 
#define DMAIV_DMA5IFG          (0x000C)       /* DMA5IFG*/
792 
 
793 
#define DMA0TSEL_0             (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
794 
#define DMA0TSEL_1             (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
795 
#define DMA0TSEL_2             (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
796 
#define DMA0TSEL_3             (3*0x0001u)    /* DMA channel 0 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
797 
#define DMA0TSEL_4             (4*0x0001u)    /* DMA channel 0 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
798 
#define DMA0TSEL_5             (5*0x0001u)    /* DMA channel 0 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
799 
#define DMA0TSEL_6             (6*0x0001u)    /* DMA channel 0 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
800 
#define DMA0TSEL_7             (7*0x0001u)    /* DMA channel 0 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
801 
#define DMA0TSEL_8             (8*0x0001u)    /* DMA channel 0 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
802 
#define DMA0TSEL_9             (9*0x0001u)    /* DMA channel 0 transfer select 9:  Reserved */
803 
#define DMA0TSEL_10            (10*0x0001u)   /* DMA channel 0 transfer select 10: Reserved */
804 
#define DMA0TSEL_11            (11*0x0001u)   /* DMA channel 0 transfer select 11: Reserved */
805 
#define DMA0TSEL_12            (12*0x0001u)   /* DMA channel 0 transfer select 12: Reserved */
806 
#define DMA0TSEL_13            (13*0x0001u)   /* DMA channel 0 transfer select 13: Reserved */
807 
#define DMA0TSEL_14            (14*0x0001u)   /* DMA channel 0 transfer select 14: Reserved */
808 
#define DMA0TSEL_15            (15*0x0001u)   /* DMA channel 0 transfer select 15: Reserved */
809 
#define DMA0TSEL_16            (16*0x0001u)   /* DMA channel 0 transfer select 16: USCIA0 receive */
810 
#define DMA0TSEL_17            (17*0x0001u)   /* DMA channel 0 transfer select 17: USCIA0 transmit */
811 
#define DMA0TSEL_18            (18*0x0001u)   /* DMA channel 0 transfer select 18: USCIB0 receive */
812 
#define DMA0TSEL_19            (19*0x0001u)   /* DMA channel 0 transfer select 19: USCIB0 transmit */
813 
#define DMA0TSEL_20            (20*0x0001u)   /* DMA channel 0 transfer select 20: USCIA1 receive */
814 
#define DMA0TSEL_21            (21*0x0001u)   /* DMA channel 0 transfer select 21: USCIA1 transmit */
815 
#define DMA0TSEL_22            (22*0x0001u)   /* DMA channel 0 transfer select 22: USCIB1 receive */
816 
#define DMA0TSEL_23            (23*0x0001u)   /* DMA channel 0 transfer select 23: USCIB1 transmit */
817 
#define DMA0TSEL_24            (24*0x0001u)   /* DMA channel 0 transfer select 24: ADC12IFGx */
818 
#define DMA0TSEL_25            (25*0x0001u)   /* DMA channel 0 transfer select 25: DAC12_0IFG */
819 
#define DMA0TSEL_26            (26*0x0001u)   /* DMA channel 0 transfer select 26: DAC12_1IFG */
820 
#define DMA0TSEL_27            (27*0x0001u)   /* DMA channel 0 transfer select 27: USB FNRXD */
821 
#define DMA0TSEL_28            (28*0x0001u)   /* DMA channel 0 transfer select 28: USB ready */
822 
#define DMA0TSEL_29            (29*0x0001u)   /* DMA channel 0 transfer select 29: Multiplier ready */
823 
#define DMA0TSEL_30            (30*0x0001u)   /* DMA channel 0 transfer select 30: previous DMA channel DMA5IFG */
824 
#define DMA0TSEL_31            (31*0x0001u)   /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
825 
 
826 
#define DMA1TSEL_0             (0*0x0100u)    /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
827 
#define DMA1TSEL_1             (1*0x0100u)    /* DMA channel 1 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
828 
#define DMA1TSEL_2             (2*0x0100u)    /* DMA channel 1 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
829 
#define DMA1TSEL_3             (3*0x0100u)    /* DMA channel 1 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
830 
#define DMA1TSEL_4             (4*0x0100u)    /* DMA channel 1 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
831 
#define DMA1TSEL_5             (5*0x0100u)    /* DMA channel 1 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
832 
#define DMA1TSEL_6             (6*0x0100u)    /* DMA channel 1 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
833 
#define DMA1TSEL_7             (7*0x0001u)    /* DMA channel 1 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
834 
#define DMA1TSEL_8             (8*0x0001u)    /* DMA channel 1 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
835 
#define DMA1TSEL_9             (9*0x0100u)    /* DMA channel 1 transfer select 9:  Reserved */
836 
#define DMA1TSEL_10            (10*0x0100u)   /* DMA channel 1 transfer select 10: Reserved */
837 
#define DMA1TSEL_11            (11*0x0100u)   /* DMA channel 1 transfer select 11: Reserved */
838 
#define DMA1TSEL_12            (12*0x0100u)   /* DMA channel 1 transfer select 12: Reserved */
839 
#define DMA1TSEL_13            (13*0x0100u)   /* DMA channel 1 transfer select 13: Reserved */
840 
#define DMA1TSEL_14            (14*0x0100u)   /* DMA channel 1 transfer select 14: Reserved */
841 
#define DMA1TSEL_15            (15*0x0100u)   /* DMA channel 1 transfer select 15: Reserved */
842 
#define DMA1TSEL_16            (16*0x0100u)   /* DMA channel 1 transfer select 16: USCIA0 receive */
843 
#define DMA1TSEL_17            (17*0x0100u)   /* DMA channel 1 transfer select 17: USCIA0 transmit */
844 
#define DMA1TSEL_18            (18*0x0100u)   /* DMA channel 1 transfer select 18: USCIB0 receive */
845 
#define DMA1TSEL_19            (19*0x0100u)   /* DMA channel 1 transfer select 19: USCIB0 transmit */
846 
#define DMA1TSEL_20            (20*0x0100u)   /* DMA channel 1 transfer select 20: USCIA1 receive */
847 
#define DMA1TSEL_21            (21*0x0100u)   /* DMA channel 1 transfer select 21: USCIA1 transmit */
848 
#define DMA1TSEL_22            (22*0x0100u)   /* DMA channel 1 transfer select 22: USCIB1 receive */
849 
#define DMA1TSEL_23            (23*0x0100u)   /* DMA channel 1 transfer select 23: USCIB1 transmit */
850 
#define DMA1TSEL_24            (24*0x0100u)   /* DMA channel 1 transfer select 24: ADC12IFGx */
851 
#define DMA1TSEL_25            (25*0x0100u)   /* DMA channel 1 transfer select 25: DAC12_0IFG */
852 
#define DMA1TSEL_26            (26*0x0100u)   /* DMA channel 1 transfer select 26: DAC12_1IFG */
853 
#define DMA1TSEL_27            (27*0x0100u)   /* DMA channel 1 transfer select 27: USB FNRXD */
854 
#define DMA1TSEL_28            (28*0x0100u)   /* DMA channel 1 transfer select 28: USB ready */
855 
#define DMA1TSEL_29            (29*0x0100u)   /* DMA channel 1 transfer select 29: Multiplier ready */
856 
#define DMA1TSEL_30            (30*0x0100u)   /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
857 
#define DMA1TSEL_31            (31*0x0100u)   /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
858 
 
859 
#define DMA2TSEL_0             (0*0x0001u)    /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
860 
#define DMA2TSEL_1             (1*0x0001u)    /* DMA channel 2 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
861 
#define DMA2TSEL_2             (2*0x0001u)    /* DMA channel 2 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
862 
#define DMA2TSEL_3             (3*0x0001u)    /* DMA channel 2 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
863 
#define DMA2TSEL_4             (4*0x0001u)    /* DMA channel 2 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
864 
#define DMA2TSEL_5             (5*0x0001u)    /* DMA channel 2 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
865 
#define DMA2TSEL_6             (6*0x0001u)    /* DMA channel 2 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
866 
#define DMA2TSEL_7             (7*0x0001u)    /* DMA channel 2 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
867 
#define DMA2TSEL_8             (8*0x0001u)    /* DMA channel 2 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
868 
#define DMA2TSEL_9             (9*0x0001u)    /* DMA channel 2 transfer select 9:  Reserved */
869 
#define DMA2TSEL_10            (10*0x0001u)   /* DMA channel 2 transfer select 10: Reserved */
870 
#define DMA2TSEL_11            (11*0x0001u)   /* DMA channel 2 transfer select 11: Reserved */
871 
#define DMA2TSEL_12            (12*0x0001u)   /* DMA channel 2 transfer select 12: Reserved */
872 
#define DMA2TSEL_13            (13*0x0001u)   /* DMA channel 2 transfer select 13: Reserved */
873 
#define DMA2TSEL_14            (14*0x0001u)   /* DMA channel 2 transfer select 14: Reserved */
874 
#define DMA2TSEL_15            (15*0x0001u)   /* DMA channel 2 transfer select 15: Reserved */
875 
#define DMA2TSEL_16            (16*0x0001u)   /* DMA channel 2 transfer select 16: USCIA0 receive */
876 
#define DMA2TSEL_17            (17*0x0001u)   /* DMA channel 2 transfer select 17: USCIA0 transmit */
877 
#define DMA2TSEL_18            (18*0x0001u)   /* DMA channel 2 transfer select 18: USCIB0 receive */
878 
#define DMA2TSEL_19            (19*0x0001u)   /* DMA channel 2 transfer select 19: USCIB0 transmit */
879 
#define DMA2TSEL_20            (20*0x0001u)   /* DMA channel 2 transfer select 20: USCIA1 receive */
880 
#define DMA2TSEL_21            (21*0x0001u)   /* DMA channel 2 transfer select 21: USCIA1 transmit */
881 
#define DMA2TSEL_22            (22*0x0001u)   /* DMA channel 2 transfer select 22: USCIB1 receive */
882 
#define DMA2TSEL_23            (23*0x0001u)   /* DMA channel 2 transfer select 23: USCIB1 transmit */
883 
#define DMA2TSEL_24            (24*0x0001u)   /* DMA channel 2 transfer select 24: ADC12IFGx */
884 
#define DMA2TSEL_25            (25*0x0001u)   /* DMA channel 2 transfer select 25: DAC12_0IFG */
885 
#define DMA2TSEL_26            (26*0x0001u)   /* DMA channel 2 transfer select 26: DAC12_1IFG */
886 
#define DMA2TSEL_27            (27*0x0001u)   /* DMA channel 2 transfer select 27: USB FNRXD */
887 
#define DMA2TSEL_28            (28*0x0001u)   /* DMA channel 2 transfer select 28: USB ready */
888 
#define DMA2TSEL_29            (29*0x0001u)   /* DMA channel 2 transfer select 29: Multiplier ready */
889 
#define DMA2TSEL_30            (30*0x0001u)   /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
890 
#define DMA2TSEL_31            (31*0x0001u)   /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
891 
 
892 
#define DMA3TSEL_0             (0*0x0100u)    /* DMA channel 3 transfer select 0:  DMA_REQ (sw) */
893 
#define DMA3TSEL_1             (1*0x0100u)    /* DMA channel 3 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
894 
#define DMA3TSEL_2             (2*0x0100u)    /* DMA channel 3 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
895 
#define DMA3TSEL_3             (3*0x0100u)    /* DMA channel 3 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
896 
#define DMA3TSEL_4             (4*0x0100u)    /* DMA channel 3 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
897 
#define DMA3TSEL_5             (5*0x0100u)    /* DMA channel 3 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
898 
#define DMA3TSEL_6             (6*0x0100u)    /* DMA channel 3 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
899 
#define DMA3TSEL_7             (7*0x0001u)    /* DMA channel 3 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
900 
#define DMA3TSEL_8             (8*0x0001u)    /* DMA channel 3 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
901 
#define DMA3TSEL_9             (9*0x0100u)    /* DMA channel 3 transfer select 9:  Reserved */
902 
#define DMA3TSEL_10            (10*0x0100u)   /* DMA channel 3 transfer select 10: Reserved */
903 
#define DMA3TSEL_11            (11*0x0100u)   /* DMA channel 3 transfer select 11: Reserved */
904 
#define DMA3TSEL_12            (12*0x0100u)   /* DMA channel 3 transfer select 12: Reserved */
905 
#define DMA3TSEL_13            (13*0x0100u)   /* DMA channel 3 transfer select 13: Reserved */
906 
#define DMA3TSEL_14            (14*0x0100u)   /* DMA channel 3 transfer select 14: Reserved */
907 
#define DMA3TSEL_15            (15*0x0100u)   /* DMA channel 3 transfer select 15: Reserved */
908 
#define DMA3TSEL_16            (16*0x0100u)   /* DMA channel 3 transfer select 16: USCIA0 receive */
909 
#define DMA3TSEL_17            (17*0x0100u)   /* DMA channel 3 transfer select 17: USCIA0 transmit */
910 
#define DMA3TSEL_18            (18*0x0100u)   /* DMA channel 3 transfer select 18: USCIB0 receive */
911 
#define DMA3TSEL_19            (19*0x0100u)   /* DMA channel 3 transfer select 19: USCIB0 transmit */
912 
#define DMA3TSEL_20            (20*0x0100u)   /* DMA channel 3 transfer select 20: USCIA1 receive */
913 
#define DMA3TSEL_21            (21*0x0100u)   /* DMA channel 3 transfer select 21: USCIA1 transmit */
914 
#define DMA3TSEL_22            (22*0x0100u)   /* DMA channel 3 transfer select 22: USCIB1 receive */
915 
#define DMA3TSEL_23            (23*0x0100u)   /* DMA channel 3 transfer select 23: USCIB1 transmit */
916 
#define DMA3TSEL_24            (24*0x0100u)   /* DMA channel 3 transfer select 24: ADC12IFGx */
917 
#define DMA3TSEL_25            (25*0x0100u)   /* DMA channel 3 transfer select 25: DAC12_0IFG */
918 
#define DMA3TSEL_26            (26*0x0100u)   /* DMA channel 3 transfer select 26: DAC12_1IFG */
919 
#define DMA3TSEL_27            (27*0x0100u)   /* DMA channel 3 transfer select 27: USB FNRXD */
920 
#define DMA3TSEL_28            (28*0x0100u)   /* DMA channel 3 transfer select 28: USB ready */
921 
#define DMA3TSEL_29            (29*0x0100u)   /* DMA channel 3 transfer select 29: Multiplier ready */
922 
#define DMA3TSEL_30            (30*0x0100u)   /* DMA channel 3 transfer select 30: previous DMA channel DMA2IFG */
923 
#define DMA3TSEL_31            (31*0x0100u)   /* DMA channel 3 transfer select 31: ext. Trigger (DMAE0) */
924 
 
925 
#define DMA4TSEL_0             (0*0x0001u)    /* DMA channel 4 transfer select 0:  DMA_REQ (sw) */
926 
#define DMA4TSEL_1             (1*0x0001u)    /* DMA channel 4 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
927 
#define DMA4TSEL_2             (2*0x0001u)    /* DMA channel 4 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
928 
#define DMA4TSEL_3             (3*0x0001u)    /* DMA channel 4 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
929 
#define DMA4TSEL_4             (4*0x0001u)    /* DMA channel 4 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
930 
#define DMA4TSEL_5             (5*0x0001u)    /* DMA channel 4 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
931 
#define DMA4TSEL_6             (6*0x0001u)    /* DMA channel 4 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
932 
#define DMA4TSEL_7             (7*0x0001u)    /* DMA channel 4 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
933 
#define DMA4TSEL_8             (8*0x0001u)    /* DMA channel 4 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
934 
#define DMA4TSEL_9             (9*0x0001u)    /* DMA channel 4 transfer select 9:  Reserved */
935 
#define DMA4TSEL_10            (10*0x0001u)   /* DMA channel 4 transfer select 10: Reserved */
936 
#define DMA4TSEL_11            (11*0x0001u)   /* DMA channel 4 transfer select 11: Reserved */
937 
#define DMA4TSEL_12            (12*0x0001u)   /* DMA channel 4 transfer select 12: Reserved */
938 
#define DMA4TSEL_13            (13*0x0001u)   /* DMA channel 4 transfer select 13: Reserved */
939 
#define DMA4TSEL_14            (14*0x0001u)   /* DMA channel 4 transfer select 14: Reserved */
940 
#define DMA4TSEL_15            (15*0x0001u)   /* DMA channel 4 transfer select 15: Reserved */
941 
#define DMA4TSEL_16            (16*0x0001u)   /* DMA channel 4 transfer select 16: USCIA0 receive */
942 
#define DMA4TSEL_17            (17*0x0001u)   /* DMA channel 4 transfer select 17: USCIA0 transmit */
943 
#define DMA4TSEL_18            (18*0x0001u)   /* DMA channel 4 transfer select 18: USCIB0 receive */
944 
#define DMA4TSEL_19            (19*0x0001u)   /* DMA channel 4 transfer select 19: USCIB0 transmit */
945 
#define DMA4TSEL_20            (20*0x0001u)   /* DMA channel 4 transfer select 20: USCIA1 receive */
946 
#define DMA4TSEL_21            (21*0x0001u)   /* DMA channel 4 transfer select 21: USCIA1 transmit */
947 
#define DMA4TSEL_22            (22*0x0001u)   /* DMA channel 4 transfer select 22: USCIB1 receive */
948 
#define DMA4TSEL_23            (23*0x0001u)   /* DMA channel 4 transfer select 23: USCIB1 transmit */
949 
#define DMA4TSEL_24            (24*0x0001u)   /* DMA channel 4 transfer select 24: ADC12IFGx */
950 
#define DMA4TSEL_25            (25*0x0001u)   /* DMA channel 4 transfer select 25: DAC12_0IFG */
951 
#define DMA4TSEL_26            (26*0x0001u)   /* DMA channel 4 transfer select 26: DAC12_1IFG */
952 
#define DMA4TSEL_27            (27*0x0001u)   /* DMA channel 4 transfer select 27: USB FNRXD */
953 
#define DMA4TSEL_28            (28*0x0001u)   /* DMA channel 4 transfer select 28: USB ready */
954 
#define DMA4TSEL_29            (29*0x0001u)   /* DMA channel 4 transfer select 29: Multiplier ready */
955 
#define DMA4TSEL_30            (30*0x0001u)   /* DMA channel 4 transfer select 30: previous DMA channel DMA3IFG */
956 
#define DMA4TSEL_31            (31*0x0001u)   /* DMA channel 4 transfer select 31: ext. Trigger (DMAE0) */
957 
 
958 
#define DMA5TSEL_0             (0*0x0100u)    /* DMA channel 5 transfer select 0:  DMA_REQ (sw) */
959 
#define DMA5TSEL_1             (1*0x0100u)    /* DMA channel 5 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
960 
#define DMA5TSEL_2             (2*0x0100u)    /* DMA channel 5 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
961 
#define DMA5TSEL_3             (3*0x0100u)    /* DMA channel 5 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
962 
#define DMA5TSEL_4             (4*0x0100u)    /* DMA channel 5 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
963 
#define DMA5TSEL_5             (5*0x0100u)    /* DMA channel 5 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
964 
#define DMA5TSEL_6             (6*0x0100u)    /* DMA channel 5 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
965 
#define DMA5TSEL_7             (7*0x0001u)    /* DMA channel 5 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
966 
#define DMA5TSEL_8             (8*0x0001u)    /* DMA channel 5 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
967 
#define DMA5TSEL_9             (9*0x0100u)    /* DMA channel 5 transfer select 9:  Reserved */
968 
#define DMA5TSEL_10            (10*0x0100u)   /* DMA channel 5 transfer select 10: Reserved */
969 
#define DMA5TSEL_11            (11*0x0100u)   /* DMA channel 5 transfer select 11: Reserved */
970 
#define DMA5TSEL_12            (12*0x0100u)   /* DMA channel 5 transfer select 12: Reserved */
971 
#define DMA5TSEL_13            (13*0x0100u)   /* DMA channel 5 transfer select 13: Reserved */
972 
#define DMA5TSEL_14            (14*0x0100u)   /* DMA channel 5 transfer select 14: Reserved */
973 
#define DMA5TSEL_15            (15*0x0100u)   /* DMA channel 5 transfer select 15: Reserved */
974 
#define DMA5TSEL_16            (16*0x0100u)   /* DMA channel 5 transfer select 16: USCIA0 receive */
975 
#define DMA5TSEL_17            (17*0x0100u)   /* DMA channel 5 transfer select 17: USCIA0 transmit */
976 
#define DMA5TSEL_18            (18*0x0100u)   /* DMA channel 5 transfer select 18: USCIB0 receive */
977 
#define DMA5TSEL_19            (19*0x0100u)   /* DMA channel 5 transfer select 19: USCIB0 transmit */
978 
#define DMA5TSEL_20            (20*0x0100u)   /* DMA channel 5 transfer select 20: USCIA1 receive */
979 
#define DMA5TSEL_21            (21*0x0100u)   /* DMA channel 5 transfer select 21: USCIA1 transmit */
980 
#define DMA5TSEL_22            (22*0x0100u)   /* DMA channel 5 transfer select 22: USCIB1 receive */
981 
#define DMA5TSEL_23            (23*0x0100u)   /* DMA channel 5 transfer select 23: USCIB1 transmit */
982 
#define DMA5TSEL_24            (24*0x0100u)   /* DMA channel 5 transfer select 24: ADC12IFGx */
983 
#define DMA5TSEL_25            (25*0x0100u)   /* DMA channel 5 transfer select 25: DAC12_0IFG */
984 
#define DMA5TSEL_26            (26*0x0100u)   /* DMA channel 5 transfer select 26: DAC12_1IFG */
985 
#define DMA5TSEL_27            (27*0x0100u)   /* DMA channel 5 transfer select 27: USB FNRXD */
986 
#define DMA5TSEL_28            (28*0x0100u)   /* DMA channel 5 transfer select 28: USB ready */
987 
#define DMA5TSEL_29            (29*0x0100u)   /* DMA channel 5 transfer select 29: Multiplier ready */
988 
#define DMA5TSEL_30            (30*0x0100u)   /* DMA channel 5 transfer select 30: previous DMA channel DMA4IFG */
989 
#define DMA5TSEL_31            (31*0x0100u)   /* DMA channel 5 transfer select 31: ext. Trigger (DMAE0) */
990 
 
991 
#define DMA0TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
992 
#define DMA0TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
993 
#define DMA0TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
994 
#define DMA0TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 0 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
995 
#define DMA0TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 0 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
996 
#define DMA0TSEL__TA2CCR0      (5*0x0001u)    /* DMA channel 0 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
997 
#define DMA0TSEL__TA2CCR2      (6*0x0001u)    /* DMA channel 0 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
998 
#define DMA0TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 0 transfer select 7:  TimerB0  (TB0CCR0.IFG) */
999 
#define DMA0TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 0 transfer select 8:  TimerB0  (TB0CCR2.IFG) */
1000 
#define DMA0TSEL__RES9         (9*0x0001u)    /* DMA channel 0 transfer select 9:  Reserved */
1001 
#define DMA0TSEL__RES10        (10*0x0001u)   /* DMA channel 0 transfer select 10: Reserved */
1002 
#define DMA0TSEL__RES11        (11*0x0001u)   /* DMA channel 0 transfer select 11: Reserved */
1003 
#define DMA0TSEL__RES12        (12*0x0001u)   /* DMA channel 0 transfer select 12: Reserved */
1004 
#define DMA0TSEL__RES13        (13*0x0001u)   /* DMA channel 0 transfer select 13: Reserved */
1005 
#define DMA0TSEL__RES14        (14*0x0001u)   /* DMA channel 0 transfer select 14: Reserved */
1006 
#define DMA0TSEL__RES15        (15*0x0001u)   /* DMA channel 0 transfer select 15: Reserved */
1007 
#define DMA0TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 0 transfer select 16: USCIA0 receive */
1008 
#define DMA0TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 0 transfer select 17: USCIA0 transmit */
1009 
#define DMA0TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 0 transfer select 18: USCIB0 receive */
1010 
#define DMA0TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 0 transfer select 19: USCIB0 transmit */
1011 
#define DMA0TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 0 transfer select 20: USCIA1 receive */
1012 
#define DMA0TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 0 transfer select 21: USCIA1 transmit */
1013 
#define DMA0TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 0 transfer select 22: USCIB1 receive */
1014 
#define DMA0TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 0 transfer select 23: USCIB1 transmit */
1015 
#define DMA0TSEL__RES24        (24*0x0001u)   /* DMA channel 0 transfer select 24: Reserved */
1016 
#define DMA0TSEL__RES25        (25*0x0001u)   /* DMA channel 0 transfer select 25: Reserved */
1017 
#define DMA0TSEL__RES26        (26*0x0001u)   /* DMA channel 0 transfer select 26: Reserved */
1018 
#define DMA0TSEL__USB_FNRXD    (27*0x0001u)   /* DMA channel 0 transfer select 27: USB FNRXD */
1019 
#define DMA0TSEL__USB_READY    (28*0x0001u)   /* DMA channel 0 transfer select 28: USB ready */
1020 
#define DMA0TSEL__MPY          (29*0x0001u)   /* DMA channel 0 transfer select 29: Multiplier ready */
1021 
#define DMA0TSEL__DMA5IFG      (30*0x0001u)   /* DMA channel 0 transfer select 30: previous DMA channel DMA5IFG */
1022 
#define DMA0TSEL__DMAE0        (31*0x0001u)   /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
1023 
 
1024 
#define DMA1TSEL__DMA_REQ      (0*0x0100u)    /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
1025 
#define DMA1TSEL__TA0CCR0      (1*0x0100u)    /* DMA channel 1 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1026 
#define DMA1TSEL__TA0CCR2      (2*0x0100u)    /* DMA channel 1 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1027 
#define DMA1TSEL__TA1CCR0      (3*0x0100u)    /* DMA channel 1 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1028 
#define DMA1TSEL__TA1CCR2      (4*0x0100u)    /* DMA channel 1 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1029 
#define DMA1TSEL__TA2CCR0      (5*0x0100u)    /* DMA channel 1 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1030 
#define DMA1TSEL__TA2CCR2      (6*0x0100u)    /* DMA channel 1 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1031 
#define DMA1TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 1 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1032 
#define DMA1TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 1 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1033 
#define DMA1TSEL__RES9         (9*0x0100u)    /* DMA channel 1 transfer select 9:  Reserved */
1034 
#define DMA1TSEL__RES10        (10*0x0100u)   /* DMA channel 1 transfer select 10: Reserved */
1035 
#define DMA1TSEL__RES11        (11*0x0100u)   /* DMA channel 1 transfer select 11: Reserved */
1036 
#define DMA1TSEL__RES12        (12*0x0100u)   /* DMA channel 1 transfer select 12: Reserved */
1037 
#define DMA1TSEL__RES13        (13*0x0100u)   /* DMA channel 1 transfer select 13: Reserved */
1038 
#define DMA1TSEL__RES14        (14*0x0100u)   /* DMA channel 1 transfer select 14: Reserved */
1039 
#define DMA1TSEL__RES15        (15*0x0100u)   /* DMA channel 1 transfer select 15: Reserved */
1040 
#define DMA1TSEL__USCIA0RX     (16*0x0100u)   /* DMA channel 1 transfer select 16: USCIA0 receive */
1041 
#define DMA1TSEL__USCIA0TX     (17*0x0100u)   /* DMA channel 1 transfer select 17: USCIA0 transmit */
1042 
#define DMA1TSEL__USCIB0RX     (18*0x0100u)   /* DMA channel 1 transfer select 18: USCIB0 receive */
1043 
#define DMA1TSEL__USCIB0TX     (19*0x0100u)   /* DMA channel 1 transfer select 19: USCIB0 transmit */
1044 
#define DMA1TSEL__USCIA1RX     (20*0x0100u)   /* DMA channel 1 transfer select 20: USCIA1 receive */
1045 
#define DMA1TSEL__USCIA1TX     (21*0x0100u)   /* DMA channel 1 transfer select 21: USCIA1 transmit */
1046 
#define DMA1TSEL__USCIB1RX     (22*0x0100u)   /* DMA channel 1 transfer select 22: USCIB1 receive */
1047 
#define DMA1TSEL__USCIB1TX     (23*0x0100u)   /* DMA channel 1 transfer select 23: USCIB1 transmit */
1048 
#define DMA1TSEL__RES24        (24*0x0100u)   /* DMA channel 1 transfer select 24: Reserved */
1049 
#define DMA1TSEL__RES25        (25*0x0100u)   /* DMA channel 1 transfer select 25: Reserved */
1050 
#define DMA1TSEL__RES26        (26*0x0100u)   /* DMA channel 1 transfer select 26: Reserved */
1051 
#define DMA1TSEL__USB_FNRXD    (27*0x0100u)   /* DMA channel 1 transfer select 27: USB FNRXD */
1052 
#define DMA1TSEL__USB_READY    (28*0x0100u)   /* DMA channel 1 transfer select 28: USB ready */
1053 
#define DMA1TSEL__MPY          (29*0x0100u)   /* DMA channel 1 transfer select 29: Multiplier ready */
1054 
#define DMA1TSEL__DMA0IFG      (30*0x0100u)   /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
1055 
#define DMA1TSEL__DMAE0        (31*0x0100u)   /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
1056 
 
1057 
#define DMA2TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
1058 
#define DMA2TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 2 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1059 
#define DMA2TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 2 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1060 
#define DMA2TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 2 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1061 
#define DMA2TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 2 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1062 
#define DMA2TSEL__TA2CCR0      (5*0x0001u)    /* DMA channel 2 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1063 
#define DMA2TSEL__TA2CCR2      (6*0x0001u)    /* DMA channel 2 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1064 
#define DMA2TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 2 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1065 
#define DMA2TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 2 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1066 
#define DMA2TSEL__RES9         (9*0x0001u)    /* DMA channel 2 transfer select 9:  Reserved */
1067 
#define DMA2TSEL__RES10        (10*0x0001u)   /* DMA channel 2 transfer select 10: Reserved */
1068 
#define DMA2TSEL__RES11        (11*0x0001u)   /* DMA channel 2 transfer select 11: Reserved */
1069 
#define DMA2TSEL__RES12        (12*0x0001u)   /* DMA channel 2 transfer select 12: Reserved */
1070 
#define DMA2TSEL__RES13        (13*0x0001u)   /* DMA channel 2 transfer select 13: Reserved */
1071 
#define DMA2TSEL__RES14        (14*0x0001u)   /* DMA channel 2 transfer select 14: Reserved */
1072 
#define DMA2TSEL__RES15        (15*0x0001u)   /* DMA channel 2 transfer select 15: Reserved */
1073 
#define DMA2TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 2 transfer select 16: USCIA0 receive */
1074 
#define DMA2TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 2 transfer select 17: USCIA0 transmit */
1075 
#define DMA2TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 2 transfer select 18: USCIB0 receive */
1076 
#define DMA2TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 2 transfer select 19: USCIB0 transmit */
1077 
#define DMA2TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 2 transfer select 20: USCIA1 receive */
1078 
#define DMA2TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 2 transfer select 21: USCIA1 transmit */
1079 
#define DMA2TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 2 transfer select 22: USCIB1 receive */
1080 
#define DMA2TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 2 transfer select 23: USCIB1 transmit */
1081 
#define DMA2TSEL__RES24        (24*0x0001u)   /* DMA channel 2 transfer select 24: Reserved */
1082 
#define DMA2TSEL__RES25        (25*0x0001u)   /* DMA channel 2 transfer select 25: Reserved */
1083 
#define DMA2TSEL__RES26        (26*0x0001u)   /* DMA channel 2 transfer select 26: Reserved */
1084 
#define DMA2TSEL__USB_FNRXD    (27*0x0001u)   /* DMA channel 2 transfer select 27: USB FNRXD */
1085 
#define DMA2TSEL__USB_READY    (28*0x0001u)   /* DMA channel 2 transfer select 28: USB ready */
1086 
#define DMA2TSEL__MPY          (29*0x0001u)   /* DMA channel 2 transfer select 29: Multiplier ready */
1087 
#define DMA2TSEL__DMA1IFG      (30*0x0001u)   /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
1088 
#define DMA2TSEL__DMAE0        (31*0x0001u)   /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
1089 
 
1090 
#define DMA3TSEL__DMA_REQ      (0*0x0100u)    /* DMA channel 3 transfer select 0:  DMA_REQ (sw) */
1091 
#define DMA3TSEL__TA0CCR0      (1*0x0100u)    /* DMA channel 3 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1092 
#define DMA3TSEL__TA0CCR2      (2*0x0100u)    /* DMA channel 3 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1093 
#define DMA3TSEL__TA1CCR0      (3*0x0100u)    /* DMA channel 3 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1094 
#define DMA3TSEL__TA1CCR2      (4*0x0100u)    /* DMA channel 3 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1095 
#define DMA3TSEL__TA2CCR0      (5*0x0100u)    /* DMA channel 3 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1096 
#define DMA3TSEL__TA2CCR2      (6*0x0100u)    /* DMA channel 3 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1097 
#define DMA3TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 3 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1098 
#define DMA3TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 3 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1099 
#define DMA3TSEL__RES9         (9*0x0100u)    /* DMA channel 3 transfer select 9:  Reserved */
1100 
#define DMA3TSEL__RES10        (10*0x0100u)   /* DMA channel 3 transfer select 10: Reserved */
1101 
#define DMA3TSEL__RES11        (11*0x0100u)   /* DMA channel 3 transfer select 11: Reserved */
1102 
#define DMA3TSEL__RES12        (12*0x0100u)   /* DMA channel 3 transfer select 12: Reserved */
1103 
#define DMA3TSEL__RES13        (13*0x0100u)   /* DMA channel 3 transfer select 13: Reserved */
1104 
#define DMA3TSEL__RES14        (14*0x0100u)   /* DMA channel 3 transfer select 14: Reserved */
1105 
#define DMA3TSEL__RES15        (15*0x0100u)   /* DMA channel 3 transfer select 15: Reserved */
1106 
#define DMA3TSEL__USCIA0RX     (16*0x0100u)   /* DMA channel 3 transfer select 16: USCIA0 receive */
1107 
#define DMA3TSEL__USCIA0TX     (17*0x0100u)   /* DMA channel 3 transfer select 17: USCIA0 transmit */
1108 
#define DMA3TSEL__USCIB0RX     (18*0x0100u)   /* DMA channel 3 transfer select 18: USCIB0 receive */
1109 
#define DMA3TSEL__USCIB0TX     (19*0x0100u)   /* DMA channel 3 transfer select 19: USCIB0 transmit */
1110 
#define DMA3TSEL__USCIA1RX     (20*0x0100u)   /* DMA channel 3 transfer select 20: USCIA1 receive */
1111 
#define DMA3TSEL__USCIA1TX     (21*0x0100u)   /* DMA channel 3 transfer select 21: USCIA1 transmit */
1112 
#define DMA3TSEL__USCIB1RX     (22*0x0100u)   /* DMA channel 3 transfer select 22: USCIB1 receive */
1113 
#define DMA3TSEL__USCIB1TX     (23*0x0100u)   /* DMA channel 3 transfer select 23: USCIB1 transmit */
1114 
#define DMA3TSEL__RES24        (24*0x0100u)   /* DMA channel 3 transfer select 24: Reserved */
1115 
#define DMA3TSEL__RES25        (25*0x0100u)   /* DMA channel 3 transfer select 25: Reserved */
1116 
#define DMA3TSEL__RES26        (26*0x0100u)   /* DMA channel 3 transfer select 26: Reserved */
1117 
#define DMA3TSEL__USB_FNRXD    (27*0x0100u)   /* DMA channel 3 transfer select 27: USB FNRXD */
1118 
#define DMA3TSEL__USB_READY    (28*0x0100u)   /* DMA channel 3 transfer select 28: USB ready */
1119 
#define DMA3TSEL__MPY          (29*0x0100u)   /* DMA channel 3 transfer select 29: Multiplier ready */
1120 
#define DMA3TSEL__DMA2IFG      (30*0x0100u)   /* DMA channel 3 transfer select 30: previous DMA channel DMA2IFG */
1121 
#define DMA3TSEL__DMAE0        (31*0x0100u)   /* DMA channel 3 transfer select 31: ext. Trigger (DMAE0) */
1122 
 
1123 
#define DMA4TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 4 transfer select 0:  DMA_REQ (sw) */
1124 
#define DMA4TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 4 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1125 
#define DMA4TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 4 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1126 
#define DMA4TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 4 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1127 
#define DMA4TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 4 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1128 
#define DMA4TSEL__TA2CCR0      (5*0x0001u)    /* DMA channel 4 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1129 
#define DMA4TSEL__TA2CCR2      (6*0x0001u)    /* DMA channel 4 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1130 
#define DMA4TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 4 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1131 
#define DMA4TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 4 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1132 
#define DMA4TSEL__RES9         (9*0x0001u)    /* DMA channel 4 transfer select 9:  Reserved */
1133 
#define DMA4TSEL__RES10        (10*0x0001u)   /* DMA channel 4 transfer select 10: Reserved */
1134 
#define DMA4TSEL__RES11        (11*0x0001u)   /* DMA channel 4 transfer select 11: Reserved */
1135 
#define DMA4TSEL__RES12        (12*0x0001u)   /* DMA channel 4 transfer select 12: Reserved */
1136 
#define DMA4TSEL__RES13        (13*0x0001u)   /* DMA channel 4 transfer select 13: Reserved */
1137 
#define DMA4TSEL__RES14        (14*0x0001u)   /* DMA channel 4 transfer select 14: Reserved */
1138 
#define DMA4TSEL__RES15        (15*0x0001u)   /* DMA channel 4 transfer select 15: Reserved */
1139 
#define DMA4TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 4 transfer select 16: USCIA0 receive */
1140 
#define DMA4TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 4 transfer select 17: USCIA0 transmit */
1141 
#define DMA4TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 4 transfer select 18: USCIB0 receive */
1142 
#define DMA4TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 4 transfer select 19: USCIB0 transmit */
1143 
#define DMA4TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 4 transfer select 20: USCIA1 receive */
1144 
#define DMA4TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 4 transfer select 21: USCIA1 transmit */
1145 
#define DMA4TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 4 transfer select 22: USCIB1 receive */
1146 
#define DMA4TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 4 transfer select 23: USCIB1 transmit */
1147 
#define DMA4TSEL__RES24        (24*0x0001u)   /* DMA channel 4 transfer select 24: Reserved */
1148 
#define DMA4TSEL__RES25        (25*0x0001u)   /* DMA channel 4 transfer select 25: Reserved */
1149 
#define DMA4TSEL__RES26        (26*0x0001u)   /* DMA channel 4 transfer select 26: Reserved */
1150 
#define DMA4TSEL__USB_FNRXD    (27*0x0001u)   /* DMA channel 4 transfer select 27: USB FNRXD */
1151 
#define DMA4TSEL__USB_READY    (28*0x0001u)   /* DMA channel 4 transfer select 28: USB ready */
1152 
#define DMA4TSEL__MPY          (29*0x0001u)   /* DMA channel 4 transfer select 29: Multiplier ready */
1153 
#define DMA4TSEL__DMA3IFG      (30*0x0001u)   /* DMA channel 4 transfer select 30: previous DMA channel DMA3IFG */
1154 
#define DMA4TSEL__DMAE0        (31*0x0001u)   /* DMA channel 4 transfer select 31: ext. Trigger (DMAE0) */
1155 
 
1156 
#define DMA5TSEL__DMA_REQ      (0*0x0100u)    /* DMA channel 5 transfer select 0:  DMA_REQ (sw) */
1157 
#define DMA5TSEL__TA0CCR0      (1*0x0100u)    /* DMA channel 5 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
1158 
#define DMA5TSEL__TA0CCR2      (2*0x0100u)    /* DMA channel 5 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
1159 
#define DMA5TSEL__TA1CCR0      (3*0x0100u)    /* DMA channel 5 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
1160 
#define DMA5TSEL__TA1CCR2      (4*0x0100u)    /* DMA channel 5 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
1161 
#define DMA5TSEL__TA2CCR0      (5*0x0100u)    /* DMA channel 5 transfer select 5:  Timer2_A (TA2CCR0.IFG) */
1162 
#define DMA5TSEL__TA2CCR2      (6*0x0100u)    /* DMA channel 5 transfer select 6:  Timer2_A (TA2CCR2.IFG) */
1163 
#define DMA5TSEL__TB0CCR0      (7*0x0001u)    /* DMA channel 5 transfer select 7:  TimerB0 (TB0CCR0.IFG) */
1164 
#define DMA5TSEL__TB0CCR2      (8*0x0001u)    /* DMA channel 5 transfer select 8:  TimerB0 (TB0CCR2.IFG) */
1165 
#define DMA5TSEL__RES9         (9*0x0100u)    /* DMA channel 5 transfer select 9:  Reserved */
1166 
#define DMA5TSEL__RES10        (10*0x0100u)   /* DMA channel 5 transfer select 10: Reserved */
1167 
#define DMA5TSEL__RES11        (11*0x0100u)   /* DMA channel 5 transfer select 11: Reserved */
1168 
#define DMA5TSEL__RES12        (12*0x0100u)   /* DMA channel 5 transfer select 12: Reserved */
1169 
#define DMA5TSEL__RES13        (13*0x0100u)   /* DMA channel 5 transfer select 13: Reserved */
1170 
#define DMA5TSEL__RES14        (14*0x0100u)   /* DMA channel 5 transfer select 14: Reserved */
1171 
#define DMA5TSEL__RES15        (15*0x0100u)   /* DMA channel 5 transfer select 15: Reserved */
1172 
#define DMA5TSEL__USCIA0RX     (16*0x0100u)   /* DMA channel 5 transfer select 16: USCIA0 receive */
1173 
#define DMA5TSEL__USCIA0TX     (17*0x0100u)   /* DMA channel 5 transfer select 17: USCIA0 transmit */
1174 
#define DMA5TSEL__USCIB0RX     (18*0x0100u)   /* DMA channel 5 transfer select 18: USCIB0 receive */
1175 
#define DMA5TSEL__USCIB0TX     (19*0x0100u)   /* DMA channel 5 transfer select 19: USCIB0 transmit */
1176 
#define DMA5TSEL__USCIA1RX     (20*0x0100u)   /* DMA channel 5 transfer select 20: USCIA1 receive */
1177 
#define DMA5TSEL__USCIA1TX     (21*0x0100u)   /* DMA channel 5 transfer select 21: USCIA1 transmit */
1178 
#define DMA5TSEL__USCIB1RX     (22*0x0100u)   /* DMA channel 5 transfer select 22: USCIB1 receive */
1179 
#define DMA5TSEL__USCIB1TX     (23*0x0100u)   /* DMA channel 5 transfer select 23: USCIB1 transmit */
1180 
#define DMA5TSEL__RES24        (24*0x0100u)   /* DMA channel 5 transfer select 24: Reserved */
1181 
#define DMA5TSEL__RES25        (25*0x0100u)   /* DMA channel 5 transfer select 25: Reserved */
1182 
#define DMA5TSEL__RES26        (26*0x0100u)   /* DMA channel 5 transfer select 26: Reserved */
1183 
#define DMA5TSEL__USB_FNRXD    (27*0x0100u)   /* DMA channel 5 transfer select 27: USB FNRXD */
1184 
#define DMA5TSEL__USB_READY    (28*0x0100u)   /* DMA channel 5 transfer select 28: USB ready */
1185 
#define DMA5TSEL__MPY          (29*0x0100u)   /* DMA channel 5 transfer select 29: Multiplier ready */
1186 
#define DMA5TSEL__DMA4IFG      (30*0x0100u)   /* DMA channel 5 transfer select 30: previous DMA channel DMA4IFG */
1187 
#define DMA5TSEL__DMAE0        (31*0x0100u)   /* DMA channel 5 transfer select 31: ext. Trigger (DMAE0) */
1188 
 
1189 
/*************************************************************
1190 
* Flash Memory
1191 
*************************************************************/
1192 
#define __MSP430_HAS_FLASH__                  /* Definition to show that Module is available */
1193 
#define __MSP430_BASEADDRESS_FLASH__ 0x0140
1194 
 
1195 
SFR_16BIT(FCTL1);                             /* FLASH Control 1 */
1196 
SFR_8BIT(FCTL1_L);                            /* FLASH Control 1 */
1197 
SFR_8BIT(FCTL1_H);                            /* FLASH Control 1 */
1198 
//sfrbw    FCTL2               (0x0142)  /* FLASH Control 2 */
1199 
SFR_16BIT(FCTL3);                             /* FLASH Control 3 */
1200 
SFR_8BIT(FCTL3_L);                            /* FLASH Control 3 */
1201 
SFR_8BIT(FCTL3_H);                            /* FLASH Control 3 */
1202 
SFR_16BIT(FCTL4);                             /* FLASH Control 4 */
1203 
SFR_8BIT(FCTL4_L);                            /* FLASH Control 4 */
1204 
SFR_8BIT(FCTL4_H);                            /* FLASH Control 4 */
1205 
 
1206 
#define FRPW                   (0x9600)       /* Flash password returned by read */
1207 
#define FWPW                   (0xA500)       /* Flash password for write */
1208 
#define FXPW                   (0x3300)       /* for use with XOR instruction */
1209 
#define FRKEY                  (0x9600)       /* (legacy definition) Flash key returned by read */
1210 
#define FWKEY                  (0xA500)       /* (legacy definition) Flash key for write */
1211 
#define FXKEY                  (0x3300)       /* (legacy definition) for use with XOR instruction */
1212 
 
1213 
/* FCTL1 Control Bits */
1214 
//#define RESERVED            (0x0001)  /* Reserved */
1215 
#define ERASE                  (0x0002)       /* Enable bit for Flash segment erase */
1216 
#define MERAS                  (0x0004)       /* Enable bit for Flash mass erase */
1217 
//#define RESERVED            (0x0008)  /* Reserved */
1218 
//#define RESERVED            (0x0010)  /* Reserved */
1219 
#define SWRT                   (0x0020)       /* Smart Write enable */
1220 
#define WRT                    (0x0040)       /* Enable bit for Flash write */
1221 
#define BLKWRT                 (0x0080)       /* Enable bit for Flash segment write */
1222 
 
1223 
/* FCTL1 Control Bits */
1224 
//#define RESERVED            (0x0001)  /* Reserved */
1225 
#define ERASE_L                (0x0002)       /* Enable bit for Flash segment erase */
1226 
#define MERAS_L                (0x0004)       /* Enable bit for Flash mass erase */
1227 
//#define RESERVED            (0x0008)  /* Reserved */
1228 
//#define RESERVED            (0x0010)  /* Reserved */
1229 
#define SWRT_L                 (0x0020)       /* Smart Write enable */
1230 
#define WRT_L                  (0x0040)       /* Enable bit for Flash write */
1231 
#define BLKWRT_L               (0x0080)       /* Enable bit for Flash segment write */
1232 
 
1233 
/* FCTL1 Control Bits */
1234 
//#define RESERVED            (0x0001)  /* Reserved */
1235 
//#define RESERVED            (0x0008)  /* Reserved */
1236 
//#define RESERVED            (0x0010)  /* Reserved */
1237 
 
1238 
/* FCTL3 Control Bits */
1239 
#define BUSY                   (0x0001)       /* Flash busy: 1 */
1240 
#define KEYV                   (0x0002)       /* Flash Key violation flag */
1241 
#define ACCVIFG                (0x0004)       /* Flash Access violation flag */
1242 
#define WAIT                   (0x0008)       /* Wait flag for segment write */
1243 
#define LOCK                   (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
1244 
#define EMEX                   (0x0020)       /* Flash Emergency Exit */
1245 
#define LOCKA                  (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
1246 
//#define RESERVED            (0x0080)  /* Reserved */
1247 
 
1248 
/* FCTL3 Control Bits */
1249 
#define BUSY_L                 (0x0001)       /* Flash busy: 1 */
1250 
#define KEYV_L                 (0x0002)       /* Flash Key violation flag */
1251 
#define ACCVIFG_L              (0x0004)       /* Flash Access violation flag */
1252 
#define WAIT_L                 (0x0008)       /* Wait flag for segment write */
1253 
#define LOCK_L                 (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
1254 
#define EMEX_L                 (0x0020)       /* Flash Emergency Exit */
1255 
#define LOCKA_L                (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
1256 
//#define RESERVED            (0x0080)  /* Reserved */
1257 
 
1258 
/* FCTL3 Control Bits */
1259 
//#define RESERVED            (0x0080)  /* Reserved */
1260 
 
1261 
/* FCTL4 Control Bits */
1262 
#define VPE                    (0x0001)       /* Voltage Changed during Program Error Flag */
1263 
#define MGR0                   (0x0010)       /* Marginal read 0 mode. */
1264 
#define MGR1                   (0x0020)       /* Marginal read 1 mode. */
1265 
#define LOCKINFO               (0x0080)       /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
1266 
 
1267 
/* FCTL4 Control Bits */
1268 
#define VPE_L                  (0x0001)       /* Voltage Changed during Program Error Flag */
1269 
#define MGR0_L                 (0x0010)       /* Marginal read 0 mode. */
1270 
#define MGR1_L                 (0x0020)       /* Marginal read 1 mode. */
1271 
#define LOCKINFO_L             (0x0080)       /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
1272 
 
1273 
/* FCTL4 Control Bits */
1274 
 
1275 
/************************************************************
1276 
* HARDWARE MULTIPLIER 32Bit
1277 
************************************************************/
1278 
#define __MSP430_HAS_MPY32__                  /* Definition to show that Module is available */
1279 
#define __MSP430_BASEADDRESS_MPY32__ 0x04C0
1280 
 
1281 
SFR_16BIT(MPY);                               /* Multiply Unsigned/Operand 1 */
1282 
SFR_8BIT(MPY_L);                              /* Multiply Unsigned/Operand 1 */
1283 
SFR_8BIT(MPY_H);                              /* Multiply Unsigned/Operand 1 */
1284 
SFR_16BIT(MPYS);                              /* Multiply Signed/Operand 1 */
1285 
SFR_8BIT(MPYS_L);                             /* Multiply Signed/Operand 1 */
1286 
SFR_8BIT(MPYS_H);                             /* Multiply Signed/Operand 1 */
1287 
SFR_16BIT(MAC);                               /* Multiply Unsigned and Accumulate/Operand 1 */
1288 
SFR_8BIT(MAC_L);                              /* Multiply Unsigned and Accumulate/Operand 1 */
1289 
SFR_8BIT(MAC_H);                              /* Multiply Unsigned and Accumulate/Operand 1 */
1290 
SFR_16BIT(MACS);                              /* Multiply Signed and Accumulate/Operand 1 */
1291 
SFR_8BIT(MACS_L);                             /* Multiply Signed and Accumulate/Operand 1 */
1292 
SFR_8BIT(MACS_H);                             /* Multiply Signed and Accumulate/Operand 1 */
1293 
SFR_16BIT(OP2);                               /* Operand 2 */
1294 
SFR_8BIT(OP2_L);                              /* Operand 2 */
1295 
SFR_8BIT(OP2_H);                              /* Operand 2 */
1296 
SFR_16BIT(RESLO);                             /* Result Low Word */
1297 
SFR_8BIT(RESLO_L);                            /* Result Low Word */
1298 
SFR_8BIT(RESLO_H);                            /* Result Low Word */
1299 
SFR_16BIT(RESHI);                             /* Result High Word */
1300 
SFR_8BIT(RESHI_L);                            /* Result High Word */
1301 
SFR_8BIT(RESHI_H);                            /* Result High Word */
1302 
SFR_16BIT(SUMEXT);                            /* Sum Extend */
1303 
SFR_8BIT(SUMEXT_L);                           /* Sum Extend */
1304 
SFR_8BIT(SUMEXT_H);                           /* Sum Extend */
1305 
 
1306 
SFR_16BIT(MPY32L);                            /* 32-bit operand 1 - multiply - low word */
1307 
SFR_8BIT(MPY32L_L);                           /* 32-bit operand 1 - multiply - low word */
1308 
SFR_8BIT(MPY32L_H);                           /* 32-bit operand 1 - multiply - low word */
1309 
SFR_16BIT(MPY32H);                            /* 32-bit operand 1 - multiply - high word */
1310 
SFR_8BIT(MPY32H_L);                           /* 32-bit operand 1 - multiply - high word */
1311 
SFR_8BIT(MPY32H_H);                           /* 32-bit operand 1 - multiply - high word */
1312 
SFR_16BIT(MPYS32L);                           /* 32-bit operand 1 - signed multiply - low word */
1313 
SFR_8BIT(MPYS32L_L);                          /* 32-bit operand 1 - signed multiply - low word */
1314 
SFR_8BIT(MPYS32L_H);                          /* 32-bit operand 1 - signed multiply - low word */
1315 
SFR_16BIT(MPYS32H);                           /* 32-bit operand 1 - signed multiply - high word */
1316 
SFR_8BIT(MPYS32H_L);                          /* 32-bit operand 1 - signed multiply - high word */
1317 
SFR_8BIT(MPYS32H_H);                          /* 32-bit operand 1 - signed multiply - high word */
1318 
SFR_16BIT(MAC32L);                            /* 32-bit operand 1 - multiply accumulate - low word */
1319 
SFR_8BIT(MAC32L_L);                           /* 32-bit operand 1 - multiply accumulate - low word */
1320 
SFR_8BIT(MAC32L_H);                           /* 32-bit operand 1 - multiply accumulate - low word */
1321 
SFR_16BIT(MAC32H);                            /* 32-bit operand 1 - multiply accumulate - high word */
1322 
SFR_8BIT(MAC32H_L);                           /* 32-bit operand 1 - multiply accumulate - high word */
1323 
SFR_8BIT(MAC32H_H);                           /* 32-bit operand 1 - multiply accumulate - high word */
1324 
SFR_16BIT(MACS32L);                           /* 32-bit operand 1 - signed multiply accumulate - low word */
1325 
SFR_8BIT(MACS32L_L);                          /* 32-bit operand 1 - signed multiply accumulate - low word */
1326 
SFR_8BIT(MACS32L_H);                          /* 32-bit operand 1 - signed multiply accumulate - low word */
1327 
SFR_16BIT(MACS32H);                           /* 32-bit operand 1 - signed multiply accumulate - high word */
1328 
SFR_8BIT(MACS32H_L);                          /* 32-bit operand 1 - signed multiply accumulate - high word */
1329 
SFR_8BIT(MACS32H_H);                          /* 32-bit operand 1 - signed multiply accumulate - high word */
1330 
SFR_16BIT(OP2L);                              /* 32-bit operand 2 - low word */
1331 
SFR_8BIT(OP2L_L);                             /* 32-bit operand 2 - low word */
1332 
SFR_8BIT(OP2L_H);                             /* 32-bit operand 2 - low word */
1333 
SFR_16BIT(OP2H);                              /* 32-bit operand 2 - high word */
1334 
SFR_8BIT(OP2H_L);                             /* 32-bit operand 2 - high word */
1335 
SFR_8BIT(OP2H_H);                             /* 32-bit operand 2 - high word */
1336 
SFR_16BIT(RES0);                              /* 32x32-bit result 0 - least significant word */
1337 
SFR_8BIT(RES0_L);                             /* 32x32-bit result 0 - least significant word */
1338 
SFR_8BIT(RES0_H);                             /* 32x32-bit result 0 - least significant word */
1339 
SFR_16BIT(RES1);                              /* 32x32-bit result 1 */
1340 
SFR_8BIT(RES1_L);                             /* 32x32-bit result 1 */
1341 
SFR_8BIT(RES1_H);                             /* 32x32-bit result 1 */
1342 
SFR_16BIT(RES2);                              /* 32x32-bit result 2 */
1343 
SFR_8BIT(RES2_L);                             /* 32x32-bit result 2 */
1344 
SFR_8BIT(RES2_H);                             /* 32x32-bit result 2 */
1345 
SFR_16BIT(RES3);                              /* 32x32-bit result 3 - most significant word */
1346 
SFR_8BIT(RES3_L);                             /* 32x32-bit result 3 - most significant word */
1347 
SFR_8BIT(RES3_H);                             /* 32x32-bit result 3 - most significant word */
1348 
SFR_16BIT(MPY32CTL0);                         /* MPY32 Control Register 0 */
1349 
SFR_8BIT(MPY32CTL0_L);                        /* MPY32 Control Register 0 */
1350 
SFR_8BIT(MPY32CTL0_H);                        /* MPY32 Control Register 0 */
1351 
 
1352 
#define MPY_B                  MPY_L          /* Multiply Unsigned/Operand 1 (Byte Access) */
1353 
#define MPYS_B                 MPYS_L         /* Multiply Signed/Operand 1 (Byte Access) */
1354 
#define MAC_B                  MAC_L          /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
1355 
#define MACS_B                 MACS_L         /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
1356 
#define OP2_B                  OP2_L          /* Operand 2 (Byte Access) */
1357 
#define MPY32L_B               MPY32L_L       /* 32-bit operand 1 - multiply - low word (Byte Access) */
1358 
#define MPY32H_B               MPY32H_L       /* 32-bit operand 1 - multiply - high word (Byte Access) */
1359 
#define MPYS32L_B              MPYS32L_L      /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
1360 
#define MPYS32H_B              MPYS32H_L      /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
1361 
#define MAC32L_B               MAC32L_L       /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
1362 
#define MAC32H_B               MAC32H_L       /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
1363 
#define MACS32L_B              MACS32L_L      /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
1364 
#define MACS32H_B              MACS32H_L      /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
1365 
#define OP2L_B                 OP2L_L         /* 32-bit operand 2 - low word (Byte Access) */
1366 
#define OP2H_B                 OP2H_L         /* 32-bit operand 2 - high word (Byte Access) */
1367 
 
1368 
/* MPY32CTL0 Control Bits */
1369 
#define MPYC                   (0x0001)       /* Carry of the multiplier */
1370 
//#define RESERVED            (0x0002)  /* Reserved */
1371 
#define MPYFRAC                (0x0004)       /* Fractional mode */
1372 
#define MPYSAT                 (0x0008)       /* Saturation mode */
1373 
#define MPYM0                  (0x0010)       /* Multiplier mode Bit:0 */
1374 
#define MPYM1                  (0x0020)       /* Multiplier mode Bit:1 */
1375 
#define OP1_32                 (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
1376 
#define OP2_32                 (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
1377 
#define MPYDLYWRTEN            (0x0100)       /* Delayed write enable */
1378 
#define MPYDLY32               (0x0200)       /* Delayed write mode */
1379 
 
1380 
/* MPY32CTL0 Control Bits */
1381 
#define MPYC_L                 (0x0001)       /* Carry of the multiplier */
1382 
//#define RESERVED            (0x0002)  /* Reserved */
1383 
#define MPYFRAC_L              (0x0004)       /* Fractional mode */
1384 
#define MPYSAT_L               (0x0008)       /* Saturation mode */
1385 
#define MPYM0_L                (0x0010)       /* Multiplier mode Bit:0 */
1386 
#define MPYM1_L                (0x0020)       /* Multiplier mode Bit:1 */
1387 
#define OP1_32_L               (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
1388 
#define OP2_32_L               (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
1389 
 
1390 
/* MPY32CTL0 Control Bits */
1391 
//#define RESERVED            (0x0002)  /* Reserved */
1392 
#define MPYDLYWRTEN_H          (0x0001)       /* Delayed write enable */
1393 
#define MPYDLY32_H             (0x0002)       /* Delayed write mode */
1394 
 
1395 
#define MPYM_0                 (0x0000)       /* Multiplier mode: MPY */
1396 
#define MPYM_1                 (0x0010)       /* Multiplier mode: MPYS */
1397 
#define MPYM_2                 (0x0020)       /* Multiplier mode: MAC */
1398 
#define MPYM_3                 (0x0030)       /* Multiplier mode: MACS */
1399 
#define MPYM__MPY              (0x0000)       /* Multiplier mode: MPY */
1400 
#define MPYM__MPYS             (0x0010)       /* Multiplier mode: MPYS */
1401 
#define MPYM__MAC              (0x0020)       /* Multiplier mode: MAC */
1402 
#define MPYM__MACS             (0x0030)       /* Multiplier mode: MACS */
1403 
 
1404 
/************************************************************
1405 
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
1406 
************************************************************/
1407 
#define __MSP430_HAS_PORT1_R__                /* Definition to show that Module is available */
1408 
#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
1409 
#define __MSP430_HAS_PORT2_R__                /* Definition to show that Module is available */
1410 
#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
1411 
#define __MSP430_HAS_PORTA_R__                /* Definition to show that Module is available */
1412 
#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
1413 
 
1414 
SFR_16BIT(PAIN);                              /* Port A Input */
1415 
SFR_8BIT(PAIN_L);                             /* Port A Input */
1416 
SFR_8BIT(PAIN_H);                             /* Port A Input */
1417 
SFR_16BIT(PAOUT);                             /* Port A Output */
1418 
SFR_8BIT(PAOUT_L);                            /* Port A Output */
1419 
SFR_8BIT(PAOUT_H);                            /* Port A Output */
1420 
SFR_16BIT(PADIR);                             /* Port A Direction */
1421 
SFR_8BIT(PADIR_L);                            /* Port A Direction */
1422 
SFR_8BIT(PADIR_H);                            /* Port A Direction */
1423 
SFR_16BIT(PAREN);                             /* Port A Resistor Enable */
1424 
SFR_8BIT(PAREN_L);                            /* Port A Resistor Enable */
1425 
SFR_8BIT(PAREN_H);                            /* Port A Resistor Enable */
1426 
SFR_16BIT(PADS);                              /* Port A Resistor Drive Strenght */
1427 
SFR_8BIT(PADS_L);                             /* Port A Resistor Drive Strenght */
1428 
SFR_8BIT(PADS_H);                             /* Port A Resistor Drive Strenght */
1429 
SFR_16BIT(PASEL);                             /* Port A Selection */
1430 
SFR_8BIT(PASEL_L);                            /* Port A Selection */
1431 
SFR_8BIT(PASEL_H);                            /* Port A Selection */
1432 
SFR_16BIT(PAIES);                             /* Port A Interrupt Edge Select */
1433 
SFR_8BIT(PAIES_L);                            /* Port A Interrupt Edge Select */
1434 
SFR_8BIT(PAIES_H);                            /* Port A Interrupt Edge Select */
1435 
SFR_16BIT(PAIE);                              /* Port A Interrupt Enable */
1436 
SFR_8BIT(PAIE_L);                             /* Port A Interrupt Enable */
1437 
SFR_8BIT(PAIE_H);                             /* Port A Interrupt Enable */
1438 
SFR_16BIT(PAIFG);                             /* Port A Interrupt Flag */
1439 
SFR_8BIT(PAIFG_L);                            /* Port A Interrupt Flag */
1440 
SFR_8BIT(PAIFG_H);                            /* Port A Interrupt Flag */
1441 
 
1442 
 
1443 
SFR_16BIT(P1IV);                              /* Port 1 Interrupt Vector Word */
1444 
SFR_16BIT(P2IV);                              /* Port 2 Interrupt Vector Word */
1445 
#define P1IN                   (PAIN_L)       /* Port 1 Input */
1446 
#define P1OUT                  (PAOUT_L)      /* Port 1 Output */
1447 
#define P1DIR                  (PADIR_L)      /* Port 1 Direction */
1448 
#define P1REN                  (PAREN_L)      /* Port 1 Resistor Enable */
1449 
#define P1DS                   (PADS_L)       /* Port 1 Resistor Drive Strenght */
1450 
#define P1SEL                  (PASEL_L)      /* Port 1 Selection */
1451 
#define P1IES                  (PAIES_L)      /* Port 1 Interrupt Edge Select */
1452 
#define P1IE                   (PAIE_L)       /* Port 1 Interrupt Enable */
1453 
#define P1IFG                  (PAIFG_L)      /* Port 1 Interrupt Flag */
1454 
 
1455 
//Definitions for P1IV
1456 
#define P1IV_NONE              (0x0000)       /* No Interrupt pending */
1457 
#define P1IV_P1IFG0            (0x0002)       /* P1IV P1IFG.0 */
1458 
#define P1IV_P1IFG1            (0x0004)       /* P1IV P1IFG.1 */
1459 
#define P1IV_P1IFG2            (0x0006)       /* P1IV P1IFG.2 */
1460 
#define P1IV_P1IFG3            (0x0008)       /* P1IV P1IFG.3 */
1461 
#define P1IV_P1IFG4            (0x000A)       /* P1IV P1IFG.4 */
1462 
#define P1IV_P1IFG5            (0x000C)       /* P1IV P1IFG.5 */
1463 
#define P1IV_P1IFG6            (0x000E)       /* P1IV P1IFG.6 */
1464 
#define P1IV_P1IFG7            (0x0010)       /* P1IV P1IFG.7 */
1465 
 
1466 
#define P2IN                   (PAIN_H)       /* Port 2 Input */
1467 
#define P2OUT                  (PAOUT_H)      /* Port 2 Output */
1468 
#define P2DIR                  (PADIR_H)      /* Port 2 Direction */
1469 
#define P2REN                  (PAREN_H)      /* Port 2 Resistor Enable */
1470 
#define P2DS                   (PADS_H)       /* Port 2 Resistor Drive Strenght */
1471 
#define P2SEL                  (PASEL_H)      /* Port 2 Selection */
1472 
#define P2IES                  (PAIES_H)      /* Port 2 Interrupt Edge Select */
1473 
#define P2IE                   (PAIE_H)       /* Port 2 Interrupt Enable */
1474 
#define P2IFG                  (PAIFG_H)      /* Port 2 Interrupt Flag */
1475 
 
1476 
//Definitions for P2IV
1477 
#define P2IV_NONE              (0x0000)       /* No Interrupt pending */
1478 
#define P2IV_P2IFG0            (0x0002)       /* P2IV P2IFG.0 */
1479 
#define P2IV_P2IFG1            (0x0004)       /* P2IV P2IFG.1 */
1480 
#define P2IV_P2IFG2            (0x0006)       /* P2IV P2IFG.2 */
1481 
#define P2IV_P2IFG3            (0x0008)       /* P2IV P2IFG.3 */
1482 
#define P2IV_P2IFG4            (0x000A)       /* P2IV P2IFG.4 */
1483 
#define P2IV_P2IFG5            (0x000C)       /* P2IV P2IFG.5 */
1484 
#define P2IV_P2IFG6            (0x000E)       /* P2IV P2IFG.6 */
1485 
#define P2IV_P2IFG7            (0x0010)       /* P2IV P2IFG.7 */
1486 
 
1487 
 
1488 
/************************************************************
1489 
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
1490 
************************************************************/
1491 
#define __MSP430_HAS_PORT3_R__                /* Definition to show that Module is available */
1492 
#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220
1493 
#define __MSP430_HAS_PORT4_R__                /* Definition to show that Module is available */
1494 
#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220
1495 
#define __MSP430_HAS_PORTB_R__                /* Definition to show that Module is available */
1496 
#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220
1497 
 
1498 
SFR_16BIT(PBIN);                              /* Port B Input */
1499 
SFR_8BIT(PBIN_L);                             /* Port B Input */
1500 
SFR_8BIT(PBIN_H);                             /* Port B Input */
1501 
SFR_16BIT(PBOUT);                             /* Port B Output */
1502 
SFR_8BIT(PBOUT_L);                            /* Port B Output */
1503 
SFR_8BIT(PBOUT_H);                            /* Port B Output */
1504 
SFR_16BIT(PBDIR);                             /* Port B Direction */
1505 
SFR_8BIT(PBDIR_L);                            /* Port B Direction */
1506 
SFR_8BIT(PBDIR_H);                            /* Port B Direction */
1507 
SFR_16BIT(PBREN);                             /* Port B Resistor Enable */
1508 
SFR_8BIT(PBREN_L);                            /* Port B Resistor Enable */
1509 
SFR_8BIT(PBREN_H);                            /* Port B Resistor Enable */
1510 
SFR_16BIT(PBDS);                              /* Port B Resistor Drive Strenght */
1511 
SFR_8BIT(PBDS_L);                             /* Port B Resistor Drive Strenght */
1512 
SFR_8BIT(PBDS_H);                             /* Port B Resistor Drive Strenght */
1513 
SFR_16BIT(PBSEL);                             /* Port B Selection */
1514 
SFR_8BIT(PBSEL_L);                            /* Port B Selection */
1515 
SFR_8BIT(PBSEL_H);                            /* Port B Selection */
1516 
SFR_16BIT(PBIES);                             /* Port B Interrupt Edge Select */
1517 
SFR_8BIT(PBIES_L);                            /* Port B Interrupt Edge Select */
1518 
SFR_8BIT(PBIES_H);                            /* Port B Interrupt Edge Select */
1519 
SFR_16BIT(PBIE);                              /* Port B Interrupt Enable */
1520 
SFR_8BIT(PBIE_L);                             /* Port B Interrupt Enable */
1521 
SFR_8BIT(PBIE_H);                             /* Port B Interrupt Enable */
1522 
SFR_16BIT(PBIFG);                             /* Port B Interrupt Flag */
1523 
SFR_8BIT(PBIFG_L);                            /* Port B Interrupt Flag */
1524 
SFR_8BIT(PBIFG_H);                            /* Port B Interrupt Flag */
1525 
 
1526 
 
1527 
SFR_16BIT(P3IV);                              /* Port 3 Interrupt Vector Word */
1528 
SFR_16BIT(P4IV);                              /* Port 4 Interrupt Vector Word */
1529 
#define P3IN                   (PBIN_L)       /* Port 3 Input */
1530 
#define P3OUT                  (PBOUT_L)      /* Port 3 Output */
1531 
#define P3DIR                  (PBDIR_L)      /* Port 3 Direction */
1532 
#define P3REN                  (PBREN_L)      /* Port 3 Resistor Enable */
1533 
#define P3DS                   (PBDS_L)       /* Port 3 Resistor Drive Strenght */
1534 
#define P3SEL                  (PBSEL_L)      /* Port 3 Selection */
1535 
#define P3IES                  (PBIES_L)      /* Port 3 Interrupt Edge Select */
1536 
#define P3IE                   (PBIE_L)       /* Port 3 Interrupt Enable */
1537 
#define P3IFG                  (PBIFG_L)      /* Port 3 Interrupt Flag */
1538 
 
1539 
//Definitions for P3IV
1540 
#define P3IV_NONE              (0x0000)       /* No Interrupt pending */
1541 
#define P3IV_P3IFG0            (0x0002)       /* P3IV P3IFG.0 */
1542 
#define P3IV_P3IFG1            (0x0004)       /* P3IV P3IFG.1 */
1543 
#define P3IV_P3IFG2            (0x0006)       /* P3IV P3IFG.2 */
1544 
#define P3IV_P3IFG3            (0x0008)       /* P3IV P3IFG.3 */
1545 
#define P3IV_P3IFG4            (0x000A)       /* P3IV P3IFG.4 */
1546 
#define P3IV_P3IFG5            (0x000C)       /* P3IV P3IFG.5 */
1547 
#define P3IV_P3IFG6            (0x000E)       /* P3IV P3IFG.6 */
1548 
#define P3IV_P3IFG7            (0x0010)       /* P3IV P3IFG.7 */
1549 
 
1550 
#define P4IN                   (PBIN_H)       /* Port 4 Input */
1551 
#define P4OUT                  (PBOUT_H)      /* Port 4 Output */
1552 
#define P4DIR                  (PBDIR_H)      /* Port 4 Direction */
1553 
#define P4REN                  (PBREN_H)      /* Port 4 Resistor Enable */
1554 
#define P4DS                   (PBDS_H)       /* Port 4 Resistor Drive Strenght */
1555 
#define P4SEL                  (PBSEL_H)      /* Port 4 Selection */
1556 
#define P4IES                  (PBIES_H)      /* Port 4 Interrupt Edge Select */
1557 
#define P4IE                   (PBIE_H)       /* Port 4 Interrupt Enable */
1558 
#define P4IFG                  (PBIFG_H)      /* Port 4 Interrupt Flag */
1559 
 
1560 
//Definitions for P4IV
1561 
#define P4IV_NONE              (0x0000)       /* No Interrupt pending */
1562 
#define P4IV_P4IFG0            (0x0002)       /* P4IV P4IFG.0 */
1563 
#define P4IV_P4IFG1            (0x0004)       /* P4IV P4IFG.1 */
1564 
#define P4IV_P4IFG2            (0x0006)       /* P4IV P4IFG.2 */
1565 
#define P4IV_P4IFG3            (0x0008)       /* P4IV P4IFG.3 */
1566 
#define P4IV_P4IFG4            (0x000A)       /* P4IV P4IFG.4 */
1567 
#define P4IV_P4IFG5            (0x000C)       /* P4IV P4IFG.5 */
1568 
#define P4IV_P4IFG6            (0x000E)       /* P4IV P4IFG.6 */
1569 
#define P4IV_P4IFG7            (0x0010)       /* P4IV P4IFG.7 */
1570 
 
1571 
 
1572 
/************************************************************
1573 
* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
1574 
************************************************************/
1575 
#define __MSP430_HAS_PORT5_R__                /* Definition to show that Module is available */
1576 
#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240
1577 
#define __MSP430_HAS_PORT6_R__                /* Definition to show that Module is available */
1578 
#define __MSP430_BASEADDRESS_PORT6_R__ 0x0240
1579 
#define __MSP430_HAS_PORTC_R__                /* Definition to show that Module is available */
1580 
#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240
1581 
 
1582 
SFR_16BIT(PCIN);                              /* Port C Input */
1583 
SFR_8BIT(PCIN_L);                             /* Port C Input */
1584 
SFR_8BIT(PCIN_H);                             /* Port C Input */
1585 
SFR_16BIT(PCOUT);                             /* Port C Output */
1586 
SFR_8BIT(PCOUT_L);                            /* Port C Output */
1587 
SFR_8BIT(PCOUT_H);                            /* Port C Output */
1588 
SFR_16BIT(PCDIR);                             /* Port C Direction */
1589 
SFR_8BIT(PCDIR_L);                            /* Port C Direction */
1590 
SFR_8BIT(PCDIR_H);                            /* Port C Direction */
1591 
SFR_16BIT(PCREN);                             /* Port C Resistor Enable */
1592 
SFR_8BIT(PCREN_L);                            /* Port C Resistor Enable */
1593 
SFR_8BIT(PCREN_H);                            /* Port C Resistor Enable */
1594 
SFR_16BIT(PCDS);                              /* Port C Resistor Drive Strenght */
1595 
SFR_8BIT(PCDS_L);                             /* Port C Resistor Drive Strenght */
1596 
SFR_8BIT(PCDS_H);                             /* Port C Resistor Drive Strenght */
1597 
SFR_16BIT(PCSEL);                             /* Port C Selection */
1598 
SFR_8BIT(PCSEL_L);                            /* Port C Selection */
1599 
SFR_8BIT(PCSEL_H);                            /* Port C Selection */
1600 
 
1601 
 
1602 
#define P5IN                   (PCIN_L)       /* Port 5 Input */
1603 
#define P5OUT                  (PCOUT_L)      /* Port 5 Output */
1604 
#define P5DIR                  (PCDIR_L)      /* Port 5 Direction */
1605 
#define P5REN                  (PCREN_L)      /* Port 5 Resistor Enable */
1606 
#define P5DS                   (PCDS_L)       /* Port 5 Resistor Drive Strenght */
1607 
#define P5SEL                  (PCSEL_L)      /* Port 5 Selection */
1608 
 
1609 
#define P6IN                   (PCIN_H)       /* Port 6 Input */
1610 
#define P6OUT                  (PCOUT_H)      /* Port 6 Output */
1611 
#define P6DIR                  (PCDIR_H)      /* Port 6 Direction */
1612 
#define P6REN                  (PCREN_H)      /* Port 6 Resistor Enable */
1613 
#define P6DS                   (PCDS_H)       /* Port 6 Resistor Drive Strenght */
1614 
#define P6SEL                  (PCSEL_H)      /* Port 6 Selection */
1615 
 
1616 
 
1617 
/************************************************************
1618 
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
1619 
************************************************************/
1620 
#define __MSP430_HAS_PORT7_R__                /* Definition to show that Module is available */
1621 
#define __MSP430_BASEADDRESS_PORT7_R__ 0x0260
1622 
#define __MSP430_HAS_PORT8_R__                /* Definition to show that Module is available */
1623 
#define __MSP430_BASEADDRESS_PORT8_R__ 0x0260
1624 
#define __MSP430_HAS_PORTD_R__                /* Definition to show that Module is available */
1625 
#define __MSP430_BASEADDRESS_PORTD_R__ 0x0260
1626 
 
1627 
SFR_16BIT(PDIN);                              /* Port D Input */
1628 
SFR_8BIT(PDIN_L);                             /* Port D Input */
1629 
SFR_8BIT(PDIN_H);                             /* Port D Input */
1630 
SFR_16BIT(PDOUT);                             /* Port D Output */
1631 
SFR_8BIT(PDOUT_L);                            /* Port D Output */
1632 
SFR_8BIT(PDOUT_H);                            /* Port D Output */
1633 
SFR_16BIT(PDDIR);                             /* Port D Direction */
1634 
SFR_8BIT(PDDIR_L);                            /* Port D Direction */
1635 
SFR_8BIT(PDDIR_H);                            /* Port D Direction */
1636 
SFR_16BIT(PDREN);                             /* Port D Resistor Enable */
1637 
SFR_8BIT(PDREN_L);                            /* Port D Resistor Enable */
1638 
SFR_8BIT(PDREN_H);                            /* Port D Resistor Enable */
1639 
SFR_16BIT(PDDS);                              /* Port D Resistor Drive Strenght */
1640 
SFR_8BIT(PDDS_L);                             /* Port D Resistor Drive Strenght */
1641 
SFR_8BIT(PDDS_H);                             /* Port D Resistor Drive Strenght */
1642 
SFR_16BIT(PDSEL);                             /* Port D Selection */
1643 
SFR_8BIT(PDSEL_L);                            /* Port D Selection */
1644 
SFR_8BIT(PDSEL_H);                            /* Port D Selection */
1645 
 
1646 
 
1647 
#define P7IN                   (PDIN_L)       /* Port 7 Input */
1648 
#define P7OUT                  (PDOUT_L)      /* Port 7 Output */
1649 
#define P7DIR                  (PDDIR_L)      /* Port 7 Direction */
1650 
#define P7REN                  (PDREN_L)      /* Port 7 Resistor Enable */
1651 
#define P7DS                   (PDDS_L)       /* Port 7 Resistor Drive Strenght */
1652 
#define P7SEL                  (PDSEL_L)      /* Port 7 Selection */
1653 
 
1654 
#define P8IN                   (PDIN_H)       /* Port 8 Input */
1655 
#define P8OUT                  (PDOUT_H)      /* Port 8 Output */
1656 
#define P8DIR                  (PDDIR_H)      /* Port 8 Direction */
1657 
#define P8REN                  (PDREN_H)      /* Port 8 Resistor Enable */
1658 
#define P8DS                   (PDDS_H)       /* Port 8 Resistor Drive Strenght */
1659 
#define P8SEL                  (PDSEL_H)      /* Port 8 Selection */
1660 
 
1661 
 
1662 
/************************************************************
1663 
* DIGITAL I/O Port9 Pull up / Pull down Resistors
1664 
************************************************************/
1665 
#define __MSP430_HAS_PORT9_R__                /* Definition to show that Module is available */
1666 
#define __MSP430_BASEADDRESS_PORT9_R__ 0x0280
1667 
#define __MSP430_HAS_PORTE_R__                /* Definition to show that Module is available */
1668 
#define __MSP430_BASEADDRESS_PORTE_R__ 0x0280
1669 
 
1670 
SFR_16BIT(PEIN);                              /* Port E Input */
1671 
SFR_8BIT(PEIN_L);                             /* Port E Input */
1672 
SFR_8BIT(PEIN_H);                             /* Port E Input */
1673 
SFR_16BIT(PEOUT);                             /* Port E Output */
1674 
SFR_8BIT(PEOUT_L);                            /* Port E Output */
1675 
SFR_8BIT(PEOUT_H);                            /* Port E Output */
1676 
SFR_16BIT(PEDIR);                             /* Port E Direction */
1677 
SFR_8BIT(PEDIR_L);                            /* Port E Direction */
1678 
SFR_8BIT(PEDIR_H);                            /* Port E Direction */
1679 
SFR_16BIT(PEREN);                             /* Port E Resistor Enable */
1680 
SFR_8BIT(PEREN_L);                            /* Port E Resistor Enable */
1681 
SFR_8BIT(PEREN_H);                            /* Port E Resistor Enable */
1682 
SFR_16BIT(PEDS);                              /* Port E Resistor Drive Strenght */
1683 
SFR_8BIT(PEDS_L);                             /* Port E Resistor Drive Strenght */
1684 
SFR_8BIT(PEDS_H);                             /* Port E Resistor Drive Strenght */
1685 
SFR_16BIT(PESEL);                             /* Port E Selection */
1686 
SFR_8BIT(PESEL_L);                            /* Port E Selection */
1687 
SFR_8BIT(PESEL_H);                            /* Port E Selection */
1688 
 
1689 
 
1690 
#define P9IN                   (PEIN_L)       /* Port 9 Input */
1691 
#define P9OUT                  (PEOUT_L)      /* Port 9 Output */
1692 
#define P9DIR                  (PEDIR_L)      /* Port 9 Direction */
1693 
#define P9REN                  (PEREN_L)      /* Port 9 Resistor Enable */
1694 
#define P9DS                   (PEDS_L)       /* Port 9 Resistor Drive Strenght */
1695 
#define P9SEL                  (PESEL_L)      /* Port 9 Selection */
1696 
 
1697 
 
1698 
/************************************************************
1699 
* DIGITAL I/O PortJ Pull up / Pull down Resistors
1700 
************************************************************/
1701 
#define __MSP430_HAS_PORTJ_R__                /* Definition to show that Module is available */
1702 
#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320
1703 
 
1704 
SFR_16BIT(PJIN);                              /* Port J Input */
1705 
SFR_8BIT(PJIN_L);                             /* Port J Input */
1706 
SFR_8BIT(PJIN_H);                             /* Port J Input */
1707 
SFR_16BIT(PJOUT);                             /* Port J Output */
1708 
SFR_8BIT(PJOUT_L);                            /* Port J Output */
1709 
SFR_8BIT(PJOUT_H);                            /* Port J Output */
1710 
SFR_16BIT(PJDIR);                             /* Port J Direction */
1711 
SFR_8BIT(PJDIR_L);                            /* Port J Direction */
1712 
SFR_8BIT(PJDIR_H);                            /* Port J Direction */
1713 
SFR_16BIT(PJREN);                             /* Port J Resistor Enable */
1714 
SFR_8BIT(PJREN_L);                            /* Port J Resistor Enable */
1715 
SFR_8BIT(PJREN_H);                            /* Port J Resistor Enable */
1716 
SFR_16BIT(PJDS);                              /* Port J Resistor Drive Strenght */
1717 
SFR_8BIT(PJDS_L);                             /* Port J Resistor Drive Strenght */
1718 
SFR_8BIT(PJDS_H);                             /* Port J Resistor Drive Strenght */
1719 
 
1720 
/************************************************************
1721 
* PORT MAPPING CONTROLLER
1722 
************************************************************/
1723 
#define __MSP430_HAS_PORT_MAPPING__                /* Definition to show that Module is available */
1724 
#define __MSP430_BASEADDRESS_PORT_MAPPING__ 0x01C0
1725 
 
1726 
SFR_16BIT(PMAPKEYID);                         /* Port Mapping Key register */
1727 
SFR_8BIT(PMAPKEYID_L);                        /* Port Mapping Key register */
1728 
SFR_8BIT(PMAPKEYID_H);                        /* Port Mapping Key register */
1729 
SFR_16BIT(PMAPCTL);                           /* Port Mapping control register */
1730 
SFR_8BIT(PMAPCTL_L);                          /* Port Mapping control register */
1731 
SFR_8BIT(PMAPCTL_H);                          /* Port Mapping control register */
1732 
 
1733 
#define  PMAPKEY               (0x2D52)       /* Port Mapping Key */
1734 
#define  PMAPPWD               PMAPKEYID      /* Legacy Definition: Mapping Key register */
1735 
#define  PMAPPW                (0x2D52)       /* Legacy Definition: Port Mapping Password */
1736 
 
1737 
/* PMAPCTL Control Bits */
1738 
#define PMAPLOCKED             (0x0001)       /* Port Mapping Lock bit. Read only */
1739 
#define PMAPRECFG              (0x0002)       /* Port Mapping re-configuration control bit */
1740 
 
1741 
/* PMAPCTL Control Bits */
1742 
#define PMAPLOCKED_L           (0x0001)       /* Port Mapping Lock bit. Read only */
1743 
#define PMAPRECFG_L            (0x0002)       /* Port Mapping re-configuration control bit */
1744 
 
1745 
/* PMAPCTL Control Bits */
1746 
 
1747 
/************************************************************
1748 
* PORT 2 MAPPING CONTROLLER
1749 
************************************************************/
1750 
#define __MSP430_HAS_PORT2_MAPPING__                /* Definition to show that Module is available */
1751 
#define __MSP430_BASEADDRESS_PORT2_MAPPING__ 0x01D0
1752 
 
1753 
SFR_16BIT(P2MAP01);                           /* Port P2.0/1 mapping register */
1754 
SFR_8BIT(P2MAP01_L);                          /* Port P2.0/1 mapping register */
1755 
SFR_8BIT(P2MAP01_H);                          /* Port P2.0/1 mapping register */
1756 
SFR_16BIT(P2MAP23);                           /* Port P2.2/3 mapping register */
1757 
SFR_8BIT(P2MAP23_L);                          /* Port P2.2/3 mapping register */
1758 
SFR_8BIT(P2MAP23_H);                          /* Port P2.2/3 mapping register */
1759 
SFR_16BIT(P2MAP45);                           /* Port P2.4/5 mapping register */
1760 
SFR_8BIT(P2MAP45_L);                          /* Port P2.4/5 mapping register */
1761 
SFR_8BIT(P2MAP45_H);                          /* Port P2.4/5 mapping register */
1762 
SFR_16BIT(P2MAP67);                           /* Port P2.6/7 mapping register */
1763 
SFR_8BIT(P2MAP67_L);                          /* Port P2.6/7 mapping register */
1764 
SFR_8BIT(P2MAP67_H);                          /* Port P2.6/7 mapping register */
1765 
 
1766 
#define  P2MAP0                P2MAP01_L      /* Port P2.0 mapping register */
1767 
#define  P2MAP1                P2MAP01_H      /* Port P2.1 mapping register */
1768 
#define  P2MAP2                P2MAP23_L      /* Port P2.2 mapping register */
1769 
#define  P2MAP3                P2MAP23_H      /* Port P2.3 mapping register */
1770 
#define  P2MAP4                P2MAP45_L      /* Port P2.4 mapping register */
1771 
#define  P2MAP5                P2MAP45_H      /* Port P2.5 mapping register */
1772 
#define  P2MAP6                P2MAP67_L      /* Port P2.6 mapping register */
1773 
#define  P2MAP7                P2MAP67_H      /* Port P2.7 mapping register */
1774 
 
1775 
#define PM_NONE                0
1776 
#define PM_CBOUT               1
1777 
#define PM_TB0CLK              1
1778 
#define PM_ADC12CLK            2
1779 
#define PM_DMAE0               2
1780 
#define PM_SVMOUT              3
1781 
#define PM_TB0OUTH             3
1782 
#define PM_TB0CCR0B            4
1783 
#define PM_TB0CCR1B            5
1784 
#define PM_TB0CCR2B            6
1785 
#define PM_TB0CCR3B            7
1786 
#define PM_TB0CCR4B            8
1787 
#define PM_TB0CCR5B            9
1788 
#define PM_TB0CCR6B            10
1789 
#define PM_UCA0RXD             11
1790 
#define PM_UCA0SOMI            11
1791 
#define PM_UCA0TXD             12
1792 
#define PM_UCA0SIMO            12
1793 
#define PM_UCA0CLK             13
1794 
#define PM_UCB0STE             13
1795 
#define PM_UCB0SOMI            14
1796 
#define PM_UCB0SCL             14
1797 
#define PM_UCB0SIMO            15
1798 
#define PM_UCB0SDA             15
1799 
#define PM_UCB0CLK             16
1800 
#define PM_UCA0STE             16
1801 
#define PM_MCLK                17
1802 
#define PM_PM_E0               18
1803 
#define PM_PM_E1               19
1804 
#define PM_ANALOG              31
1805 
 
1806 
/************************************************************
1807 
* PMM - Power Management System
1808 
************************************************************/
1809 
#define __MSP430_HAS_PMM__                    /* Definition to show that Module is available */
1810 
#define __MSP430_BASEADDRESS_PMM__ 0x0120
1811 
 
1812 
SFR_16BIT(PMMCTL0);                           /* PMM Control 0 */
1813 
SFR_8BIT(PMMCTL0_L);                          /* PMM Control 0 */
1814 
SFR_8BIT(PMMCTL0_H);                          /* PMM Control 0 */
1815 
SFR_16BIT(PMMCTL1);                           /* PMM Control 1 */
1816 
SFR_8BIT(PMMCTL1_L);                          /* PMM Control 1 */
1817 
SFR_8BIT(PMMCTL1_H);                          /* PMM Control 1 */
1818 
SFR_16BIT(SVSMHCTL);                          /* SVS and SVM high side control register */
1819 
SFR_8BIT(SVSMHCTL_L);                         /* SVS and SVM high side control register */
1820 
SFR_8BIT(SVSMHCTL_H);                         /* SVS and SVM high side control register */
1821 
SFR_16BIT(SVSMLCTL);                          /* SVS and SVM low side control register */
1822 
SFR_8BIT(SVSMLCTL_L);                         /* SVS and SVM low side control register */
1823 
SFR_8BIT(SVSMLCTL_H);                         /* SVS and SVM low side control register */
1824 
SFR_16BIT(SVSMIO);                            /* SVSIN and SVSOUT control register */
1825 
SFR_8BIT(SVSMIO_L);                           /* SVSIN and SVSOUT control register */
1826 
SFR_8BIT(SVSMIO_H);                           /* SVSIN and SVSOUT control register */
1827 
SFR_16BIT(PMMIFG);                            /* PMM Interrupt Flag */
1828 
SFR_8BIT(PMMIFG_L);                           /* PMM Interrupt Flag */
1829 
SFR_8BIT(PMMIFG_H);                           /* PMM Interrupt Flag */
1830 
SFR_16BIT(PMMRIE);                            /* PMM and RESET Interrupt Enable */
1831 
SFR_8BIT(PMMRIE_L);                           /* PMM and RESET Interrupt Enable */
1832 
SFR_8BIT(PMMRIE_H);                           /* PMM and RESET Interrupt Enable */
1833 
SFR_16BIT(PM5CTL0);                           /* PMM Power Mode 5 Control Register 0 */
1834 
SFR_8BIT(PM5CTL0_L);                          /* PMM Power Mode 5 Control Register 0 */
1835 
SFR_8BIT(PM5CTL0_H);                          /* PMM Power Mode 5 Control Register 0 */
1836 
 
1837 
#define PMMPW                  (0xA500)       /* PMM Register Write Password */
1838 
#define PMMPW_H                (0xA5)         /* PMM Register Write Password for high word access */
1839 
 
1840 
/* PMMCTL0 Control Bits */
1841 
#define PMMCOREV0              (0x0001)       /* PMM Core Voltage Bit: 0 */
1842 
#define PMMCOREV1              (0x0002)       /* PMM Core Voltage Bit: 1 */
1843 
#define PMMSWBOR               (0x0004)       /* PMM Software BOR */
1844 
#define PMMSWPOR               (0x0008)       /* PMM Software POR */
1845 
#define PMMREGOFF              (0x0010)       /* PMM Turn Regulator off */
1846 
#define PMMHPMRE               (0x0080)       /* PMM Global High Power Module Request Enable */
1847 
 
1848 
/* PMMCTL0 Control Bits */
1849 
#define PMMCOREV0_L            (0x0001)       /* PMM Core Voltage Bit: 0 */
1850 
#define PMMCOREV1_L            (0x0002)       /* PMM Core Voltage Bit: 1 */
1851 
#define PMMSWBOR_L             (0x0004)       /* PMM Software BOR */
1852 
#define PMMSWPOR_L             (0x0008)       /* PMM Software POR */
1853 
#define PMMREGOFF_L            (0x0010)       /* PMM Turn Regulator off */
1854 
#define PMMHPMRE_L             (0x0080)       /* PMM Global High Power Module Request Enable */
1855 
 
1856 
/* PMMCTL0 Control Bits */
1857 
 
1858 
#define PMMCOREV_0             (0x0000)       /* PMM Core Voltage 0 (1.35V) */
1859 
#define PMMCOREV_1             (0x0001)       /* PMM Core Voltage 1 (1.55V) */
1860 
#define PMMCOREV_2             (0x0002)       /* PMM Core Voltage 2 (1.75V) */
1861 
#define PMMCOREV_3             (0x0003)       /* PMM Core Voltage 3 (1.85V) */
1862 
 
1863 
/* PMMCTL1 Control Bits */
1864 
#define PMMREFMD               (0x0001)       /* PMM Reference Mode */
1865 
#define PMMCMD0                (0x0010)       /* PMM Voltage Regulator Current Mode Bit: 0 */
1866 
#define PMMCMD1                (0x0020)       /* PMM Voltage Regulator Current Mode Bit: 1 */
1867 
 
1868 
/* PMMCTL1 Control Bits */
1869 
#define PMMREFMD_L             (0x0001)       /* PMM Reference Mode */
1870 
#define PMMCMD0_L              (0x0010)       /* PMM Voltage Regulator Current Mode Bit: 0 */
1871 
#define PMMCMD1_L              (0x0020)       /* PMM Voltage Regulator Current Mode Bit: 1 */
1872 
 
1873 
/* PMMCTL1 Control Bits */
1874 
 
1875 
/* SVSMHCTL Control Bits */
1876 
#define SVSMHRRL0              (0x0001)       /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
1877 
#define SVSMHRRL1              (0x0002)       /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
1878 
#define SVSMHRRL2              (0x0004)       /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
1879 
#define SVSMHDLYST             (0x0008)       /* SVS and SVM high side delay status */
1880 
#define SVSHMD                 (0x0010)       /* SVS high side mode */
1881 
#define SVSMHEVM               (0x0040)       /* SVS and SVM high side event mask */
1882 
#define SVSMHACE               (0x0080)       /* SVS and SVM high side auto control enable */
1883 
#define SVSHRVL0               (0x0100)       /* SVS high side reset voltage level Bit: 0 */
1884 
#define SVSHRVL1               (0x0200)       /* SVS high side reset voltage level Bit: 1 */
1885 
#define SVSHE                  (0x0400)       /* SVS high side enable */
1886 
#define SVSHFP                 (0x0800)       /* SVS high side full performace mode */
1887 
#define SVMHOVPE               (0x1000)       /* SVM high side over-voltage enable */
1888 
#define SVMHE                  (0x4000)       /* SVM high side enable */
1889 
#define SVMHFP                 (0x8000)       /* SVM high side full performace mode */
1890 
 
1891 
/* SVSMHCTL Control Bits */
1892 
#define SVSMHRRL0_L            (0x0001)       /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
1893 
#define SVSMHRRL1_L            (0x0002)       /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
1894 
#define SVSMHRRL2_L            (0x0004)       /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
1895 
#define SVSMHDLYST_L           (0x0008)       /* SVS and SVM high side delay status */
1896 
#define SVSHMD_L               (0x0010)       /* SVS high side mode */
1897 
#define SVSMHEVM_L             (0x0040)       /* SVS and SVM high side event mask */
1898 
#define SVSMHACE_L             (0x0080)       /* SVS and SVM high side auto control enable */
1899 
 
1900 
/* SVSMHCTL Control Bits */
1901 
#define SVSHRVL0_H             (0x0001)       /* SVS high side reset voltage level Bit: 0 */
1902 
#define SVSHRVL1_H             (0x0002)       /* SVS high side reset voltage level Bit: 1 */
1903 
#define SVSHE_H                (0x0004)       /* SVS high side enable */
1904 
#define SVSHFP_H               (0x0008)       /* SVS high side full performace mode */
1905 
#define SVMHOVPE_H             (0x0010)       /* SVM high side over-voltage enable */
1906 
#define SVMHE_H                (0x0040)       /* SVM high side enable */
1907 
#define SVMHFP_H               (0x0080)       /* SVM high side full performace mode */
1908 
 
1909 
#define SVSMHRRL_0             (0x0000)       /* SVS and SVM high side Reset Release Voltage Level 0 */
1910 
#define SVSMHRRL_1             (0x0001)       /* SVS and SVM high side Reset Release Voltage Level 1 */
1911 
#define SVSMHRRL_2             (0x0002)       /* SVS and SVM high side Reset Release Voltage Level 2 */
1912 
#define SVSMHRRL_3             (0x0003)       /* SVS and SVM high side Reset Release Voltage Level 3 */
1913 
#define SVSMHRRL_4             (0x0004)       /* SVS and SVM high side Reset Release Voltage Level 4 */
1914 
#define SVSMHRRL_5             (0x0005)       /* SVS and SVM high side Reset Release Voltage Level 5 */
1915 
#define SVSMHRRL_6             (0x0006)       /* SVS and SVM high side Reset Release Voltage Level 6 */
1916 
#define SVSMHRRL_7             (0x0007)       /* SVS and SVM high side Reset Release Voltage Level 7 */
1917 
 
1918 
#define SVSHRVL_0              (0x0000)       /* SVS high side Reset Release Voltage Level 0 */
1919 
#define SVSHRVL_1              (0x0100)       /* SVS high side Reset Release Voltage Level 1 */
1920 
#define SVSHRVL_2              (0x0200)       /* SVS high side Reset Release Voltage Level 2 */
1921 
#define SVSHRVL_3              (0x0300)       /* SVS high side Reset Release Voltage Level 3 */
1922 
 
1923 
/* SVSMLCTL Control Bits */
1924 
#define SVSMLRRL0              (0x0001)       /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
1925 
#define SVSMLRRL1              (0x0002)       /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
1926 
#define SVSMLRRL2              (0x0004)       /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
1927 
#define SVSMLDLYST             (0x0008)       /* SVS and SVM low side delay status */
1928 
#define SVSLMD                 (0x0010)       /* SVS low side mode */
1929 
#define SVSMLEVM               (0x0040)       /* SVS and SVM low side event mask */
1930 
#define SVSMLACE               (0x0080)       /* SVS and SVM low side auto control enable */
1931 
#define SVSLRVL0               (0x0100)       /* SVS low side reset voltage level Bit: 0 */
1932 
#define SVSLRVL1               (0x0200)       /* SVS low side reset voltage level Bit: 1 */
1933 
#define SVSLE                  (0x0400)       /* SVS low side enable */
1934 
#define SVSLFP                 (0x0800)       /* SVS low side full performace mode */
1935 
#define SVMLOVPE               (0x1000)       /* SVM low side over-voltage enable */
1936 
#define SVMLE                  (0x4000)       /* SVM low side enable */
1937 
#define SVMLFP                 (0x8000)       /* SVM low side full performace mode */
1938 
 
1939 
/* SVSMLCTL Control Bits */
1940 
#define SVSMLRRL0_L            (0x0001)       /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
1941 
#define SVSMLRRL1_L            (0x0002)       /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
1942 
#define SVSMLRRL2_L            (0x0004)       /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
1943 
#define SVSMLDLYST_L           (0x0008)       /* SVS and SVM low side delay status */
1944 
#define SVSLMD_L               (0x0010)       /* SVS low side mode */
1945 
#define SVSMLEVM_L             (0x0040)       /* SVS and SVM low side event mask */
1946 
#define SVSMLACE_L             (0x0080)       /* SVS and SVM low side auto control enable */
1947 
 
1948 
/* SVSMLCTL Control Bits */
1949 
#define SVSLRVL0_H             (0x0001)       /* SVS low side reset voltage level Bit: 0 */
1950 
#define SVSLRVL1_H             (0x0002)       /* SVS low side reset voltage level Bit: 1 */
1951 
#define SVSLE_H                (0x0004)       /* SVS low side enable */
1952 
#define SVSLFP_H               (0x0008)       /* SVS low side full performace mode */
1953 
#define SVMLOVPE_H             (0x0010)       /* SVM low side over-voltage enable */
1954 
#define SVMLE_H                (0x0040)       /* SVM low side enable */
1955 
#define SVMLFP_H               (0x0080)       /* SVM low side full performace mode */
1956 
 
1957 
#define SVSMLRRL_0             (0x0000)       /* SVS and SVM low side Reset Release Voltage Level 0 */
1958 
#define SVSMLRRL_1             (0x0001)       /* SVS and SVM low side Reset Release Voltage Level 1 */
1959 
#define SVSMLRRL_2             (0x0002)       /* SVS and SVM low side Reset Release Voltage Level 2 */
1960 
#define SVSMLRRL_3             (0x0003)       /* SVS and SVM low side Reset Release Voltage Level 3 */
1961 
#define SVSMLRRL_4             (0x0004)       /* SVS and SVM low side Reset Release Voltage Level 4 */
1962 
#define SVSMLRRL_5             (0x0005)       /* SVS and SVM low side Reset Release Voltage Level 5 */
1963 
#define SVSMLRRL_6             (0x0006)       /* SVS and SVM low side Reset Release Voltage Level 6 */
1964 
#define SVSMLRRL_7             (0x0007)       /* SVS and SVM low side Reset Release Voltage Level 7 */
1965 
 
1966 
#define SVSLRVL_0              (0x0000)       /* SVS low side Reset Release Voltage Level 0 */
1967 
#define SVSLRVL_1              (0x0100)       /* SVS low side Reset Release Voltage Level 1 */
1968 
#define SVSLRVL_2              (0x0200)       /* SVS low side Reset Release Voltage Level 2 */
1969 
#define SVSLRVL_3              (0x0300)       /* SVS low side Reset Release Voltage Level 3 */
1970 
 
1971 
/* SVSMIO Control Bits */
1972 
#define SVMLOE                 (0x0008)       /* SVM low side output enable */
1973 
#define SVMLVLROE              (0x0010)       /* SVM low side voltage level reached output enable */
1974 
#define SVMOUTPOL              (0x0020)       /* SVMOUT pin polarity */
1975 
#define SVMHOE                 (0x0800)       /* SVM high side output enable */
1976 
#define SVMHVLROE              (0x1000)       /* SVM high side voltage level reached output enable */
1977 
 
1978 
/* SVSMIO Control Bits */
1979 
#define SVMLOE_L               (0x0008)       /* SVM low side output enable */
1980 
#define SVMLVLROE_L            (0x0010)       /* SVM low side voltage level reached output enable */
1981 
#define SVMOUTPOL_L            (0x0020)       /* SVMOUT pin polarity */
1982 
 
1983 
/* SVSMIO Control Bits */
1984 
#define SVMHOE_H               (0x0008)       /* SVM high side output enable */
1985 
#define SVMHVLROE_H            (0x0010)       /* SVM high side voltage level reached output enable */
1986 
 
1987 
/* PMMIFG Control Bits */
1988 
#define SVSMLDLYIFG            (0x0001)       /* SVS and SVM low side Delay expired interrupt flag */
1989 
#define SVMLIFG                (0x0002)       /* SVM low side interrupt flag */
1990 
#define SVMLVLRIFG             (0x0004)       /* SVM low side Voltage Level Reached interrupt flag */
1991 
#define SVSMHDLYIFG            (0x0010)       /* SVS and SVM high side Delay expired interrupt flag */
1992 
#define SVMHIFG                (0x0020)       /* SVM high side interrupt flag */
1993 
#define SVMHVLRIFG             (0x0040)       /* SVM high side Voltage Level Reached interrupt flag */
1994 
#define PMMBORIFG              (0x0100)       /* PMM Software BOR interrupt flag */
1995 
#define PMMRSTIFG              (0x0200)       /* PMM RESET pin interrupt flag */
1996 
#define PMMPORIFG              (0x0400)       /* PMM Software POR interrupt flag */
1997 
#define SVSHIFG                (0x1000)       /* SVS low side interrupt flag */
1998 
#define SVSLIFG                (0x2000)       /* SVS high side interrupt flag */
1999 
#define PMMLPM5IFG             (0x8000)       /* LPM5 indication Flag */
2000 
 
2001 
/* PMMIFG Control Bits */
2002 
#define SVSMLDLYIFG_L          (0x0001)       /* SVS and SVM low side Delay expired interrupt flag */
2003 
#define SVMLIFG_L              (0x0002)       /* SVM low side interrupt flag */
2004 
#define SVMLVLRIFG_L           (0x0004)       /* SVM low side Voltage Level Reached interrupt flag */
2005 
#define SVSMHDLYIFG_L          (0x0010)       /* SVS and SVM high side Delay expired interrupt flag */
2006 
#define SVMHIFG_L              (0x0020)       /* SVM high side interrupt flag */
2007 
#define SVMHVLRIFG_L           (0x0040)       /* SVM high side Voltage Level Reached interrupt flag */
2008 
 
2009 
/* PMMIFG Control Bits */
2010 
#define PMMBORIFG_H            (0x0001)       /* PMM Software BOR interrupt flag */
2011 
#define PMMRSTIFG_H            (0x0002)       /* PMM RESET pin interrupt flag */
2012 
#define PMMPORIFG_H            (0x0004)       /* PMM Software POR interrupt flag */
2013 
#define SVSHIFG_H              (0x0010)       /* SVS low side interrupt flag */
2014 
#define SVSLIFG_H              (0x0020)       /* SVS high side interrupt flag */
2015 
#define PMMLPM5IFG_H           (0x0080)       /* LPM5 indication Flag */
2016 
 
2017 
#define PMMRSTLPM5IFG          PMMLPM5IFG     /* LPM5 indication Flag */
2018 
 
2019 
/* PMMIE and RESET Control Bits */
2020 
#define SVSMLDLYIE             (0x0001)       /* SVS and SVM low side Delay expired interrupt enable */
2021 
#define SVMLIE                 (0x0002)       /* SVM low side interrupt enable */
2022 
#define SVMLVLRIE              (0x0004)       /* SVM low side Voltage Level Reached interrupt enable */
2023 
#define SVSMHDLYIE             (0x0010)       /* SVS and SVM high side Delay expired interrupt enable */
2024 
#define SVMHIE                 (0x0020)       /* SVM high side interrupt enable */
2025 
#define SVMHVLRIE              (0x0040)       /* SVM high side Voltage Level Reached interrupt enable */
2026 
#define SVSLPE                 (0x0100)       /* SVS low side POR enable */
2027 
#define SVMLVLRPE              (0x0200)       /* SVM low side Voltage Level reached POR enable */
2028 
#define SVSHPE                 (0x1000)       /* SVS high side POR enable */
2029 
#define SVMHVLRPE              (0x2000)       /* SVM high side Voltage Level reached POR enable */
2030 
 
2031 
/* PMMIE and RESET Control Bits */
2032 
#define SVSMLDLYIE_L           (0x0001)       /* SVS and SVM low side Delay expired interrupt enable */
2033 
#define SVMLIE_L               (0x0002)       /* SVM low side interrupt enable */
2034 
#define SVMLVLRIE_L            (0x0004)       /* SVM low side Voltage Level Reached interrupt enable */
2035 
#define SVSMHDLYIE_L           (0x0010)       /* SVS and SVM high side Delay expired interrupt enable */
2036 
#define SVMHIE_L               (0x0020)       /* SVM high side interrupt enable */
2037 
#define SVMHVLRIE_L            (0x0040)       /* SVM high side Voltage Level Reached interrupt enable */
2038 
 
2039 
/* PMMIE and RESET Control Bits */
2040 
#define SVSLPE_H               (0x0001)       /* SVS low side POR enable */
2041 
#define SVMLVLRPE_H            (0x0002)       /* SVM low side Voltage Level reached POR enable */
2042 
#define SVSHPE_H               (0x0010)       /* SVS high side POR enable */
2043 
#define SVMHVLRPE_H            (0x0020)       /* SVM high side Voltage Level reached POR enable */
2044 
 
2045 
/* PM5CTL0 Power Mode 5 Control Bits */
2046 
#define LOCKLPM5               (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
2047 
 
2048 
/* PM5CTL0 Power Mode 5 Control Bits */
2049 
#define LOCKLPM5_L             (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
2050 
 
2051 
/* PM5CTL0 Power Mode 5 Control Bits */
2052 
#define LOCKIO                 LOCKLPM5       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
2053 
 
2054 
/*************************************************************
2055 
* RAM Control Module
2056 
*************************************************************/
2057 
#define __MSP430_HAS_RC__                     /* Definition to show that Module is available */
2058 
#define __MSP430_BASEADDRESS_RC__ 0x0158
2059 
 
2060 
SFR_16BIT(RCCTL0);                            /* Ram Controller Control Register */
2061 
SFR_8BIT(RCCTL0_L);                           /* Ram Controller Control Register */
2062 
SFR_8BIT(RCCTL0_H);                           /* Ram Controller Control Register */
2063 
 
2064 
/* RCCTL0 Control Bits */
2065 
#define RCRS0OFF               (0x0001)       /* RAM Controller RAM Sector 0 Off */
2066 
#define RCRS1OFF               (0x0002)       /* RAM Controller RAM Sector 1 Off */
2067 
#define RCRS2OFF               (0x0004)       /* RAM Controller RAM Sector 2 Off */
2068 
#define RCRS3OFF               (0x0008)       /* RAM Controller RAM Sector 3 Off */
2069 
#define RCRS7OFF               (0x0080)       /* RAM Controller RAM Sector 7 (USB) Off */
2070 
 
2071 
/* RCCTL0 Control Bits */
2072 
#define RCRS0OFF_L             (0x0001)       /* RAM Controller RAM Sector 0 Off */
2073 
#define RCRS1OFF_L             (0x0002)       /* RAM Controller RAM Sector 1 Off */
2074 
#define RCRS2OFF_L             (0x0004)       /* RAM Controller RAM Sector 2 Off */
2075 
#define RCRS3OFF_L             (0x0008)       /* RAM Controller RAM Sector 3 Off */
2076 
#define RCRS7OFF_L             (0x0080)       /* RAM Controller RAM Sector 7 (USB) Off */
2077 
 
2078 
/* RCCTL0 Control Bits */
2079 
 
2080 
#define RCKEY                  (0x5A00)
2081 
 
2082 
/************************************************************
2083 
* Shared Reference
2084 
************************************************************/
2085 
#define __MSP430_HAS_REF__                    /* Definition to show that Module is available */
2086 
#define __MSP430_BASEADDRESS_REF__ 0x01B0
2087 
 
2088 
SFR_16BIT(REFCTL0);                           /* REF Shared Reference control register 0 */
2089 
SFR_8BIT(REFCTL0_L);                          /* REF Shared Reference control register 0 */
2090 
SFR_8BIT(REFCTL0_H);                          /* REF Shared Reference control register 0 */
2091 
 
2092 
/* REFCTL0 Control Bits */
2093 
#define REFON                  (0x0001)       /* REF Reference On */
2094 
#define REFOUT                 (0x0002)       /* REF Reference output Buffer On */
2095 
//#define RESERVED            (0x0004)  /* Reserved */
2096 
#define REFTCOFF               (0x0008)       /* REF Temp.Sensor off */
2097 
#define REFVSEL0               (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
2098 
#define REFVSEL1               (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
2099 
//#define RESERVED            (0x0040)  /* Reserved */
2100 
#define REFMSTR                (0x0080)       /* REF Master Control */
2101 
#define REFGENACT              (0x0100)       /* REF Reference generator active */
2102 
#define REFBGACT               (0x0200)       /* REF Reference bandgap active */
2103 
#define REFGENBUSY             (0x0400)       /* REF Reference generator busy */
2104 
#define BGMODE                 (0x0800)       /* REF Bandgap mode */
2105 
//#define RESERVED            (0x1000)  /* Reserved */
2106 
//#define RESERVED            (0x2000)  /* Reserved */
2107 
//#define RESERVED            (0x4000)  /* Reserved */
2108 
//#define RESERVED            (0x8000)  /* Reserved */
2109 
 
2110 
/* REFCTL0 Control Bits */
2111 
#define REFON_L                (0x0001)       /* REF Reference On */
2112 
#define REFOUT_L               (0x0002)       /* REF Reference output Buffer On */
2113 
//#define RESERVED            (0x0004)  /* Reserved */
2114 
#define REFTCOFF_L             (0x0008)       /* REF Temp.Sensor off */
2115 
#define REFVSEL0_L             (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
2116 
#define REFVSEL1_L             (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
2117 
//#define RESERVED            (0x0040)  /* Reserved */
2118 
#define REFMSTR_L              (0x0080)       /* REF Master Control */
2119 
//#define RESERVED            (0x1000)  /* Reserved */
2120 
//#define RESERVED            (0x2000)  /* Reserved */
2121 
//#define RESERVED            (0x4000)  /* Reserved */
2122 
//#define RESERVED            (0x8000)  /* Reserved */
2123 
 
2124 
/* REFCTL0 Control Bits */
2125 
//#define RESERVED            (0x0004)  /* Reserved */
2126 
//#define RESERVED            (0x0040)  /* Reserved */
2127 
#define REFGENACT_H            (0x0001)       /* REF Reference generator active */
2128 
#define REFBGACT_H             (0x0002)       /* REF Reference bandgap active */
2129 
#define REFGENBUSY_H           (0x0004)       /* REF Reference generator busy */
2130 
#define BGMODE_H               (0x0008)       /* REF Bandgap mode */
2131 
//#define RESERVED            (0x1000)  /* Reserved */
2132 
//#define RESERVED            (0x2000)  /* Reserved */
2133 
//#define RESERVED            (0x4000)  /* Reserved */
2134 
//#define RESERVED            (0x8000)  /* Reserved */
2135 
 
2136 
#define REFVSEL_0              (0x0000)       /* REF Reference Voltage Level Select 1.5V */
2137 
#define REFVSEL_1              (0x0010)       /* REF Reference Voltage Level Select 2.0V */
2138 
#define REFVSEL_2              (0x0020)       /* REF Reference Voltage Level Select 2.5V */
2139 
#define REFVSEL_3              (0x0030)       /* REF Reference Voltage Level Select 2.5V */
2140 
 
2141 
/************************************************************
2142 
* Real Time Clock
2143 
************************************************************/
2144 
#define __MSP430_HAS_RTC_B__                  /* Definition to show that Module is available */
2145 
#define __MSP430_BASEADDRESS_RTC_B__ 0x04A0
2146 
 
2147 
SFR_16BIT(RTCCTL01);                          /* Real Timer Control 0/1 */
2148 
SFR_8BIT(RTCCTL01_L);                         /* Real Timer Control 0/1 */
2149 
SFR_8BIT(RTCCTL01_H);                         /* Real Timer Control 0/1 */
2150 
SFR_16BIT(RTCCTL23);                          /* Real Timer Control 2/3 */
2151 
SFR_8BIT(RTCCTL23_L);                         /* Real Timer Control 2/3 */
2152 
SFR_8BIT(RTCCTL23_H);                         /* Real Timer Control 2/3 */
2153 
SFR_16BIT(RTCPS0CTL);                         /* Real Timer Prescale Timer 0 Control */
2154 
SFR_8BIT(RTCPS0CTL_L);                        /* Real Timer Prescale Timer 0 Control */
2155 
SFR_8BIT(RTCPS0CTL_H);                        /* Real Timer Prescale Timer 0 Control */
2156 
SFR_16BIT(RTCPS1CTL);                         /* Real Timer Prescale Timer 1 Control */
2157 
SFR_8BIT(RTCPS1CTL_L);                        /* Real Timer Prescale Timer 1 Control */
2158 
SFR_8BIT(RTCPS1CTL_H);                        /* Real Timer Prescale Timer 1 Control */
2159 
SFR_16BIT(RTCPS);                             /* Real Timer Prescale Timer Control */
2160 
SFR_8BIT(RTCPS_L);                            /* Real Timer Prescale Timer Control */
2161 
SFR_8BIT(RTCPS_H);                            /* Real Timer Prescale Timer Control */
2162 
SFR_16BIT(RTCIV);                             /* Real Time Clock Interrupt Vector */
2163 
SFR_16BIT(RTCTIM0);                           /* Real Time Clock Time 0 */
2164 
SFR_8BIT(RTCTIM0_L);                          /* Real Time Clock Time 0 */
2165 
SFR_8BIT(RTCTIM0_H);                          /* Real Time Clock Time 0 */
2166 
SFR_16BIT(RTCTIM1);                           /* Real Time Clock Time 1 */
2167 
SFR_8BIT(RTCTIM1_L);                          /* Real Time Clock Time 1 */
2168 
SFR_8BIT(RTCTIM1_H);                          /* Real Time Clock Time 1 */
2169 
SFR_16BIT(RTCDATE);                           /* Real Time Clock Date */
2170 
SFR_8BIT(RTCDATE_L);                          /* Real Time Clock Date */
2171 
SFR_8BIT(RTCDATE_H);                          /* Real Time Clock Date */
2172 
SFR_16BIT(RTCYEAR);                           /* Real Time Clock Year */
2173 
SFR_8BIT(RTCYEAR_L);                          /* Real Time Clock Year */
2174 
SFR_8BIT(RTCYEAR_H);                          /* Real Time Clock Year */
2175 
SFR_16BIT(RTCAMINHR);                         /* Real Time Clock Alarm Min/Hour */
2176 
SFR_8BIT(RTCAMINHR_L);                        /* Real Time Clock Alarm Min/Hour */
2177 
SFR_8BIT(RTCAMINHR_H);                        /* Real Time Clock Alarm Min/Hour */
2178 
SFR_16BIT(RTCADOWDAY);                        /* Real Time Clock Alarm day of week/day */
2179 
SFR_8BIT(RTCADOWDAY_L);                       /* Real Time Clock Alarm day of week/day */
2180 
SFR_8BIT(RTCADOWDAY_H);                       /* Real Time Clock Alarm day of week/day */
2181 
SFR_16BIT(BIN2BCD);                           /* Real Time Binary-to-BCD conversion register */
2182 
SFR_16BIT(BCD2BIN);                           /* Real Time BCD-to-binary conversion register */
2183 
 
2184 
#define RTCCTL0                RTCCTL01_L     /* Real Time Clock Control 0 */
2185 
#define RTCCTL1                RTCCTL01_H     /* Real Time Clock Control 1 */
2186 
#define RTCCTL2                RTCCTL23_L     /* Real Time Clock Control 2 */
2187 
#define RTCCTL3                RTCCTL23_H     /* Real Time Clock Control 3 */
2188 
#define RTCNT12                RTCTIM0
2189 
#define RTCNT34                RTCTIM1
2190 
#define RTCNT1                 RTCTIM0_L
2191 
#define RTCNT2                 RTCTIM0_H
2192 
#define RTCNT3                 RTCTIM1_L
2193 
#define RTCNT4                 RTCTIM1_H
2194 
#define RTCSEC                 RTCTIM0_L
2195 
#define RTCMIN                 RTCTIM0_H
2196 
#define RTCHOUR                RTCTIM1_L
2197 
#define RTCDOW                 RTCTIM1_H
2198 
#define RTCDAY                 RTCDATE_L
2199 
#define RTCMON                 RTCDATE_H
2200 
#define RTCYEARL               RTCYEAR_L
2201 
#define RTCYEARH               RTCYEAR_H
2202 
#define RT0PS                  RTCPS_L
2203 
#define RT1PS                  RTCPS_H
2204 
#define RTCAMIN                RTCAMINHR_L    /* Real Time Clock Alarm Min */
2205 
#define RTCAHOUR               RTCAMINHR_H    /* Real Time Clock Alarm Hour */
2206 
#define RTCADOW                RTCADOWDAY_L   /* Real Time Clock Alarm day of week */
2207 
#define RTCADAY                RTCADOWDAY_H   /* Real Time Clock Alarm day */
2208 
 
2209 
/* RTCCTL01 Control Bits */
2210 
#define RTCBCD                 (0x8000)       /* RTC BCD  0:Binary / 1:BCD */
2211 
#define RTCHOLD                (0x4000)       /* RTC Hold */
2212 
//#define RESERVED            (0x2000)     /* RESERVED */
2213 
#define RTCRDY                 (0x1000)       /* RTC Ready */
2214 
//#define RESERVED            (0x0800)     /* RESERVED */
2215 
//#define RESERVED            (0x0400)     /* RESERVED */
2216 
#define RTCTEV1                (0x0200)       /* RTC Time Event 1 */
2217 
#define RTCTEV0                (0x0100)       /* RTC Time Event 0 */
2218 
#define RTCOFIE                (0x0080)       /* RTC 32kHz cyrstal oscillator fault interrupt enable */
2219 
#define RTCTEVIE               (0x0040)       /* RTC Time Event Interrupt Enable Flag */
2220 
#define RTCAIE                 (0x0020)       /* RTC Alarm Interrupt Enable Flag */
2221 
#define RTCRDYIE               (0x0010)       /* RTC Ready Interrupt Enable Flag */
2222 
#define RTCOFIFG               (0x0008)       /* RTC 32kHz cyrstal oscillator fault interrupt flag */
2223 
#define RTCTEVIFG              (0x0004)       /* RTC Time Event Interrupt Flag */
2224 
#define RTCAIFG                (0x0002)       /* RTC Alarm Interrupt Flag */
2225 
#define RTCRDYIFG              (0x0001)       /* RTC Ready Interrupt Flag */
2226 
 
2227 
/* RTCCTL01 Control Bits */
2228 
//#define RESERVED            (0x2000)     /* RESERVED */
2229 
//#define RESERVED            (0x0800)     /* RESERVED */
2230 
//#define RESERVED            (0x0400)     /* RESERVED */
2231 
#define RTCOFIE_L              (0x0080)       /* RTC 32kHz cyrstal oscillator fault interrupt enable */
2232 
#define RTCTEVIE_L             (0x0040)       /* RTC Time Event Interrupt Enable Flag */
2233 
#define RTCAIE_L               (0x0020)       /* RTC Alarm Interrupt Enable Flag */
2234 
#define RTCRDYIE_L             (0x0010)       /* RTC Ready Interrupt Enable Flag */
2235 
#define RTCOFIFG_L             (0x0008)       /* RTC 32kHz cyrstal oscillator fault interrupt flag */
2236 
#define RTCTEVIFG_L            (0x0004)       /* RTC Time Event Interrupt Flag */
2237 
#define RTCAIFG_L              (0x0002)       /* RTC Alarm Interrupt Flag */
2238 
#define RTCRDYIFG_L            (0x0001)       /* RTC Ready Interrupt Flag */
2239 
 
2240 
/* RTCCTL01 Control Bits */
2241 
#define RTCBCD_H               (0x0080)       /* RTC BCD  0:Binary / 1:BCD */
2242 
#define RTCHOLD_H              (0x0040)       /* RTC Hold */
2243 
//#define RESERVED            (0x2000)     /* RESERVED */
2244 
#define RTCRDY_H               (0x0010)       /* RTC Ready */
2245 
//#define RESERVED            (0x0800)     /* RESERVED */
2246 
//#define RESERVED            (0x0400)     /* RESERVED */
2247 
#define RTCTEV1_H              (0x0002)       /* RTC Time Event 1 */
2248 
#define RTCTEV0_H              (0x0001)       /* RTC Time Event 0 */
2249 
 
2250 
#define RTCTEV_0               (0x0000)       /* RTC Time Event: 0 (Min. changed) */
2251 
#define RTCTEV_1               (0x0100)       /* RTC Time Event: 1 (Hour changed) */
2252 
#define RTCTEV_2               (0x0200)       /* RTC Time Event: 2 (12:00 changed) */
2253 
#define RTCTEV_3               (0x0300)       /* RTC Time Event: 3 (00:00 changed) */
2254 
#define RTCTEV__MIN            (0x0000)       /* RTC Time Event: 0 (Min. changed) */
2255 
#define RTCTEV__HOUR           (0x0100)       /* RTC Time Event: 1 (Hour changed) */
2256 
#define RTCTEV__0000           (0x0200)       /* RTC Time Event: 3 (00:00 changed) */
2257 
#define RTCTEV__1200           (0x0300)       /* RTC Time Event: 2 (12:00 changed) */
2258 
 
2259 
/* RTCCTL23 Control Bits */
2260 
#define RTCCALF1               (0x0200)       /* RTC Calibration Frequency Bit 1 */
2261 
#define RTCCALF0               (0x0100)       /* RTC Calibration Frequency Bit 0 */
2262 
#define RTCCALS                (0x0080)       /* RTC Calibration Sign */
2263 
//#define Reserved          (0x0040)
2264 
#define RTCCAL5                (0x0020)       /* RTC Calibration Bit 5 */
2265 
#define RTCCAL4                (0x0010)       /* RTC Calibration Bit 4 */
2266 
#define RTCCAL3                (0x0008)       /* RTC Calibration Bit 3 */
2267 
#define RTCCAL2                (0x0004)       /* RTC Calibration Bit 2 */
2268 
#define RTCCAL1                (0x0002)       /* RTC Calibration Bit 1 */
2269 
#define RTCCAL0                (0x0001)       /* RTC Calibration Bit 0 */
2270 
 
2271 
/* RTCCTL23 Control Bits */
2272 
#define RTCCALS_L              (0x0080)       /* RTC Calibration Sign */
2273 
//#define Reserved          (0x0040)
2274 
#define RTCCAL5_L              (0x0020)       /* RTC Calibration Bit 5 */
2275 
#define RTCCAL4_L              (0x0010)       /* RTC Calibration Bit 4 */
2276 
#define RTCCAL3_L              (0x0008)       /* RTC Calibration Bit 3 */
2277 
#define RTCCAL2_L              (0x0004)       /* RTC Calibration Bit 2 */
2278 
#define RTCCAL1_L              (0x0002)       /* RTC Calibration Bit 1 */
2279 
#define RTCCAL0_L              (0x0001)       /* RTC Calibration Bit 0 */
2280 
 
2281 
/* RTCCTL23 Control Bits */
2282 
#define RTCCALF1_H             (0x0002)       /* RTC Calibration Frequency Bit 1 */
2283 
#define RTCCALF0_H             (0x0001)       /* RTC Calibration Frequency Bit 0 */
2284 
//#define Reserved          (0x0040)
2285 
 
2286 
#define RTCCALF_0              (0x0000)       /* RTC Calibration Frequency: No Output */
2287 
#define RTCCALF_1              (0x0100)       /* RTC Calibration Frequency: 512 Hz */
2288 
#define RTCCALF_2              (0x0200)       /* RTC Calibration Frequency: 256 Hz */
2289 
#define RTCCALF_3              (0x0300)       /* RTC Calibration Frequency: 1 Hz */
2290 
 
2291 
/* RTCPS0CTL Control Bits */
2292 
//#define Reserved          (0x0080)
2293 
//#define Reserved          (0x0040)
2294 
//#define Reserved          (0x0020)
2295 
#define RT0IP2                 (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
2296 
#define RT0IP1                 (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
2297 
#define RT0IP0                 (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
2298 
#define RT0PSIE                (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
2299 
#define RT0PSIFG               (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
2300 
 
2301 
/* RTCPS0CTL Control Bits */
2302 
//#define Reserved          (0x0080)
2303 
//#define Reserved          (0x0040)
2304 
//#define Reserved          (0x0020)
2305 
#define RT0IP2_L               (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
2306 
#define RT0IP1_L               (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
2307 
#define RT0IP0_L               (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
2308 
#define RT0PSIE_L              (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
2309 
#define RT0PSIFG_L             (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
2310 
 
2311 
/* RTCPS0CTL Control Bits */
2312 
//#define Reserved          (0x0080)
2313 
//#define Reserved          (0x0040)
2314 
//#define Reserved          (0x0020)
2315 
 
2316 
#define RT0IP_0                (0x0000)       /* RTC Prescale Timer 0 Interrupt Interval /2 */
2317 
#define RT0IP_1                (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval /4 */
2318 
#define RT0IP_2                (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval /8 */
2319 
#define RT0IP_3                (0x000C)       /* RTC Prescale Timer 0 Interrupt Interval /16 */
2320 
#define RT0IP_4                (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval /32 */
2321 
#define RT0IP_5                (0x0014)       /* RTC Prescale Timer 0 Interrupt Interval /64 */
2322 
#define RT0IP_6                (0x0018)       /* RTC Prescale Timer 0 Interrupt Interval /128 */
2323 
#define RT0IP_7                (0x001C)       /* RTC Prescale Timer 0 Interrupt Interval /256 */
2324 
 
2325 
#define RT0IP__2               (0x0000)       /* RTC Prescale Timer 0 Interrupt Interval /2 */
2326 
#define RT0IP__4               (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval /4 */
2327 
#define RT0IP__8               (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval /8 */
2328 
#define RT0IP__16              (0x000C)       /* RTC Prescale Timer 0 Interrupt Interval /16 */
2329 
#define RT0IP__32              (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval /32 */
2330 
#define RT0IP__64              (0x0014)       /* RTC Prescale Timer 0 Interrupt Interval /64 */
2331 
#define RT0IP__128             (0x0018)       /* RTC Prescale Timer 0 Interrupt Interval /128 */
2332 
#define RT0IP__256             (0x001C)       /* RTC Prescale Timer 0 Interrupt Interval /256 */
2333 
 
2334 
/* RTCPS1CTL Control Bits */
2335 
//#define Reserved          (0x0080)
2336 
//#define Reserved          (0x0040)
2337 
//#define Reserved          (0x0020)
2338 
#define RT1IP2                 (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
2339 
#define RT1IP1                 (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
2340 
#define RT1IP0                 (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
2341 
#define RT1PSIE                (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
2342 
#define RT1PSIFG               (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
2343 
 
2344 
/* RTCPS1CTL Control Bits */
2345 
//#define Reserved          (0x0080)
2346 
//#define Reserved          (0x0040)
2347 
//#define Reserved          (0x0020)
2348 
#define RT1IP2_L               (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
2349 
#define RT1IP1_L               (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
2350 
#define RT1IP0_L               (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
2351 
#define RT1PSIE_L              (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
2352 
#define RT1PSIFG_L             (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
2353 
 
2354 
/* RTCPS1CTL Control Bits */
2355 
//#define Reserved          (0x0080)
2356 
//#define Reserved          (0x0040)
2357 
//#define Reserved          (0x0020)
2358 
 
2359 
#define RT1IP_0                (0x0000)       /* RTC Prescale Timer 1 Interrupt Interval /2 */
2360 
#define RT1IP_1                (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval /4 */
2361 
#define RT1IP_2                (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval /8 */
2362 
#define RT1IP_3                (0x000C)       /* RTC Prescale Timer 1 Interrupt Interval /16 */
2363 
#define RT1IP_4                (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval /32 */
2364 
#define RT1IP_5                (0x0014)       /* RTC Prescale Timer 1 Interrupt Interval /64 */
2365 
#define RT1IP_6                (0x0018)       /* RTC Prescale Timer 1 Interrupt Interval /128 */
2366 
#define RT1IP_7                (0x001C)       /* RTC Prescale Timer 1 Interrupt Interval /256 */
2367 
 
2368 
#define RT1IP__2               (0x0000)       /* RTC Prescale Timer 1 Interrupt Interval /2 */
2369 
#define RT1IP__4               (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval /4 */
2370 
#define RT1IP__8               (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval /8 */
2371 
#define RT1IP__16              (0x000C)       /* RTC Prescale Timer 1 Interrupt Interval /16 */
2372 
#define RT1IP__32              (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval /32 */
2373 
#define RT1IP__64              (0x0014)       /* RTC Prescale Timer 1 Interrupt Interval /64 */
2374 
#define RT1IP__128             (0x0018)       /* RTC Prescale Timer 1 Interrupt Interval /128 */
2375 
#define RT1IP__256             (0x001C)       /* RTC Prescale Timer 1 Interrupt Interval /256 */
2376 
 
2377 
/* RTC Definitions */
2378 
#define RTCIV_NONE             (0x0000)       /* No Interrupt pending */
2379 
#define RTCIV_RTCRDYIFG        (0x0002)       /* RTC ready: RTCRDYIFG */
2380 
#define RTCIV_RTCTEVIFG        (0x0004)       /* RTC interval timer: RTCTEVIFG */
2381 
#define RTCIV_RTCAIFG          (0x0006)       /* RTC user alarm: RTCAIFG */
2382 
#define RTCIV_RT0PSIFG         (0x0008)       /* RTC prescaler 0: RT0PSIFG */
2383 
#define RTCIV_RT1PSIFG         (0x000A)       /* RTC prescaler 1: RT1PSIFG */
2384 
#define RTCIV_RTCOFIFG         (0x000C)       /* RTC Oscillator fault */
2385 
 
2386 
/* Legacy Definitions */
2387 
#define RTC_NONE               (0x0000)       /* No Interrupt pending */
2388 
#define RTC_RTCRDYIFG          (0x0002)       /* RTC ready: RTCRDYIFG */
2389 
#define RTC_RTCTEVIFG          (0x0004)       /* RTC interval timer: RTCTEVIFG */
2390 
#define RTC_RTCAIFG            (0x0006)       /* RTC user alarm: RTCAIFG */
2391 
#define RTC_RT0PSIFG           (0x0008)       /* RTC prescaler 0: RT0PSIFG */
2392 
#define RTC_RT1PSIFG           (0x000A)       /* RTC prescaler 1: RT1PSIFG */
2393 
#define RTC_RTCOFIFG           (0x000C)       /* RTC Oscillator fault */
2394 
 
2395 
/************************************************************
2396 
* SFR - Special Function Register Module
2397 
************************************************************/
2398 
#define __MSP430_HAS_SFR__                    /* Definition to show that Module is available */
2399 
#define __MSP430_BASEADDRESS_SFR__ 0x0100
2400 
 
2401 
SFR_16BIT(SFRIE1);                            /* Interrupt Enable 1 */
2402 
SFR_8BIT(SFRIE1_L);                           /* Interrupt Enable 1 */
2403 
SFR_8BIT(SFRIE1_H);                           /* Interrupt Enable 1 */
2404 
 
2405 
/* SFRIE1 Control Bits */
2406 
#define WDTIE                  (0x0001)       /* WDT Interrupt Enable */
2407 
#define OFIE                   (0x0002)       /* Osc Fault Enable */
2408 
//#define Reserved          (0x0004)
2409 
#define VMAIE                  (0x0008)       /* Vacant Memory Interrupt Enable */
2410 
#define NMIIE                  (0x0010)       /* NMI Interrupt Enable */
2411 
#define ACCVIE                 (0x0020)       /* Flash Access Violation Interrupt Enable */
2412 
#define JMBINIE                (0x0040)       /* JTAG Mail Box input Interrupt Enable */
2413 
#define JMBOUTIE               (0x0080)       /* JTAG Mail Box output Interrupt Enable */
2414 
 
2415 
#define WDTIE_L                (0x0001)       /* WDT Interrupt Enable */
2416 
#define OFIE_L                 (0x0002)       /* Osc Fault Enable */
2417 
//#define Reserved          (0x0004)
2418 
#define VMAIE_L                (0x0008)       /* Vacant Memory Interrupt Enable */
2419 
#define NMIIE_L                (0x0010)       /* NMI Interrupt Enable */
2420 
#define ACCVIE_L               (0x0020)       /* Flash Access Violation Interrupt Enable */
2421 
#define JMBINIE_L              (0x0040)       /* JTAG Mail Box input Interrupt Enable */
2422 
#define JMBOUTIE_L             (0x0080)       /* JTAG Mail Box output Interrupt Enable */
2423 
 
2424 
//#define Reserved          (0x0004)
2425 
 
2426 
SFR_16BIT(SFRIFG1);                           /* Interrupt Flag 1 */
2427 
SFR_8BIT(SFRIFG1_L);                          /* Interrupt Flag 1 */
2428 
SFR_8BIT(SFRIFG1_H);                          /* Interrupt Flag 1 */
2429 
/* SFRIFG1 Control Bits */
2430 
#define WDTIFG                 (0x0001)       /* WDT Interrupt Flag */
2431 
#define OFIFG                  (0x0002)       /* Osc Fault Flag */
2432 
//#define Reserved          (0x0004)
2433 
#define VMAIFG                 (0x0008)       /* Vacant Memory Interrupt Flag */
2434 
#define NMIIFG                 (0x0010)       /* NMI Interrupt Flag */
2435 
//#define Reserved          (0x0020)
2436 
#define JMBINIFG               (0x0040)       /* JTAG Mail Box input Interrupt Flag */
2437 
#define JMBOUTIFG              (0x0080)       /* JTAG Mail Box output Interrupt Flag */
2438 
 
2439 
#define WDTIFG_L               (0x0001)       /* WDT Interrupt Flag */
2440 
#define OFIFG_L                (0x0002)       /* Osc Fault Flag */
2441 
//#define Reserved          (0x0004)
2442 
#define VMAIFG_L               (0x0008)       /* Vacant Memory Interrupt Flag */
2443 
#define NMIIFG_L               (0x0010)       /* NMI Interrupt Flag */
2444 
//#define Reserved          (0x0020)
2445 
#define JMBINIFG_L             (0x0040)       /* JTAG Mail Box input Interrupt Flag */
2446 
#define JMBOUTIFG_L            (0x0080)       /* JTAG Mail Box output Interrupt Flag */
2447 
 
2448 
//#define Reserved          (0x0004)
2449 
//#define Reserved          (0x0020)
2450 
 
2451 
SFR_16BIT(SFRRPCR);                           /* RESET Pin Control Register */
2452 
SFR_8BIT(SFRRPCR_L);                          /* RESET Pin Control Register */
2453 
SFR_8BIT(SFRRPCR_H);                          /* RESET Pin Control Register */
2454 
/* SFRRPCR Control Bits */
2455 
#define SYSNMI                 (0x0001)       /* NMI select */
2456 
#define SYSNMIIES              (0x0002)       /* NMI edge select */
2457 
#define SYSRSTUP               (0x0004)       /* RESET Pin pull down/up select */
2458 
#define SYSRSTRE               (0x0008)       /* RESET Pin Resistor enable */
2459 
 
2460 
#define SYSNMI_L               (0x0001)       /* NMI select */
2461 
#define SYSNMIIES_L            (0x0002)       /* NMI edge select */
2462 
#define SYSRSTUP_L             (0x0004)       /* RESET Pin pull down/up select */
2463 
#define SYSRSTRE_L             (0x0008)       /* RESET Pin Resistor enable */
2464 
 
2465 
/************************************************************
2466 
* SYS - System Module
2467 
************************************************************/
2468 
#define __MSP430_HAS_SYS__                    /* Definition to show that Module is available */
2469 
#define __MSP430_BASEADDRESS_SYS__ 0x0180
2470 
 
2471 
SFR_16BIT(SYSCTL);                            /* System control */
2472 
SFR_8BIT(SYSCTL_L);                           /* System control */
2473 
SFR_8BIT(SYSCTL_H);                           /* System control */
2474 
SFR_16BIT(SYSBSLC);                           /* Boot strap configuration area */
2475 
SFR_8BIT(SYSBSLC_L);                          /* Boot strap configuration area */
2476 
SFR_8BIT(SYSBSLC_H);                          /* Boot strap configuration area */
2477 
SFR_16BIT(SYSJMBC);                           /* JTAG mailbox control */
2478 
SFR_8BIT(SYSJMBC_L);                          /* JTAG mailbox control */
2479 
SFR_8BIT(SYSJMBC_H);                          /* JTAG mailbox control */
2480 
SFR_16BIT(SYSJMBI0);                          /* JTAG mailbox input 0 */
2481 
SFR_8BIT(SYSJMBI0_L);                         /* JTAG mailbox input 0 */
2482 
SFR_8BIT(SYSJMBI0_H);                         /* JTAG mailbox input 0 */
2483 
SFR_16BIT(SYSJMBI1);                          /* JTAG mailbox input 1 */
2484 
SFR_8BIT(SYSJMBI1_L);                         /* JTAG mailbox input 1 */
2485 
SFR_8BIT(SYSJMBI1_H);                         /* JTAG mailbox input 1 */
2486 
SFR_16BIT(SYSJMBO0);                          /* JTAG mailbox output 0 */
2487 
SFR_8BIT(SYSJMBO0_L);                         /* JTAG mailbox output 0 */
2488 
SFR_8BIT(SYSJMBO0_H);                         /* JTAG mailbox output 0 */
2489 
SFR_16BIT(SYSJMBO1);                          /* JTAG mailbox output 1 */
2490 
SFR_8BIT(SYSJMBO1_L);                         /* JTAG mailbox output 1 */
2491 
SFR_8BIT(SYSJMBO1_H);                         /* JTAG mailbox output 1 */
2492 
 
2493 
SFR_16BIT(SYSBERRIV);                         /* Bus Error vector generator */
2494 
SFR_8BIT(SYSBERRIV_L);                        /* Bus Error vector generator */
2495 
SFR_8BIT(SYSBERRIV_H);                        /* Bus Error vector generator */
2496 
SFR_16BIT(SYSUNIV);                           /* User NMI vector generator */
2497 
SFR_8BIT(SYSUNIV_L);                          /* User NMI vector generator */
2498 
SFR_8BIT(SYSUNIV_H);                          /* User NMI vector generator */
2499 
SFR_16BIT(SYSSNIV);                           /* System NMI vector generator */
2500 
SFR_8BIT(SYSSNIV_L);                          /* System NMI vector generator */
2501 
SFR_8BIT(SYSSNIV_H);                          /* System NMI vector generator */
2502 
SFR_16BIT(SYSRSTIV);                          /* Reset vector generator */
2503 
SFR_8BIT(SYSRSTIV_L);                         /* Reset vector generator */
2504 
SFR_8BIT(SYSRSTIV_H);                         /* Reset vector generator */
2505 
 
2506 
/* SYSCTL Control Bits */
2507 
#define SYSRIVECT              (0x0001)       /* SYS - RAM based interrupt vectors */
2508 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2509 
#define SYSPMMPE               (0x0004)       /* SYS - PMM access protect */
2510 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2511 
#define SYSBSLIND              (0x0010)       /* SYS - TCK/RST indication detected */
2512 
#define SYSJTAGPIN             (0x0020)       /* SYS - Dedicated JTAG pins enabled */
2513 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2514 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2515 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2516 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2517 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2518 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2519 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2520 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2521 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2522 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2523 
 
2524 
/* SYSCTL Control Bits */
2525 
#define SYSRIVECT_L            (0x0001)       /* SYS - RAM based interrupt vectors */
2526 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2527 
#define SYSPMMPE_L             (0x0004)       /* SYS - PMM access protect */
2528 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2529 
#define SYSBSLIND_L            (0x0010)       /* SYS - TCK/RST indication detected */
2530 
#define SYSJTAGPIN_L           (0x0020)       /* SYS - Dedicated JTAG pins enabled */
2531 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2532 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2533 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2534 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2535 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2536 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2537 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2538 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2539 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2540 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2541 
 
2542 
/* SYSCTL Control Bits */
2543 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2544 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2545 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2546 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2547 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2548 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2549 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2550 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2551 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2552 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2553 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2554 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2555 
 
2556 
/* SYSBSLC Control Bits */
2557 
#define SYSBSLSIZE0            (0x0001)       /* SYS - BSL Protection Size 0 */
2558 
#define SYSBSLSIZE1            (0x0002)       /* SYS - BSL Protection Size 1 */
2559 
#define SYSBSLR                (0x0004)       /* SYS - RAM assigned to BSL */
2560 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2561 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
2562 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2563 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2564 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2565 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2566 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2567 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2568 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2569 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2570 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2571 
#define SYSBSLOFF              (0x4000)       /* SYS - BSL Memeory disabled */
2572 
#define SYSBSLPE               (0x8000)       /* SYS - BSL Memory protection enabled */
2573 
 
2574 
/* SYSBSLC Control Bits */
2575 
#define SYSBSLSIZE0_L          (0x0001)       /* SYS - BSL Protection Size 0 */
2576 
#define SYSBSLSIZE1_L          (0x0002)       /* SYS - BSL Protection Size 1 */
2577 
#define SYSBSLR_L              (0x0004)       /* SYS - RAM assigned to BSL */
2578 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2579 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
2580 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2581 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2582 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2583 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2584 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2585 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2586 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2587 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2588 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2589 
 
2590 
/* SYSBSLC Control Bits */
2591 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2592 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
2593 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2594 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2595 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2596 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2597 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2598 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2599 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2600 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2601 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2602 
#define SYSBSLOFF_H            (0x0040)       /* SYS - BSL Memeory disabled */
2603 
#define SYSBSLPE_H             (0x0080)       /* SYS - BSL Memory protection enabled */
2604 
 
2605 
/* SYSJMBC Control Bits */
2606 
#define JMBIN0FG               (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
2607 
#define JMBIN1FG               (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
2608 
#define JMBOUT0FG              (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
2609 
#define JMBOUT1FG              (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
2610 
#define JMBMODE                (0x0010)       /* SYS - JMB 16/32 Bit Mode */
2611 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2612 
#define JMBCLR0OFF             (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
2613 
#define JMBCLR1OFF             (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
2614 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2615 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2616 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2617 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2618 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2619 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2620 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2621 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2622 
 
2623 
/* SYSJMBC Control Bits */
2624 
#define JMBIN0FG_L             (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
2625 
#define JMBIN1FG_L             (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
2626 
#define JMBOUT0FG_L            (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
2627 
#define JMBOUT1FG_L            (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
2628 
#define JMBMODE_L              (0x0010)       /* SYS - JMB 16/32 Bit Mode */
2629 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2630 
#define JMBCLR0OFF_L           (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
2631 
#define JMBCLR1OFF_L           (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
2632 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2633 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2634 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2635 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2636 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2637 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2638 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2639 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2640 
 
2641 
/* SYSJMBC Control Bits */
2642 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2643 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2644 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2645 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2646 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2647 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2648 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2649 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2650 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2651 
 
2652 
/* SYSUNIV Definitions */
2653 
#define SYSUNIV_NONE           (0x0000)       /* No Interrupt pending */
2654 
#define SYSUNIV_NMIIFG         (0x0002)       /* SYSUNIV : NMIIFG */
2655 
#define SYSUNIV_OFIFG          (0x0004)       /* SYSUNIV : Osc. Fail - OFIFG */
2656 
#define SYSUNIV_ACCVIFG        (0x0006)       /* SYSUNIV : Access Violation - ACCVIFG */
2657 
#define SYSUNIV_BUSIFG         (0x0008)       /* SYSUNIV : Bus Error */
2658 
 
2659 
/* SYSBERRIV Definitions */
2660 
#define SYSBERRIV_NONE         (0x0000)       /* No Interrupt pending */
2661 
#define SYSBERRIV_USB          (0x0002)       /* SYSBERRIV : USB Waitstate Error */
2662 
 
2663 
/* SYSSNIV Definitions */
2664 
#define SYSSNIV_NONE           (0x0000)       /* No Interrupt pending */
2665 
#define SYSSNIV_SVMLIFG        (0x0002)       /* SYSSNIV : SVMLIFG */
2666 
#define SYSSNIV_SVMHIFG        (0x0004)       /* SYSSNIV : SVMHIFG */
2667 
#define SYSSNIV_DLYLIFG        (0x0006)       /* SYSSNIV : DLYLIFG */
2668 
#define SYSSNIV_DLYHIFG        (0x0008)       /* SYSSNIV : DLYHIFG */
2669 
#define SYSSNIV_VMAIFG         (0x000A)       /* SYSSNIV : VMAIFG */
2670 
#define SYSSNIV_JMBINIFG       (0x000C)       /* SYSSNIV : JMBINIFG */
2671 
#define SYSSNIV_JMBOUTIFG      (0x000E)       /* SYSSNIV : JMBOUTIFG */
2672 
#define SYSSNIV_VLRLIFG        (0x0010)       /* SYSSNIV : VLRLIFG */
2673 
#define SYSSNIV_VLRHIFG        (0x0012)       /* SYSSNIV : VLRHIFG */
2674 
 
2675 
/* SYSRSTIV Definitions */
2676 
#define SYSRSTIV_NONE          (0x0000)       /* No Interrupt pending */
2677 
#define SYSRSTIV_BOR           (0x0002)       /* SYSRSTIV : BOR */
2678 
#define SYSRSTIV_RSTNMI        (0x0004)       /* SYSRSTIV : RST/NMI */
2679 
#define SYSRSTIV_DOBOR         (0x0006)       /* SYSRSTIV : Do BOR */
2680 
#define SYSRSTIV_LPM5WU        (0x0008)       /* SYSRSTIV : Port LPM5 Wake Up */
2681 
#define SYSRSTIV_SECYV         (0x000A)       /* SYSRSTIV : Security violation */
2682 
#define SYSRSTIV_SVSL          (0x000C)       /* SYSRSTIV : SVSL */
2683 
#define SYSRSTIV_SVSH          (0x000E)       /* SYSRSTIV : SVSH */
2684 
#define SYSRSTIV_SVML_OVP      (0x0010)       /* SYSRSTIV : SVML_OVP */
2685 
#define SYSRSTIV_SVMH_OVP      (0x0012)       /* SYSRSTIV : SVMH_OVP */
2686 
#define SYSRSTIV_DOPOR         (0x0014)       /* SYSRSTIV : Do POR */
2687 
#define SYSRSTIV_WDTTO         (0x0016)       /* SYSRSTIV : WDT Time out */
2688 
#define SYSRSTIV_WDTKEY        (0x0018)       /* SYSRSTIV : WDTKEY violation */
2689 
#define SYSRSTIV_KEYV          (0x001A)       /* SYSRSTIV : Flash Key violation */
2690 
#define SYSRSTIV_FLLUL         (0x001C)       /* SYSRSTIV : FLL unlock */
2691 
#define SYSRSTIV_PERF          (0x001E)       /* SYSRSTIV : peripheral/config area fetch */
2692 
#define SYSRSTIV_PMMKEY        (0x0020)       /* SYSRSTIV : PMMKEY violation */
2693 
 
2694 
/************************************************************
2695 
* Timer0_A5
2696 
************************************************************/
2697 
#define __MSP430_HAS_T0A5__                   /* Definition to show that Module is available */
2698 
#define __MSP430_BASEADDRESS_T0A5__ 0x0340
2699 
 
2700 
SFR_16BIT(TA0CTL);                            /* Timer0_A5 Control */
2701 
SFR_16BIT(TA0CCTL0);                          /* Timer0_A5 Capture/Compare Control 0 */
2702 
SFR_16BIT(TA0CCTL1);                          /* Timer0_A5 Capture/Compare Control 1 */
2703 
SFR_16BIT(TA0CCTL2);                          /* Timer0_A5 Capture/Compare Control 2 */
2704 
SFR_16BIT(TA0CCTL3);                          /* Timer0_A5 Capture/Compare Control 3 */
2705 
SFR_16BIT(TA0CCTL4);                          /* Timer0_A5 Capture/Compare Control 4 */
2706 
SFR_16BIT(TA0R);                              /* Timer0_A5 */
2707 
SFR_16BIT(TA0CCR0);                           /* Timer0_A5 Capture/Compare 0 */
2708 
SFR_16BIT(TA0CCR1);                           /* Timer0_A5 Capture/Compare 1 */
2709 
SFR_16BIT(TA0CCR2);                           /* Timer0_A5 Capture/Compare 2 */
2710 
SFR_16BIT(TA0CCR3);                           /* Timer0_A5 Capture/Compare 3 */
2711 
SFR_16BIT(TA0CCR4);                           /* Timer0_A5 Capture/Compare 4 */
2712 
SFR_16BIT(TA0IV);                             /* Timer0_A5 Interrupt Vector Word */
2713 
SFR_16BIT(TA0EX0);                            /* Timer0_A5 Expansion Register 0 */
2714 
 
2715 
/* TAxCTL Control Bits */
2716 
#define TASSEL1                (0x0200)       /* Timer A clock source select 0 */
2717 
#define TASSEL0                (0x0100)       /* Timer A clock source select 1 */
2718 
#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
2719 
#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
2720 
#define MC1                    (0x0020)       /* Timer A mode control 1 */
2721 
#define MC0                    (0x0010)       /* Timer A mode control 0 */
2722 
#define TACLR                  (0x0004)       /* Timer A counter clear */
2723 
#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
2724 
#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
2725 
 
2726 
#define MC_0                   (0*0x10u)      /* Timer A mode control: 0 - Stop */
2727 
#define MC_1                   (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
2728 
#define MC_2                   (2*0x10u)      /* Timer A mode control: 2 - Continous up */
2729 
#define MC_3                   (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
2730 
#define ID_0                   (0*0x40u)      /* Timer A input divider: 0 - /1 */
2731 
#define ID_1                   (1*0x40u)      /* Timer A input divider: 1 - /2 */
2732 
#define ID_2                   (2*0x40u)      /* Timer A input divider: 2 - /4 */
2733 
#define ID_3                   (3*0x40u)      /* Timer A input divider: 3 - /8 */
2734 
#define TASSEL_0               (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
2735 
#define TASSEL_1               (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
2736 
#define TASSEL_2               (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
2737 
#define TASSEL_3               (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
2738 
#define MC__STOP               (0*0x10u)      /* Timer A mode control: 0 - Stop */
2739 
#define MC__UP                 (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
2740 
#define MC__CONTINOUS          (2*0x10u)      /* Timer A mode control: 2 - Continous up */
2741 
#define MC__UPDOWN             (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
2742 
#define ID__1                  (0*0x40u)      /* Timer A input divider: 0 - /1 */
2743 
#define ID__2                  (1*0x40u)      /* Timer A input divider: 1 - /2 */
2744 
#define ID__4                  (2*0x40u)      /* Timer A input divider: 2 - /4 */
2745 
#define ID__8                  (3*0x40u)      /* Timer A input divider: 3 - /8 */
2746 
#define TASSEL__TACLK          (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
2747 
#define TASSEL__ACLK           (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
2748 
#define TASSEL__SMCLK          (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
2749 
#define TASSEL__INCLK          (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
2750 
 
2751 
/* TAxCCTLx Control Bits */
2752 
#define CM1                    (0x8000)       /* Capture mode 1 */
2753 
#define CM0                    (0x4000)       /* Capture mode 0 */
2754 
#define CCIS1                  (0x2000)       /* Capture input select 1 */
2755 
#define CCIS0                  (0x1000)       /* Capture input select 0 */
2756 
#define SCS                    (0x0800)       /* Capture sychronize */
2757 
#define SCCI                   (0x0400)       /* Latched capture signal (read) */
2758 
#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
2759 
#define OUTMOD2                (0x0080)       /* Output mode 2 */
2760 
#define OUTMOD1                (0x0040)       /* Output mode 1 */
2761 
#define OUTMOD0                (0x0020)       /* Output mode 0 */
2762 
#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
2763 
#define CCI                    (0x0008)       /* Capture input signal (read) */
2764 
#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
2765 
#define COV                    (0x0002)       /* Capture/compare overflow flag */
2766 
#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
2767 
 
2768 
#define OUTMOD_0               (0*0x20u)      /* PWM output mode: 0 - output only */
2769 
#define OUTMOD_1               (1*0x20u)      /* PWM output mode: 1 - set */
2770 
#define OUTMOD_2               (2*0x20u)      /* PWM output mode: 2 - PWM toggle/reset */
2771 
#define OUTMOD_3               (3*0x20u)      /* PWM output mode: 3 - PWM set/reset */
2772 
#define OUTMOD_4               (4*0x20u)      /* PWM output mode: 4 - toggle */
2773 
#define OUTMOD_5               (5*0x20u)      /* PWM output mode: 5 - Reset */
2774 
#define OUTMOD_6               (6*0x20u)      /* PWM output mode: 6 - PWM toggle/set */
2775 
#define OUTMOD_7               (7*0x20u)      /* PWM output mode: 7 - PWM reset/set */
2776 
#define CCIS_0                 (0*0x1000u)    /* Capture input select: 0 - CCIxA */
2777 
#define CCIS_1                 (1*0x1000u)    /* Capture input select: 1 - CCIxB */
2778 
#define CCIS_2                 (2*0x1000u)    /* Capture input select: 2 - GND */
2779 
#define CCIS_3                 (3*0x1000u)    /* Capture input select: 3 - Vcc */
2780 
#define CM_0                   (0*0x4000u)    /* Capture mode: 0 - disabled */
2781 
#define CM_1                   (1*0x4000u)    /* Capture mode: 1 - pos. edge */
2782 
#define CM_2                   (2*0x4000u)    /* Capture mode: 1 - neg. edge */
2783 
#define CM_3                   (3*0x4000u)    /* Capture mode: 1 - both edges */
2784 
 
2785 
/* TAxEX0 Control Bits */
2786 
#define TAIDEX0                (0x0001)       /* Timer A Input divider expansion Bit: 0 */
2787 
#define TAIDEX1                (0x0002)       /* Timer A Input divider expansion Bit: 1 */
2788 
#define TAIDEX2                (0x0004)       /* Timer A Input divider expansion Bit: 2 */
2789 
 
2790 
#define TAIDEX_0               (0*0x0001u)    /* Timer A Input divider expansion : /1 */
2791 
#define TAIDEX_1               (1*0x0001u)    /* Timer A Input divider expansion : /2 */
2792 
#define TAIDEX_2               (2*0x0001u)    /* Timer A Input divider expansion : /3 */
2793 
#define TAIDEX_3               (3*0x0001u)    /* Timer A Input divider expansion : /4 */
2794 
#define TAIDEX_4               (4*0x0001u)    /* Timer A Input divider expansion : /5 */
2795 
#define TAIDEX_5               (5*0x0001u)    /* Timer A Input divider expansion : /6 */
2796 
#define TAIDEX_6               (6*0x0001u)    /* Timer A Input divider expansion : /7 */
2797 
#define TAIDEX_7               (7*0x0001u)    /* Timer A Input divider expansion : /8 */
2798 
 
2799 
/* T0A5IV Definitions */
2800 
#define TA0IV_NONE             (0x0000)       /* No Interrupt pending */
2801 
#define TA0IV_TA0CCR1          (0x0002)       /* TA0CCR1_CCIFG */
2802 
#define TA0IV_TA0CCR2          (0x0004)       /* TA0CCR2_CCIFG */
2803 
#define TA0IV_TA0CCR3          (0x0006)       /* TA0CCR3_CCIFG */
2804 
#define TA0IV_TA0CCR4          (0x0008)       /* TA0CCR4_CCIFG */
2805 
#define TA0IV_5                (0x000A)       /* Reserved */
2806 
#define TA0IV_6                (0x000C)       /* Reserved */
2807 
#define TA0IV_TA0IFG           (0x000E)       /* TA0IFG */
2808 
 
2809 
/************************************************************
2810 
* Timer1_A3
2811 
************************************************************/
2812 
#define __MSP430_HAS_T1A3__                   /* Definition to show that Module is available */
2813 
#define __MSP430_BASEADDRESS_T1A3__ 0x0380
2814 
 
2815 
SFR_16BIT(TA1CTL);                            /* Timer1_A3 Control */
2816 
SFR_16BIT(TA1CCTL0);                          /* Timer1_A3 Capture/Compare Control 0 */
2817 
SFR_16BIT(TA1CCTL1);                          /* Timer1_A3 Capture/Compare Control 1 */
2818 
SFR_16BIT(TA1CCTL2);                          /* Timer1_A3 Capture/Compare Control 2 */
2819 
SFR_16BIT(TA1R);                              /* Timer1_A3 */
2820 
SFR_16BIT(TA1CCR0);                           /* Timer1_A3 Capture/Compare 0 */
2821 
SFR_16BIT(TA1CCR1);                           /* Timer1_A3 Capture/Compare 1 */
2822 
SFR_16BIT(TA1CCR2);                           /* Timer1_A3 Capture/Compare 2 */
2823 
SFR_16BIT(TA1IV);                             /* Timer1_A3 Interrupt Vector Word */
2824 
SFR_16BIT(TA1EX0);                            /* Timer1_A3 Expansion Register 0 */
2825 
 
2826 
/* Bits are already defined within the Timer0_Ax */
2827 
 
2828 
/* TA1IV Definitions */
2829 
#define TA1IV_NONE             (0x0000)       /* No Interrupt pending */
2830 
#define TA1IV_TA1CCR1          (0x0002)       /* TA1CCR1_CCIFG */
2831 
#define TA1IV_TA1CCR2          (0x0004)       /* TA1CCR2_CCIFG */
2832 
#define TA1IV_3                (0x0006)       /* Reserved */
2833 
#define TA1IV_4                (0x0008)       /* Reserved */
2834 
#define TA1IV_5                (0x000A)       /* Reserved */
2835 
#define TA1IV_6                (0x000C)       /* Reserved */
2836 
#define TA1IV_TA1IFG           (0x000E)       /* TA1IFG */
2837 
 
2838 
/************************************************************
2839 
* Timer2_A3
2840 
************************************************************/
2841 
#define __MSP430_HAS_T2A3__                   /* Definition to show that Module is available */
2842 
#define __MSP430_BASEADDRESS_T2A3__ 0x0400
2843 
 
2844 
SFR_16BIT(TA2CTL);                            /* Timer2_A3 Control */
2845 
SFR_16BIT(TA2CCTL0);                          /* Timer2_A3 Capture/Compare Control 0 */
2846 
SFR_16BIT(TA2CCTL1);                          /* Timer2_A3 Capture/Compare Control 1 */
2847 
SFR_16BIT(TA2CCTL2);                          /* Timer2_A3 Capture/Compare Control 2 */
2848 
SFR_16BIT(TA2R);                              /* Timer2_A3 */
2849 
SFR_16BIT(TA2CCR0);                           /* Timer2_A3 Capture/Compare 0 */
2850 
SFR_16BIT(TA2CCR1);                           /* Timer2_A3 Capture/Compare 1 */
2851 
SFR_16BIT(TA2CCR2);                           /* Timer2_A3 Capture/Compare 2 */
2852 
SFR_16BIT(TA2IV);                             /* Timer2_A3 Interrupt Vector Word */
2853 
SFR_16BIT(TA2EX0);                            /* Timer2_A3 Expansion Register 0 */
2854 
 
2855 
/* Bits are already defined within the Timer0_Ax */
2856 
 
2857 
/* TA2IV Definitions */
2858 
#define TA2IV_NONE             (0x0000)       /* No Interrupt pending */
2859 
#define TA2IV_TA1CCR1          (0x0002)       /* TA2CCR1_CCIFG */
2860 
#define TA2IV_TA1CCR2          (0x0004)       /* TA2CCR2_CCIFG */
2861 
#define TA2IV_3                (0x0006)       /* Reserved */
2862 
#define TA2IV_4                (0x0008)       /* Reserved */
2863 
#define TA2IV_5                (0x000A)       /* Reserved */
2864 
#define TA2IV_6                (0x000C)       /* Reserved */
2865 
#define TA2IV_TA2IFG           (0x000E)       /* TA2IFG */
2866 
 
2867 
/************************************************************
2868 
* Timer0_B7
2869 
************************************************************/
2870 
#define __MSP430_HAS_T0B7__                   /* Definition to show that Module is available */
2871 
#define __MSP430_BASEADDRESS_T0B7__ 0x03C0
2872 
 
2873 
SFR_16BIT(TB0CTL);                            /* Timer0_B7 Control */
2874 
SFR_16BIT(TB0CCTL0);                          /* Timer0_B7 Capture/Compare Control 0 */
2875 
SFR_16BIT(TB0CCTL1);                          /* Timer0_B7 Capture/Compare Control 1 */
2876 
SFR_16BIT(TB0CCTL2);                          /* Timer0_B7 Capture/Compare Control 2 */
2877 
SFR_16BIT(TB0CCTL3);                          /* Timer0_B7 Capture/Compare Control 3 */
2878 
SFR_16BIT(TB0CCTL4);                          /* Timer0_B7 Capture/Compare Control 4 */
2879 
SFR_16BIT(TB0CCTL5);                          /* Timer0_B7 Capture/Compare Control 5 */
2880 
SFR_16BIT(TB0CCTL6);                          /* Timer0_B7 Capture/Compare Control 6 */
2881 
SFR_16BIT(TB0R);                              /* Timer0_B7 */
2882 
SFR_16BIT(TB0CCR0);                           /* Timer0_B7 Capture/Compare 0 */
2883 
SFR_16BIT(TB0CCR1);                           /* Timer0_B7 Capture/Compare 1 */
2884 
SFR_16BIT(TB0CCR2);                           /* Timer0_B7 Capture/Compare 2 */
2885 
SFR_16BIT(TB0CCR3);                           /* Timer0_B7 Capture/Compare 3 */
2886 
SFR_16BIT(TB0CCR4);                           /* Timer0_B7 Capture/Compare 4 */
2887 
SFR_16BIT(TB0CCR5);                           /* Timer0_B7 Capture/Compare 5 */
2888 
SFR_16BIT(TB0CCR6);                           /* Timer0_B7 Capture/Compare 6 */
2889 
SFR_16BIT(TB0EX0);                            /* Timer0_B7 Expansion Register 0 */
2890 
SFR_16BIT(TB0IV);                             /* Timer0_B7 Interrupt Vector Word */
2891 
 
2892 
/* Legacy Type Definitions for TimerB */
2893 
#define TBCTL                  TB0CTL         /* Timer0_B7 Control */
2894 
#define TBCCTL0                TB0CCTL0       /* Timer0_B7 Capture/Compare Control 0 */
2895 
#define TBCCTL1                TB0CCTL1       /* Timer0_B7 Capture/Compare Control 1 */
2896 
#define TBCCTL2                TB0CCTL2       /* Timer0_B7 Capture/Compare Control 2 */
2897 
#define TBCCTL3                TB0CCTL3       /* Timer0_B7 Capture/Compare Control 3 */
2898 
#define TBCCTL4                TB0CCTL4       /* Timer0_B7 Capture/Compare Control 4 */
2899 
#define TBCCTL5                TB0CCTL5       /* Timer0_B7 Capture/Compare Control 5 */
2900 
#define TBCCTL6                TB0CCTL6       /* Timer0_B7 Capture/Compare Control 6 */
2901 
#define TBR                    TB0R           /* Timer0_B7 */
2902 
#define TBCCR0                 TB0CCR0        /* Timer0_B7 Capture/Compare 0 */
2903 
#define TBCCR1                 TB0CCR1        /* Timer0_B7 Capture/Compare 1 */
2904 
#define TBCCR2                 TB0CCR2        /* Timer0_B7 Capture/Compare 2 */
2905 
#define TBCCR3                 TB0CCR3        /* Timer0_B7 Capture/Compare 3 */
2906 
#define TBCCR4                 TB0CCR4        /* Timer0_B7 Capture/Compare 4 */
2907 
#define TBCCR5                 TB0CCR5        /* Timer0_B7 Capture/Compare 5 */
2908 
#define TBCCR6                 TB0CCR6        /* Timer0_B7 Capture/Compare 6 */
2909 
#define TBEX0                  TB0EX0         /* Timer0_B7 Expansion Register 0 */
2910 
#define TBIV                   TB0IV          /* Timer0_B7 Interrupt Vector Word */
2911 
#define TIMERB1_VECTOR       TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
2912 
#define TIMERB0_VECTOR       TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
2913 
 
2914 
/* TBxCTL Control Bits */
2915 
#define TBCLGRP1               (0x4000)       /* Timer0_B7 Compare latch load group 1 */
2916 
#define TBCLGRP0               (0x2000)       /* Timer0_B7 Compare latch load group 0 */
2917 
#define CNTL1                  (0x1000)       /* Counter lenght 1 */
2918 
#define CNTL0                  (0x0800)       /* Counter lenght 0 */
2919 
#define TBSSEL1                (0x0200)       /* Clock source 1 */
2920 
#define TBSSEL0                (0x0100)       /* Clock source 0 */
2921 
#define TBCLR                  (0x0004)       /* Timer0_B7 counter clear */
2922 
#define TBIE                   (0x0002)       /* Timer0_B7 interrupt enable */
2923 
#define TBIFG                  (0x0001)       /* Timer0_B7 interrupt flag */
2924 
 
2925 
#define SHR1                   (0x4000)       /* Timer0_B7 Compare latch load group 1 */
2926 
#define SHR0                   (0x2000)       /* Timer0_B7 Compare latch load group 0 */
2927 
 
2928 
#define TBSSEL_0               (0*0x0100u)    /* Clock Source: TBCLK */
2929 
#define TBSSEL_1               (1*0x0100u)    /* Clock Source: ACLK  */
2930 
#define TBSSEL_2               (2*0x0100u)    /* Clock Source: SMCLK */
2931 
#define TBSSEL_3               (3*0x0100u)    /* Clock Source: INCLK */
2932 
#define CNTL_0                 (0*0x0800u)    /* Counter lenght: 16 bit */
2933 
#define CNTL_1                 (1*0x0800u)    /* Counter lenght: 12 bit */
2934 
#define CNTL_2                 (2*0x0800u)    /* Counter lenght: 10 bit */
2935 
#define CNTL_3                 (3*0x0800u)    /* Counter lenght:  8 bit */
2936 
#define SHR_0                  (0*0x2000u)    /* Timer0_B7 Group: 0 - individually */
2937 
#define SHR_1                  (1*0x2000u)    /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
2938 
#define SHR_2                  (2*0x2000u)    /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
2939 
#define SHR_3                  (3*0x2000u)    /* Timer0_B7 Group: 3 - 1 group (all) */
2940 
#define TBCLGRP_0              (0*0x2000u)    /* Timer0_B7 Group: 0 - individually */
2941 
#define TBCLGRP_1              (1*0x2000u)    /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
2942 
#define TBCLGRP_2              (2*0x2000u)    /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
2943 
#define TBCLGRP_3              (3*0x2000u)    /* Timer0_B7 Group: 3 - 1 group (all) */
2944 
#define TBSSEL__TACLK          (0*0x100u)     /* Timer0_B7 clock source select: 0 - TACLK */
2945 
#define TBSSEL__ACLK           (1*0x100u)     /* Timer0_B7 clock source select: 1 - ACLK  */
2946 
#define TBSSEL__SMCLK          (2*0x100u)     /* Timer0_B7 clock source select: 2 - SMCLK */
2947 
#define TBSSEL__INCLK          (3*0x100u)     /* Timer0_B7 clock source select: 3 - INCLK */
2948 
#define CNTL__16               (0*0x0800u)    /* Counter lenght: 16 bit */
2949 
#define CNTL__12               (1*0x0800u)    /* Counter lenght: 12 bit */
2950 
#define CNTL__10               (2*0x0800u)    /* Counter lenght: 10 bit */
2951 
#define CNTL__8                (3*0x0800u)    /* Counter lenght:  8 bit */
2952 
 
2953 
/* Additional Timer B Control Register bits are defined in Timer A */
2954 
/* TBxCCTLx Control Bits */
2955 
#define CLLD1                  (0x0400)       /* Compare latch load source 1 */
2956 
#define CLLD0                  (0x0200)       /* Compare latch load source 0 */
2957 
 
2958 
#define SLSHR1                 (0x0400)       /* Compare latch load source 1 */
2959 
#define SLSHR0                 (0x0200)       /* Compare latch load source 0 */
2960 
 
2961 
#define SLSHR_0                (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
2962 
#define SLSHR_1                (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
2963 
#define SLSHR_2                (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
2964 
#define SLSHR_3                (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
2965 
 
2966 
#define CLLD_0                 (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
2967 
#define CLLD_1                 (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
2968 
#define CLLD_2                 (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
2969 
#define CLLD_3                 (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
2970 
 
2971 
/* TBxEX0 Control Bits */
2972 
#define TBIDEX0                (0x0001)       /* Timer0_B7 Input divider expansion Bit: 0 */
2973 
#define TBIDEX1                (0x0002)       /* Timer0_B7 Input divider expansion Bit: 1 */
2974 
#define TBIDEX2                (0x0004)       /* Timer0_B7 Input divider expansion Bit: 2 */
2975 
 
2976 
#define TBIDEX_0               (0*0x0001u)    /* Timer0_B7 Input divider expansion : /1 */
2977 
#define TBIDEX_1               (1*0x0001u)    /* Timer0_B7 Input divider expansion : /2 */
2978 
#define TBIDEX_2               (2*0x0001u)    /* Timer0_B7 Input divider expansion : /3 */
2979 
#define TBIDEX_3               (3*0x0001u)    /* Timer0_B7 Input divider expansion : /4 */
2980 
#define TBIDEX_4               (4*0x0001u)    /* Timer0_B7 Input divider expansion : /5 */
2981 
#define TBIDEX_5               (5*0x0001u)    /* Timer0_B7 Input divider expansion : /6 */
2982 
#define TBIDEX_6               (6*0x0001u)    /* Timer0_B7 Input divider expansion : /7 */
2983 
#define TBIDEX_7               (7*0x0001u)    /* Timer0_B7 Input divider expansion : /8 */
2984 
#define TBIDEX__1              (0*0x0001u)    /* Timer0_B7 Input divider expansion : /1 */
2985 
#define TBIDEX__2              (1*0x0001u)    /* Timer0_B7 Input divider expansion : /2 */
2986 
#define TBIDEX__3              (2*0x0001u)    /* Timer0_B7 Input divider expansion : /3 */
2987 
#define TBIDEX__4              (3*0x0001u)    /* Timer0_B7 Input divider expansion : /4 */
2988 
#define TBIDEX__5              (4*0x0001u)    /* Timer0_B7 Input divider expansion : /5 */
2989 
#define TBIDEX__6              (5*0x0001u)    /* Timer0_B7 Input divider expansion : /6 */
2990 
#define TBIDEX__7              (6*0x0001u)    /* Timer0_B7 Input divider expansion : /7 */
2991 
#define TBIDEX__8              (7*0x0001u)    /* Timer0_B7 Input divider expansion : /8 */
2992 
 
2993 
/* TB0IV Definitions */
2994 
#define TB0IV_NONE             (0x0000)       /* No Interrupt pending */
2995 
#define TB0IV_TB1CCR1          (0x0002)       /* TBCCR1_CCIFG */
2996 
#define TB0IV_TB1CCR2          (0x0004)       /* TBCCR2_CCIFG */
2997 
#define TB0IV_3                (0x0006)       /* Reserved */
2998 
#define TB0IV_4                (0x0008)       /* Reserved */
2999 
#define TB0IV_5                (0x000A)       /* Reserved */
3000 
#define TB0IV_6                (0x000C)       /* Reserved */
3001 
#define TB0IV_TB0IFG           (0x000E)       /* TBIFG */
3002 
 
3003 
 
3004 
/************************************************************
3005 
* USB
3006 
************************************************************/
3007 
#define __MSP430_HAS_USB__                    /* Definition to show that Module is available */
3008 
#define __MSP430_BASEADDRESS_USB__ 0x0900
3009 
 
3010 
/* ========================================================================= */
3011 
/* USB Configuration Registers */
3012 
/* ========================================================================= */
3013 
SFR_16BIT(USBKEYID);                          /* USB Controller key register */
3014 
SFR_8BIT(USBKEYID_L);                         /* USB Controller key register */
3015 
SFR_8BIT(USBKEYID_H);                         /* USB Controller key register */
3016 
SFR_16BIT(USBCNF);                            /* USB Module  configuration register */
3017 
SFR_8BIT(USBCNF_L);                           /* USB Module  configuration register */
3018 
SFR_8BIT(USBCNF_H);                           /* USB Module  configuration register */
3019 
SFR_16BIT(USBPHYCTL);                         /* USB PHY control register */
3020 
SFR_8BIT(USBPHYCTL_L);                        /* USB PHY control register */
3021 
SFR_8BIT(USBPHYCTL_H);                        /* USB PHY control register */
3022 
SFR_16BIT(USBPWRCTL);                         /* USB Power control register */
3023 
SFR_8BIT(USBPWRCTL_L);                        /* USB Power control register */
3024 
SFR_8BIT(USBPWRCTL_H);                        /* USB Power control register */
3025 
SFR_16BIT(USBPLLCTL);                         /* USB PLL control register */
3026 
SFR_8BIT(USBPLLCTL_L);                        /* USB PLL control register */
3027 
SFR_8BIT(USBPLLCTL_H);                        /* USB PLL control register */
3028 
SFR_16BIT(USBPLLDIVB);                        /* USB PLL Clock Divider Buffer control register */
3029 
SFR_8BIT(USBPLLDIVB_L);                       /* USB PLL Clock Divider Buffer control register */
3030 
SFR_8BIT(USBPLLDIVB_H);                       /* USB PLL Clock Divider Buffer control register */
3031 
SFR_16BIT(USBPLLIR);                          /* USB PLL Interrupt control register */
3032 
SFR_8BIT(USBPLLIR_L);                         /* USB PLL Interrupt control register */
3033 
SFR_8BIT(USBPLLIR_H);                         /* USB PLL Interrupt control register */
3034 
 
3035 
#define USBKEYPID              USBKEYID       /* Legacy Definition: USB Controller key register */
3036 
#define USBKEY                 (0x9628)       /* USB Control Register key */
3037 
 
3038 
/* USBCNF Control Bits */
3039 
#define USB_EN                 (0x0001)       /* USB - Module enable */
3040 
#define PUR_EN                 (0x0002)       /* USB - PUR pin enable */
3041 
#define PUR_IN                 (0x0004)       /* USB - PUR pin input value */
3042 
#define BLKRDY                 (0x0008)       /* USB - Block ready signal for DMA */
3043 
#define FNTEN                  (0x0010)       /* USB - Frame Number receive Trigger enable for DMA */
3044 
//#define RESERVED            (0x0020)  /* USB -  */
3045 
//#define RESERVED            (0x0040)  /* USB -  */
3046 
//#define RESERVED            (0x0080)  /* USB -  */
3047 
//#define RESERVED            (0x0100)  /* USB -  */
3048 
//#define RESERVED            (0x0200)  /* USB -  */
3049 
//#define RESERVED            (0x0400)  /* USB -  */
3050 
//#define RESERVED            (0x0800)  /* USB -  */
3051 
//#define RESERVED            (0x1000)  /* USB -  */
3052 
//#define RESERVED            (0x2000)  /* USB -  */
3053 
//#define RESERVED            (0x4000)  /* USB -  */
3054 
//#define RESERVED            (0x8000)  /* USB -  */
3055 
 
3056 
/* USBCNF Control Bits */
3057 
#define USB_EN_L               (0x0001)       /* USB - Module enable */
3058 
#define PUR_EN_L               (0x0002)       /* USB - PUR pin enable */
3059 
#define PUR_IN_L               (0x0004)       /* USB - PUR pin input value */
3060 
#define BLKRDY_L               (0x0008)       /* USB - Block ready signal for DMA */
3061 
#define FNTEN_L                (0x0010)       /* USB - Frame Number receive Trigger enable for DMA */
3062 
//#define RESERVED            (0x0020)  /* USB -  */
3063 
//#define RESERVED            (0x0040)  /* USB -  */
3064 
//#define RESERVED            (0x0080)  /* USB -  */
3065 
//#define RESERVED            (0x0100)  /* USB -  */
3066 
//#define RESERVED            (0x0200)  /* USB -  */
3067 
//#define RESERVED            (0x0400)  /* USB -  */
3068 
//#define RESERVED            (0x0800)  /* USB -  */
3069 
//#define RESERVED            (0x1000)  /* USB -  */
3070 
//#define RESERVED            (0x2000)  /* USB -  */
3071 
//#define RESERVED            (0x4000)  /* USB -  */
3072 
//#define RESERVED            (0x8000)  /* USB -  */
3073 
 
3074 
/* USBCNF Control Bits */
3075 
//#define RESERVED            (0x0020)  /* USB -  */
3076 
//#define RESERVED            (0x0040)  /* USB -  */
3077 
//#define RESERVED            (0x0080)  /* USB -  */
3078 
//#define RESERVED            (0x0100)  /* USB -  */
3079 
//#define RESERVED            (0x0200)  /* USB -  */
3080 
//#define RESERVED            (0x0400)  /* USB -  */
3081 
//#define RESERVED            (0x0800)  /* USB -  */
3082 
//#define RESERVED            (0x1000)  /* USB -  */
3083 
//#define RESERVED            (0x2000)  /* USB -  */
3084 
//#define RESERVED            (0x4000)  /* USB -  */
3085 
//#define RESERVED            (0x8000)  /* USB -  */
3086 
 
3087 
/* USBPHYCTL Control Bits */
3088 
#define PUOUT0                 (0x0001)       /* USB - USB Port Output Signal Bit 0 */
3089 
#define PUOUT1                 (0x0002)       /* USB - USB Port Output Signal Bit 1 */
3090 
#define PUIN0                  (0x0004)       /* USB - PU0/DP Input Data */
3091 
#define PUIN1                  (0x0008)       /* USB - PU1/DM Input Data */
3092 
//#define RESERVED            (0x0010)  /* USB -  */
3093 
#define PUOPE                  (0x0020)       /* USB - USB Port Output Enable */
3094 
//#define RESERVED            (0x0040)  /* USB -  */
3095 
#define PUSEL                  (0x0080)       /* USB - USB Port Function Select */
3096 
#define PUIPE                  (0x0100)       /* USB - PHY Single Ended Input enable */
3097 
//#define RESERVED            (0x0200)  /* USB -  */
3098 
//#define RESERVED            (0x0100)  /* USB -  */
3099 
//#define RESERVED            (0x0200)  /* USB -  */
3100 
//#define RESERVED            (0x0400)  /* USB -  */
3101 
//#define RESERVED            (0x0800)  /* USB -  */
3102 
//#define RESERVED            (0x1000)  /* USB -  */
3103 
//#define RESERVED            (0x2000)  /* USB -  */
3104 
//#define RESERVED            (0x4000)  /* USB -  */
3105 
//#define RESERVED            (0x8000)  /* USB -  */
3106 
 
3107 
/* USBPHYCTL Control Bits */
3108 
#define PUOUT0_L               (0x0001)       /* USB - USB Port Output Signal Bit 0 */
3109 
#define PUOUT1_L               (0x0002)       /* USB - USB Port Output Signal Bit 1 */
3110 
#define PUIN0_L                (0x0004)       /* USB - PU0/DP Input Data */
3111 
#define PUIN1_L                (0x0008)       /* USB - PU1/DM Input Data */
3112 
//#define RESERVED            (0x0010)  /* USB -  */
3113 
#define PUOPE_L                (0x0020)       /* USB - USB Port Output Enable */
3114 
//#define RESERVED            (0x0040)  /* USB -  */
3115 
#define PUSEL_L                (0x0080)       /* USB - USB Port Function Select */
3116 
//#define RESERVED            (0x0200)  /* USB -  */
3117 
//#define RESERVED            (0x0100)  /* USB -  */
3118 
//#define RESERVED            (0x0200)  /* USB -  */
3119 
//#define RESERVED            (0x0400)  /* USB -  */
3120 
//#define RESERVED            (0x0800)  /* USB -  */
3121 
//#define RESERVED            (0x1000)  /* USB -  */
3122 
//#define RESERVED            (0x2000)  /* USB -  */
3123 
//#define RESERVED            (0x4000)  /* USB -  */
3124 
//#define RESERVED            (0x8000)  /* USB -  */
3125 
 
3126 
/* USBPHYCTL Control Bits */
3127 
//#define RESERVED            (0x0010)  /* USB -  */
3128 
//#define RESERVED            (0x0040)  /* USB -  */
3129 
#define PUIPE_H                (0x0001)       /* USB - PHY Single Ended Input enable */
3130 
//#define RESERVED            (0x0200)  /* USB -  */
3131 
//#define RESERVED            (0x0100)  /* USB -  */
3132 
//#define RESERVED            (0x0200)  /* USB -  */
3133 
//#define RESERVED            (0x0400)  /* USB -  */
3134 
//#define RESERVED            (0x0800)  /* USB -  */
3135 
//#define RESERVED            (0x1000)  /* USB -  */
3136 
//#define RESERVED            (0x2000)  /* USB -  */
3137 
//#define RESERVED            (0x4000)  /* USB -  */
3138 
//#define RESERVED            (0x8000)  /* USB -  */
3139 
 
3140 
#define PUDIR                  (0x0020)       /* USB - Legacy Definition: USB Port Output Enable */
3141 
#define PSEIEN                 (0x0100)       /* USB - Legacy Definition: PHY Single Ended Input enable */
3142 
 
3143 
/* USBPWRCTL Control Bits */
3144 
#define VUOVLIFG               (0x0001)       /* USB - VUSB Overload Interrupt Flag */
3145 
#define VBONIFG                (0x0002)       /* USB - VBUS "Coming ON" Interrupt Flag */
3146 
#define VBOFFIFG               (0x0004)       /* USB - VBUS "Going OFF" Interrupt Flag */
3147 
#define USBBGVBV               (0x0008)       /* USB - USB Bandgap and VBUS valid */
3148 
#define USBDETEN               (0x0010)       /* USB - VBUS on/off events enable */
3149 
#define OVLAOFF                (0x0020)       /* USB - LDO overload auto off enable */
3150 
#define SLDOAON                (0x0040)       /* USB - Secondary LDO auto on enable */
3151 
//#define RESERVED            (0x0080)  /* USB -  */
3152 
#define VUOVLIE                (0x0100)       /* USB - Overload indication Interrupt Enable */
3153 
#define VBONIE                 (0x0200)       /* USB - VBUS "Coming ON" Interrupt Enable */
3154 
#define VBOFFIE                (0x0400)       /* USB - VBUS "Going OFF" Interrupt Enable */
3155 
#define VUSBEN                 (0x0800)       /* USB - LDO Enable (3.3V) */
3156 
#define SLDOEN                 (0x1000)       /* USB - Secondary LDO Enable (1.8V) */
3157 
//#define RESERVED            (0x2000)  /* USB -  */
3158 
//#define RESERVED            (0x4000)  /* USB -  */
3159 
//#define RESERVED            (0x8000)  /* USB -  */
3160 
 
3161 
/* USBPWRCTL Control Bits */
3162 
#define VUOVLIFG_L             (0x0001)       /* USB - VUSB Overload Interrupt Flag */
3163 
#define VBONIFG_L              (0x0002)       /* USB - VBUS "Coming ON" Interrupt Flag */
3164 
#define VBOFFIFG_L             (0x0004)       /* USB - VBUS "Going OFF" Interrupt Flag */
3165 
#define USBBGVBV_L             (0x0008)       /* USB - USB Bandgap and VBUS valid */
3166 
#define USBDETEN_L             (0x0010)       /* USB - VBUS on/off events enable */
3167 
#define OVLAOFF_L              (0x0020)       /* USB - LDO overload auto off enable */
3168 
#define SLDOAON_L              (0x0040)       /* USB - Secondary LDO auto on enable */
3169 
//#define RESERVED            (0x0080)  /* USB -  */
3170 
//#define RESERVED            (0x2000)  /* USB -  */
3171 
//#define RESERVED            (0x4000)  /* USB -  */
3172 
//#define RESERVED            (0x8000)  /* USB -  */
3173 
 
3174 
/* USBPWRCTL Control Bits */
3175 
//#define RESERVED            (0x0080)  /* USB -  */
3176 
#define VUOVLIE_H              (0x0001)       /* USB - Overload indication Interrupt Enable */
3177 
#define VBONIE_H               (0x0002)       /* USB - VBUS "Coming ON" Interrupt Enable */
3178 
#define VBOFFIE_H              (0x0004)       /* USB - VBUS "Going OFF" Interrupt Enable */
3179 
#define VUSBEN_H               (0x0008)       /* USB - LDO Enable (3.3V) */
3180 
#define SLDOEN_H               (0x0010)       /* USB - Secondary LDO Enable (1.8V) */
3181 
//#define RESERVED            (0x2000)  /* USB -  */
3182 
//#define RESERVED            (0x4000)  /* USB -  */
3183 
//#define RESERVED            (0x8000)  /* USB -  */
3184 
 
3185 
/* USBPLLCTL Control Bits */
3186 
//#define RESERVED            (0x0001)  /* USB -  */
3187 
//#define RESERVED            (0x0002)  /* USB -  */
3188 
//#define RESERVED            (0x0004)  /* USB -  */
3189 
//#define RESERVED            (0x0008)  /* USB -  */
3190 
//#define RESERVED            (0x0010)  /* USB -  */
3191 
//#define RESERVED            (0x0020)  /* USB -  */
3192 
#define UCLKSEL0               (0x0040)       /* USB - Module Clock Select Bit 0 */
3193 
#define UCLKSEL1               (0x0080)       /* USB - Module Clock Select Bit 1 */
3194 
#define UPLLEN                 (0x0100)       /* USB - PLL enable */
3195 
#define UPFDEN                 (0x0200)       /* USB - Phase Freq. Discriminator enable */
3196 
//#define RESERVED            (0x0400)  /* USB -  */
3197 
//#define RESERVED            (0x0800)  /* USB -  */
3198 
#define UPCS0                  (0x1000)       /* USB - PLL Clock Select Bit 0 */
3199 
//#define RESERVED            (0x2000)  /* USB -  */
3200 
//#define RESERVED            (0x4000)  /* USB -  */
3201 
//#define RESERVED            (0x8000)  /* USB -  */
3202 
 
3203 
/* USBPLLCTL Control Bits */
3204 
//#define RESERVED            (0x0001)  /* USB -  */
3205 
//#define RESERVED            (0x0002)  /* USB -  */
3206 
//#define RESERVED            (0x0004)  /* USB -  */
3207 
//#define RESERVED            (0x0008)  /* USB -  */
3208 
//#define RESERVED            (0x0010)  /* USB -  */
3209 
//#define RESERVED            (0x0020)  /* USB -  */
3210 
#define UCLKSEL0_L             (0x0040)       /* USB - Module Clock Select Bit 0 */
3211 
#define UCLKSEL1_L             (0x0080)       /* USB - Module Clock Select Bit 1 */
3212 
//#define RESERVED            (0x0400)  /* USB -  */
3213 
//#define RESERVED            (0x0800)  /* USB -  */
3214 
//#define RESERVED            (0x2000)  /* USB -  */
3215 
//#define RESERVED            (0x4000)  /* USB -  */
3216 
//#define RESERVED            (0x8000)  /* USB -  */
3217 
 
3218 
/* USBPLLCTL Control Bits */
3219 
//#define RESERVED            (0x0001)  /* USB -  */
3220 
//#define RESERVED            (0x0002)  /* USB -  */
3221 
//#define RESERVED            (0x0004)  /* USB -  */
3222 
//#define RESERVED            (0x0008)  /* USB -  */
3223 
//#define RESERVED            (0x0010)  /* USB -  */
3224 
//#define RESERVED            (0x0020)  /* USB -  */
3225 
#define UPLLEN_H               (0x0001)       /* USB - PLL enable */
3226 
#define UPFDEN_H               (0x0002)       /* USB - Phase Freq. Discriminator enable */
3227 
//#define RESERVED            (0x0400)  /* USB -  */
3228 
//#define RESERVED            (0x0800)  /* USB -  */
3229 
#define UPCS0_H                (0x0010)       /* USB - PLL Clock Select Bit 0 */
3230 
//#define RESERVED            (0x2000)  /* USB -  */
3231 
//#define RESERVED            (0x4000)  /* USB -  */
3232 
//#define RESERVED            (0x8000)  /* USB -  */
3233 
 
3234 
#define UCLKSEL_0              (0x0000)       /* USB - Module Clock Select: 0 */
3235 
#define UCLKSEL_1              (0x0040)       /* USB - Module Clock Select: 1 */
3236 
#define UCLKSEL_2              (0x0080)       /* USB - Module Clock Select: 2 */
3237 
#define UCLKSEL_3              (0x00C0)       /* USB - Module Clock Select: 3 (Reserved) */
3238 
 
3239 
#define UCLKSEL__PLLCLK        (0x0000)       /* USB - Module Clock Select: PLLCLK */
3240 
#define UCLKSEL__XT1CLK        (0x0040)       /* USB - Module Clock Select: XT1CLK */
3241 
#define UCLKSEL__XT2CLK        (0x0080)       /* USB - Module Clock Select: XT2CLK */
3242 
 
3243 
/* USBPLLDIVB Control Bits */
3244 
#define UPMB0                  (0x0001)       /* USB - PLL feedback divider buffer Bit 0 */
3245 
#define UPMB1                  (0x0002)       /* USB - PLL feedback divider buffer Bit 1 */
3246 
#define UPMB2                  (0x0004)       /* USB - PLL feedback divider buffer Bit 2 */
3247 
#define UPMB3                  (0x0008)       /* USB - PLL feedback divider buffer Bit 3 */
3248 
#define UPMB4                  (0x0010)       /* USB - PLL feedback divider buffer Bit 4 */
3249 
#define UPMB5                  (0x0020)       /* USB - PLL feedback divider buffer Bit 5 */
3250 
//#define RESERVED            (0x0040)  /* USB -  */
3251 
//#define RESERVED            (0x0080)  /* USB -  */
3252 
#define UPQB0                  (0x0100)       /* USB - PLL prescale divider buffer Bit 0 */
3253 
#define UPQB1                  (0x0200)       /* USB - PLL prescale divider buffer Bit 1 */
3254 
#define UPQB2                  (0x0400)       /* USB - PLL prescale divider buffer Bit 2 */
3255 
//#define RESERVED            (0x0800)  /* USB -  */
3256 
//#define RESERVED            (0x1000)  /* USB -  */
3257 
//#define RESERVED            (0x2000)  /* USB -  */
3258 
//#define RESERVED            (0x4000)  /* USB -  */
3259 
//#define RESERVED            (0x8000)  /* USB -  */
3260 
 
3261 
/* USBPLLDIVB Control Bits */
3262 
#define UPMB0_L                (0x0001)       /* USB - PLL feedback divider buffer Bit 0 */
3263 
#define UPMB1_L                (0x0002)       /* USB - PLL feedback divider buffer Bit 1 */
3264 
#define UPMB2_L                (0x0004)       /* USB - PLL feedback divider buffer Bit 2 */
3265 
#define UPMB3_L                (0x0008)       /* USB - PLL feedback divider buffer Bit 3 */
3266 
#define UPMB4_L                (0x0010)       /* USB - PLL feedback divider buffer Bit 4 */
3267 
#define UPMB5_L                (0x0020)       /* USB - PLL feedback divider buffer Bit 5 */
3268 
//#define RESERVED            (0x0040)  /* USB -  */
3269 
//#define RESERVED            (0x0080)  /* USB -  */
3270 
//#define RESERVED            (0x0800)  /* USB -  */
3271 
//#define RESERVED            (0x1000)  /* USB -  */
3272 
//#define RESERVED            (0x2000)  /* USB -  */
3273 
//#define RESERVED            (0x4000)  /* USB -  */
3274 
//#define RESERVED            (0x8000)  /* USB -  */
3275 
 
3276 
/* USBPLLDIVB Control Bits */
3277 
//#define RESERVED            (0x0040)  /* USB -  */
3278 
//#define RESERVED            (0x0080)  /* USB -  */
3279 
#define UPQB0_H                (0x0001)       /* USB - PLL prescale divider buffer Bit 0 */
3280 
#define UPQB1_H                (0x0002)       /* USB - PLL prescale divider buffer Bit 1 */
3281 
#define UPQB2_H                (0x0004)       /* USB - PLL prescale divider buffer Bit 2 */
3282 
//#define RESERVED            (0x0800)  /* USB -  */
3283 
//#define RESERVED            (0x1000)  /* USB -  */
3284 
//#define RESERVED            (0x2000)  /* USB -  */
3285 
//#define RESERVED            (0x4000)  /* USB -  */
3286 
//#define RESERVED            (0x8000)  /* USB -  */
3287 
 
3288 
#define USBPLL_SETCLK_1_5      (UPMB0*31      | UPQB0*0)  /* USB - PLL Set for 1.5 MHz input clock */
3289 
#define USBPLL_SETCLK_1_6      (UPMB0*29      | UPQB0*0)  /* USB - PLL Set for 1.6 MHz input clock */
3290 
#define USBPLL_SETCLK_1_7778   (UPMB0*26      | UPQB0*0)  /* USB - PLL Set for 1.7778 MHz input clock */
3291 
#define USBPLL_SETCLK_1_8432   (UPMB0*25      | UPQB0*0)  /* USB - PLL Set for 1.8432 MHz input clock */
3292 
#define USBPLL_SETCLK_1_8461   (UPMB0*25      | UPQB0*0)  /* USB - PLL Set for 1.8461 MHz input clock */
3293 
#define USBPLL_SETCLK_1_92     (UPMB0*24      | UPQB0*0)  /* USB - PLL Set for 1.92 MHz input clock */
3294 
#define USBPLL_SETCLK_2_0      (UPMB0*23      | UPQB0*0)  /* USB - PLL Set for 2.0 MHz input clock */
3295 
#define USBPLL_SETCLK_2_4      (UPMB0*19      | UPQB0*0)  /* USB - PLL Set for 2.4 MHz input clock */
3296 
#define USBPLL_SETCLK_2_6667   (UPMB0*17      | UPQB0*0)  /* USB - PLL Set for 2.6667 MHz input clock */
3297 
#define USBPLL_SETCLK_3_0      (UPMB0*15      | UPQB0*0)  /* USB - PLL Set for 3.0 MHz input clock */
3298 
#define USBPLL_SETCLK_3_2      (UPMB0*29      | UPQB0*1)  /* USB - PLL Set for 3.2 MHz input clock */
3299 
#define USBPLL_SETCLK_3_5556   (UPMB0*26      | UPQB0*1)  /* USB - PLL Set for 3.5556 MHz input clock */
3300 
#define USBPLL_SETCLK_3_579545 (UPMB0*26      | UPQB0*1)  /* USB - PLL Set for 3.579546 MHz input clock */
3301 
#define USBPLL_SETCLK_3_84     (UPMB0*24      | UPQB0*1)  /* USB - PLL Set for 3.84 MHz input clock */
3302 
#define USBPLL_SETCLK_4_0      (UPMB0*23      | UPQB0*1)  /* USB - PLL Set for 4.0 MHz input clock */
3303 
#define USBPLL_SETCLK_4_1739   (UPMB0*22      | UPQB0*1)  /* USB - PLL Set for 4.1739 MHz input clock */
3304 
#define USBPLL_SETCLK_4_1943   (UPMB0*22      | UPQB0*1)  /* USB - PLL Set for 4.1943 MHz input clock */
3305 
#define USBPLL_SETCLK_4_332    (UPMB0*21      | UPQB0*1)  /* USB - PLL Set for 4.332 MHz input clock */
3306 
#define USBPLL_SETCLK_4_3636   (UPMB0*21      | UPQB0*1)  /* USB - PLL Set for 4.3636 MHz input clock */
3307 
#define USBPLL_SETCLK_4_5      (UPMB0*31      | UPQB0*2)  /* USB - PLL Set for 4.5 MHz input clock */
3308 
#define USBPLL_SETCLK_4_8      (UPMB0*19      | UPQB0*1)  /* USB - PLL Set for 4.8 MHz input clock */
3309 
#define USBPLL_SETCLK_5_33     (UPMB0*17      | UPQB0*1)  /* USB - PLL Set for 5.33 MHz input clock */
3310 
#define USBPLL_SETCLK_5_76     (UPMB0*24      | UPQB0*2)  /* USB - PLL Set for 5.76 MHz input clock */
3311 
#define USBPLL_SETCLK_6_0      (UPMB0*23      | UPQB0*2)  /* USB - PLL Set for 6.0 MHz input clock */
3312 
#define USBPLL_SETCLK_6_4      (UPMB0*29      | UPQB0*3)  /* USB - PLL Set for 6.4 MHz input clock */
3313 
#define USBPLL_SETCLK_7_2      (UPMB0*19      | UPQB0*2)  /* USB - PLL Set for 7.2 MHz input clock */
3314 
#define USBPLL_SETCLK_7_68     (UPMB0*24      | UPQB0*3)  /* USB - PLL Set for 7.68 MHz input clock */
3315 
#define USBPLL_SETCLK_8_0      (UPMB0*17      | UPQB0*2)  /* USB - PLL Set for 8.0 MHz input clock */
3316 
#define USBPLL_SETCLK_9_0      (UPMB0*15      | UPQB0*2)  /* USB - PLL Set for 9.0 MHz input clock */
3317 
#define USBPLL_SETCLK_9_6      (UPMB0*19      | UPQB0*3)  /* USB - PLL Set for 9.6 MHz input clock */
3318 
#define USBPLL_SETCLK_10_66    (UPMB0*17      | UPQB0*3)  /* USB - PLL Set for 10.66 MHz input clock */
3319 
#define USBPLL_SETCLK_12_0     (UPMB0*15      | UPQB0*3)  /* USB - PLL Set for 12.0 MHz input clock */
3320 
#define USBPLL_SETCLK_12_8     (UPMB0*29      | UPQB0*5)  /* USB - PLL Set for 12.8 MHz input clock */
3321 
#define USBPLL_SETCLK_14_4     (UPMB0*19      | UPQB0*4)  /* USB - PLL Set for 14.4 MHz input clock */
3322 
#define USBPLL_SETCLK_16_0     (UPMB0*17      | UPQB0*4)  /* USB - PLL Set for 16.0 MHz input clock */
3323 
#define USBPLL_SETCLK_16_9344  (UPMB0*16      | UPQB0*4)  /* USB - PLL Set for 16.9344 MHz input clock */
3324 
#define USBPLL_SETCLK_16_94118 (UPMB0*16      | UPQB0*4)  /* USB - PLL Set for 16.94118 MHz input clock */
3325 
#define USBPLL_SETCLK_18_0     (UPMB0*15      | UPQB0*4)  /* USB - PLL Set for 18.0 MHz input clock */
3326 
#define USBPLL_SETCLK_19_2     (UPMB0*19      | UPQB0*5)  /* USB - PLL Set for 19.2 MHz input clock */
3327 
#define USBPLL_SETCLK_24_0     (UPMB0*15      | UPQB0*5)  /* USB - PLL Set for 24.0 MHz input clock */
3328 
#define USBPLL_SETCLK_25_6     (UPMB0*29      | UPQB0*7)  /* USB - PLL Set for 25.6 MHz input clock */
3329 
#define USBPLL_SETCLK_26_0     (UPMB0*23      | UPQB0*6)  /* USB - PLL Set for 26.0 MHz input clock */
3330 
#define USBPLL_SETCLK_32_0     (UPMB0*23      | UPQB0*7)  /* USB - PLL Set for 32.0 MHz input clock */
3331 
 
3332 
/* USBPLLIR Control Bits */
3333 
#define USBOOLIFG              (0x0001)       /* USB - PLL out of lock Interrupt Flag */
3334 
#define USBLOSIFG              (0x0002)       /* USB - PLL loss of signal Interrupt Flag */
3335 
#define USBOORIFG              (0x0004)       /* USB - PLL out of range Interrupt Flag */
3336 
//#define RESERVED            (0x0008)  /* USB -  */
3337 
//#define RESERVED            (0x0010)  /* USB -  */
3338 
//#define RESERVED            (0x0020)  /* USB -  */
3339 
//#define RESERVED            (0x0040)  /* USB -  */
3340 
//#define RESERVED            (0x0080)  /* USB -  */
3341 
#define USBOOLIE               (0x0100)       /* USB - PLL out of lock Interrupt enable */
3342 
#define USBLOSIE               (0x0200)       /* USB - PLL loss of signal Interrupt enable */
3343 
#define USBOORIE               (0x0400)       /* USB - PLL out of range Interrupt enable */
3344 
//#define RESERVED            (0x0800)  /* USB -  */
3345 
//#define RESERVED            (0x1000)  /* USB -  */
3346 
//#define RESERVED            (0x2000)  /* USB -  */
3347 
//#define RESERVED            (0x4000)  /* USB -  */
3348 
//#define RESERVED            (0x8000)  /* USB -  */
3349 
 
3350 
/* USBPLLIR Control Bits */
3351 
#define USBOOLIFG_L            (0x0001)       /* USB - PLL out of lock Interrupt Flag */
3352 
#define USBLOSIFG_L            (0x0002)       /* USB - PLL loss of signal Interrupt Flag */
3353 
#define USBOORIFG_L            (0x0004)       /* USB - PLL out of range Interrupt Flag */
3354 
//#define RESERVED            (0x0008)  /* USB -  */
3355 
//#define RESERVED            (0x0010)  /* USB -  */
3356 
//#define RESERVED            (0x0020)  /* USB -  */
3357 
//#define RESERVED            (0x0040)  /* USB -  */
3358 
//#define RESERVED            (0x0080)  /* USB -  */
3359 
//#define RESERVED            (0x0800)  /* USB -  */
3360 
//#define RESERVED            (0x1000)  /* USB -  */
3361 
//#define RESERVED            (0x2000)  /* USB -  */
3362 
//#define RESERVED            (0x4000)  /* USB -  */
3363 
//#define RESERVED            (0x8000)  /* USB -  */
3364 
 
3365 
/* USBPLLIR Control Bits */
3366 
//#define RESERVED            (0x0008)  /* USB -  */
3367 
//#define RESERVED            (0x0010)  /* USB -  */
3368 
//#define RESERVED            (0x0020)  /* USB -  */
3369 
//#define RESERVED            (0x0040)  /* USB -  */
3370 
//#define RESERVED            (0x0080)  /* USB -  */
3371 
#define USBOOLIE_H             (0x0001)       /* USB - PLL out of lock Interrupt enable */
3372 
#define USBLOSIE_H             (0x0002)       /* USB - PLL loss of signal Interrupt enable */
3373 
#define USBOORIE_H             (0x0004)       /* USB - PLL out of range Interrupt enable */
3374 
//#define RESERVED            (0x0800)  /* USB -  */
3375 
//#define RESERVED            (0x1000)  /* USB -  */
3376 
//#define RESERVED            (0x2000)  /* USB -  */
3377 
//#define RESERVED            (0x4000)  /* USB -  */
3378 
//#define RESERVED            (0x8000)  /* USB -  */
3379 
 
3380 
/* ========================================================================= */
3381 
/* USB Control Registers */
3382 
/* ========================================================================= */
3383 
SFR_8BIT(USBIEPCNF_0);                        /* USB Input endpoint_0: Configuration */
3384 
SFR_8BIT(USBIEPCNT_0);                        /* USB Input endpoint_0: Byte Count */
3385 
SFR_8BIT(USBOEPCNF_0);                        /* USB Output endpoint_0: Configuration */
3386 
SFR_8BIT(USBOEPCNT_0);                        /* USB Output endpoint_0: byte count */
3387 
SFR_8BIT(USBIEPIE);                           /* USB Input endpoint interrupt enable flags */
3388 
SFR_8BIT(USBOEPIE);                           /* USB Output endpoint interrupt enable flags */
3389 
SFR_8BIT(USBIEPIFG);                          /* USB Input endpoint interrupt flags */
3390 
SFR_8BIT(USBOEPIFG);                          /* USB Output endpoint interrupt flags */
3391 
SFR_16BIT(USBVECINT);                         /* USB Vector interrupt register */
3392 
SFR_8BIT(USBVECINT_L);                        /* USB Vector interrupt register */
3393 
SFR_8BIT(USBVECINT_H);                        /* USB Vector interrupt register */
3394 
SFR_16BIT(USBMAINT);                          /* USB maintenance register */
3395 
SFR_8BIT(USBMAINT_L);                         /* USB maintenance register */
3396 
SFR_8BIT(USBMAINT_H);                         /* USB maintenance register */
3397 
SFR_16BIT(USBTSREG);                          /* USB Time Stamp register */
3398 
SFR_8BIT(USBTSREG_L);                         /* USB Time Stamp register */
3399 
SFR_8BIT(USBTSREG_H);                         /* USB Time Stamp register */
3400 
SFR_16BIT(USBFN);                             /* USB Frame number */
3401 
SFR_8BIT(USBFN_L);                            /* USB Frame number */
3402 
SFR_8BIT(USBFN_H);                            /* USB Frame number */
3403 
SFR_8BIT(USBCTL);                             /* USB control register */
3404 
SFR_8BIT(USBIE);                              /* USB interrupt enable register */
3405 
SFR_8BIT(USBIFG);                             /* USB interrupt flag register */
3406 
SFR_8BIT(USBFUNADR);                          /* USB Function address register */
3407 
 
3408 
#define USBIV                  USBVECINT      /* USB Vector interrupt register (alternate define) */
3409 
 
3410 
/* USBIEPCNF_0 Control Bits */
3411 
/* USBOEPCNF_0 Control Bits */
3412 
//#define RESERVED       (0x0001)  /* USB -  */
3413 
//#define RESERVED       (0x0001)  /* USB -  */
3414 
#define USBIIE                 (0x0004)       /* USB - Transaction Interrupt indication enable */
3415 
#define STALL                  (0x0008)       /* USB - Stall Condition */
3416 
//#define RESERVED       (0x0010)  /* USB -  */
3417 
#define TOGGLE                 (0x0020)       /* USB - Toggle Bit */
3418 
//#define RESERVED       (0x0040)  /* USB -  */
3419 
#define UBME                   (0x0080)       /* USB - UBM In-Endpoint Enable */
3420 
 
3421 
/* USBIEPBCNT_0 Control Bits */
3422 
/* USBOEPBCNT_0 Control Bits */
3423 
#define CNT0                   (0x0001)       /* USB - Byte Count Bit 0 */
3424 
#define CNT1                   (0x0001)       /* USB - Byte Count Bit 1 */
3425 
#define CNT2                   (0x0004)       /* USB - Byte Count Bit 2 */
3426 
#define CNT3                   (0x0008)       /* USB - Byte Count Bit 3 */
3427 
//#define RESERVED       (0x0010)  /* USB -  */
3428 
//#define RESERVED       (0x0020)  /* USB -  */
3429 
//#define RESERVED       (0x0040)  /* USB -  */
3430 
#define NAK                    (0x0080)       /* USB - No Acknowledge Status Bit */
3431 
 
3432 
/* USBMAINT Control Bits */
3433 
#define UTIFG                  (0x0001)       /* USB - Timer Interrupt Flag */
3434 
#define UTIE                   (0x0002)       /* USB - Timer Interrupt Enable */
3435 
//#define RESERVED       (0x0004)  /* USB -  */
3436 
//#define RESERVED       (0x0008)  /* USB -  */
3437 
//#define RESERVED       (0x0010)  /* USB -  */
3438 
//#define RESERVED       (0x0020)  /* USB -  */
3439 
//#define RESERVED       (0x0040)  /* USB -  */
3440 
//#define RESERVED       (0x0080)  /* USB -  */
3441 
#define TSGEN                  (0x0100)       /* USB - Time Stamp Generator Enable */
3442 
#define TSESEL0                (0x0200)       /* USB - Time Stamp Event Select Bit 0 */
3443 
#define TSESEL1                (0x0400)       /* USB - Time Stamp Event Select Bit 1 */
3444 
#define TSE3                   (0x0800)       /* USB - Time Stamp Event #3 Bit */
3445 
//#define RESERVED       (0x1000)  /* USB -  */
3446 
#define UTSEL0                 (0x2000)       /* USB - Timer Select Bit 0 */
3447 
#define UTSEL1                 (0x4000)       /* USB - Timer Select Bit 1 */
3448 
#define UTSEL2                 (0x8000)       /* USB - Timer Select Bit 2 */
3449 
 
3450 
/* USBMAINT Control Bits */
3451 
#define UTIFG_L                (0x0001)       /* USB - Timer Interrupt Flag */
3452 
#define UTIE_L                 (0x0002)       /* USB - Timer Interrupt Enable */
3453 
//#define RESERVED       (0x0004)  /* USB -  */
3454 
//#define RESERVED       (0x0008)  /* USB -  */
3455 
//#define RESERVED       (0x0010)  /* USB -  */
3456 
//#define RESERVED       (0x0020)  /* USB -  */
3457 
//#define RESERVED       (0x0040)  /* USB -  */
3458 
//#define RESERVED       (0x0080)  /* USB -  */
3459 
//#define RESERVED       (0x1000)  /* USB -  */
3460 
 
3461 
/* USBMAINT Control Bits */
3462 
//#define RESERVED       (0x0004)  /* USB -  */
3463 
//#define RESERVED       (0x0008)  /* USB -  */
3464 
//#define RESERVED       (0x0010)  /* USB -  */
3465 
//#define RESERVED       (0x0020)  /* USB -  */
3466 
//#define RESERVED       (0x0040)  /* USB -  */
3467 
//#define RESERVED       (0x0080)  /* USB -  */
3468 
#define TSGEN_H                (0x0001)       /* USB - Time Stamp Generator Enable */
3469 
#define TSESEL0_H              (0x0002)       /* USB - Time Stamp Event Select Bit 0 */
3470 
#define TSESEL1_H              (0x0004)       /* USB - Time Stamp Event Select Bit 1 */
3471 
#define TSE3_H                 (0x0008)       /* USB - Time Stamp Event #3 Bit */
3472 
//#define RESERVED       (0x1000)  /* USB -  */
3473 
#define UTSEL0_H               (0x0020)       /* USB - Timer Select Bit 0 */
3474 
#define UTSEL1_H               (0x0040)       /* USB - Timer Select Bit 1 */
3475 
#define UTSEL2_H               (0x0080)       /* USB - Timer Select Bit 2 */
3476 
 
3477 
#define TSESEL_0               (0x0000)       /* USB - Time Stamp Event Select: 0 */
3478 
#define TSESEL_1               (0x0200)       /* USB - Time Stamp Event Select: 1 */
3479 
#define TSESEL_2               (0x0400)       /* USB - Time Stamp Event Select: 2 */
3480 
#define TSESEL_3               (0x0600)       /* USB - Time Stamp Event Select: 3 */
3481 
 
3482 
#define UTSEL_0                (0x0000)       /* USB - Timer Select: 0 */
3483 
#define UTSEL_1                (0x2000)       /* USB - Timer Select: 1 */
3484 
#define UTSEL_2                (0x4000)       /* USB - Timer Select: 2 */
3485 
#define UTSEL_3                (0x6000)       /* USB - Timer Select: 3 */
3486 
#define UTSEL_4                (0x8000)       /* USB - Timer Select: 4 */
3487 
#define UTSEL_5                (0xA000)       /* USB - Timer Select: 5 */
3488 
#define UTSEL_6                (0xC000)       /* USB - Timer Select: 6 */
3489 
#define UTSEL_7                (0xE000)       /* USB - Timer Select: 7 */
3490 
 
3491 
/* USBCTL Control Bits */
3492 
#define DIR                    (0x0001)       /* USB - Data Response Bit */
3493 
//#define RESERVED       (0x0002)  /* USB -  */
3494 
//#define RESERVED       (0x0004)  /* USB -  */
3495 
//#define RESERVED       (0x0008)  /* USB -  */
3496 
#define FRSTE                  (0x0010)       /* USB - Function Reset Connection Enable */
3497 
#define RWUP                   (0x0020)       /* USB - Device Remote Wakeup Request */
3498 
#define FEN                    (0x0040)       /* USB - Function Enable Bit */
3499 
//#define RESERVED       (0x0080)  /* USB -  */
3500 
 
3501 
/* USBIE Control Bits */
3502 
#define STPOWIE                (0x0001)       /* USB - Setup Overwrite Interrupt Enable */
3503 
//#define RESERVED       (0x0002)  /* USB -  */
3504 
#define SETUPIE                (0x0004)       /* USB - Setup Interrupt Enable */
3505 
//#define RESERVED       (0x0008)  /* USB -  */
3506 
//#define RESERVED       (0x0010)  /* USB -  */
3507 
#define RESRIE                 (0x0020)       /* USB - Function Resume Request Interrupt Enable */
3508 
#define SUSRIE                 (0x0040)       /* USB - Function Suspend Request Interrupt Enable */
3509 
#define RSTRIE                 (0x0080)       /* USB - Function Reset Request Interrupt Enable */
3510 
 
3511 
/* USBIFG Control Bits */
3512 
#define STPOWIFG               (0x0001)       /* USB - Setup Overwrite Interrupt Flag */
3513 
//#define RESERVED       (0x0002)  /* USB -  */
3514 
#define SETUPIFG               (0x0004)       /* USB - Setup Interrupt Flag */
3515 
//#define RESERVED       (0x0008)  /* USB -  */
3516 
//#define RESERVED       (0x0010)  /* USB -  */
3517 
#define RESRIFG                (0x0020)       /* USB - Function Resume Request Interrupt Flag */
3518 
#define SUSRIFG                (0x0040)       /* USB - Function Suspend Request Interrupt Flag */
3519 
#define RSTRIFG                (0x0080)       /* USB - Function Reset Request Interrupt Flag */
3520 
 
3521 
//values of USBVECINT when USB-interrupt occured
3522 
#define     USBVECINT_NONE     0x00
3523 
#define     USBVECINT_PWR_DROP 0x02
3524 
#define     USBVECINT_PLL_LOCK 0x04
3525 
#define     USBVECINT_PLL_SIGNAL 0x06
3526 
#define     USBVECINT_PLL_RANGE 0x08
3527 
#define     USBVECINT_PWR_VBUSOn 0x0A
3528 
#define     USBVECINT_PWR_VBUSOff 0x0C
3529 
#define     USBVECINT_USB_TIMESTAMP 0x10
3530 
#define     USBVECINT_INPUT_ENDPOINT0 0x12
3531 
#define     USBVECINT_OUTPUT_ENDPOINT0 0x14
3532 
#define     USBVECINT_RSTR     0x16
3533 
#define     USBVECINT_SUSR     0x18
3534 
#define     USBVECINT_RESR     0x1A
3535 
#define     USBVECINT_SETUP_PACKET_RECEIVED 0x20
3536 
#define     USBVECINT_STPOW_PACKET_RECEIVED 0x22
3537 
#define     USBVECINT_INPUT_ENDPOINT1 0x24
3538 
#define     USBVECINT_INPUT_ENDPOINT2 0x26
3539 
#define     USBVECINT_INPUT_ENDPOINT3 0x28
3540 
#define     USBVECINT_INPUT_ENDPOINT4 0x2A
3541 
#define     USBVECINT_INPUT_ENDPOINT5 0x2C
3542 
#define     USBVECINT_INPUT_ENDPOINT6 0x2E
3543 
#define     USBVECINT_INPUT_ENDPOINT7 0x30
3544 
#define     USBVECINT_OUTPUT_ENDPOINT1 0x32
3545 
#define     USBVECINT_OUTPUT_ENDPOINT2 0x34
3546 
#define     USBVECINT_OUTPUT_ENDPOINT3 0x36
3547 
#define     USBVECINT_OUTPUT_ENDPOINT4 0x38
3548 
#define     USBVECINT_OUTPUT_ENDPOINT5 0x3A
3549 
#define     USBVECINT_OUTPUT_ENDPOINT6 0x3C
3550 
#define     USBVECINT_OUTPUT_ENDPOINT7 0x3E
3551 
 
3552 
 
3553 
/* ========================================================================= */
3554 
/* USB Operation Registers */
3555 
/* ========================================================================= */
3556 
 
3557 
SFR_8BIT(USBIEPSIZXY_7);                      /* Input Endpoint_7: X/Y-buffer size  */
3558 
SFR_8BIT(USBIEPBCTY_7);                       /* Input Endpoint_7: Y-byte count  */
3559 
SFR_8BIT(USBIEPBBAY_7);                       /* Input Endpoint_7: Y-buffer base addr.  */
3560 
//sfrb    Spare    (0x23FC)   /* Not used  */
3561 
//sfrb    Spare    (0x23FB)   /* Not used  */
3562 
SFR_8BIT(USBIEPBCTX_7);                       /* Input Endpoint_7: X-byte count  */
3563 
SFR_8BIT(USBIEPBBAX_7);                       /* Input Endpoint_7: X-buffer base addr. */
3564 
SFR_8BIT(USBIEPCNF_7);                        /* Input Endpoint_7: Configuration  */
3565 
SFR_8BIT(USBIEPSIZXY_6);                      /* Input Endpoint_6: X/Y-buffer size  */
3566 
SFR_8BIT(USBIEPBCTY_6);                       /* Input Endpoint_6: Y-byte count */
3567 
SFR_8BIT(USBIEPBBAY_6);                       /* Input Endpoint_6: Y-buffer base addr. */
3568 
//sfrb    Spare    (0x23F4)   /* Not used  */
3569 
//sfrb    Spare    (0x23F3)   /* Not used  */
3570 
SFR_8BIT(USBIEPBCTX_6);                       /* Input Endpoint_6: X-byte count */
3571 
SFR_8BIT(USBIEPBBAX_6);                       /* Input Endpoint_6: X-buffer base addr. */
3572 
SFR_8BIT(USBIEPCNF_6);                        /* Input Endpoint_6: Configuration */
3573 
SFR_8BIT(USBIEPSIZXY_5);                      /* Input Endpoint_5: X/Y-buffer size */
3574 
SFR_8BIT(USBIEPBCTY_5);                       /* Input Endpoint_5: Y-byte count */
3575 
SFR_8BIT(USBIEPBBAY_5);                       /* Input Endpoint_5: Y-buffer base addr. */
3576 
//sfrb    Spare    (0x23EC)   /* Not used */
3577 
//sfrb    Spare    (0x23EB)   /* Not used */
3578 
SFR_8BIT(USBIEPBCTX_5);                       /* Input Endpoint_5: X-byte count */
3579 
SFR_8BIT(USBIEPBBAX_5);                       /* Input Endpoint_5: X-buffer base addr. */
3580 
SFR_8BIT(USBIEPCNF_5);                        /* Input Endpoint_5: Configuration */
3581 
SFR_8BIT(USBIEPSIZXY_4);                      /* Input Endpoint_4: X/Y-buffer size */
3582 
SFR_8BIT(USBIEPBCTY_4);                       /* Input Endpoint_4: Y-byte count */
3583 
SFR_8BIT(USBIEPBBAY_4);                       /* Input Endpoint_4: Y-buffer base addr. */
3584 
//sfrb    Spare    (0x23E4)   /* Not used */
3585 
//sfrb    Spare    (0x23E3)   /* Not used */
3586 
SFR_8BIT(USBIEPBCTX_4);                       /* Input Endpoint_4: X-byte count */
3587 
SFR_8BIT(USBIEPBBAX_4);                       /* Input Endpoint_4: X-buffer base addr. */
3588 
SFR_8BIT(USBIEPCNF_4);                        /* Input Endpoint_4: Configuration */
3589 
SFR_8BIT(USBIEPSIZXY_3);                      /* Input Endpoint_3: X/Y-buffer size */
3590 
SFR_8BIT(USBIEPBCTY_3);                       /* Input Endpoint_3: Y-byte count */
3591 
SFR_8BIT(USBIEPBBAY_3);                       /* Input Endpoint_3: Y-buffer base addr. */
3592 
//sfrb    Spare    (0x23DC)   /* Not used */
3593 
//sfrb    Spare    (0x23DB)   /* Not used */
3594 
SFR_8BIT(USBIEPBCTX_3);                       /* Input Endpoint_3: X-byte count */
3595 
SFR_8BIT(USBIEPBBAX_3);                       /* Input Endpoint_3: X-buffer base addr. */
3596 
SFR_8BIT(USBIEPCNF_3);                        /* Input Endpoint_3: Configuration */
3597 
SFR_8BIT(USBIEPSIZXY_2);                      /* Input Endpoint_2: X/Y-buffer size */
3598 
SFR_8BIT(USBIEPBCTY_2);                       /* Input Endpoint_2: Y-byte count */
3599 
SFR_8BIT(USBIEPBBAY_2);                       /* Input Endpoint_2: Y-buffer base addr. */
3600 
//sfrb    Spare    (0x23D4)   /* Not used */
3601 
//sfrb    Spare    (0x23D3)   /* Not used */
3602 
SFR_8BIT(USBIEPBCTX_2);                       /* Input Endpoint_2: X-byte count */
3603 
SFR_8BIT(USBIEPBBAX_2);                       /* Input Endpoint_2: X-buffer base addr. */
3604 
SFR_8BIT(USBIEPCNF_2);                        /* Input Endpoint_2: Configuration */
3605 
SFR_8BIT(USBIEPSIZXY_1);                      /* Input Endpoint_1: X/Y-buffer size */
3606 
SFR_8BIT(USBIEPBCTY_1);                       /* Input Endpoint_1: Y-byte count */
3607 
SFR_8BIT(USBIEPBBAY_1);                       /* Input Endpoint_1: Y-buffer base addr. */
3608 
//sfrb    Spare    (0x23CC)   /* Not used */
3609 
//sfrb    Spare    (0x23CB)   /* Not used */
3610 
SFR_8BIT(USBIEPBCTX_1);                       /* Input Endpoint_1: X-byte count */
3611 
SFR_8BIT(USBIEPBBAX_1);                       /* Input Endpoint_1: X-buffer base addr. */
3612 
SFR_8BIT(USBIEPCNF_1);                        /* Input Endpoint_1: Configuration */
3613 
//sfrb       (0x23C7)   0x0000 */
3614 
//sfrb     RESERVED      (0x1C00)    /* */
3615 
//sfrb       (0x23C0)   0x0000 */
3616 
SFR_8BIT(USBOEPSIZXY_7);                      /* Output Endpoint_7: X/Y-buffer size */
3617 
SFR_8BIT(USBOEPBCTY_7);                       /* Output Endpoint_7: Y-byte count */
3618 
SFR_8BIT(USBOEPBBAY_7);                       /* Output Endpoint_7: Y-buffer base addr. */
3619 
//sfrb    Spare    (0x23BC)   /* Not used */
3620 
//sfrb    Spare    (0x23BB)   /* Not used */
3621 
SFR_8BIT(USBOEPBCTX_7);                       /* Output Endpoint_7: X-byte count */
3622 
SFR_8BIT(USBOEPBBAX_7);                       /* Output Endpoint_7: X-buffer base addr. */
3623 
SFR_8BIT(USBOEPCNF_7);                        /* Output Endpoint_7: Configuration */
3624 
SFR_8BIT(USBOEPSIZXY_6);                      /* Output Endpoint_6: X/Y-buffer size */
3625 
SFR_8BIT(USBOEPBCTY_6);                       /* Output Endpoint_6: Y-byte count */
3626 
SFR_8BIT(USBOEPBBAY_6);                       /* Output Endpoint_6: Y-buffer base addr. */
3627 
//sfrb    Spare    (0x23B4)   /* Not used */
3628 
//sfrb    Spare    (0x23B3)   /* Not used */
3629 
SFR_8BIT(USBOEPBCTX_6);                       /* Output Endpoint_6: X-byte count */
3630 
SFR_8BIT(USBOEPBBAX_6);                       /* Output Endpoint_6: X-buffer base addr. */
3631 
SFR_8BIT(USBOEPCNF_6);                        /* Output Endpoint_6: Configuration */
3632 
SFR_8BIT(USBOEPSIZXY_5);                      /* Output Endpoint_5: X/Y-buffer size */
3633 
SFR_8BIT(USBOEPBCTY_5);                       /* Output Endpoint_5: Y-byte count */
3634 
SFR_8BIT(USBOEPBBAY_5);                       /* Output Endpoint_5: Y-buffer base addr. */
3635 
//sfrb    Spare    (0x23AC)   /* Not used */
3636 
//sfrb    Spare    (0x23AB)   /* Not used */
3637 
SFR_8BIT(USBOEPBCTX_5);                       /* Output Endpoint_5: X-byte count */
3638 
SFR_8BIT(USBOEPBBAX_5);                       /* Output Endpoint_5: X-buffer base addr. */
3639 
SFR_8BIT(USBOEPCNF_5);                        /* Output Endpoint_5: Configuration */
3640 
SFR_8BIT(USBOEPSIZXY_4);                      /* Output Endpoint_4: X/Y-buffer size */
3641 
SFR_8BIT(USBOEPBCTY_4);                       /* Output Endpoint_4: Y-byte count */
3642 
SFR_8BIT(USBOEPBBAY_4);                       /* Output Endpoint_4: Y-buffer base addr. */
3643 
//sfrb    Spare    (0x23A4)   /* Not used */
3644 
//sfrb    Spare    (0x23A3)   /* Not used */
3645 
SFR_8BIT(USBOEPBCTX_4);                       /* Output Endpoint_4: X-byte count */
3646 
SFR_8BIT(USBOEPBBAX_4);                       /* Output Endpoint_4: X-buffer base addr. */
3647 
SFR_8BIT(USBOEPCNF_4);                        /* Output Endpoint_4: Configuration */
3648 
SFR_8BIT(USBOEPSIZXY_3);                      /* Output Endpoint_3: X/Y-buffer size */
3649 
SFR_8BIT(USBOEPBCTY_3);                       /* Output Endpoint_3: Y-byte count */
3650 
SFR_8BIT(USBOEPBBAY_3);                       /* Output Endpoint_3: Y-buffer base addr. */
3651 
//sfrb    Spare    (0x239C)   /* Not used */
3652 
//sfrb    Spare    (0x239B)   /* Not used */
3653 
SFR_8BIT(USBOEPBCTX_3);                       /* Output Endpoint_3: X-byte count */
3654 
SFR_8BIT(USBOEPBBAX_3);                       /* Output Endpoint_3: X-buffer base addr. */
3655 
SFR_8BIT(USBOEPCNF_3);                        /* Output Endpoint_3: Configuration */
3656 
SFR_8BIT(USBOEPSIZXY_2);                      /* Output Endpoint_2: X/Y-buffer size */
3657 
SFR_8BIT(USBOEPBCTY_2);                       /* Output Endpoint_2: Y-byte count */
3658 
SFR_8BIT(USBOEPBBAY_2);                       /* Output Endpoint_2: Y-buffer base addr. */
3659 
//sfrb    Spare    (0x2394)   /* Not used */
3660 
//sfrb    Spare    (0x2393)   /* Not used */
3661 
SFR_8BIT(USBOEPBCTX_2);                       /* Output Endpoint_2: X-byte count */
3662 
SFR_8BIT(USBOEPBBAX_2);                       /* Output Endpoint_2: X-buffer base addr. */
3663 
SFR_8BIT(USBOEPCNF_2);                        /* Output Endpoint_2: Configuration */
3664 
SFR_8BIT(USBOEPSIZXY_1);                      /* Output Endpoint_1: X/Y-buffer size */
3665 
SFR_8BIT(USBOEPBCTY_1);                       /* Output Endpoint_1: Y-byte count */
3666 
SFR_8BIT(USBOEPBBAY_1);                       /* Output Endpoint_1: Y-buffer base addr. */
3667 
//sfrb    Spare    (0x238C)   /* Not used */
3668 
//sfrb    Spare    (0x238B)   /* Not used */
3669 
SFR_8BIT(USBOEPBCTX_1);                       /* Output Endpoint_1: X-byte count */
3670 
SFR_8BIT(USBOEPBBAX_1);                       /* Output Endpoint_1: X-buffer base addr. */
3671 
SFR_8BIT(USBOEPCNF_1);                        /* Output Endpoint_1: Configuration */
3672 
SFR_8BIT(USBSUBLK);                           /* Setup Packet Block */
3673 
SFR_8BIT(USBIEP0BUF);                         /* Input endpoint_0 buffer */
3674 
SFR_8BIT(USBOEP0BUF);                         /* Output endpoint_0 buffer */
3675 
SFR_8BIT(USBTOPBUFF);                         /* Top of buffer space */
3676 
//         (1904 Bytes)               /* Buffer space */
3677 
SFR_8BIT(USBSTABUFF);                         /* Start of buffer space */
3678 
 
3679 
/* USBIEPCNF_n Control Bits */
3680 
/* USBOEPCNF_n Control Bits */
3681 
//#define RESERVED       (0x0001)  /* USB -  */
3682 
//#define RESERVED       (0x0001)  /* USB -  */
3683 
#define DBUF                   (0x0010)       /* USB - Double Buffer Enable */
3684 
//#define RESERVED       (0x0040)  /* USB -  */
3685 
 
3686 
/* USBIEPBCNT_n Control Bits */
3687 
/* USBOEPBCNT_n Control Bits */
3688 
#define CNT4                   (0x0010)       /* USB - Byte Count Bit 3 */
3689 
#define CNT5                   (0x0020)       /* USB - Byte Count Bit 3 */
3690 
#define CNT6                   (0x0040)       /* USB - Byte Count Bit 3 */
3691 
/************************************************************
3692 
* UNIFIED CLOCK SYSTEM
3693 
************************************************************/
3694 
#define __MSP430_HAS_UCS__                    /* Definition to show that Module is available */
3695 
#define __MSP430_BASEADDRESS_UCS__ 0x0160
3696 
 
3697 
SFR_16BIT(UCSCTL0);                           /* UCS Control Register 0 */
3698 
SFR_8BIT(UCSCTL0_L);                          /* UCS Control Register 0 */
3699 
SFR_8BIT(UCSCTL0_H);                          /* UCS Control Register 0 */
3700 
SFR_16BIT(UCSCTL1);                           /* UCS Control Register 1 */
3701 
SFR_8BIT(UCSCTL1_L);                          /* UCS Control Register 1 */
3702 
SFR_8BIT(UCSCTL1_H);                          /* UCS Control Register 1 */
3703 
SFR_16BIT(UCSCTL2);                           /* UCS Control Register 2 */
3704 
SFR_8BIT(UCSCTL2_L);                          /* UCS Control Register 2 */
3705 
SFR_8BIT(UCSCTL2_H);                          /* UCS Control Register 2 */
3706 
SFR_16BIT(UCSCTL3);                           /* UCS Control Register 3 */
3707 
SFR_8BIT(UCSCTL3_L);                          /* UCS Control Register 3 */
3708 
SFR_8BIT(UCSCTL3_H);                          /* UCS Control Register 3 */
3709 
SFR_16BIT(UCSCTL4);                           /* UCS Control Register 4 */
3710 
SFR_8BIT(UCSCTL4_L);                          /* UCS Control Register 4 */
3711 
SFR_8BIT(UCSCTL4_H);                          /* UCS Control Register 4 */
3712 
SFR_16BIT(UCSCTL5);                           /* UCS Control Register 5 */
3713 
SFR_8BIT(UCSCTL5_L);                          /* UCS Control Register 5 */
3714 
SFR_8BIT(UCSCTL5_H);                          /* UCS Control Register 5 */
3715 
SFR_16BIT(UCSCTL6);                           /* UCS Control Register 6 */
3716 
SFR_8BIT(UCSCTL6_L);                          /* UCS Control Register 6 */
3717 
SFR_8BIT(UCSCTL6_H);                          /* UCS Control Register 6 */
3718 
SFR_16BIT(UCSCTL7);                           /* UCS Control Register 7 */
3719 
SFR_8BIT(UCSCTL7_L);                          /* UCS Control Register 7 */
3720 
SFR_8BIT(UCSCTL7_H);                          /* UCS Control Register 7 */
3721 
SFR_16BIT(UCSCTL8);                           /* UCS Control Register 8 */
3722 
SFR_8BIT(UCSCTL8_L);                          /* UCS Control Register 8 */
3723 
SFR_8BIT(UCSCTL8_H);                          /* UCS Control Register 8 */
3724 
 
3725 
/* UCSCTL0 Control Bits */
3726 
//#define RESERVED            (0x0001)    /* RESERVED */
3727 
//#define RESERVED            (0x0002)    /* RESERVED */
3728 
//#define RESERVED            (0x0004)    /* RESERVED */
3729 
#define MOD0                   (0x0008)       /* Modulation Bit Counter Bit : 0 */
3730 
#define MOD1                   (0x0010)       /* Modulation Bit Counter Bit : 1 */
3731 
#define MOD2                   (0x0020)       /* Modulation Bit Counter Bit : 2 */
3732 
#define MOD3                   (0x0040)       /* Modulation Bit Counter Bit : 3 */
3733 
#define MOD4                   (0x0080)       /* Modulation Bit Counter Bit : 4 */
3734 
#define DCO0                   (0x0100)       /* DCO TAP Bit : 0 */
3735 
#define DCO1                   (0x0200)       /* DCO TAP Bit : 1 */
3736 
#define DCO2                   (0x0400)       /* DCO TAP Bit : 2 */
3737 
#define DCO3                   (0x0800)       /* DCO TAP Bit : 3 */
3738 
#define DCO4                   (0x1000)       /* DCO TAP Bit : 4 */
3739 
//#define RESERVED            (0x2000)    /* RESERVED */
3740 
//#define RESERVED            (0x4000)    /* RESERVED */
3741 
//#define RESERVED            (0x8000)    /* RESERVED */
3742 
 
3743 
/* UCSCTL0 Control Bits */
3744 
//#define RESERVED            (0x0001)    /* RESERVED */
3745 
//#define RESERVED            (0x0002)    /* RESERVED */
3746 
//#define RESERVED            (0x0004)    /* RESERVED */
3747 
#define MOD0_L                 (0x0008)       /* Modulation Bit Counter Bit : 0 */
3748 
#define MOD1_L                 (0x0010)       /* Modulation Bit Counter Bit : 1 */
3749 
#define MOD2_L                 (0x0020)       /* Modulation Bit Counter Bit : 2 */
3750 
#define MOD3_L                 (0x0040)       /* Modulation Bit Counter Bit : 3 */
3751 
#define MOD4_L                 (0x0080)       /* Modulation Bit Counter Bit : 4 */
3752 
//#define RESERVED            (0x2000)    /* RESERVED */
3753 
//#define RESERVED            (0x4000)    /* RESERVED */
3754 
//#define RESERVED            (0x8000)    /* RESERVED */
3755 
 
3756 
/* UCSCTL0 Control Bits */
3757 
//#define RESERVED            (0x0001)    /* RESERVED */
3758 
//#define RESERVED            (0x0002)    /* RESERVED */
3759 
//#define RESERVED            (0x0004)    /* RESERVED */
3760 
#define DCO0_H                 (0x0001)       /* DCO TAP Bit : 0 */
3761 
#define DCO1_H                 (0x0002)       /* DCO TAP Bit : 1 */
3762 
#define DCO2_H                 (0x0004)       /* DCO TAP Bit : 2 */
3763 
#define DCO3_H                 (0x0008)       /* DCO TAP Bit : 3 */
3764 
#define DCO4_H                 (0x0010)       /* DCO TAP Bit : 4 */
3765 
//#define RESERVED            (0x2000)    /* RESERVED */
3766 
//#define RESERVED            (0x4000)    /* RESERVED */
3767 
//#define RESERVED            (0x8000)    /* RESERVED */
3768 
 
3769 
/* UCSCTL1 Control Bits */
3770 
#define DISMOD                 (0x0001)       /* Disable Modulation */
3771 
//#define RESERVED            (0x0002)    /* RESERVED */
3772 
//#define RESERVED            (0x0004)    /* RESERVED */
3773 
//#define RESERVED            (0x0008)    /* RESERVED */
3774 
#define DCORSEL0               (0x0010)       /* DCO Freq. Range Select Bit : 0 */
3775 
#define DCORSEL1               (0x0020)       /* DCO Freq. Range Select Bit : 1 */
3776 
#define DCORSEL2               (0x0040)       /* DCO Freq. Range Select Bit : 2 */
3777 
//#define RESERVED            (0x0080)    /* RESERVED */
3778 
//#define RESERVED            (0x0100)    /* RESERVED */
3779 
//#define RESERVED            (0x0200)    /* RESERVED */
3780 
//#define RESERVED            (0x0400)    /* RESERVED */
3781 
//#define RESERVED            (0x0800)    /* RESERVED */
3782 
//#define RESERVED            (0x1000)    /* RESERVED */
3783 
//#define RESERVED            (0x2000)    /* RESERVED */
3784 
//#define RESERVED            (0x4000)    /* RESERVED */
3785 
//#define RESERVED            (0x8000)    /* RESERVED */
3786 
 
3787 
/* UCSCTL1 Control Bits */
3788 
#define DISMOD_L               (0x0001)       /* Disable Modulation */
3789 
//#define RESERVED            (0x0002)    /* RESERVED */
3790 
//#define RESERVED            (0x0004)    /* RESERVED */
3791 
//#define RESERVED            (0x0008)    /* RESERVED */
3792 
#define DCORSEL0_L             (0x0010)       /* DCO Freq. Range Select Bit : 0 */
3793 
#define DCORSEL1_L             (0x0020)       /* DCO Freq. Range Select Bit : 1 */
3794 
#define DCORSEL2_L             (0x0040)       /* DCO Freq. Range Select Bit : 2 */
3795 
//#define RESERVED            (0x0080)    /* RESERVED */
3796 
//#define RESERVED            (0x0100)    /* RESERVED */
3797 
//#define RESERVED            (0x0200)    /* RESERVED */
3798 
//#define RESERVED            (0x0400)    /* RESERVED */
3799 
//#define RESERVED            (0x0800)    /* RESERVED */
3800 
//#define RESERVED            (0x1000)    /* RESERVED */
3801 
//#define RESERVED            (0x2000)    /* RESERVED */
3802 
//#define RESERVED            (0x4000)    /* RESERVED */
3803 
//#define RESERVED            (0x8000)    /* RESERVED */
3804 
 
3805 
/* UCSCTL1 Control Bits */
3806 
//#define RESERVED            (0x0002)    /* RESERVED */
3807 
//#define RESERVED            (0x0004)    /* RESERVED */
3808 
//#define RESERVED            (0x0008)    /* RESERVED */
3809 
//#define RESERVED            (0x0080)    /* RESERVED */
3810 
//#define RESERVED            (0x0100)    /* RESERVED */
3811 
//#define RESERVED            (0x0200)    /* RESERVED */
3812 
//#define RESERVED            (0x0400)    /* RESERVED */
3813 
//#define RESERVED            (0x0800)    /* RESERVED */
3814 
//#define RESERVED            (0x1000)    /* RESERVED */
3815 
//#define RESERVED            (0x2000)    /* RESERVED */
3816 
//#define RESERVED            (0x4000)    /* RESERVED */
3817 
//#define RESERVED            (0x8000)    /* RESERVED */
3818 
 
3819 
#define DCORSEL_0              (0x0000)       /* DCO RSEL 0 */
3820 
#define DCORSEL_1              (0x0010)       /* DCO RSEL 1 */
3821 
#define DCORSEL_2              (0x0020)       /* DCO RSEL 2 */
3822 
#define DCORSEL_3              (0x0030)       /* DCO RSEL 3 */
3823 
#define DCORSEL_4              (0x0040)       /* DCO RSEL 4 */
3824 
#define DCORSEL_5              (0x0050)       /* DCO RSEL 5 */
3825 
#define DCORSEL_6              (0x0060)       /* DCO RSEL 6 */
3826 
#define DCORSEL_7              (0x0070)       /* DCO RSEL 7 */
3827 
 
3828 
/* UCSCTL2 Control Bits */
3829 
#define FLLN0                  (0x0001)       /* FLL Multipier Bit : 0 */
3830 
#define FLLN1                  (0x0002)       /* FLL Multipier Bit : 1 */
3831 
#define FLLN2                  (0x0004)       /* FLL Multipier Bit : 2 */
3832 
#define FLLN3                  (0x0008)       /* FLL Multipier Bit : 3 */
3833 
#define FLLN4                  (0x0010)       /* FLL Multipier Bit : 4 */
3834 
#define FLLN5                  (0x0020)       /* FLL Multipier Bit : 5 */
3835 
#define FLLN6                  (0x0040)       /* FLL Multipier Bit : 6 */
3836 
#define FLLN7                  (0x0080)       /* FLL Multipier Bit : 7 */
3837 
#define FLLN8                  (0x0100)       /* FLL Multipier Bit : 8 */
3838 
#define FLLN9                  (0x0200)       /* FLL Multipier Bit : 9 */
3839 
//#define RESERVED            (0x0400)    /* RESERVED */
3840 
//#define RESERVED            (0x0800)    /* RESERVED */
3841 
#define FLLD0                  (0x1000)       /* Loop Divider Bit : 0 */
3842 
#define FLLD1                  (0x2000)       /* Loop Divider Bit : 1 */
3843 
#define FLLD2                  (0x4000)       /* Loop Divider Bit : 1 */
3844 
//#define RESERVED            (0x8000)    /* RESERVED */
3845 
 
3846 
/* UCSCTL2 Control Bits */
3847 
#define FLLN0_L                (0x0001)       /* FLL Multipier Bit : 0 */
3848 
#define FLLN1_L                (0x0002)       /* FLL Multipier Bit : 1 */
3849 
#define FLLN2_L                (0x0004)       /* FLL Multipier Bit : 2 */
3850 
#define FLLN3_L                (0x0008)       /* FLL Multipier Bit : 3 */
3851 
#define FLLN4_L                (0x0010)       /* FLL Multipier Bit : 4 */
3852 
#define FLLN5_L                (0x0020)       /* FLL Multipier Bit : 5 */
3853 
#define FLLN6_L                (0x0040)       /* FLL Multipier Bit : 6 */
3854 
#define FLLN7_L                (0x0080)       /* FLL Multipier Bit : 7 */
3855 
//#define RESERVED            (0x0400)    /* RESERVED */
3856 
//#define RESERVED            (0x0800)    /* RESERVED */
3857 
//#define RESERVED            (0x8000)    /* RESERVED */
3858 
 
3859 
/* UCSCTL2 Control Bits */
3860 
#define FLLN8_H                (0x0001)       /* FLL Multipier Bit : 8 */
3861 
#define FLLN9_H                (0x0002)       /* FLL Multipier Bit : 9 */
3862 
//#define RESERVED            (0x0400)    /* RESERVED */
3863 
//#define RESERVED            (0x0800)    /* RESERVED */
3864 
#define FLLD0_H                (0x0010)       /* Loop Divider Bit : 0 */
3865 
#define FLLD1_H                (0x0020)       /* Loop Divider Bit : 1 */
3866 
#define FLLD2_H                (0x0040)       /* Loop Divider Bit : 1 */
3867 
//#define RESERVED            (0x8000)    /* RESERVED */
3868 
 
3869 
#define FLLD_0                 (0x0000)       /* Multiply Selected Loop Freq. 1 */
3870 
#define FLLD_1                 (0x1000)       /* Multiply Selected Loop Freq. 2 */
3871 
#define FLLD_2                 (0x2000)       /* Multiply Selected Loop Freq. 4 */
3872 
#define FLLD_3                 (0x3000)       /* Multiply Selected Loop Freq. 8 */
3873 
#define FLLD_4                 (0x4000)       /* Multiply Selected Loop Freq. 16 */
3874 
#define FLLD_5                 (0x5000)       /* Multiply Selected Loop Freq. 32 */
3875 
#define FLLD_6                 (0x6000)       /* Multiply Selected Loop Freq. 32 */
3876 
#define FLLD_7                 (0x7000)       /* Multiply Selected Loop Freq. 32 */
3877 
#define FLLD__1                (0x0000)       /* Multiply Selected Loop Freq. By 1 */
3878 
#define FLLD__2                (0x1000)       /* Multiply Selected Loop Freq. By 2 */
3879 
#define FLLD__4                (0x2000)       /* Multiply Selected Loop Freq. By 4 */
3880 
#define FLLD__8                (0x3000)       /* Multiply Selected Loop Freq. By 8 */
3881 
#define FLLD__16               (0x4000)       /* Multiply Selected Loop Freq. By 16 */
3882 
#define FLLD__32               (0x5000)       /* Multiply Selected Loop Freq. By 32 */
3883 
 
3884 
/* UCSCTL3 Control Bits */
3885 
#define FLLREFDIV0             (0x0001)       /* Reference Divider Bit : 0 */
3886 
#define FLLREFDIV1             (0x0002)       /* Reference Divider Bit : 1 */
3887 
#define FLLREFDIV2             (0x0004)       /* Reference Divider Bit : 2 */
3888 
//#define RESERVED            (0x0008)    /* RESERVED */
3889 
#define SELREF0                (0x0010)       /* FLL Reference Clock Select Bit : 0 */
3890 
#define SELREF1                (0x0020)       /* FLL Reference Clock Select Bit : 1 */
3891 
#define SELREF2                (0x0040)       /* FLL Reference Clock Select Bit : 2 */
3892 
//#define RESERVED            (0x0080)    /* RESERVED */
3893 
//#define RESERVED            (0x0100)    /* RESERVED */
3894 
//#define RESERVED            (0x0200)    /* RESERVED */
3895 
//#define RESERVED            (0x0400)    /* RESERVED */
3896 
//#define RESERVED            (0x0800)    /* RESERVED */
3897 
//#define RESERVED            (0x1000)    /* RESERVED */
3898 
//#define RESERVED            (0x2000)    /* RESERVED */
3899 
//#define RESERVED            (0x4000)    /* RESERVED */
3900 
//#define RESERVED            (0x8000)    /* RESERVED */
3901 
 
3902 
/* UCSCTL3 Control Bits */
3903 
#define FLLREFDIV0_L           (0x0001)       /* Reference Divider Bit : 0 */
3904 
#define FLLREFDIV1_L           (0x0002)       /* Reference Divider Bit : 1 */
3905 
#define FLLREFDIV2_L           (0x0004)       /* Reference Divider Bit : 2 */
3906 
//#define RESERVED            (0x0008)    /* RESERVED */
3907 
#define SELREF0_L              (0x0010)       /* FLL Reference Clock Select Bit : 0 */
3908 
#define SELREF1_L              (0x0020)       /* FLL Reference Clock Select Bit : 1 */
3909 
#define SELREF2_L              (0x0040)       /* FLL Reference Clock Select Bit : 2 */
3910 
//#define RESERVED            (0x0080)    /* RESERVED */
3911 
//#define RESERVED            (0x0100)    /* RESERVED */
3912 
//#define RESERVED            (0x0200)    /* RESERVED */
3913 
//#define RESERVED            (0x0400)    /* RESERVED */
3914 
//#define RESERVED            (0x0800)    /* RESERVED */
3915 
//#define RESERVED            (0x1000)    /* RESERVED */
3916 
//#define RESERVED            (0x2000)    /* RESERVED */
3917 
//#define RESERVED            (0x4000)    /* RESERVED */
3918 
//#define RESERVED            (0x8000)    /* RESERVED */
3919 
 
3920 
/* UCSCTL3 Control Bits */
3921 
//#define RESERVED            (0x0008)    /* RESERVED */
3922 
//#define RESERVED            (0x0080)    /* RESERVED */
3923 
//#define RESERVED            (0x0100)    /* RESERVED */
3924 
//#define RESERVED            (0x0200)    /* RESERVED */
3925 
//#define RESERVED            (0x0400)    /* RESERVED */
3926 
//#define RESERVED            (0x0800)    /* RESERVED */
3927 
//#define RESERVED            (0x1000)    /* RESERVED */
3928 
//#define RESERVED            (0x2000)    /* RESERVED */
3929 
//#define RESERVED            (0x4000)    /* RESERVED */
3930 
//#define RESERVED            (0x8000)    /* RESERVED */
3931 
 
3932 
#define FLLREFDIV_0            (0x0000)       /* Reference Divider: f(LFCLK)/1 */
3933 
#define FLLREFDIV_1            (0x0001)       /* Reference Divider: f(LFCLK)/2 */
3934 
#define FLLREFDIV_2            (0x0002)       /* Reference Divider: f(LFCLK)/4 */
3935 
#define FLLREFDIV_3            (0x0003)       /* Reference Divider: f(LFCLK)/8 */
3936 
#define FLLREFDIV_4            (0x0004)       /* Reference Divider: f(LFCLK)/12 */
3937 
#define FLLREFDIV_5            (0x0005)       /* Reference Divider: f(LFCLK)/16 */
3938 
#define FLLREFDIV_6            (0x0006)       /* Reference Divider: f(LFCLK)/16 */
3939 
#define FLLREFDIV_7            (0x0007)       /* Reference Divider: f(LFCLK)/16 */
3940 
#define FLLREFDIV__1           (0x0000)       /* Reference Divider: f(LFCLK)/1 */
3941 
#define FLLREFDIV__2           (0x0001)       /* Reference Divider: f(LFCLK)/2 */
3942 
#define FLLREFDIV__4           (0x0002)       /* Reference Divider: f(LFCLK)/4 */
3943 
#define FLLREFDIV__8           (0x0003)       /* Reference Divider: f(LFCLK)/8 */
3944 
#define FLLREFDIV__12          (0x0004)       /* Reference Divider: f(LFCLK)/12 */
3945 
#define FLLREFDIV__16          (0x0005)       /* Reference Divider: f(LFCLK)/16 */
3946 
#define SELREF_0               (0x0000)       /* FLL Reference Clock Select 0 */
3947 
#define SELREF_1               (0x0010)       /* FLL Reference Clock Select 1 */
3948 
#define SELREF_2               (0x0020)       /* FLL Reference Clock Select 2 */
3949 
#define SELREF_3               (0x0030)       /* FLL Reference Clock Select 3 */
3950 
#define SELREF_4               (0x0040)       /* FLL Reference Clock Select 4 */
3951 
#define SELREF_5               (0x0050)       /* FLL Reference Clock Select 5 */
3952 
#define SELREF_6               (0x0060)       /* FLL Reference Clock Select 6 */
3953 
#define SELREF_7               (0x0070)       /* FLL Reference Clock Select 7 */
3954 
#define SELREF__XT1CLK         (0x0000)       /* Multiply Selected Loop Freq. By XT1CLK */
3955 
#define SELREF__REFOCLK        (0x0020)       /* Multiply Selected Loop Freq. By REFOCLK */
3956 
#define SELREF__XT2CLK         (0x0050)       /* Multiply Selected Loop Freq. By XT2CLK */
3957 
 
3958 
/* UCSCTL4 Control Bits */
3959 
#define SELM0                  (0x0001)       /* MCLK Source Select Bit: 0 */
3960 
#define SELM1                  (0x0002)       /* MCLK Source Select Bit: 1 */
3961 
#define SELM2                  (0x0004)       /* MCLK Source Select Bit: 2 */
3962 
//#define RESERVED            (0x0008)    /* RESERVED */
3963 
#define SELS0                  (0x0010)       /* SMCLK Source Select Bit: 0 */
3964 
#define SELS1                  (0x0020)       /* SMCLK Source Select Bit: 1 */
3965 
#define SELS2                  (0x0040)       /* SMCLK Source Select Bit: 2 */
3966 
//#define RESERVED            (0x0080)    /* RESERVED */
3967 
#define SELA0                  (0x0100)       /* ACLK Source Select Bit: 0 */
3968 
#define SELA1                  (0x0200)       /* ACLK Source Select Bit: 1 */
3969 
#define SELA2                  (0x0400)       /* ACLK Source Select Bit: 2 */
3970 
//#define RESERVED            (0x0800)    /* RESERVED */
3971 
//#define RESERVED            (0x1000)    /* RESERVED */
3972 
//#define RESERVED            (0x2000)    /* RESERVED */
3973 
//#define RESERVED            (0x4000)    /* RESERVED */
3974 
//#define RESERVED            (0x8000)    /* RESERVED */
3975 
 
3976 
/* UCSCTL4 Control Bits */
3977 
#define SELM0_L                (0x0001)       /* MCLK Source Select Bit: 0 */
3978 
#define SELM1_L                (0x0002)       /* MCLK Source Select Bit: 1 */
3979 
#define SELM2_L                (0x0004)       /* MCLK Source Select Bit: 2 */
3980 
//#define RESERVED            (0x0008)    /* RESERVED */
3981 
#define SELS0_L                (0x0010)       /* SMCLK Source Select Bit: 0 */
3982 
#define SELS1_L                (0x0020)       /* SMCLK Source Select Bit: 1 */
3983 
#define SELS2_L                (0x0040)       /* SMCLK Source Select Bit: 2 */
3984 
//#define RESERVED            (0x0080)    /* RESERVED */
3985 
//#define RESERVED            (0x0800)    /* RESERVED */
3986 
//#define RESERVED            (0x1000)    /* RESERVED */
3987 
//#define RESERVED            (0x2000)    /* RESERVED */
3988 
//#define RESERVED            (0x4000)    /* RESERVED */
3989 
//#define RESERVED            (0x8000)    /* RESERVED */
3990 
 
3991 
/* UCSCTL4 Control Bits */
3992 
//#define RESERVED            (0x0008)    /* RESERVED */
3993 
//#define RESERVED            (0x0080)    /* RESERVED */
3994 
#define SELA0_H                (0x0001)       /* ACLK Source Select Bit: 0 */
3995 
#define SELA1_H                (0x0002)       /* ACLK Source Select Bit: 1 */
3996 
#define SELA2_H                (0x0004)       /* ACLK Source Select Bit: 2 */
3997 
//#define RESERVED            (0x0800)    /* RESERVED */
3998 
//#define RESERVED            (0x1000)    /* RESERVED */
3999 
//#define RESERVED            (0x2000)    /* RESERVED */
4000 
//#define RESERVED            (0x4000)    /* RESERVED */
4001 
//#define RESERVED            (0x8000)    /* RESERVED */
4002 
 
4003 
#define SELM_0                 (0x0000)       /* MCLK Source Select 0 */
4004 
#define SELM_1                 (0x0001)       /* MCLK Source Select 1 */
4005 
#define SELM_2                 (0x0002)       /* MCLK Source Select 2 */
4006 
#define SELM_3                 (0x0003)       /* MCLK Source Select 3 */
4007 
#define SELM_4                 (0x0004)       /* MCLK Source Select 4 */
4008 
#define SELM_5                 (0x0005)       /* MCLK Source Select 5 */
4009 
#define SELM_6                 (0x0006)       /* MCLK Source Select 6 */
4010 
#define SELM_7                 (0x0007)       /* MCLK Source Select 7 */
4011 
#define SELM__XT1CLK           (0x0000)       /* MCLK Source Select XT1CLK */
4012 
#define SELM__VLOCLK           (0x0001)       /* MCLK Source Select VLOCLK */
4013 
#define SELM__REFOCLK          (0x0002)       /* MCLK Source Select REFOCLK */
4014 
#define SELM__DCOCLK           (0x0003)       /* MCLK Source Select DCOCLK */
4015 
#define SELM__DCOCLKDIV        (0x0004)       /* MCLK Source Select DCOCLKDIV */
4016 
#define SELM__XT2CLK           (0x0005)       /* MCLK Source Select XT2CLK */
4017 
 
4018 
#define SELS_0                 (0x0000)       /* SMCLK Source Select 0 */
4019 
#define SELS_1                 (0x0010)       /* SMCLK Source Select 1 */
4020 
#define SELS_2                 (0x0020)       /* SMCLK Source Select 2 */
4021 
#define SELS_3                 (0x0030)       /* SMCLK Source Select 3 */
4022 
#define SELS_4                 (0x0040)       /* SMCLK Source Select 4 */
4023 
#define SELS_5                 (0x0050)       /* SMCLK Source Select 5 */
4024 
#define SELS_6                 (0x0060)       /* SMCLK Source Select 6 */
4025 
#define SELS_7                 (0x0070)       /* SMCLK Source Select 7 */
4026 
#define SELS__XT1CLK           (0x0000)       /* SMCLK Source Select XT1CLK */
4027 
#define SELS__VLOCLK           (0x0010)       /* SMCLK Source Select VLOCLK */
4028 
#define SELS__REFOCLK          (0x0020)       /* SMCLK Source Select REFOCLK */
4029 
#define SELS__DCOCLK           (0x0030)       /* SMCLK Source Select DCOCLK */
4030 
#define SELS__DCOCLKDIV        (0x0040)       /* SMCLK Source Select DCOCLKDIV */
4031 
#define SELS__XT2CLK           (0x0050)       /* SMCLK Source Select XT2CLK */
4032 
 
4033 
#define SELA_0                 (0x0000)       /* ACLK Source Select 0 */
4034 
#define SELA_1                 (0x0100)       /* ACLK Source Select 1 */
4035 
#define SELA_2                 (0x0200)       /* ACLK Source Select 2 */
4036 
#define SELA_3                 (0x0300)       /* ACLK Source Select 3 */
4037 
#define SELA_4                 (0x0400)       /* ACLK Source Select 4 */
4038 
#define SELA_5                 (0x0500)       /* ACLK Source Select 5 */
4039 
#define SELA_6                 (0x0600)       /* ACLK Source Select 6 */
4040 
#define SELA_7                 (0x0700)       /* ACLK Source Select 7 */
4041 
#define SELA__XT1CLK           (0x0000)       /* ACLK Source Select XT1CLK */
4042 
#define SELA__VLOCLK           (0x0100)       /* ACLK Source Select VLOCLK */
4043 
#define SELA__REFOCLK          (0x0200)       /* ACLK Source Select REFOCLK */
4044 
#define SELA__DCOCLK           (0x0300)       /* ACLK Source Select DCOCLK */
4045 
#define SELA__DCOCLKDIV        (0x0400)       /* ACLK Source Select DCOCLKDIV */
4046 
#define SELA__XT2CLK           (0x0500)       /* ACLK Source Select XT2CLK */
4047 
 
4048 
/* UCSCTL5 Control Bits */
4049 
#define DIVM0                  (0x0001)       /* MCLK Divider Bit: 0 */
4050 
#define DIVM1                  (0x0002)       /* MCLK Divider Bit: 1 */
4051 
#define DIVM2                  (0x0004)       /* MCLK Divider Bit: 2 */
4052 
//#define RESERVED            (0x0008)    /* RESERVED */
4053 
#define DIVS0                  (0x0010)       /* SMCLK Divider Bit: 0 */
4054 
#define DIVS1                  (0x0020)       /* SMCLK Divider Bit: 1 */
4055 
#define DIVS2                  (0x0040)       /* SMCLK Divider Bit: 2 */
4056 
//#define RESERVED            (0x0080)    /* RESERVED */
4057 
#define DIVA0                  (0x0100)       /* ACLK Divider Bit: 0 */
4058 
#define DIVA1                  (0x0200)       /* ACLK Divider Bit: 1 */
4059 
#define DIVA2                  (0x0400)       /* ACLK Divider Bit: 2 */
4060 
//#define RESERVED            (0x0800)    /* RESERVED */
4061 
#define DIVPA0                 (0x1000)       /* ACLK from Pin Divider Bit: 0 */
4062 
#define DIVPA1                 (0x2000)       /* ACLK from Pin Divider Bit: 1 */
4063 
#define DIVPA2                 (0x4000)       /* ACLK from Pin Divider Bit: 2 */
4064 
//#define RESERVED            (0x8000)    /* RESERVED */
4065 
 
4066 
/* UCSCTL5 Control Bits */
4067 
#define DIVM0_L                (0x0001)       /* MCLK Divider Bit: 0 */
4068 
#define DIVM1_L                (0x0002)       /* MCLK Divider Bit: 1 */
4069 
#define DIVM2_L                (0x0004)       /* MCLK Divider Bit: 2 */
4070 
//#define RESERVED            (0x0008)    /* RESERVED */
4071 
#define DIVS0_L                (0x0010)       /* SMCLK Divider Bit: 0 */
4072 
#define DIVS1_L                (0x0020)       /* SMCLK Divider Bit: 1 */
4073 
#define DIVS2_L                (0x0040)       /* SMCLK Divider Bit: 2 */
4074 
//#define RESERVED            (0x0080)    /* RESERVED */
4075 
//#define RESERVED            (0x0800)    /* RESERVED */
4076 
//#define RESERVED            (0x8000)    /* RESERVED */
4077 
 
4078 
/* UCSCTL5 Control Bits */
4079 
//#define RESERVED            (0x0008)    /* RESERVED */
4080 
//#define RESERVED            (0x0080)    /* RESERVED */
4081 
#define DIVA0_H                (0x0001)       /* ACLK Divider Bit: 0 */
4082 
#define DIVA1_H                (0x0002)       /* ACLK Divider Bit: 1 */
4083 
#define DIVA2_H                (0x0004)       /* ACLK Divider Bit: 2 */
4084 
//#define RESERVED            (0x0800)    /* RESERVED */
4085 
#define DIVPA0_H               (0x0010)       /* ACLK from Pin Divider Bit: 0 */
4086 
#define DIVPA1_H               (0x0020)       /* ACLK from Pin Divider Bit: 1 */
4087 
#define DIVPA2_H               (0x0040)       /* ACLK from Pin Divider Bit: 2 */
4088 
//#define RESERVED            (0x8000)    /* RESERVED */
4089 
 
4090 
#define DIVM_0                 (0x0000)       /* MCLK Source Divider 0 */
4091 
#define DIVM_1                 (0x0001)       /* MCLK Source Divider 1 */
4092 
#define DIVM_2                 (0x0002)       /* MCLK Source Divider 2 */
4093 
#define DIVM_3                 (0x0003)       /* MCLK Source Divider 3 */
4094 
#define DIVM_4                 (0x0004)       /* MCLK Source Divider 4 */
4095 
#define DIVM_5                 (0x0005)       /* MCLK Source Divider 5 */
4096 
#define DIVM_6                 (0x0006)       /* MCLK Source Divider 6 */
4097 
#define DIVM_7                 (0x0007)       /* MCLK Source Divider 7 */
4098 
#define DIVM__1                (0x0000)       /* MCLK Source Divider f(MCLK)/1 */
4099 
#define DIVM__2                (0x0001)       /* MCLK Source Divider f(MCLK)/2 */
4100 
#define DIVM__4                (0x0002)       /* MCLK Source Divider f(MCLK)/4 */
4101 
#define DIVM__8                (0x0003)       /* MCLK Source Divider f(MCLK)/8 */
4102 
#define DIVM__16               (0x0004)       /* MCLK Source Divider f(MCLK)/16 */
4103 
#define DIVM__32               (0x0005)       /* MCLK Source Divider f(MCLK)/32 */
4104 
 
4105 
#define DIVS_0                 (0x0000)       /* SMCLK Source Divider 0 */
4106 
#define DIVS_1                 (0x0010)       /* SMCLK Source Divider 1 */
4107 
#define DIVS_2                 (0x0020)       /* SMCLK Source Divider 2 */
4108 
#define DIVS_3                 (0x0030)       /* SMCLK Source Divider 3 */
4109 
#define DIVS_4                 (0x0040)       /* SMCLK Source Divider 4 */
4110 
#define DIVS_5                 (0x0050)       /* SMCLK Source Divider 5 */
4111 
#define DIVS_6                 (0x0060)       /* SMCLK Source Divider 6 */
4112 
#define DIVS_7                 (0x0070)       /* SMCLK Source Divider 7 */
4113 
#define DIVS__1                (0x0000)       /* SMCLK Source Divider f(SMCLK)/1 */
4114 
#define DIVS__2                (0x0010)       /* SMCLK Source Divider f(SMCLK)/2 */
4115 
#define DIVS__4                (0x0020)       /* SMCLK Source Divider f(SMCLK)/4 */
4116 
#define DIVS__8                (0x0030)       /* SMCLK Source Divider f(SMCLK)/8 */
4117 
#define DIVS__16               (0x0040)       /* SMCLK Source Divider f(SMCLK)/16 */
4118 
#define DIVS__32               (0x0050)       /* SMCLK Source Divider f(SMCLK)/32 */
4119 
 
4120 
#define DIVA_0                 (0x0000)       /* ACLK Source Divider 0 */
4121 
#define DIVA_1                 (0x0100)       /* ACLK Source Divider 1 */
4122 
#define DIVA_2                 (0x0200)       /* ACLK Source Divider 2 */
4123 
#define DIVA_3                 (0x0300)       /* ACLK Source Divider 3 */
4124 
#define DIVA_4                 (0x0400)       /* ACLK Source Divider 4 */
4125 
#define DIVA_5                 (0x0500)       /* ACLK Source Divider 5 */
4126 
#define DIVA_6                 (0x0600)       /* ACLK Source Divider 6 */
4127 
#define DIVA_7                 (0x0700)       /* ACLK Source Divider 7 */
4128 
#define DIVA__1                (0x0000)       /* ACLK Source Divider f(ACLK)/1 */
4129 
#define DIVA__2                (0x0100)       /* ACLK Source Divider f(ACLK)/2 */
4130 
#define DIVA__4                (0x0200)       /* ACLK Source Divider f(ACLK)/4 */
4131 
#define DIVA__8                (0x0300)       /* ACLK Source Divider f(ACLK)/8 */
4132 
#define DIVA__16               (0x0400)       /* ACLK Source Divider f(ACLK)/16 */
4133 
#define DIVA__32               (0x0500)       /* ACLK Source Divider f(ACLK)/32 */
4134 
 
4135 
#define DIVPA_0                (0x0000)       /* ACLK from Pin Source Divider 0 */
4136 
#define DIVPA_1                (0x1000)       /* ACLK from Pin Source Divider 1 */
4137 
#define DIVPA_2                (0x2000)       /* ACLK from Pin Source Divider 2 */
4138 
#define DIVPA_3                (0x3000)       /* ACLK from Pin Source Divider 3 */
4139 
#define DIVPA_4                (0x4000)       /* ACLK from Pin Source Divider 4 */
4140 
#define DIVPA_5                (0x5000)       /* ACLK from Pin Source Divider 5 */
4141 
#define DIVPA_6                (0x6000)       /* ACLK from Pin Source Divider 6 */
4142 
#define DIVPA_7                (0x7000)       /* ACLK from Pin Source Divider 7 */
4143 
#define DIVPA__1               (0x0000)       /* ACLK from Pin Source Divider f(ACLK)/1 */
4144 
#define DIVPA__2               (0x1000)       /* ACLK from Pin Source Divider f(ACLK)/2 */
4145 
#define DIVPA__4               (0x2000)       /* ACLK from Pin Source Divider f(ACLK)/4 */
4146 
#define DIVPA__8               (0x3000)       /* ACLK from Pin Source Divider f(ACLK)/8 */
4147 
#define DIVPA__16              (0x4000)       /* ACLK from Pin Source Divider f(ACLK)/16 */
4148 
#define DIVPA__32              (0x5000)       /* ACLK from Pin Source Divider f(ACLK)/32 */
4149 
 
4150 
/* UCSCTL6 Control Bits */
4151 
#define XT1OFF                 (0x0001)       /* High Frequency Oscillator 1 (XT1) disable */
4152 
#define SMCLKOFF               (0x0002)       /* SMCLK Off */
4153 
#define XCAP0                  (0x0004)       /* XIN/XOUT Cap Bit: 0 */
4154 
#define XCAP1                  (0x0008)       /* XIN/XOUT Cap Bit: 1 */
4155 
#define XT1BYPASS              (0x0010)       /* XT1 bypass mode : 0: internal 1:sourced from external pin */
4156 
#define XTS                    (0x0020)       /* 1: Selects high-freq. oscillator */
4157 
#define XT1DRIVE0              (0x0040)       /* XT1 Drive Level mode Bit 0 */
4158 
#define XT1DRIVE1              (0x0080)       /* XT1 Drive Level mode Bit 1 */
4159 
#define XT2OFF                 (0x0100)       /* High Frequency Oscillator 2 (XT2) disable */
4160 
//#define RESERVED            (0x0200)    /* RESERVED */
4161 
//#define RESERVED            (0x0400)    /* RESERVED */
4162 
//#define RESERVED            (0x0800)    /* RESERVED */
4163 
#define XT2BYPASS              (0x1000)       /* XT2 bypass mode : 0: internal 1:sourced from external pin */
4164 
//#define RESERVED            (0x2000)    /* RESERVED */
4165 
#define XT2DRIVE0              (0x4000)       /* XT2 Drive Level mode Bit 0 */
4166 
#define XT2DRIVE1              (0x8000)       /* XT2 Drive Level mode Bit 1 */
4167 
 
4168 
/* UCSCTL6 Control Bits */
4169 
#define XT1OFF_L               (0x0001)       /* High Frequency Oscillator 1 (XT1) disable */
4170 
#define SMCLKOFF_L             (0x0002)       /* SMCLK Off */
4171 
#define XCAP0_L                (0x0004)       /* XIN/XOUT Cap Bit: 0 */
4172 
#define XCAP1_L                (0x0008)       /* XIN/XOUT Cap Bit: 1 */
4173 
#define XT1BYPASS_L            (0x0010)       /* XT1 bypass mode : 0: internal 1:sourced from external pin */
4174 
#define XTS_L                  (0x0020)       /* 1: Selects high-freq. oscillator */
4175 
#define XT1DRIVE0_L            (0x0040)       /* XT1 Drive Level mode Bit 0 */
4176 
#define XT1DRIVE1_L            (0x0080)       /* XT1 Drive Level mode Bit 1 */
4177 
//#define RESERVED            (0x0200)    /* RESERVED */
4178 
//#define RESERVED            (0x0400)    /* RESERVED */
4179 
//#define RESERVED            (0x0800)    /* RESERVED */
4180 
//#define RESERVED            (0x2000)    /* RESERVED */
4181 
 
4182 
/* UCSCTL6 Control Bits */
4183 
#define XT2OFF_H               (0x0001)       /* High Frequency Oscillator 2 (XT2) disable */
4184 
//#define RESERVED            (0x0200)    /* RESERVED */
4185 
//#define RESERVED            (0x0400)    /* RESERVED */
4186 
//#define RESERVED            (0x0800)    /* RESERVED */
4187 
#define XT2BYPASS_H            (0x0010)       /* XT2 bypass mode : 0: internal 1:sourced from external pin */
4188 
//#define RESERVED            (0x2000)    /* RESERVED */
4189 
#define XT2DRIVE0_H            (0x0040)       /* XT2 Drive Level mode Bit 0 */
4190 
#define XT2DRIVE1_H            (0x0080)       /* XT2 Drive Level mode Bit 1 */
4191 
 
4192 
#define XCAP_0                 (0x0000)       /* XIN/XOUT Cap 0 */
4193 
#define XCAP_1                 (0x0004)       /* XIN/XOUT Cap 1 */
4194 
#define XCAP_2                 (0x0008)       /* XIN/XOUT Cap 2 */
4195 
#define XCAP_3                 (0x000C)       /* XIN/XOUT Cap 3 */
4196 
#define XT1DRIVE_0             (0x0000)       /* XT1 Drive Level mode: 0 */
4197 
#define XT1DRIVE_1             (0x0040)       /* XT1 Drive Level mode: 1 */
4198 
#define XT1DRIVE_2             (0x0080)       /* XT1 Drive Level mode: 2 */
4199 
#define XT1DRIVE_3             (0x00C0)       /* XT1 Drive Level mode: 3 */
4200 
#define XT2DRIVE_0             (0x0000)       /* XT2 Drive Level mode: 0 */
4201 
#define XT2DRIVE_1             (0x4000)       /* XT2 Drive Level mode: 1 */
4202 
#define XT2DRIVE_2             (0x8000)       /* XT2 Drive Level mode: 2 */
4203 
#define XT2DRIVE_3             (0xC000)       /* XT2 Drive Level mode: 3 */
4204 
 
4205 
/* UCSCTL7 Control Bits */
4206 
#define DCOFFG                 (0x0001)       /* DCO Fault Flag */
4207 
#define XT1LFOFFG              (0x0002)       /* XT1 Low Frequency Oscillator Fault Flag */
4208 
#define XT1HFOFFG              (0x0004)       /* XT1 High Frequency Oscillator 1 Fault Flag */
4209 
#define XT2OFFG                (0x0008)       /* High Frequency Oscillator 2 Fault Flag */
4210 
//#define RESERVED            (0x0010)    /* RESERVED */
4211 
//#define RESERVED            (0x0020)    /* RESERVED */
4212 
//#define RESERVED            (0x0040)    /* RESERVED */
4213 
//#define RESERVED            (0x0080)    /* RESERVED */
4214 
//#define RESERVED            (0x0100)    /* RESERVED */
4215 
//#define RESERVED            (0x0200)    /* RESERVED */
4216 
//#define RESERVED            (0x0400)    /* RESERVED */
4217 
//#define RESERVED            (0x0800)    /* RESERVED */
4218 
//#define RESERVED            (0x1000)    /* RESERVED */
4219 
//#define RESERVED            (0x2000)    /* RESERVED */
4220 
//#define RESERVED            (0x4000)    /* RESERVED */
4221 
//#define RESERVED            (0x8000)    /* RESERVED */
4222 
 
4223 
/* UCSCTL7 Control Bits */
4224 
#define DCOFFG_L               (0x0001)       /* DCO Fault Flag */
4225 
#define XT1LFOFFG_L            (0x0002)       /* XT1 Low Frequency Oscillator Fault Flag */
4226 
#define XT1HFOFFG_L            (0x0004)       /* XT1 High Frequency Oscillator 1 Fault Flag */
4227 
#define XT2OFFG_L              (0x0008)       /* High Frequency Oscillator 2 Fault Flag */
4228 
//#define RESERVED            (0x0010)    /* RESERVED */
4229 
//#define RESERVED            (0x0020)    /* RESERVED */
4230 
//#define RESERVED            (0x0040)    /* RESERVED */
4231 
//#define RESERVED            (0x0080)    /* RESERVED */
4232 
//#define RESERVED            (0x0100)    /* RESERVED */
4233 
//#define RESERVED            (0x0200)    /* RESERVED */
4234 
//#define RESERVED            (0x0400)    /* RESERVED */
4235 
//#define RESERVED            (0x0800)    /* RESERVED */
4236 
//#define RESERVED            (0x1000)    /* RESERVED */
4237 
//#define RESERVED            (0x2000)    /* RESERVED */
4238 
//#define RESERVED            (0x4000)    /* RESERVED */
4239 
//#define RESERVED            (0x8000)    /* RESERVED */
4240 
 
4241 
/* UCSCTL7 Control Bits */
4242 
//#define RESERVED            (0x0010)    /* RESERVED */
4243 
//#define RESERVED            (0x0020)    /* RESERVED */
4244 
//#define RESERVED            (0x0040)    /* RESERVED */
4245 
//#define RESERVED            (0x0080)    /* RESERVED */
4246 
//#define RESERVED            (0x0100)    /* RESERVED */
4247 
//#define RESERVED            (0x0200)    /* RESERVED */
4248 
//#define RESERVED            (0x0400)    /* RESERVED */
4249 
//#define RESERVED            (0x0800)    /* RESERVED */
4250 
//#define RESERVED            (0x1000)    /* RESERVED */
4251 
//#define RESERVED            (0x2000)    /* RESERVED */
4252 
//#define RESERVED            (0x4000)    /* RESERVED */
4253 
//#define RESERVED            (0x8000)    /* RESERVED */
4254 
 
4255 
/* UCSCTL8 Control Bits */
4256 
#define ACLKREQEN              (0x0001)       /* ACLK Clock Request Enable */
4257 
#define MCLKREQEN              (0x0002)       /* MCLK Clock Request Enable */
4258 
#define SMCLKREQEN             (0x0004)       /* SMCLK Clock Request Enable */
4259 
#define MODOSCREQEN            (0x0008)       /* MODOSC Clock Request Enable */
4260 
//#define RESERVED            (0x0010)    /* RESERVED */
4261 
//#define RESERVED            (0x0020)    /* RESERVED */
4262 
//#define RESERVED            (0x0040)    /* RESERVED */
4263 
//#define RESERVED            (0x0080)    /* RESERVED */
4264 
//#define RESERVED            (0x0100)    /* RESERVED */
4265 
//#define RESERVED            (0x0200)    /* RESERVED */
4266 
//#define RESERVED            (0x0400)    /* RESERVED */
4267 
//#define RESERVED            (0x0800)    /* RESERVED */
4268 
//#define RESERVED            (0x1000)    /* RESERVED */
4269 
//#define RESERVED            (0x2000)    /* RESERVED */
4270 
//#define RESERVED            (0x4000)    /* RESERVED */
4271 
//#define RESERVED            (0x8000)    /* RESERVED */
4272 
 
4273 
/* UCSCTL8 Control Bits */
4274 
#define ACLKREQEN_L            (0x0001)       /* ACLK Clock Request Enable */
4275 
#define MCLKREQEN_L            (0x0002)       /* MCLK Clock Request Enable */
4276 
#define SMCLKREQEN_L           (0x0004)       /* SMCLK Clock Request Enable */
4277 
#define MODOSCREQEN_L          (0x0008)       /* MODOSC Clock Request Enable */
4278 
//#define RESERVED            (0x0010)    /* RESERVED */
4279 
//#define RESERVED            (0x0020)    /* RESERVED */
4280 
//#define RESERVED            (0x0040)    /* RESERVED */
4281 
//#define RESERVED            (0x0080)    /* RESERVED */
4282 
//#define RESERVED            (0x0100)    /* RESERVED */
4283 
//#define RESERVED            (0x0200)    /* RESERVED */
4284 
//#define RESERVED            (0x0400)    /* RESERVED */
4285 
//#define RESERVED            (0x0800)    /* RESERVED */
4286 
//#define RESERVED            (0x1000)    /* RESERVED */
4287 
//#define RESERVED            (0x2000)    /* RESERVED */
4288 
//#define RESERVED            (0x4000)    /* RESERVED */
4289 
//#define RESERVED            (0x8000)    /* RESERVED */
4290 
 
4291 
/* UCSCTL8 Control Bits */
4292 
//#define RESERVED            (0x0010)    /* RESERVED */
4293 
//#define RESERVED            (0x0020)    /* RESERVED */
4294 
//#define RESERVED            (0x0040)    /* RESERVED */
4295 
//#define RESERVED            (0x0080)    /* RESERVED */
4296 
//#define RESERVED            (0x0100)    /* RESERVED */
4297 
//#define RESERVED            (0x0200)    /* RESERVED */
4298 
//#define RESERVED            (0x0400)    /* RESERVED */
4299 
//#define RESERVED            (0x0800)    /* RESERVED */
4300 
//#define RESERVED            (0x1000)    /* RESERVED */
4301 
//#define RESERVED            (0x2000)    /* RESERVED */
4302 
//#define RESERVED            (0x4000)    /* RESERVED */
4303 
//#define RESERVED            (0x8000)    /* RESERVED */
4304 
 
4305 
/************************************************************
4306 
* USCI A0
4307 
************************************************************/
4308 
#define __MSP430_HAS_USCI_A0__                /* Definition to show that Module is available */
4309 
#define __MSP430_BASEADDRESS_USCI_A0__ 0x05C0
4310 
 
4311 
SFR_16BIT(UCA0CTLW0);                         /* USCI A0 Control Word Register 0 */
4312 
SFR_8BIT(UCA0CTLW0_L);                        /* USCI A0 Control Word Register 0 */
4313 
SFR_8BIT(UCA0CTLW0_H);                        /* USCI A0 Control Word Register 0 */
4314 
#define UCA0CTL1               UCA0CTLW0_L    /* USCI A0 Control Register 1 */
4315 
#define UCA0CTL0               UCA0CTLW0_H    /* USCI A0 Control Register 0 */
4316 
SFR_16BIT(UCA0BRW);                           /* USCI A0 Baud Word Rate 0 */
4317 
SFR_8BIT(UCA0BRW_L);                          /* USCI A0 Baud Word Rate 0 */
4318 
SFR_8BIT(UCA0BRW_H);                          /* USCI A0 Baud Word Rate 0 */
4319 
#define UCA0BR0                UCA0BRW_L      /* USCI A0 Baud Rate 0 */
4320 
#define UCA0BR1                UCA0BRW_H      /* USCI A0 Baud Rate 1 */
4321 
SFR_8BIT(UCA0MCTL);                           /* USCI A0 Modulation Control */
4322 
SFR_8BIT(UCA0STAT);                           /* USCI A0 Status Register */
4323 
SFR_8BIT(UCA0RXBUF);                          /* USCI A0 Receive Buffer */
4324 
SFR_8BIT(UCA0TXBUF);                          /* USCI A0 Transmit Buffer */
4325 
SFR_8BIT(UCA0ABCTL);                          /* USCI A0 LIN Control */
4326 
SFR_16BIT(UCA0IRCTL);                         /* USCI A0 IrDA Transmit Control */
4327 
SFR_8BIT(UCA0IRCTL_L);                        /* USCI A0 IrDA Transmit Control */
4328 
SFR_8BIT(UCA0IRCTL_H);                        /* USCI A0 IrDA Transmit Control */
4329 
#define UCA0IRTCTL             UCA0IRCTL_L    /* USCI A0 IrDA Transmit Control */
4330 
#define UCA0IRRCTL             UCA0IRCTL_H    /* USCI A0 IrDA Receive Control */
4331 
SFR_16BIT(UCA0ICTL);                          /* USCI A0 Interrupt Enable Register */
4332 
SFR_8BIT(UCA0ICTL_L);                         /* USCI A0 Interrupt Enable Register */
4333 
SFR_8BIT(UCA0ICTL_H);                         /* USCI A0 Interrupt Enable Register */
4334 
#define UCA0IE                 UCA0ICTL_L     /* USCI A0 Interrupt Enable Register */
4335 
#define UCA0IFG                UCA0ICTL_H     /* USCI A0 Interrupt Flags Register */
4336 
SFR_16BIT(UCA0IV);                            /* USCI A0 Interrupt Vector Register */
4337 
 
4338 
 
4339 
/************************************************************
4340 
* USCI B0
4341 
************************************************************/
4342 
#define __MSP430_HAS_USCI_B0__                /* Definition to show that Module is available */
4343 
#define __MSP430_BASEADDRESS_USCI_B0__ 0x05E0
4344 
 
4345 
 
4346 
SFR_16BIT(UCB0CTLW0);                         /* USCI B0 Control Word Register 0 */
4347 
SFR_8BIT(UCB0CTLW0_L);                        /* USCI B0 Control Word Register 0 */
4348 
SFR_8BIT(UCB0CTLW0_H);                        /* USCI B0 Control Word Register 0 */
4349 
#define UCB0CTL1               UCB0CTLW0_L    /* USCI B0 Control Register 1 */
4350 
#define UCB0CTL0               UCB0CTLW0_H    /* USCI B0 Control Register 0 */
4351 
SFR_16BIT(UCB0BRW);                           /* USCI B0 Baud Word Rate 0 */
4352 
SFR_8BIT(UCB0BRW_L);                          /* USCI B0 Baud Word Rate 0 */
4353 
SFR_8BIT(UCB0BRW_H);                          /* USCI B0 Baud Word Rate 0 */
4354 
#define UCB0BR0                UCB0BRW_L      /* USCI B0 Baud Rate 0 */
4355 
#define UCB0BR1                UCB0BRW_H      /* USCI B0 Baud Rate 1 */
4356 
SFR_8BIT(UCB0STAT);                           /* USCI B0 Status Register */
4357 
SFR_8BIT(UCB0RXBUF);                          /* USCI B0 Receive Buffer */
4358 
SFR_8BIT(UCB0TXBUF);                          /* USCI B0 Transmit Buffer */
4359 
SFR_16BIT(UCB0I2COA);                         /* USCI B0 I2C Own Address */
4360 
SFR_8BIT(UCB0I2COA_L);                        /* USCI B0 I2C Own Address */
4361 
SFR_8BIT(UCB0I2COA_H);                        /* USCI B0 I2C Own Address */
4362 
SFR_16BIT(UCB0I2CSA);                         /* USCI B0 I2C Slave Address */
4363 
SFR_8BIT(UCB0I2CSA_L);                        /* USCI B0 I2C Slave Address */
4364 
SFR_8BIT(UCB0I2CSA_H);                        /* USCI B0 I2C Slave Address */
4365 
SFR_16BIT(UCB0ICTL);                          /* USCI B0 Interrupt Enable Register */
4366 
SFR_8BIT(UCB0ICTL_L);                         /* USCI B0 Interrupt Enable Register */
4367 
SFR_8BIT(UCB0ICTL_H);                         /* USCI B0 Interrupt Enable Register */
4368 
#define UCB0IE                 UCB0ICTL_L     /* USCI B0 Interrupt Enable Register */
4369 
#define UCB0IFG                UCB0ICTL_H     /* USCI B0 Interrupt Flags Register */
4370 
SFR_16BIT(UCB0IV);                            /* USCI B0 Interrupt Vector Register */
4371 
 
4372 
// UCAxCTL0 UART-Mode Control Bits
4373 
#define UCPEN                  (0x80)         /* Async. Mode: Parity enable */
4374 
#define UCPAR                  (0x40)         /* Async. Mode: Parity     0:odd / 1:even */
4375 
#define UCMSB                  (0x20)         /* Async. Mode: MSB first  0:LSB / 1:MSB */
4376 
#define UC7BIT                 (0x10)         /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
4377 
#define UCSPB                  (0x08)         /* Async. Mode: Stop Bits  0:one / 1: two */
4378 
#define UCMODE1                (0x04)         /* Async. Mode: USCI Mode 1 */
4379 
#define UCMODE0                (0x02)         /* Async. Mode: USCI Mode 0 */
4380 
#define UCSYNC                 (0x01)         /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
4381 
 
4382 
// UCxxCTL0 SPI-Mode Control Bits
4383 
#define UCCKPH                 (0x80)         /* Sync. Mode: Clock Phase */
4384 
#define UCCKPL                 (0x40)         /* Sync. Mode: Clock Polarity */
4385 
#define UCMST                  (0x08)         /* Sync. Mode: Master Select */
4386 
 
4387 
// UCBxCTL0 I2C-Mode Control Bits
4388 
#define UCA10                  (0x80)         /* 10-bit Address Mode */
4389 
#define UCSLA10                (0x40)         /* 10-bit Slave Address Mode */
4390 
#define UCMM                   (0x20)         /* Multi-Master Environment */
4391 
//#define res               (0x10)    /* reserved */
4392 
#define UCMODE_0               (0x00)         /* Sync. Mode: USCI Mode: 0 */
4393 
#define UCMODE_1               (0x02)         /* Sync. Mode: USCI Mode: 1 */
4394 
#define UCMODE_2               (0x04)         /* Sync. Mode: USCI Mode: 2 */
4395 
#define UCMODE_3               (0x06)         /* Sync. Mode: USCI Mode: 3 */
4396 
 
4397 
// UCAxCTL1 UART-Mode Control Bits
4398 
#define UCSSEL1                (0x80)         /* USCI 0 Clock Source Select 1 */
4399 
#define UCSSEL0                (0x40)         /* USCI 0 Clock Source Select 0 */
4400 
#define UCRXEIE                (0x20)         /* RX Error interrupt enable */
4401 
#define UCBRKIE                (0x10)         /* Break interrupt enable */
4402 
#define UCDORM                 (0x08)         /* Dormant (Sleep) Mode */
4403 
#define UCTXADDR               (0x04)         /* Send next Data as Address */
4404 
#define UCTXBRK                (0x02)         /* Send next Data as Break */
4405 
#define UCSWRST                (0x01)         /* USCI Software Reset */
4406 
 
4407 
// UCxxCTL1 SPI-Mode Control Bits
4408 
//#define res               (0x20)    /* reserved */
4409 
//#define res               (0x10)    /* reserved */
4410 
//#define res               (0x08)    /* reserved */
4411 
//#define res               (0x04)    /* reserved */
4412 
//#define res               (0x02)    /* reserved */
4413 
 
4414 
// UCBxCTL1 I2C-Mode Control Bits
4415 
//#define res               (0x20)    /* reserved */
4416 
#define UCTR                   (0x10)         /* Transmit/Receive Select/Flag */
4417 
#define UCTXNACK               (0x08)         /* Transmit NACK */
4418 
#define UCTXSTP                (0x04)         /* Transmit STOP */
4419 
#define UCTXSTT                (0x02)         /* Transmit START */
4420 
#define UCSSEL_0               (0x00)         /* USCI 0 Clock Source: 0 */
4421 
#define UCSSEL_1               (0x40)         /* USCI 0 Clock Source: 1 */
4422 
#define UCSSEL_2               (0x80)         /* USCI 0 Clock Source: 2 */
4423 
#define UCSSEL_3               (0xC0)         /* USCI 0 Clock Source: 3 */
4424 
#define UCSSEL__UCLK           (0x00)         /* USCI 0 Clock Source: UCLK */
4425 
#define UCSSEL__ACLK           (0x40)         /* USCI 0 Clock Source: ACLK */
4426 
#define UCSSEL__SMCLK          (0x80)         /* USCI 0 Clock Source: SMCLK */
4427 
 
4428 
/* UCAxMCTL Control Bits */
4429 
#define UCBRF3                 (0x80)         /* USCI First Stage Modulation Select 3 */
4430 
#define UCBRF2                 (0x40)         /* USCI First Stage Modulation Select 2 */
4431 
#define UCBRF1                 (0x20)         /* USCI First Stage Modulation Select 1 */
4432 
#define UCBRF0                 (0x10)         /* USCI First Stage Modulation Select 0 */
4433 
#define UCBRS2                 (0x08)         /* USCI Second Stage Modulation Select 2 */
4434 
#define UCBRS1                 (0x04)         /* USCI Second Stage Modulation Select 1 */
4435 
#define UCBRS0                 (0x02)         /* USCI Second Stage Modulation Select 0 */
4436 
#define UCOS16                 (0x01)         /* USCI 16-times Oversampling enable */
4437 
 
4438 
#define UCBRF_0                (0x00)         /* USCI First Stage Modulation: 0 */
4439 
#define UCBRF_1                (0x10)         /* USCI First Stage Modulation: 1 */
4440 
#define UCBRF_2                (0x20)         /* USCI First Stage Modulation: 2 */
4441 
#define UCBRF_3                (0x30)         /* USCI First Stage Modulation: 3 */
4442 
#define UCBRF_4                (0x40)         /* USCI First Stage Modulation: 4 */
4443 
#define UCBRF_5                (0x50)         /* USCI First Stage Modulation: 5 */
4444 
#define UCBRF_6                (0x60)         /* USCI First Stage Modulation: 6 */
4445 
#define UCBRF_7                (0x70)         /* USCI First Stage Modulation: 7 */
4446 
#define UCBRF_8                (0x80)         /* USCI First Stage Modulation: 8 */
4447 
#define UCBRF_9                (0x90)         /* USCI First Stage Modulation: 9 */
4448 
#define UCBRF_10               (0xA0)         /* USCI First Stage Modulation: A */
4449 
#define UCBRF_11               (0xB0)         /* USCI First Stage Modulation: B */
4450 
#define UCBRF_12               (0xC0)         /* USCI First Stage Modulation: C */
4451 
#define UCBRF_13               (0xD0)         /* USCI First Stage Modulation: D */
4452 
#define UCBRF_14               (0xE0)         /* USCI First Stage Modulation: E */
4453 
#define UCBRF_15               (0xF0)         /* USCI First Stage Modulation: F */
4454 
 
4455 
#define UCBRS_0                (0x00)         /* USCI Second Stage Modulation: 0 */
4456 
#define UCBRS_1                (0x02)         /* USCI Second Stage Modulation: 1 */
4457 
#define UCBRS_2                (0x04)         /* USCI Second Stage Modulation: 2 */
4458 
#define UCBRS_3                (0x06)         /* USCI Second Stage Modulation: 3 */
4459 
#define UCBRS_4                (0x08)         /* USCI Second Stage Modulation: 4 */
4460 
#define UCBRS_5                (0x0A)         /* USCI Second Stage Modulation: 5 */
4461 
#define UCBRS_6                (0x0C)         /* USCI Second Stage Modulation: 6 */
4462 
#define UCBRS_7                (0x0E)         /* USCI Second Stage Modulation: 7 */
4463 
 
4464 
/* UCAxSTAT Control Bits */
4465 
#define UCLISTEN               (0x80)         /* USCI Listen mode */
4466 
#define UCFE                   (0x40)         /* USCI Frame Error Flag */
4467 
#define UCOE                   (0x20)         /* USCI Overrun Error Flag */
4468 
#define UCPE                   (0x10)         /* USCI Parity Error Flag */
4469 
#define UCBRK                  (0x08)         /* USCI Break received */
4470 
#define UCRXERR                (0x04)         /* USCI RX Error Flag */
4471 
#define UCADDR                 (0x02)         /* USCI Address received Flag */
4472 
#define UCBUSY                 (0x01)         /* USCI Busy Flag */
4473 
#define UCIDLE                 (0x02)         /* USCI Idle line detected Flag */
4474 
 
4475 
/* UCBxSTAT Control Bits */
4476 
#define UCSCLLOW               (0x40)         /* SCL low */
4477 
#define UCGC                   (0x20)         /* General Call address received Flag */
4478 
#define UCBBUSY                (0x10)         /* Bus Busy Flag */
4479 
 
4480 
/* UCAxIRTCTL Control Bits */
4481 
#define UCIRTXPL5              (0x80)         /* IRDA Transmit Pulse Length 5 */
4482 
#define UCIRTXPL4              (0x40)         /* IRDA Transmit Pulse Length 4 */
4483 
#define UCIRTXPL3              (0x20)         /* IRDA Transmit Pulse Length 3 */
4484 
#define UCIRTXPL2              (0x10)         /* IRDA Transmit Pulse Length 2 */
4485 
#define UCIRTXPL1              (0x08)         /* IRDA Transmit Pulse Length 1 */
4486 
#define UCIRTXPL0              (0x04)         /* IRDA Transmit Pulse Length 0 */
4487 
#define UCIRTXCLK              (0x02)         /* IRDA Transmit Pulse Clock Select */
4488 
#define UCIREN                 (0x01)         /* IRDA Encoder/Decoder enable */
4489 
 
4490 
/* UCAxIRRCTL Control Bits */
4491 
#define UCIRRXFL5              (0x80)         /* IRDA Receive Filter Length 5 */
4492 
#define UCIRRXFL4              (0x40)         /* IRDA Receive Filter Length 4 */
4493 
#define UCIRRXFL3              (0x20)         /* IRDA Receive Filter Length 3 */
4494 
#define UCIRRXFL2              (0x10)         /* IRDA Receive Filter Length 2 */
4495 
#define UCIRRXFL1              (0x08)         /* IRDA Receive Filter Length 1 */
4496 
#define UCIRRXFL0              (0x04)         /* IRDA Receive Filter Length 0 */
4497 
#define UCIRRXPL               (0x02)         /* IRDA Receive Input Polarity */
4498 
#define UCIRRXFE               (0x01)         /* IRDA Receive Filter enable */
4499 
 
4500 
/* UCAxABCTL Control Bits */
4501 
//#define res               (0x80)    /* reserved */
4502 
//#define res               (0x40)    /* reserved */
4503 
#define UCDELIM1               (0x20)         /* Break Sync Delimiter 1 */
4504 
#define UCDELIM0               (0x10)         /* Break Sync Delimiter 0 */
4505 
#define UCSTOE                 (0x08)         /* Sync-Field Timeout error */
4506 
#define UCBTOE                 (0x04)         /* Break Timeout error */
4507 
//#define res               (0x02)    /* reserved */
4508 
#define UCABDEN                (0x01)         /* Auto Baud Rate detect enable */
4509 
 
4510 
/* UCBxI2COA Control Bits */
4511 
#define UCGCEN                 (0x8000)       /* I2C General Call enable */
4512 
#define UCOA9                  (0x0200)       /* I2C Own Address 9 */
4513 
#define UCOA8                  (0x0100)       /* I2C Own Address 8 */
4514 
#define UCOA7                  (0x0080)       /* I2C Own Address 7 */
4515 
#define UCOA6                  (0x0040)       /* I2C Own Address 6 */
4516 
#define UCOA5                  (0x0020)       /* I2C Own Address 5 */
4517 
#define UCOA4                  (0x0010)       /* I2C Own Address 4 */
4518 
#define UCOA3                  (0x0008)       /* I2C Own Address 3 */
4519 
#define UCOA2                  (0x0004)       /* I2C Own Address 2 */
4520 
#define UCOA1                  (0x0002)       /* I2C Own Address 1 */
4521 
#define UCOA0                  (0x0001)       /* I2C Own Address 0 */
4522 
 
4523 
/* UCBxI2COA Control Bits */
4524 
#define UCOA7_L                (0x0080)       /* I2C Own Address 7 */
4525 
#define UCOA6_L                (0x0040)       /* I2C Own Address 6 */
4526 
#define UCOA5_L                (0x0020)       /* I2C Own Address 5 */
4527 
#define UCOA4_L                (0x0010)       /* I2C Own Address 4 */
4528 
#define UCOA3_L                (0x0008)       /* I2C Own Address 3 */
4529 
#define UCOA2_L                (0x0004)       /* I2C Own Address 2 */
4530 
#define UCOA1_L                (0x0002)       /* I2C Own Address 1 */
4531 
#define UCOA0_L                (0x0001)       /* I2C Own Address 0 */
4532 
 
4533 
/* UCBxI2COA Control Bits */
4534 
#define UCGCEN_H               (0x0080)       /* I2C General Call enable */
4535 
#define UCOA9_H                (0x0002)       /* I2C Own Address 9 */
4536 
#define UCOA8_H                (0x0001)       /* I2C Own Address 8 */
4537 
 
4538 
/* UCBxI2CSA Control Bits */
4539 
#define UCSA9                  (0x0200)       /* I2C Slave Address 9 */
4540 
#define UCSA8                  (0x0100)       /* I2C Slave Address 8 */
4541 
#define UCSA7                  (0x0080)       /* I2C Slave Address 7 */
4542 
#define UCSA6                  (0x0040)       /* I2C Slave Address 6 */
4543 
#define UCSA5                  (0x0020)       /* I2C Slave Address 5 */
4544 
#define UCSA4                  (0x0010)       /* I2C Slave Address 4 */
4545 
#define UCSA3                  (0x0008)       /* I2C Slave Address 3 */
4546 
#define UCSA2                  (0x0004)       /* I2C Slave Address 2 */
4547 
#define UCSA1                  (0x0002)       /* I2C Slave Address 1 */
4548 
#define UCSA0                  (0x0001)       /* I2C Slave Address 0 */
4549 
 
4550 
/* UCBxI2CSA Control Bits */
4551 
#define UCSA7_L                (0x0080)       /* I2C Slave Address 7 */
4552 
#define UCSA6_L                (0x0040)       /* I2C Slave Address 6 */
4553 
#define UCSA5_L                (0x0020)       /* I2C Slave Address 5 */
4554 
#define UCSA4_L                (0x0010)       /* I2C Slave Address 4 */
4555 
#define UCSA3_L                (0x0008)       /* I2C Slave Address 3 */
4556 
#define UCSA2_L                (0x0004)       /* I2C Slave Address 2 */
4557 
#define UCSA1_L                (0x0002)       /* I2C Slave Address 1 */
4558 
#define UCSA0_L                (0x0001)       /* I2C Slave Address 0 */
4559 
 
4560 
/* UCBxI2CSA Control Bits */
4561 
#define UCSA9_H                (0x0002)       /* I2C Slave Address 9 */
4562 
#define UCSA8_H                (0x0001)       /* I2C Slave Address 8 */
4563 
 
4564 
/* UCAxIE Control Bits */
4565 
#define UCTXIE                 (0x0002)       /* USCI Transmit Interrupt Enable */
4566 
#define UCRXIE                 (0x0001)       /* USCI Receive Interrupt Enable */
4567 
 
4568 
/* UCBxIE Control Bits */
4569 
#define UCNACKIE               (0x0020)       /* NACK Condition interrupt enable */
4570 
#define UCALIE                 (0x0010)       /* Arbitration Lost interrupt enable */
4571 
#define UCSTPIE                (0x0008)       /* STOP Condition interrupt enable */
4572 
#define UCSTTIE                (0x0004)       /* START Condition interrupt enable */
4573 
#define UCTXIE                 (0x0002)       /* USCI Transmit Interrupt Enable */
4574 
#define UCRXIE                 (0x0001)       /* USCI Receive Interrupt Enable */
4575 
 
4576 
/* UCAxIFG Control Bits */
4577 
#define UCTXIFG                (0x0002)       /* USCI Transmit Interrupt Flag */
4578 
#define UCRXIFG                (0x0001)       /* USCI Receive Interrupt Flag */
4579 
 
4580 
/* UCBxIFG Control Bits */
4581 
#define UCNACKIFG              (0x0020)       /* NAK Condition interrupt Flag */
4582 
#define UCALIFG                (0x0010)       /* Arbitration Lost interrupt Flag */
4583 
#define UCSTPIFG               (0x0008)       /* STOP Condition interrupt Flag */
4584 
#define UCSTTIFG               (0x0004)       /* START Condition interrupt Flag */
4585 
#define UCTXIFG                (0x0002)       /* USCI Transmit Interrupt Flag */
4586 
#define UCRXIFG                (0x0001)       /* USCI Receive Interrupt Flag */
4587 
 
4588 
/* USCI Definitions */
4589 
#define USCI_NONE              (0x0000)       /* No Interrupt pending */
4590 
#define USCI_UCRXIFG           (0x0002)       /* USCI UCRXIFG */
4591 
#define USCI_UCTXIFG           (0x0004)       /* USCI UCTXIFG */
4592 
#define USCI_I2C_UCALIFG       (0x0002)       /* USCI I2C Mode: UCALIFG */
4593 
#define USCI_I2C_UCNACKIFG     (0x0004)       /* USCI I2C Mode: UCNACKIFG */
4594 
#define USCI_I2C_UCSTTIFG      (0x0006)       /* USCI I2C Mode: UCSTTIFG*/
4595 
#define USCI_I2C_UCSTPIFG      (0x0008)       /* USCI I2C Mode: UCSTPIFG*/
4596 
#define USCI_I2C_UCRXIFG       (0x000A)       /* USCI I2C Mode: UCRXIFG */
4597 
#define USCI_I2C_UCTXIFG       (0x000C)       /* USCI I2C Mode: UCTXIFG */
4598 
 
4599 
/************************************************************
4600 
* USCI A1
4601 
************************************************************/
4602 
#define __MSP430_HAS_USCI_A1__                /* Definition to show that Module is available */
4603 
#define __MSP430_BASEADDRESS_USCI_A1__ 0x0600
4604 
 
4605 
SFR_16BIT(UCA1CTLW0);                         /* USCI A1 Control Word Register 0 */
4606 
SFR_8BIT(UCA1CTLW0_L);                        /* USCI A1 Control Word Register 0 */
4607 
SFR_8BIT(UCA1CTLW0_H);                        /* USCI A1 Control Word Register 0 */
4608 
#define UCA1CTL1               UCA1CTLW0_L    /* USCI A1 Control Register 1 */
4609 
#define UCA1CTL0               UCA1CTLW0_H    /* USCI A1 Control Register 0 */
4610 
SFR_16BIT(UCA1BRW);                           /* USCI A1 Baud Word Rate 0 */
4611 
SFR_8BIT(UCA1BRW_L);                          /* USCI A1 Baud Word Rate 0 */
4612 
SFR_8BIT(UCA1BRW_H);                          /* USCI A1 Baud Word Rate 0 */
4613 
#define UCA1BR0                UCA1BRW_L      /* USCI A1 Baud Rate 0 */
4614 
#define UCA1BR1                UCA1BRW_H      /* USCI A1 Baud Rate 1 */
4615 
SFR_8BIT(UCA1MCTL);                           /* USCI A1 Modulation Control */
4616 
SFR_8BIT(UCA1STAT);                           /* USCI A1 Status Register */
4617 
SFR_8BIT(UCA1RXBUF);                          /* USCI A1 Receive Buffer */
4618 
SFR_8BIT(UCA1TXBUF);                          /* USCI A1 Transmit Buffer */
4619 
SFR_8BIT(UCA1ABCTL);                          /* USCI A1 LIN Control */
4620 
SFR_16BIT(UCA1IRCTL);                         /* USCI A1 IrDA Transmit Control */
4621 
SFR_8BIT(UCA1IRCTL_L);                        /* USCI A1 IrDA Transmit Control */
4622 
SFR_8BIT(UCA1IRCTL_H);                        /* USCI A1 IrDA Transmit Control */
4623 
#define UCA1IRTCTL             UCA1IRCTL_L    /* USCI A1 IrDA Transmit Control */
4624 
#define UCA1IRRCTL             UCA1IRCTL_H    /* USCI A1 IrDA Receive Control */
4625 
SFR_16BIT(UCA1ICTL);                          /* USCI A1 Interrupt Enable Register */
4626 
SFR_8BIT(UCA1ICTL_L);                         /* USCI A1 Interrupt Enable Register */
4627 
SFR_8BIT(UCA1ICTL_H);                         /* USCI A1 Interrupt Enable Register */
4628 
#define UCA1IE                 UCA1ICTL_L     /* USCI A1 Interrupt Enable Register */
4629 
#define UCA1IFG                UCA1ICTL_H     /* USCI A1 Interrupt Flags Register */
4630 
SFR_16BIT(UCA1IV);                            /* USCI A1 Interrupt Vector Register */
4631 
 
4632 
 
4633 
/************************************************************
4634 
* USCI B1
4635 
************************************************************/
4636 
#define __MSP430_HAS_USCI_B1__                /* Definition to show that Module is available */
4637 
#define __MSP430_BASEADDRESS_USCI_B1__ 0x0620
4638 
 
4639 
 
4640 
SFR_16BIT(UCB1CTLW0);                         /* USCI B1 Control Word Register 0 */
4641 
SFR_8BIT(UCB1CTLW0_L);                        /* USCI B1 Control Word Register 0 */
4642 
SFR_8BIT(UCB1CTLW0_H);                        /* USCI B1 Control Word Register 0 */
4643 
#define UCB1CTL1               UCB1CTLW0_L    /* USCI B1 Control Register 1 */
4644 
#define UCB1CTL0               UCB1CTLW0_H    /* USCI B1 Control Register 0 */
4645 
SFR_16BIT(UCB1BRW);                           /* USCI B1 Baud Word Rate 0 */
4646 
SFR_8BIT(UCB1BRW_L);                          /* USCI B1 Baud Word Rate 0 */
4647 
SFR_8BIT(UCB1BRW_H);                          /* USCI B1 Baud Word Rate 0 */
4648 
#define UCB1BR0                UCB1BRW_L      /* USCI B1 Baud Rate 0 */
4649 
#define UCB1BR1                UCB1BRW_H      /* USCI B1 Baud Rate 1 */
4650 
SFR_8BIT(UCB1STAT);                           /* USCI B1 Status Register */
4651 
SFR_8BIT(UCB1RXBUF);                          /* USCI B1 Receive Buffer */
4652 
SFR_8BIT(UCB1TXBUF);                          /* USCI B1 Transmit Buffer */
4653 
SFR_16BIT(UCB1I2COA);                         /* USCI B1 I2C Own Address */
4654 
SFR_8BIT(UCB1I2COA_L);                        /* USCI B1 I2C Own Address */
4655 
SFR_8BIT(UCB1I2COA_H);                        /* USCI B1 I2C Own Address */
4656 
SFR_16BIT(UCB1I2CSA);                         /* USCI B1 I2C Slave Address */
4657 
SFR_8BIT(UCB1I2CSA_L);                        /* USCI B1 I2C Slave Address */
4658 
SFR_8BIT(UCB1I2CSA_H);                        /* USCI B1 I2C Slave Address */
4659 
SFR_16BIT(UCB1ICTL);                          /* USCI B1 Interrupt Enable Register */
4660 
SFR_8BIT(UCB1ICTL_L);                         /* USCI B1 Interrupt Enable Register */
4661 
SFR_8BIT(UCB1ICTL_H);                         /* USCI B1 Interrupt Enable Register */
4662 
#define UCB1IE                 UCB1ICTL_L     /* USCI B1 Interrupt Enable Register */
4663 
#define UCB1IFG                UCB1ICTL_H     /* USCI B1 Interrupt Flags Register */
4664 
SFR_16BIT(UCB1IV);                            /* USCI B1 Interrupt Vector Register */
4665 
 
4666 
/************************************************************
4667 
* WATCHDOG TIMER A
4668 
************************************************************/
4669 
#define __MSP430_HAS_WDT_A__                  /* Definition to show that Module is available */
4670 
#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
4671 
 
4672 
SFR_16BIT(WDTCTL);                            /* Watchdog Timer Control */
4673 
SFR_8BIT(WDTCTL_L);                           /* Watchdog Timer Control */
4674 
SFR_8BIT(WDTCTL_H);                           /* Watchdog Timer Control */
4675 
/* The bit names have been prefixed with "WDT" */
4676 
/* WDTCTL Control Bits */
4677 
#define WDTIS0                 (0x0001)       /* WDT - Timer Interval Select 0 */
4678 
#define WDTIS1                 (0x0002)       /* WDT - Timer Interval Select 1 */
4679 
#define WDTIS2                 (0x0004)       /* WDT - Timer Interval Select 2 */
4680 
#define WDTCNTCL               (0x0008)       /* WDT - Timer Clear */
4681 
#define WDTTMSEL               (0x0010)       /* WDT - Timer Mode Select */
4682 
#define WDTSSEL0               (0x0020)       /* WDT - Timer Clock Source Select 0 */
4683 
#define WDTSSEL1               (0x0040)       /* WDT - Timer Clock Source Select 1 */
4684 
#define WDTHOLD                (0x0080)       /* WDT - Timer hold */
4685 
 
4686 
/* WDTCTL Control Bits */
4687 
#define WDTIS0_L               (0x0001)       /* WDT - Timer Interval Select 0 */
4688 
#define WDTIS1_L               (0x0002)       /* WDT - Timer Interval Select 1 */
4689 
#define WDTIS2_L               (0x0004)       /* WDT - Timer Interval Select 2 */
4690 
#define WDTCNTCL_L             (0x0008)       /* WDT - Timer Clear */
4691 
#define WDTTMSEL_L             (0x0010)       /* WDT - Timer Mode Select */
4692 
#define WDTSSEL0_L             (0x0020)       /* WDT - Timer Clock Source Select 0 */
4693 
#define WDTSSEL1_L             (0x0040)       /* WDT - Timer Clock Source Select 1 */
4694 
#define WDTHOLD_L              (0x0080)       /* WDT - Timer hold */
4695 
 
4696 
/* WDTCTL Control Bits */
4697 
 
4698 
#define WDTPW                  (0x5A00)
4699 
 
4700 
#define WDTIS_0                (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
4701 
#define WDTIS_1                (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
4702 
#define WDTIS_2                (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
4703 
#define WDTIS_3                (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
4704 
#define WDTIS_4                (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
4705 
#define WDTIS_5                (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
4706 
#define WDTIS_6                (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
4707 
#define WDTIS_7                (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
4708 
#define WDTIS__2G              (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
4709 
#define WDTIS__128M            (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
4710 
#define WDTIS__8192K           (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
4711 
#define WDTIS__512K            (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
4712 
#define WDTIS__32K             (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
4713 
#define WDTIS__8192            (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
4714 
#define WDTIS__512             (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
4715 
#define WDTIS__64              (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
4716 
 
4717 
#define WDTSSEL_0              (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
4718 
#define WDTSSEL_1              (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
4719 
#define WDTSSEL_2              (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
4720 
#define WDTSSEL_3              (3*0x0020u)    /* WDT - Timer Clock Source Select: reserved */
4721 
#define WDTSSEL__SMCLK         (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
4722 
#define WDTSSEL__ACLK          (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
4723 
#define WDTSSEL__VLO           (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
4724 
 
4725 
/* WDT-interval times [1ms] coded with Bits 0-2 */
4726 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
4727 
#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2)                         /* 32ms interval (default) */
4728 
#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0)                  /* 8ms     " */
4729 
#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1)                  /* 0.5ms   " */
4730 
#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)           /* 0.064ms " */
4731 
/* WDT is clocked by fACLK (assumed 32KHz) */
4732 
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)                /* 1000ms  " */
4733 
#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0)         /* 250ms   " */
4734 
#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1)         /* 16ms    " */
4735 
#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0)  /* 1.9ms   " */
4736 
/* Watchdog mode -> reset after expired time */
4737 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
4738 
#define WDT_MRST_32         (WDTPW+WDTCNTCL+WDTIS2)                                  /* 32ms interval (default) */
4739 
#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS2+WDTIS0)                           /* 8ms     " */
4740 
#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS2+WDTIS1)                           /* 0.5ms   " */
4741 
#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)                    /* 0.064ms " */
4742 
/* WDT is clocked by fACLK (assumed 32KHz) */
4743 
#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2)                         /* 1000ms  " */
4744 
#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0)                  /* 250ms   " */
4745 
#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1)                  /* 16ms    " */
4746 
#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0)           /* 1.9ms   " */
4747 
 
4748 
 
4749 
/************************************************************
4750 
* TLV Descriptors
4751 
************************************************************/
4752 
#define __MSP430_HAS_TLV__                    /* Definition to show that Module is available */
4753 
 
4754 
#define TLV_START              (0x1A08)       /* Start Address of the TLV structure */
4755 
#define TLV_END                (0x1AFF)       /* End Address of the TLV structure */
4756 
 
4757 
#define TLV_LDTAG              (0x01)         /*  Legacy descriptor (1xx, 2xx, 4xx families) */
4758 
#define TLV_PDTAG              (0x02)         /*  Peripheral discovery descriptor */
4759 
#define TLV_Reserved3          (0x03)         /*  Future usage */
4760 
#define TLV_Reserved4          (0x04)         /*  Future usage */
4761 
#define TLV_BLANK              (0x05)         /*  Blank descriptor */
4762 
#define TLV_Reserved6          (0x06)         /*  Future usage */
4763 
#define TLV_Reserved7          (0x07)         /*  Serial Number */
4764 
#define TLV_DIERECORD          (0x08)         /*  Die Record  */
4765 
#define TLV_ADCCAL             (0x11)         /*  ADC12 calibration */
4766 
#define TLV_ADC12CAL           (0x11)         /*  ADC12 calibration */
4767 
#define TLV_ADC10CAL           (0x13)         /*  ADC10 calibration */
4768 
#define TLV_REFCAL             (0x12)         /*  REF calibration */
4769 
#define TLV_TAGEXT             (0xFE)         /*  Tag extender */
4770 
#define TLV_TAGEND             (0xFF)         //  Tag End of Table
4771 
 
4772 
/************************************************************
4773 
* Interrupt Vectors (offset from 0xFF80)
4774 
************************************************************/
4775 
 
4776 
#pragma diag_suppress 1107
4777 
#define VECTOR_NAME(name)             name##_ptr
4778 
#define EMIT_PRAGMA(x)                _Pragma(#x)
4779 
#define CREATE_VECTOR(name)           void * const VECTOR_NAME(name) = (void *)(long)&name
4780 
#define PLACE_VECTOR(vector,section)  EMIT_PRAGMA(DATA_SECTION(vector,section))
4781 
#define PLACE_INTERRUPT(func)         EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
4782 
#define ISR_VECTOR(func,offset)       CREATE_VECTOR(func); \
4783 
                                      PLACE_VECTOR(VECTOR_NAME(func), offset) \
4784 
                                      PLACE_INTERRUPT(func)
4785 
 
4786 
 
4787 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4788 
#define PORT4_VECTOR            ".int37"                    /* 0xFFCA Port 4 */
4789 
#else
4790 
#define PORT4_VECTOR            (37 * 1u)                    /* 0xFFCA Port 4 */
4791 
/*#define PORT4_ISR(func)         ISR_VECTOR(func, ".int37")  */ /* 0xFFCA Port 4 */ /* CCE V2 Style */
4792 
#endif
4793 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4794 
#define PORT3_VECTOR            ".int38"                    /* 0xFFCC Port 3 */
4795 
#else
4796 
#define PORT3_VECTOR            (38 * 1u)                    /* 0xFFCC Port 3 */
4797 
/*#define PORT3_ISR(func)         ISR_VECTOR(func, ".int38")  */ /* 0xFFCC Port 3 */ /* CCE V2 Style */
4798 
#endif
4799 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4800 
#define TIMER2_A1_VECTOR        ".int39"                    /* 0xFFCE Timer0_A5 CC1-4, TA */
4801 
#else
4802 
#define TIMER2_A1_VECTOR        (39 * 1u)                    /* 0xFFCE Timer0_A5 CC1-4, TA */
4803 
/*#define TIMER2_A1_ISR(func)     ISR_VECTOR(func, ".int39")  */ /* 0xFFCE Timer0_A5 CC1-4, TA */ /* CCE V2 Style */
4804 
#endif
4805 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4806 
#define TIMER2_A0_VECTOR        ".int40"                    /* 0xFFD0 Timer0_A5 CC0 */
4807 
#else
4808 
#define TIMER2_A0_VECTOR        (40 * 1u)                    /* 0xFFD0 Timer0_A5 CC0 */
4809 
/*#define TIMER2_A0_ISR(func)     ISR_VECTOR(func, ".int40")  */ /* 0xFFD0 Timer0_A5 CC0 */ /* CCE V2 Style */
4810 
#endif
4811 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4812 
#define RTC_VECTOR              ".int42"                    /* 0xFFD4 RTC */
4813 
#else
4814 
#define RTC_VECTOR              (42 * 1u)                    /* 0xFFD4 RTC */
4815 
/*#define RTC_ISR(func)           ISR_VECTOR(func, ".int42")  */ /* 0xFFD4 RTC */ /* CCE V2 Style */
4816 
#endif
4817 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4818 
#define PORT2_VECTOR            ".int44"                    /* 0xFFD8 Port 2 */
4819 
#else
4820 
#define PORT2_VECTOR            (44 * 1u)                    /* 0xFFD8 Port 2 */
4821 
/*#define PORT2_ISR(func)         ISR_VECTOR(func, ".int44")  */ /* 0xFFD8 Port 2 */ /* CCE V2 Style */
4822 
#endif
4823 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4824 
#define USCI_B1_VECTOR          ".int45"                    /* 0xFFDA USCI B1 Receive/Transmit */
4825 
#else
4826 
#define USCI_B1_VECTOR          (45 * 1u)                    /* 0xFFDA USCI B1 Receive/Transmit */
4827 
/*#define USCI_B1_ISR(func)       ISR_VECTOR(func, ".int45")  */ /* 0xFFDA USCI B1 Receive/Transmit */ /* CCE V2 Style */
4828 
#endif
4829 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4830 
#define USCI_A1_VECTOR          ".int46"                    /* 0xFFDC USCI A1 Receive/Transmit */
4831 
#else
4832 
#define USCI_A1_VECTOR          (46 * 1u)                    /* 0xFFDC USCI A1 Receive/Transmit */
4833 
/*#define USCI_A1_ISR(func)       ISR_VECTOR(func, ".int46")  */ /* 0xFFDC USCI A1 Receive/Transmit */ /* CCE V2 Style */
4834 
#endif
4835 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4836 
#define PORT1_VECTOR            ".int47"                    /* 0xFFDE Port 1 */
4837 
#else
4838 
#define PORT1_VECTOR            (47 * 1u)                    /* 0xFFDE Port 1 */
4839 
/*#define PORT1_ISR(func)         ISR_VECTOR(func, ".int47")  */ /* 0xFFDE Port 1 */ /* CCE V2 Style */
4840 
#endif
4841 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4842 
#define TIMER1_A1_VECTOR        ".int48"                    /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
4843 
#else
4844 
#define TIMER1_A1_VECTOR        (48 * 1u)                    /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
4845 
/*#define TIMER1_A1_ISR(func)     ISR_VECTOR(func, ".int48")  */ /* 0xFFE0 Timer1_A3 CC1-2, TA1 */ /* CCE V2 Style */
4846 
#endif
4847 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4848 
#define TIMER1_A0_VECTOR        ".int49"                    /* 0xFFE2 Timer1_A3 CC0 */
4849 
#else
4850 
#define TIMER1_A0_VECTOR        (49 * 1u)                    /* 0xFFE2 Timer1_A3 CC0 */
4851 
/*#define TIMER1_A0_ISR(func)     ISR_VECTOR(func, ".int49")  */ /* 0xFFE2 Timer1_A3 CC0 */ /* CCE V2 Style */
4852 
#endif
4853 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4854 
#define DMA_VECTOR              ".int50"                    /* 0xFFE4 DMA */
4855 
#else
4856 
#define DMA_VECTOR              (50 * 1u)                    /* 0xFFE4 DMA */
4857 
/*#define DMA_ISR(func)           ISR_VECTOR(func, ".int50")  */ /* 0xFFE4 DMA */ /* CCE V2 Style */
4858 
#endif
4859 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4860 
#define USB_UBM_VECTOR          ".int51"                    /* 0xFFE6 USB Timer / cable event / USB reset */
4861 
#else
4862 
#define USB_UBM_VECTOR          (51 * 1u)                    /* 0xFFE6 USB Timer / cable event / USB reset */
4863 
/*#define USB_UBM_ISR(func)       ISR_VECTOR(func, ".int51")  */ /* 0xFFE6 USB Timer / cable event / USB reset */ /* CCE V2 Style */
4864 
#endif
4865 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4866 
#define TIMER0_A1_VECTOR        ".int52"                    /* 0xFFE8 Timer0_A5 CC1-4, TA */
4867 
#else
4868 
#define TIMER0_A1_VECTOR        (52 * 1u)                    /* 0xFFE8 Timer0_A5 CC1-4, TA */
4869 
/*#define TIMER0_A1_ISR(func)     ISR_VECTOR(func, ".int52")  */ /* 0xFFE8 Timer0_A5 CC1-4, TA */ /* CCE V2 Style */
4870 
#endif
4871 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4872 
#define TIMER0_A0_VECTOR        ".int53"                    /* 0xFFEA Timer0_A5 CC0 */
4873 
#else
4874 
#define TIMER0_A0_VECTOR        (53 * 1u)                    /* 0xFFEA Timer0_A5 CC0 */
4875 
/*#define TIMER0_A0_ISR(func)     ISR_VECTOR(func, ".int53")  */ /* 0xFFEA Timer0_A5 CC0 */ /* CCE V2 Style */
4876 
#endif
4877 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4878 
#define USCI_B0_VECTOR          ".int55"                    /* 0xFFEE USCI B0 Receive/Transmit */
4879 
#else
4880 
#define USCI_B0_VECTOR          (55 * 1u)                    /* 0xFFEE USCI B0 Receive/Transmit */
4881 
/*#define USCI_B0_ISR(func)       ISR_VECTOR(func, ".int55")  */ /* 0xFFEE USCI B0 Receive/Transmit */ /* CCE V2 Style */
4882 
#endif
4883 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4884 
#define USCI_A0_VECTOR          ".int56"                    /* 0xFFF0 USCI A0 Receive/Transmit */
4885 
#else
4886 
#define USCI_A0_VECTOR          (56 * 1u)                    /* 0xFFF0 USCI A0 Receive/Transmit */
4887 
/*#define USCI_A0_ISR(func)       ISR_VECTOR(func, ".int56")  */ /* 0xFFF0 USCI A0 Receive/Transmit */ /* CCE V2 Style */
4888 
#endif
4889 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4890 
#define WDT_VECTOR              ".int57"                    /* 0xFFF2 Watchdog Timer */
4891 
#else
4892 
#define WDT_VECTOR              (57 * 1u)                    /* 0xFFF2 Watchdog Timer */
4893 
/*#define WDT_ISR(func)           ISR_VECTOR(func, ".int57")  */ /* 0xFFF2 Watchdog Timer */ /* CCE V2 Style */
4894 
#endif
4895 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4896 
#define TIMER0_B1_VECTOR        ".int58"                    /* 0xFFF4 Timer0_B7 CC1-6, TB */
4897 
#else
4898 
#define TIMER0_B1_VECTOR        (58 * 1u)                    /* 0xFFF4 Timer0_B7 CC1-6, TB */
4899 
/*#define TIMER0_B1_ISR(func)     ISR_VECTOR(func, ".int58")  */ /* 0xFFF4 Timer0_B7 CC1-6, TB */ /* CCE V2 Style */
4900 
#endif
4901 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4902 
#define TIMER0_B0_VECTOR        ".int59"                    /* 0xFFF6 Timer0_B7 CC0 */
4903 
#else
4904 
#define TIMER0_B0_VECTOR        (59 * 1u)                    /* 0xFFF6 Timer0_B7 CC0 */
4905 
/*#define TIMER0_B0_ISR(func)     ISR_VECTOR(func, ".int59")  */ /* 0xFFF6 Timer0_B7 CC0 */ /* CCE V2 Style */
4906 
#endif
4907 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4908 
#define COMP_B_VECTOR           ".int60"                    /* 0xFFF8 Comparator B */
4909 
#else
4910 
#define COMP_B_VECTOR           (60 * 1u)                    /* 0xFFF8 Comparator B */
4911 
/*#define COMP_B_ISR(func)        ISR_VECTOR(func, ".int60")  */ /* 0xFFF8 Comparator B */ /* CCE V2 Style */
4912 
#endif
4913 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4914 
#define UNMI_VECTOR             ".int61"                    /* 0xFFFA User Non-maskable */
4915 
#else
4916 
#define UNMI_VECTOR             (61 * 1u)                    /* 0xFFFA User Non-maskable */
4917 
/*#define UNMI_ISR(func)          ISR_VECTOR(func, ".int61")  */ /* 0xFFFA User Non-maskable */ /* CCE V2 Style */
4918 
#endif
4919 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4920 
#define SYSNMI_VECTOR           ".int62"                    /* 0xFFFC System Non-maskable */
4921 
#else
4922 
#define SYSNMI_VECTOR           (62 * 1u)                    /* 0xFFFC System Non-maskable */
4923 
/*#define SYSNMI_ISR(func)        ISR_VECTOR(func, ".int62")  */ /* 0xFFFC System Non-maskable */ /* CCE V2 Style */
4924 
#endif
4925 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4926 
#define RESET_VECTOR            ".reset"                    /* 0xFFFE Reset [Highest Priority] */
4927 
#else
4928 
#define RESET_VECTOR            (63 * 1u)                    /* 0xFFFE Reset [Highest Priority] */
4929 
/*#define RESET_ISR(func)         ISR_VECTOR(func, ".int63")  */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
4930 
#endif
4931 
 
4932 
/************************************************************
4933 
* End of Modules
4934 
************************************************************/
4935 
 
4936 
#ifdef __cplusplus
4937 
}
4938 
#endif /* extern "C" */
4939 
 
4940 
#endif /* #ifndef __MSP430F5632 */
4941