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dpurdie |
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* MSP430F5131 device.
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*
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* Texas Instruments, Version 1.2
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*
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* Rev. 1.0, Setup
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* Rev. 1.1 Changed access type of TimerA/D registers to word only
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* Rev. 1.2 Fixed PortMapper Definitons
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*
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*
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********************************************************************/
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#ifndef __MSP430F5131
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#define __MSP430F5131
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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//#define SFR_20BIT(address) extern volatile unsigned int address
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typedef void (* __SFR_FARPTR)();
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#define SFR_20BIT(address) extern __SFR_FARPTR address
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#define SFR_32BIT(address) extern volatile unsigned long address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* CPU
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************************************************************/
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#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* Comparator B
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************************************************************/
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#define __MSP430_HAS_COMPB__ /* Definition to show that Module is available */
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#define __MSP430_BASEADDRESS_COMPB__ 0x08C0
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SFR_16BIT(CBCTL0); /* Comparator B Control Register 0 */
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SFR_8BIT(CBCTL0_L); /* Comparator B Control Register 0 */
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SFR_8BIT(CBCTL0_H); /* Comparator B Control Register 0 */
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SFR_16BIT(CBCTL1); /* Comparator B Control Register 1 */
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SFR_8BIT(CBCTL1_L); /* Comparator B Control Register 1 */
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SFR_8BIT(CBCTL1_H); /* Comparator B Control Register 1 */
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SFR_16BIT(CBCTL2); /* Comparator B Control Register 2 */
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SFR_8BIT(CBCTL2_L); /* Comparator B Control Register 2 */
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SFR_8BIT(CBCTL2_H); /* Comparator B Control Register 2 */
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SFR_16BIT(CBCTL3); /* Comparator B Control Register 3 */
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SFR_8BIT(CBCTL3_L); /* Comparator B Control Register 3 */
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SFR_8BIT(CBCTL3_H); /* Comparator B Control Register 3 */
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SFR_16BIT(CBINT); /* Comparator B Interrupt Register */
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SFR_8BIT(CBINT_L); /* Comparator B Interrupt Register */
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SFR_8BIT(CBINT_H); /* Comparator B Interrupt Register */
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SFR_16BIT(CBIV); /* Comparator B Interrupt Vector Word */
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/* CBCTL0 Control Bits */
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#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */
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#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */
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#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */
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#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */
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//#define RESERVED (0x0010) /* Comp. B */
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//#define RESERVED (0x0020) /* Comp. B */
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//#define RESERVED (0x0040) /* Comp. B */
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#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */
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#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */
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#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */
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#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */
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#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */
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//#define RESERVED (0x1000) /* Comp. B */
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//#define RESERVED (0x2000) /* Comp. B */
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//#define RESERVED (0x4000) /* Comp. B */
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#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */
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/* CBCTL0 Control Bits */
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#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */
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#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */
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#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */
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#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */
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//#define RESERVED (0x0010) /* Comp. B */
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//#define RESERVED (0x0020) /* Comp. B */
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//#define RESERVED (0x0040) /* Comp. B */
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#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */
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//#define RESERVED (0x1000) /* Comp. B */
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//#define RESERVED (0x2000) /* Comp. B */
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//#define RESERVED (0x4000) /* Comp. B */
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/* CBCTL0 Control Bits */
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//#define RESERVED (0x0010) /* Comp. B */
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//#define RESERVED (0x0020) /* Comp. B */
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//#define RESERVED (0x0040) /* Comp. B */
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#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */
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#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */
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#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */
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#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */
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//#define RESERVED (0x1000) /* Comp. B */
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//#define RESERVED (0x2000) /* Comp. B */
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//#define RESERVED (0x4000) /* Comp. B */
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#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */
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#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */
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#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */
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#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */
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#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */
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#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */
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#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */
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#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */
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#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */
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#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */
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#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */
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#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */
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#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */
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#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */
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#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */
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#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */
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#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */
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#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */
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#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */
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#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */
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#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */
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#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */
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#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */
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#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */
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#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */
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#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */
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#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */
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#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */
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#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */
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#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */
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#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */
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#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */
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#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */
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/* CBCTL1 Control Bits */
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#define CBOUT (0x0001) /* Comp. B Output */
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#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */
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#define CBF (0x0004) /* Comp. B Enable Output Filter */
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#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */
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#define CBSHORT (0x0010) /* Comp. B Input Short */
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#define CBEX (0x0020) /* Comp. B Exchange Inputs */
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#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */
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#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */
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#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */
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#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */
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#define CBON (0x0400) /* Comp. B enable */
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#define CBMRVL (0x0800) /* Comp. B CBMRV Level */
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#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/
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//#define RESERVED (0x2000) /* Comp. B */
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//#define RESERVED (0x4000) /* Comp. B */
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//#define RESERVED (0x8000) /* Comp. B */
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/* CBCTL1 Control Bits */
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#define CBOUT_L (0x0001) /* Comp. B Output */
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#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */
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#define CBF_L (0x0004) /* Comp. B Enable Output Filter */
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#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */
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#define CBSHORT_L (0x0010) /* Comp. B Input Short */
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#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */
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#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */
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#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */
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//#define RESERVED (0x2000) /* Comp. B */
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//#define RESERVED (0x4000) /* Comp. B */
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//#define RESERVED (0x8000) /* Comp. B */
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/* CBCTL1 Control Bits */
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#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */
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#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */
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#define CBON_H (0x0004) /* Comp. B enable */
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#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */
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#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/
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//#define RESERVED (0x2000) /* Comp. B */
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//#define RESERVED (0x4000) /* Comp. B */
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//#define RESERVED (0x8000) /* Comp. B */
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#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */
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#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */
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#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */
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#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */
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#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */
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#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */
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#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/
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#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */
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/* CBCTL2 Control Bits */
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#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
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#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
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#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
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#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
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#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
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#define CBRSEL (0x0020) /* Comp. B Reference select */
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#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */
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#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */
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#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */
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277 |
#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */
|
|
|
278 |
#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */
|
|
|
279 |
#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */
|
|
|
280 |
#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */
|
|
|
281 |
#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */
|
|
|
282 |
#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */
|
|
|
283 |
#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */
|
|
|
284 |
|
|
|
285 |
/* CBCTL2 Control Bits */
|
|
|
286 |
#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
|
|
|
287 |
#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
|
|
|
288 |
#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
|
|
|
289 |
#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
|
|
|
290 |
#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
|
|
|
291 |
#define CBRSEL_L (0x0020) /* Comp. B Reference select */
|
|
|
292 |
#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */
|
|
|
293 |
#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */
|
|
|
294 |
|
|
|
295 |
/* CBCTL2 Control Bits */
|
|
|
296 |
#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */
|
|
|
297 |
#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */
|
|
|
298 |
#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */
|
|
|
299 |
#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */
|
|
|
300 |
#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */
|
|
|
301 |
#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */
|
|
|
302 |
#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */
|
|
|
303 |
#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */
|
|
|
304 |
|
|
|
305 |
#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */
|
|
|
306 |
#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */
|
|
|
307 |
#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */
|
|
|
308 |
#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */
|
|
|
309 |
#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */
|
|
|
310 |
#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */
|
|
|
311 |
#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */
|
|
|
312 |
#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */
|
|
|
313 |
#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */
|
|
|
314 |
#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */
|
|
|
315 |
#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */
|
|
|
316 |
#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */
|
|
|
317 |
#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */
|
|
|
318 |
#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */
|
|
|
319 |
#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */
|
|
|
320 |
#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */
|
|
|
321 |
#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */
|
|
|
322 |
#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */
|
|
|
323 |
#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */
|
|
|
324 |
#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */
|
|
|
325 |
#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */
|
|
|
326 |
#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */
|
|
|
327 |
#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */
|
|
|
328 |
#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */
|
|
|
329 |
#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */
|
|
|
330 |
#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */
|
|
|
331 |
#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */
|
|
|
332 |
#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */
|
|
|
333 |
#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */
|
|
|
334 |
#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */
|
|
|
335 |
#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */
|
|
|
336 |
#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */
|
|
|
337 |
|
|
|
338 |
#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */
|
|
|
339 |
#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */
|
|
|
340 |
#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */
|
|
|
341 |
#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */
|
|
|
342 |
|
|
|
343 |
#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */
|
|
|
344 |
#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */
|
|
|
345 |
#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */
|
|
|
346 |
#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */
|
|
|
347 |
#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */
|
|
|
348 |
#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */
|
|
|
349 |
#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */
|
|
|
350 |
#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */
|
|
|
351 |
#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */
|
|
|
352 |
#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */
|
|
|
353 |
#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */
|
|
|
354 |
#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */
|
|
|
355 |
#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */
|
|
|
356 |
#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */
|
|
|
357 |
#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */
|
|
|
358 |
#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */
|
|
|
359 |
#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */
|
|
|
360 |
#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */
|
|
|
361 |
#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */
|
|
|
362 |
#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */
|
|
|
363 |
#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */
|
|
|
364 |
#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */
|
|
|
365 |
#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */
|
|
|
366 |
#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */
|
|
|
367 |
#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */
|
|
|
368 |
#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */
|
|
|
369 |
#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */
|
|
|
370 |
#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */
|
|
|
371 |
#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */
|
|
|
372 |
#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */
|
|
|
373 |
#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */
|
|
|
374 |
#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */
|
|
|
375 |
|
|
|
376 |
#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */
|
|
|
377 |
#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */
|
|
|
378 |
#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */
|
|
|
379 |
#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */
|
|
|
380 |
|
|
|
381 |
#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
|
|
|
382 |
#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
|
|
|
383 |
#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
|
|
|
384 |
#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
|
|
|
385 |
#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
|
|
|
386 |
#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
|
|
|
387 |
#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
|
|
|
388 |
#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
|
|
|
389 |
#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */
|
|
|
390 |
#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */
|
|
|
391 |
#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */
|
|
|
392 |
#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */
|
|
|
393 |
#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */
|
|
|
394 |
#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */
|
|
|
395 |
#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */
|
|
|
396 |
#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */
|
|
|
397 |
|
|
|
398 |
#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
|
|
|
399 |
#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
|
|
|
400 |
#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
|
|
|
401 |
#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
|
|
|
402 |
#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
|
|
|
403 |
#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
|
|
|
404 |
#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
|
|
|
405 |
#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
|
|
|
406 |
|
|
|
407 |
#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */
|
|
|
408 |
#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */
|
|
|
409 |
#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */
|
|
|
410 |
#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */
|
|
|
411 |
#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */
|
|
|
412 |
#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */
|
|
|
413 |
#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */
|
|
|
414 |
#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */
|
|
|
415 |
|
|
|
416 |
/* CBINT Control Bits */
|
|
|
417 |
#define CBIFG (0x0001) /* Comp. B Interrupt Flag */
|
|
|
418 |
#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
|
|
|
419 |
//#define RESERVED (0x0004) /* Comp. B */
|
|
|
420 |
//#define RESERVED (0x0008) /* Comp. B */
|
|
|
421 |
//#define RESERVED (0x0010) /* Comp. B */
|
|
|
422 |
//#define RESERVED (0x0020) /* Comp. B */
|
|
|
423 |
//#define RESERVED (0x0040) /* Comp. B */
|
|
|
424 |
//#define RESERVED (0x0080) /* Comp. B */
|
|
|
425 |
#define CBIE (0x0100) /* Comp. B Interrupt Enable */
|
|
|
426 |
#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */
|
|
|
427 |
//#define RESERVED (0x0400) /* Comp. B */
|
|
|
428 |
//#define RESERVED (0x0800) /* Comp. B */
|
|
|
429 |
//#define RESERVED (0x1000) /* Comp. B */
|
|
|
430 |
//#define RESERVED (0x2000) /* Comp. B */
|
|
|
431 |
//#define RESERVED (0x4000) /* Comp. B */
|
|
|
432 |
//#define RESERVED (0x8000) /* Comp. B */
|
|
|
433 |
|
|
|
434 |
/* CBINT Control Bits */
|
|
|
435 |
#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */
|
|
|
436 |
#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
|
|
|
437 |
//#define RESERVED (0x0004) /* Comp. B */
|
|
|
438 |
//#define RESERVED (0x0008) /* Comp. B */
|
|
|
439 |
//#define RESERVED (0x0010) /* Comp. B */
|
|
|
440 |
//#define RESERVED (0x0020) /* Comp. B */
|
|
|
441 |
//#define RESERVED (0x0040) /* Comp. B */
|
|
|
442 |
//#define RESERVED (0x0080) /* Comp. B */
|
|
|
443 |
//#define RESERVED (0x0400) /* Comp. B */
|
|
|
444 |
//#define RESERVED (0x0800) /* Comp. B */
|
|
|
445 |
//#define RESERVED (0x1000) /* Comp. B */
|
|
|
446 |
//#define RESERVED (0x2000) /* Comp. B */
|
|
|
447 |
//#define RESERVED (0x4000) /* Comp. B */
|
|
|
448 |
//#define RESERVED (0x8000) /* Comp. B */
|
|
|
449 |
|
|
|
450 |
/* CBINT Control Bits */
|
|
|
451 |
//#define RESERVED (0x0004) /* Comp. B */
|
|
|
452 |
//#define RESERVED (0x0008) /* Comp. B */
|
|
|
453 |
//#define RESERVED (0x0010) /* Comp. B */
|
|
|
454 |
//#define RESERVED (0x0020) /* Comp. B */
|
|
|
455 |
//#define RESERVED (0x0040) /* Comp. B */
|
|
|
456 |
//#define RESERVED (0x0080) /* Comp. B */
|
|
|
457 |
#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */
|
|
|
458 |
#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */
|
|
|
459 |
//#define RESERVED (0x0400) /* Comp. B */
|
|
|
460 |
//#define RESERVED (0x0800) /* Comp. B */
|
|
|
461 |
//#define RESERVED (0x1000) /* Comp. B */
|
|
|
462 |
//#define RESERVED (0x2000) /* Comp. B */
|
|
|
463 |
//#define RESERVED (0x4000) /* Comp. B */
|
|
|
464 |
//#define RESERVED (0x8000) /* Comp. B */
|
|
|
465 |
|
|
|
466 |
/* CBIV Definitions */
|
|
|
467 |
#define CBIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
468 |
#define CBIV_CBIFG (0x0002) /* CBIFG */
|
|
|
469 |
#define CBIV_CBIIFG (0x0004) /* CBIIFG */
|
|
|
470 |
|
|
|
471 |
/*************************************************************
|
|
|
472 |
* CRC Module
|
|
|
473 |
*************************************************************/
|
|
|
474 |
#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */
|
|
|
475 |
#define __MSP430_BASEADDRESS_CRC__ 0x0150
|
|
|
476 |
|
|
|
477 |
SFR_16BIT(CRCDI); /* CRC Data In Register */
|
|
|
478 |
SFR_8BIT(CRCDI_L); /* CRC Data In Register */
|
|
|
479 |
SFR_8BIT(CRCDI_H); /* CRC Data In Register */
|
|
|
480 |
SFR_16BIT(CRCDIRB); /* CRC data in reverse byte Register */
|
|
|
481 |
SFR_8BIT(CRCDIRB_L); /* CRC data in reverse byte Register */
|
|
|
482 |
SFR_8BIT(CRCDIRB_H); /* CRC data in reverse byte Register */
|
|
|
483 |
SFR_16BIT(CRCINIRES); /* CRC Initialisation Register and Result Register */
|
|
|
484 |
SFR_8BIT(CRCINIRES_L); /* CRC Initialisation Register and Result Register */
|
|
|
485 |
SFR_8BIT(CRCINIRES_H); /* CRC Initialisation Register and Result Register */
|
|
|
486 |
SFR_16BIT(CRCRESR); /* CRC reverse result Register */
|
|
|
487 |
SFR_8BIT(CRCRESR_L); /* CRC reverse result Register */
|
|
|
488 |
SFR_8BIT(CRCRESR_H); /* CRC reverse result Register */
|
|
|
489 |
|
|
|
490 |
/************************************************************
|
|
|
491 |
* DMA_X
|
|
|
492 |
************************************************************/
|
|
|
493 |
#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
|
|
|
494 |
#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500
|
|
|
495 |
|
|
|
496 |
SFR_16BIT(DMACTL0); /* DMA Module Control 0 */
|
|
|
497 |
SFR_8BIT(DMACTL0_L); /* DMA Module Control 0 */
|
|
|
498 |
SFR_8BIT(DMACTL0_H); /* DMA Module Control 0 */
|
|
|
499 |
SFR_16BIT(DMACTL1); /* DMA Module Control 1 */
|
|
|
500 |
SFR_8BIT(DMACTL1_L); /* DMA Module Control 1 */
|
|
|
501 |
SFR_8BIT(DMACTL1_H); /* DMA Module Control 1 */
|
|
|
502 |
SFR_16BIT(DMACTL2); /* DMA Module Control 2 */
|
|
|
503 |
SFR_8BIT(DMACTL2_L); /* DMA Module Control 2 */
|
|
|
504 |
SFR_8BIT(DMACTL2_H); /* DMA Module Control 2 */
|
|
|
505 |
SFR_16BIT(DMACTL3); /* DMA Module Control 3 */
|
|
|
506 |
SFR_8BIT(DMACTL3_L); /* DMA Module Control 3 */
|
|
|
507 |
SFR_8BIT(DMACTL3_H); /* DMA Module Control 3 */
|
|
|
508 |
SFR_16BIT(DMACTL4); /* DMA Module Control 4 */
|
|
|
509 |
SFR_8BIT(DMACTL4_L); /* DMA Module Control 4 */
|
|
|
510 |
SFR_8BIT(DMACTL4_H); /* DMA Module Control 4 */
|
|
|
511 |
SFR_16BIT(DMAIV); /* DMA Interrupt Vector Word */
|
|
|
512 |
SFR_8BIT(DMAIV_L); /* DMA Interrupt Vector Word */
|
|
|
513 |
SFR_8BIT(DMAIV_H); /* DMA Interrupt Vector Word */
|
|
|
514 |
|
|
|
515 |
SFR_16BIT(DMA0CTL); /* DMA Channel 0 Control */
|
|
|
516 |
SFR_8BIT(DMA0CTL_L); /* DMA Channel 0 Control */
|
|
|
517 |
SFR_8BIT(DMA0CTL_H); /* DMA Channel 0 Control */
|
|
|
518 |
SFR_20BIT(DMA0SA); /* DMA Channel 0 Source Address */
|
|
|
519 |
SFR_16BIT(DMA0SAL); /* DMA Channel 0 Source Address */
|
|
|
520 |
SFR_20BIT(DMA0DA); /* DMA Channel 0 Destination Address */
|
|
|
521 |
SFR_16BIT(DMA0DAL); /* DMA Channel 0 Destination Address */
|
|
|
522 |
SFR_16BIT(DMA0SZ); /* DMA Channel 0 Transfer Size */
|
|
|
523 |
|
|
|
524 |
SFR_16BIT(DMA1CTL); /* DMA Channel 1 Control */
|
|
|
525 |
SFR_8BIT(DMA1CTL_L); /* DMA Channel 1 Control */
|
|
|
526 |
SFR_8BIT(DMA1CTL_H); /* DMA Channel 1 Control */
|
|
|
527 |
SFR_20BIT(DMA1SA); /* DMA Channel 1 Source Address */
|
|
|
528 |
SFR_16BIT(DMA1SAL); /* DMA Channel 1 Source Address */
|
|
|
529 |
SFR_20BIT(DMA1DA); /* DMA Channel 1 Destination Address */
|
|
|
530 |
SFR_16BIT(DMA1DAL); /* DMA Channel 1 Destination Address */
|
|
|
531 |
SFR_16BIT(DMA1SZ); /* DMA Channel 1 Transfer Size */
|
|
|
532 |
|
|
|
533 |
SFR_16BIT(DMA2CTL); /* DMA Channel 2 Control */
|
|
|
534 |
SFR_8BIT(DMA2CTL_L); /* DMA Channel 2 Control */
|
|
|
535 |
SFR_8BIT(DMA2CTL_H); /* DMA Channel 2 Control */
|
|
|
536 |
SFR_20BIT(DMA2SA); /* DMA Channel 2 Source Address */
|
|
|
537 |
SFR_16BIT(DMA2SAL); /* DMA Channel 2 Source Address */
|
|
|
538 |
SFR_20BIT(DMA2DA); /* DMA Channel 2 Destination Address */
|
|
|
539 |
SFR_16BIT(DMA2DAL); /* DMA Channel 2 Destination Address */
|
|
|
540 |
SFR_16BIT(DMA2SZ); /* DMA Channel 2 Transfer Size */
|
|
|
541 |
|
|
|
542 |
/* DMACTL0 Control Bits */
|
|
|
543 |
#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
|
|
|
544 |
#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
|
|
|
545 |
#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
|
|
|
546 |
#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
|
|
|
547 |
#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
|
|
|
548 |
#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
|
|
|
549 |
#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
|
|
|
550 |
#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
|
|
|
551 |
#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
|
|
|
552 |
#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
|
|
|
553 |
|
|
|
554 |
/* DMACTL0 Control Bits */
|
|
|
555 |
#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
|
|
|
556 |
#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
|
|
|
557 |
#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
|
|
|
558 |
#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
|
|
|
559 |
#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
|
|
|
560 |
|
|
|
561 |
/* DMACTL0 Control Bits */
|
|
|
562 |
#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
|
|
|
563 |
#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
|
|
|
564 |
#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
|
|
|
565 |
#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
|
|
|
566 |
#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
|
|
|
567 |
|
|
|
568 |
/* DMACTL01 Control Bits */
|
|
|
569 |
#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
|
|
|
570 |
#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
|
|
|
571 |
#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
|
|
|
572 |
#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
|
|
|
573 |
#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
|
|
|
574 |
|
|
|
575 |
/* DMACTL01 Control Bits */
|
|
|
576 |
#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
|
|
|
577 |
#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
|
|
|
578 |
#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
|
|
|
579 |
#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
|
|
|
580 |
#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
|
|
|
581 |
|
|
|
582 |
/* DMACTL01 Control Bits */
|
|
|
583 |
|
|
|
584 |
/* DMACTL4 Control Bits */
|
|
|
585 |
#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
|
|
|
586 |
#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
|
|
|
587 |
#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
|
|
|
588 |
|
|
|
589 |
/* DMACTL4 Control Bits */
|
|
|
590 |
#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
|
|
|
591 |
#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
|
|
|
592 |
#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
|
|
|
593 |
|
|
|
594 |
/* DMACTL4 Control Bits */
|
|
|
595 |
|
|
|
596 |
/* DMAxCTL Control Bits */
|
|
|
597 |
#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
|
|
|
598 |
#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
|
|
|
599 |
#define DMAIE (0x0004) /* DMA interrupt enable */
|
|
|
600 |
#define DMAIFG (0x0008) /* DMA interrupt flag */
|
|
|
601 |
#define DMAEN (0x0010) /* DMA enable */
|
|
|
602 |
#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
|
|
|
603 |
#define DMASRCBYTE (0x0040) /* DMA source byte */
|
|
|
604 |
#define DMADSTBYTE (0x0080) /* DMA destination byte */
|
|
|
605 |
#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
|
|
|
606 |
#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
|
|
|
607 |
#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
|
|
|
608 |
#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
|
|
|
609 |
#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
|
|
|
610 |
#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
|
|
|
611 |
#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
|
|
|
612 |
|
|
|
613 |
/* DMAxCTL Control Bits */
|
|
|
614 |
#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
|
|
|
615 |
#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
|
|
|
616 |
#define DMAIE_L (0x0004) /* DMA interrupt enable */
|
|
|
617 |
#define DMAIFG_L (0x0008) /* DMA interrupt flag */
|
|
|
618 |
#define DMAEN_L (0x0010) /* DMA enable */
|
|
|
619 |
#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
|
|
|
620 |
#define DMASRCBYTE_L (0x0040) /* DMA source byte */
|
|
|
621 |
#define DMADSTBYTE_L (0x0080) /* DMA destination byte */
|
|
|
622 |
|
|
|
623 |
/* DMAxCTL Control Bits */
|
|
|
624 |
#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
|
|
|
625 |
#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
|
|
|
626 |
#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
|
|
|
627 |
#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
|
|
|
628 |
#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
|
|
|
629 |
#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
|
|
|
630 |
#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
|
|
|
631 |
|
|
|
632 |
#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
|
|
|
633 |
#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
|
|
|
634 |
#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
|
|
|
635 |
#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
|
|
|
636 |
|
|
|
637 |
#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
|
|
|
638 |
#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
|
|
|
639 |
#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
|
|
|
640 |
#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
|
|
|
641 |
|
|
|
642 |
#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
|
|
|
643 |
#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
|
|
|
644 |
#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
|
|
|
645 |
#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
|
|
|
646 |
|
|
|
647 |
#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
|
|
|
648 |
#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
|
|
|
649 |
#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
|
|
|
650 |
#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
|
|
|
651 |
#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
|
|
|
652 |
#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
|
|
|
653 |
#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
|
|
|
654 |
#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
|
|
|
655 |
|
|
|
656 |
/* DMAIV Definitions */
|
|
|
657 |
#define DMAIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
658 |
#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
|
|
|
659 |
#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
|
|
|
660 |
#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
|
|
|
661 |
|
|
|
662 |
#define DMA0TSEL_0 (0*0x0001u) /* DMA channel 0 transfer select 0 */
|
|
|
663 |
#define DMA0TSEL_1 (1*0x0001u) /* DMA channel 0 transfer select 1 */
|
|
|
664 |
#define DMA0TSEL_2 (2*0x0001u) /* DMA channel 0 transfer select 2 */
|
|
|
665 |
#define DMA0TSEL_3 (3*0x0001u) /* DMA channel 0 transfer select 3 */
|
|
|
666 |
#define DMA0TSEL_4 (4*0x0001u) /* DMA channel 0 transfer select 4 */
|
|
|
667 |
#define DMA0TSEL_5 (5*0x0001u) /* DMA channel 0 transfer select 5 */
|
|
|
668 |
#define DMA0TSEL_6 (6*0x0001u) /* DMA channel 0 transfer select 6 */
|
|
|
669 |
#define DMA0TSEL_7 (7*0x0001u) /* DMA channel 0 transfer select 7 */
|
|
|
670 |
#define DMA0TSEL_8 (8*0x0001u) /* DMA channel 0 transfer select 8 */
|
|
|
671 |
#define DMA0TSEL_9 (9*0x0001u) /* DMA channel 0 transfer select 9 */
|
|
|
672 |
#define DMA0TSEL_10 (10*0x0001u) /* DMA channel 0 transfer select 10 */
|
|
|
673 |
#define DMA0TSEL_11 (11*0x0001u) /* DMA channel 0 transfer select 11 */
|
|
|
674 |
#define DMA0TSEL_12 (12*0x0001u) /* DMA channel 0 transfer select 12 */
|
|
|
675 |
#define DMA0TSEL_13 (13*0x0001u) /* DMA channel 0 transfer select 13 */
|
|
|
676 |
#define DMA0TSEL_14 (14*0x0001u) /* DMA channel 0 transfer select 14 */
|
|
|
677 |
#define DMA0TSEL_15 (15*0x0001u) /* DMA channel 0 transfer select 15 */
|
|
|
678 |
#define DMA0TSEL_16 (16*0x0001u) /* DMA channel 0 transfer select 16 */
|
|
|
679 |
#define DMA0TSEL_17 (17*0x0001u) /* DMA channel 0 transfer select 17 */
|
|
|
680 |
#define DMA0TSEL_18 (18*0x0001u) /* DMA channel 0 transfer select 18 */
|
|
|
681 |
#define DMA0TSEL_19 (19*0x0001u) /* DMA channel 0 transfer select 19 */
|
|
|
682 |
#define DMA0TSEL_20 (20*0x0001u) /* DMA channel 0 transfer select 20 */
|
|
|
683 |
#define DMA0TSEL_21 (21*0x0001u) /* DMA channel 0 transfer select 21 */
|
|
|
684 |
#define DMA0TSEL_22 (22*0x0001u) /* DMA channel 0 transfer select 22 */
|
|
|
685 |
#define DMA0TSEL_23 (23*0x0001u) /* DMA channel 0 transfer select 23 */
|
|
|
686 |
#define DMA0TSEL_24 (24*0x0001u) /* DMA channel 0 transfer select 24 */
|
|
|
687 |
#define DMA0TSEL_25 (25*0x0001u) /* DMA channel 0 transfer select 25 */
|
|
|
688 |
#define DMA0TSEL_26 (26*0x0001u) /* DMA channel 0 transfer select 26 */
|
|
|
689 |
#define DMA0TSEL_27 (27*0x0001u) /* DMA channel 0 transfer select 27 */
|
|
|
690 |
#define DMA0TSEL_28 (28*0x0001u) /* DMA channel 0 transfer select 28 */
|
|
|
691 |
#define DMA0TSEL_29 (29*0x0001u) /* DMA channel 0 transfer select 29 */
|
|
|
692 |
#define DMA0TSEL_30 (30*0x0001u) /* DMA channel 0 transfer select 30 */
|
|
|
693 |
#define DMA0TSEL_31 (31*0x0001u) /* DMA channel 0 transfer select 31 */
|
|
|
694 |
|
|
|
695 |
#define DMA1TSEL_0 (0*0x0100u) /* DMA channel 1 transfer select 0 */
|
|
|
696 |
#define DMA1TSEL_1 (1*0x0100u) /* DMA channel 1 transfer select 1 */
|
|
|
697 |
#define DMA1TSEL_2 (2*0x0100u) /* DMA channel 1 transfer select 2 */
|
|
|
698 |
#define DMA1TSEL_3 (3*0x0100u) /* DMA channel 1 transfer select 3 */
|
|
|
699 |
#define DMA1TSEL_4 (4*0x0100u) /* DMA channel 1 transfer select 4 */
|
|
|
700 |
#define DMA1TSEL_5 (5*0x0100u) /* DMA channel 1 transfer select 5 */
|
|
|
701 |
#define DMA1TSEL_6 (6*0x0100u) /* DMA channel 1 transfer select 6 */
|
|
|
702 |
#define DMA1TSEL_7 (7*0x0100u) /* DMA channel 1 transfer select 7 */
|
|
|
703 |
#define DMA1TSEL_8 (8*0x0100u) /* DMA channel 1 transfer select 8 */
|
|
|
704 |
#define DMA1TSEL_9 (9*0x0100u) /* DMA channel 1 transfer select 9 */
|
|
|
705 |
#define DMA1TSEL_10 (10*0x0100u) /* DMA channel 1 transfer select 10 */
|
|
|
706 |
#define DMA1TSEL_11 (11*0x0100u) /* DMA channel 1 transfer select 11 */
|
|
|
707 |
#define DMA1TSEL_12 (12*0x0100u) /* DMA channel 1 transfer select 12 */
|
|
|
708 |
#define DMA1TSEL_13 (13*0x0100u) /* DMA channel 1 transfer select 13 */
|
|
|
709 |
#define DMA1TSEL_14 (14*0x0100u) /* DMA channel 1 transfer select 14 */
|
|
|
710 |
#define DMA1TSEL_15 (15*0x0100u) /* DMA channel 1 transfer select 15 */
|
|
|
711 |
#define DMA1TSEL_16 (16*0x0100u) /* DMA channel 1 transfer select 16 */
|
|
|
712 |
#define DMA1TSEL_17 (17*0x0100u) /* DMA channel 1 transfer select 17 */
|
|
|
713 |
#define DMA1TSEL_18 (18*0x0100u) /* DMA channel 1 transfer select 18 */
|
|
|
714 |
#define DMA1TSEL_19 (19*0x0100u) /* DMA channel 1 transfer select 19 */
|
|
|
715 |
#define DMA1TSEL_20 (20*0x0100u) /* DMA channel 1 transfer select 20 */
|
|
|
716 |
#define DMA1TSEL_21 (21*0x0100u) /* DMA channel 1 transfer select 21 */
|
|
|
717 |
#define DMA1TSEL_22 (22*0x0100u) /* DMA channel 1 transfer select 22 */
|
|
|
718 |
#define DMA1TSEL_23 (23*0x0100u) /* DMA channel 1 transfer select 23 */
|
|
|
719 |
#define DMA1TSEL_24 (24*0x0100u) /* DMA channel 1 transfer select 24 */
|
|
|
720 |
#define DMA1TSEL_25 (25*0x0100u) /* DMA channel 1 transfer select 25 */
|
|
|
721 |
#define DMA1TSEL_26 (26*0x0100u) /* DMA channel 1 transfer select 26 */
|
|
|
722 |
#define DMA1TSEL_27 (27*0x0100u) /* DMA channel 1 transfer select 27 */
|
|
|
723 |
#define DMA1TSEL_28 (28*0x0100u) /* DMA channel 1 transfer select 28 */
|
|
|
724 |
#define DMA1TSEL_29 (29*0x0100u) /* DMA channel 1 transfer select 29 */
|
|
|
725 |
#define DMA1TSEL_30 (30*0x0100u) /* DMA channel 1 transfer select 30 */
|
|
|
726 |
#define DMA1TSEL_31 (31*0x0100u) /* DMA channel 1 transfer select 31 */
|
|
|
727 |
|
|
|
728 |
#define DMA2TSEL_0 (0*0x0001u) /* DMA channel 2 transfer select 0 */
|
|
|
729 |
#define DMA2TSEL_1 (1*0x0001u) /* DMA channel 2 transfer select 1 */
|
|
|
730 |
#define DMA2TSEL_2 (2*0x0001u) /* DMA channel 2 transfer select 2 */
|
|
|
731 |
#define DMA2TSEL_3 (3*0x0001u) /* DMA channel 2 transfer select 3 */
|
|
|
732 |
#define DMA2TSEL_4 (4*0x0001u) /* DMA channel 2 transfer select 4 */
|
|
|
733 |
#define DMA2TSEL_5 (5*0x0001u) /* DMA channel 2 transfer select 5 */
|
|
|
734 |
#define DMA2TSEL_6 (6*0x0001u) /* DMA channel 2 transfer select 6 */
|
|
|
735 |
#define DMA2TSEL_7 (7*0x0001u) /* DMA channel 2 transfer select 7 */
|
|
|
736 |
#define DMA2TSEL_8 (8*0x0001u) /* DMA channel 2 transfer select 8 */
|
|
|
737 |
#define DMA2TSEL_9 (9*0x0001u) /* DMA channel 2 transfer select 9 */
|
|
|
738 |
#define DMA2TSEL_10 (10*0x0001u) /* DMA channel 2 transfer select 10 */
|
|
|
739 |
#define DMA2TSEL_11 (11*0x0001u) /* DMA channel 2 transfer select 11 */
|
|
|
740 |
#define DMA2TSEL_12 (12*0x0001u) /* DMA channel 2 transfer select 12 */
|
|
|
741 |
#define DMA2TSEL_13 (13*0x0001u) /* DMA channel 2 transfer select 13 */
|
|
|
742 |
#define DMA2TSEL_14 (14*0x0001u) /* DMA channel 2 transfer select 14 */
|
|
|
743 |
#define DMA2TSEL_15 (15*0x0001u) /* DMA channel 2 transfer select 15 */
|
|
|
744 |
#define DMA2TSEL_16 (16*0x0001u) /* DMA channel 2 transfer select 16 */
|
|
|
745 |
#define DMA2TSEL_17 (17*0x0001u) /* DMA channel 2 transfer select 17 */
|
|
|
746 |
#define DMA2TSEL_18 (18*0x0001u) /* DMA channel 2 transfer select 18 */
|
|
|
747 |
#define DMA2TSEL_19 (19*0x0001u) /* DMA channel 2 transfer select 19 */
|
|
|
748 |
#define DMA2TSEL_20 (20*0x0001u) /* DMA channel 2 transfer select 20 */
|
|
|
749 |
#define DMA2TSEL_21 (21*0x0001u) /* DMA channel 2 transfer select 21 */
|
|
|
750 |
#define DMA2TSEL_22 (22*0x0001u) /* DMA channel 2 transfer select 22 */
|
|
|
751 |
#define DMA2TSEL_23 (23*0x0001u) /* DMA channel 2 transfer select 23 */
|
|
|
752 |
#define DMA2TSEL_24 (24*0x0001u) /* DMA channel 2 transfer select 24 */
|
|
|
753 |
#define DMA2TSEL_25 (25*0x0001u) /* DMA channel 2 transfer select 25 */
|
|
|
754 |
#define DMA2TSEL_26 (26*0x0001u) /* DMA channel 2 transfer select 26 */
|
|
|
755 |
#define DMA2TSEL_27 (27*0x0001u) /* DMA channel 2 transfer select 27 */
|
|
|
756 |
#define DMA2TSEL_28 (28*0x0001u) /* DMA channel 2 transfer select 28 */
|
|
|
757 |
#define DMA2TSEL_29 (29*0x0001u) /* DMA channel 2 transfer select 29 */
|
|
|
758 |
#define DMA2TSEL_30 (30*0x0001u) /* DMA channel 2 transfer select 30 */
|
|
|
759 |
#define DMA2TSEL_31 (31*0x0001u) /* DMA channel 2 transfer select 31 */
|
|
|
760 |
|
|
|
761 |
#define DMA0TSEL__DMA_REQ (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
|
|
|
762 |
#define DMA0TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */
|
|
|
763 |
#define DMA0TSEL__TA0CCR2 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */
|
|
|
764 |
#define DMA0TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */
|
|
|
765 |
#define DMA0TSEL__TA1CCR2 (4*0x0001u) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */
|
|
|
766 |
#define DMA0TSEL__TB0CCR0 (5*0x0001u) /* DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG) */
|
|
|
767 |
#define DMA0TSEL__TB0CCR2 (6*0x0001u) /* DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG) */
|
|
|
768 |
#define DMA0TSEL__RES7 (7*0x0001u) /* DMA channel 0 transfer select 7: Reserved */
|
|
|
769 |
#define DMA0TSEL__RES8 (8*0x0001u) /* DMA channel 0 transfer select 8: Reserved */
|
|
|
770 |
#define DMA0TSEL__RES9 (9*0x0001u) /* DMA channel 0 transfer select 9: Reserved */
|
|
|
771 |
#define DMA0TSEL__RES10 (10*0x0001u) /* DMA channel 0 transfer select 10: Reserved */
|
|
|
772 |
#define DMA0TSEL__RES11 (11*0x0001u) /* DMA channel 0 transfer select 11: Reserved */
|
|
|
773 |
#define DMA0TSEL__RES12 (12*0x0001u) /* DMA channel 0 transfer select 12: Reserved */
|
|
|
774 |
#define DMA0TSEL__RES13 (13*0x0001u) /* DMA channel 0 transfer select 13: Reserved */
|
|
|
775 |
#define DMA0TSEL__RES14 (14*0x0001u) /* DMA channel 0 transfer select 14: Reserved */
|
|
|
776 |
#define DMA0TSEL__RES15 (15*0x0001u) /* DMA channel 0 transfer select 15: Reserved */
|
|
|
777 |
#define DMA0TSEL__USCIA0RX (16*0x0001u) /* DMA channel 0 transfer select 16: USCIA0 receive */
|
|
|
778 |
#define DMA0TSEL__USCIA0TX (17*0x0001u) /* DMA channel 0 transfer select 17: USCIA0 transmit */
|
|
|
779 |
#define DMA0TSEL__USCIB0RX (18*0x0001u) /* DMA channel 0 transfer select 18: USCIB0 receive */
|
|
|
780 |
#define DMA0TSEL__USCIB0TX (19*0x0001u) /* DMA channel 0 transfer select 19: USCIB0 transmit */
|
|
|
781 |
#define DMA0TSEL__USCIA1RX (20*0x0001u) /* DMA channel 0 transfer select 20: USCIA1 receive */
|
|
|
782 |
#define DMA0TSEL__USCIA1TX (21*0x0001u) /* DMA channel 0 transfer select 21: USCIA1 transmit */
|
|
|
783 |
#define DMA0TSEL__USCIB1RX (22*0x0001u) /* DMA channel 0 transfer select 22: USCIB1 receive */
|
|
|
784 |
#define DMA0TSEL__USCIB1TX (23*0x0001u) /* DMA channel 0 transfer select 23: USCIB1 transmit */
|
|
|
785 |
#define DMA0TSEL__RES24 (24*0x0001u) /* DMA channel 0 transfer select 24: Reserved */
|
|
|
786 |
#define DMA0TSEL__RES25 (25*0x0001u) /* DMA channel 0 transfer select 25: Reserved */
|
|
|
787 |
#define DMA0TSEL__RES26 (26*0x0001u) /* DMA channel 0 transfer select 26: Reserved */
|
|
|
788 |
#define DMA0TSEL__RES27 (27*0x0001u) /* DMA channel 0 transfer select 27: Reserved */
|
|
|
789 |
#define DMA0TSEL__RES28 (28*0x0001u) /* DMA channel 0 transfer select 28: Reserved */
|
|
|
790 |
#define DMA0TSEL__MPY (29*0x0001u) /* DMA channel 0 transfer select 29: Multiplier ready */
|
|
|
791 |
#define DMA0TSEL__DMA2IFG (30*0x0001u) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
|
|
|
792 |
#define DMA0TSEL__DMAE0 (31*0x0001u) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
|
|
|
793 |
|
|
|
794 |
#define DMA1TSEL__DMA_REQ (0*0x0100u) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
|
|
|
795 |
#define DMA1TSEL__TA0CCR0 (1*0x0100u) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */
|
|
|
796 |
#define DMA1TSEL__TA0CCR2 (2*0x0100u) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */
|
|
|
797 |
#define DMA1TSEL__TA1CCR0 (3*0x0100u) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */
|
|
|
798 |
#define DMA1TSEL__TA1CCR2 (4*0x0100u) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */
|
|
|
799 |
#define DMA1TSEL__TB0CCR0 (5*0x0100u) /* DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG) */
|
|
|
800 |
#define DMA1TSEL__TB0CCR2 (6*0x0100u) /* DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG) */
|
|
|
801 |
#define DMA1TSEL__RES7 (7*0x0100u) /* DMA channel 1 transfer select 7: Reserved */
|
|
|
802 |
#define DMA1TSEL__RES8 (8*0x0100u) /* DMA channel 1 transfer select 8: Reserved */
|
|
|
803 |
#define DMA1TSEL__RES9 (9*0x0100u) /* DMA channel 1 transfer select 9: Reserved */
|
|
|
804 |
#define DMA1TSEL__RES10 (10*0x0100u) /* DMA channel 1 transfer select 10: Reserved */
|
|
|
805 |
#define DMA1TSEL__RES11 (11*0x0100u) /* DMA channel 1 transfer select 11: Reserved */
|
|
|
806 |
#define DMA1TSEL__RES12 (12*0x0100u) /* DMA channel 1 transfer select 12: Reserved */
|
|
|
807 |
#define DMA1TSEL__RES13 (13*0x0100u) /* DMA channel 1 transfer select 13: Reserved */
|
|
|
808 |
#define DMA1TSEL__RES14 (14*0x0100u) /* DMA channel 1 transfer select 14: Reserved */
|
|
|
809 |
#define DMA1TSEL__RES15 (15*0x0100u) /* DMA channel 1 transfer select 15: Reserved */
|
|
|
810 |
#define DMA1TSEL__USCIA0RX (16*0x0100u) /* DMA channel 1 transfer select 16: USCIA0 receive */
|
|
|
811 |
#define DMA1TSEL__USCIA0TX (17*0x0100u) /* DMA channel 1 transfer select 17: USCIA0 transmit */
|
|
|
812 |
#define DMA1TSEL__USCIB0RX (18*0x0100u) /* DMA channel 1 transfer select 18: USCIB0 receive */
|
|
|
813 |
#define DMA1TSEL__USCIB0TX (19*0x0100u) /* DMA channel 1 transfer select 19: USCIB0 transmit */
|
|
|
814 |
#define DMA1TSEL__USCIA1RX (20*0x0100u) /* DMA channel 1 transfer select 20: USCIA1 receive */
|
|
|
815 |
#define DMA1TSEL__USCIA1TX (21*0x0100u) /* DMA channel 1 transfer select 21: USCIA1 transmit */
|
|
|
816 |
#define DMA1TSEL__USCIB1RX (22*0x0100u) /* DMA channel 1 transfer select 22: USCIB1 receive */
|
|
|
817 |
#define DMA1TSEL__USCIB1TX (23*0x0100u) /* DMA channel 1 transfer select 23: USCIB1 transmit */
|
|
|
818 |
#define DMA1TSEL__RES24 (24*0x0100u) /* DMA channel 1 transfer select 24: Reserved */
|
|
|
819 |
#define DMA1TSEL__RES25 (25*0x0100u) /* DMA channel 1 transfer select 25: Reserved */
|
|
|
820 |
#define DMA1TSEL__RES26 (26*0x0100u) /* DMA channel 1 transfer select 26: Reserved */
|
|
|
821 |
#define DMA1TSEL__RES27 (27*0x0100u) /* DMA channel 1 transfer select 27: Reserved */
|
|
|
822 |
#define DMA1TSEL__RES28 (28*0x0100u) /* DMA channel 1 transfer select 28: Reserved */
|
|
|
823 |
#define DMA1TSEL__MPY (29*0x0100u) /* DMA channel 1 transfer select 29: Multiplier ready */
|
|
|
824 |
#define DMA1TSEL__DMA0IFG (30*0x0100u) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
|
|
|
825 |
#define DMA1TSEL__DMAE0 (31*0x0100u) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
|
|
|
826 |
|
|
|
827 |
#define DMA2TSEL__DMA_REQ (0*0x0001u) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
|
|
|
828 |
#define DMA2TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */
|
|
|
829 |
#define DMA2TSEL__TA0CCR2 (2*0x0001u) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */
|
|
|
830 |
#define DMA2TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */
|
|
|
831 |
#define DMA2TSEL__TA1CCR2 (4*0x0001u) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */
|
|
|
832 |
#define DMA2TSEL__TB0CCR0 (5*0x0001u) /* DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG) */
|
|
|
833 |
#define DMA2TSEL__TB0CCR2 (6*0x0001u) /* DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG) */
|
|
|
834 |
#define DMA2TSEL__RES7 (7*0x0001u) /* DMA channel 2 transfer select 7: Reserved */
|
|
|
835 |
#define DMA2TSEL__RES8 (8*0x0001u) /* DMA channel 2 transfer select 8: Reserved */
|
|
|
836 |
#define DMA2TSEL__RES9 (9*0x0001u) /* DMA channel 2 transfer select 9: Reserved */
|
|
|
837 |
#define DMA2TSEL__RES10 (10*0x0001u) /* DMA channel 2 transfer select 10: Reserved */
|
|
|
838 |
#define DMA2TSEL__RES11 (11*0x0001u) /* DMA channel 2 transfer select 11: Reserved */
|
|
|
839 |
#define DMA2TSEL__RES12 (12*0x0001u) /* DMA channel 2 transfer select 12: Reserved */
|
|
|
840 |
#define DMA2TSEL__RES13 (13*0x0001u) /* DMA channel 2 transfer select 13: Reserved */
|
|
|
841 |
#define DMA2TSEL__RES14 (14*0x0001u) /* DMA channel 2 transfer select 14: Reserved */
|
|
|
842 |
#define DMA2TSEL__RES15 (15*0x0001u) /* DMA channel 2 transfer select 15: Reserved */
|
|
|
843 |
#define DMA2TSEL__USCIA0RX (16*0x0001u) /* DMA channel 2 transfer select 16: USCIA0 receive */
|
|
|
844 |
#define DMA2TSEL__USCIA0TX (17*0x0001u) /* DMA channel 2 transfer select 17: USCIA0 transmit */
|
|
|
845 |
#define DMA2TSEL__USCIB0RX (18*0x0001u) /* DMA channel 2 transfer select 18: USCIB0 receive */
|
|
|
846 |
#define DMA2TSEL__USCIB0TX (19*0x0001u) /* DMA channel 2 transfer select 19: USCIB0 transmit */
|
|
|
847 |
#define DMA2TSEL__USCIA1RX (20*0x0001u) /* DMA channel 2 transfer select 20: USCIA1 receive */
|
|
|
848 |
#define DMA2TSEL__USCIA1TX (21*0x0001u) /* DMA channel 2 transfer select 21: USCIA1 transmit */
|
|
|
849 |
#define DMA2TSEL__USCIB1RX (22*0x0001u) /* DMA channel 2 transfer select 22: USCIB1 receive */
|
|
|
850 |
#define DMA2TSEL__USCIB1TX (23*0x0001u) /* DMA channel 2 transfer select 23: USCIB1 transmit */
|
|
|
851 |
#define DMA2TSEL__RES24 (24*0x0001u) /* DMA channel 2 transfer select 24: Reserved */
|
|
|
852 |
#define DMA2TSEL__RES25 (25*0x0001u) /* DMA channel 2 transfer select 25: Reserved */
|
|
|
853 |
#define DMA2TSEL__RES26 (26*0x0001u) /* DMA channel 2 transfer select 26: Reserved */
|
|
|
854 |
#define DMA2TSEL__RES27 (27*0x0001u) /* DMA channel 2 transfer select 27: Reserved */
|
|
|
855 |
#define DMA2TSEL__RES28 (28*0x0001u) /* DMA channel 2 transfer select 28: Reserved */
|
|
|
856 |
#define DMA2TSEL__MPY (29*0x0001u) /* DMA channel 2 transfer select 29: Multiplier ready */
|
|
|
857 |
#define DMA2TSEL__DMA1IFG (30*0x0001u) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
|
|
|
858 |
#define DMA2TSEL__DMAE0 (31*0x0001u) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
|
|
|
859 |
|
|
|
860 |
/*************************************************************
|
|
|
861 |
* Flash Memory
|
|
|
862 |
*************************************************************/
|
|
|
863 |
#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
|
|
|
864 |
#define __MSP430_BASEADDRESS_FLASH__ 0x0140
|
|
|
865 |
|
|
|
866 |
SFR_16BIT(FCTL1); /* FLASH Control 1 */
|
|
|
867 |
SFR_8BIT(FCTL1_L); /* FLASH Control 1 */
|
|
|
868 |
SFR_8BIT(FCTL1_H); /* FLASH Control 1 */
|
|
|
869 |
//sfrbw FCTL2 (0x0142) /* FLASH Control 2 */
|
|
|
870 |
SFR_16BIT(FCTL3); /* FLASH Control 3 */
|
|
|
871 |
SFR_8BIT(FCTL3_L); /* FLASH Control 3 */
|
|
|
872 |
SFR_8BIT(FCTL3_H); /* FLASH Control 3 */
|
|
|
873 |
SFR_16BIT(FCTL4); /* FLASH Control 4 */
|
|
|
874 |
SFR_8BIT(FCTL4_L); /* FLASH Control 4 */
|
|
|
875 |
SFR_8BIT(FCTL4_H); /* FLASH Control 4 */
|
|
|
876 |
|
|
|
877 |
#define FRPW (0x9600) /* Flash password returned by read */
|
|
|
878 |
#define FWPW (0xA500) /* Flash password for write */
|
|
|
879 |
#define FXPW (0x3300) /* for use with XOR instruction */
|
|
|
880 |
#define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */
|
|
|
881 |
#define FWKEY (0xA500) /* (legacy definition) Flash key for write */
|
|
|
882 |
#define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */
|
|
|
883 |
|
|
|
884 |
/* FCTL1 Control Bits */
|
|
|
885 |
//#define RESERVED (0x0001) /* Reserved */
|
|
|
886 |
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
|
|
|
887 |
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
|
|
|
888 |
//#define RESERVED (0x0008) /* Reserved */
|
|
|
889 |
//#define RESERVED (0x0010) /* Reserved */
|
|
|
890 |
#define SWRT (0x0020) /* Smart Write enable */
|
|
|
891 |
#define WRT (0x0040) /* Enable bit for Flash write */
|
|
|
892 |
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
|
|
|
893 |
|
|
|
894 |
/* FCTL1 Control Bits */
|
|
|
895 |
//#define RESERVED (0x0001) /* Reserved */
|
|
|
896 |
#define ERASE_L (0x0002) /* Enable bit for Flash segment erase */
|
|
|
897 |
#define MERAS_L (0x0004) /* Enable bit for Flash mass erase */
|
|
|
898 |
//#define RESERVED (0x0008) /* Reserved */
|
|
|
899 |
//#define RESERVED (0x0010) /* Reserved */
|
|
|
900 |
#define SWRT_L (0x0020) /* Smart Write enable */
|
|
|
901 |
#define WRT_L (0x0040) /* Enable bit for Flash write */
|
|
|
902 |
#define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */
|
|
|
903 |
|
|
|
904 |
/* FCTL1 Control Bits */
|
|
|
905 |
//#define RESERVED (0x0001) /* Reserved */
|
|
|
906 |
//#define RESERVED (0x0008) /* Reserved */
|
|
|
907 |
//#define RESERVED (0x0010) /* Reserved */
|
|
|
908 |
|
|
|
909 |
/* FCTL3 Control Bits */
|
|
|
910 |
#define BUSY (0x0001) /* Flash busy: 1 */
|
|
|
911 |
#define KEYV (0x0002) /* Flash Key violation flag */
|
|
|
912 |
#define ACCVIFG (0x0004) /* Flash Access violation flag */
|
|
|
913 |
#define WAIT (0x0008) /* Wait flag for segment write */
|
|
|
914 |
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
915 |
#define EMEX (0x0020) /* Flash Emergency Exit */
|
|
|
916 |
#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
|
|
|
917 |
//#define RESERVED (0x0080) /* Reserved */
|
|
|
918 |
|
|
|
919 |
/* FCTL3 Control Bits */
|
|
|
920 |
#define BUSY_L (0x0001) /* Flash busy: 1 */
|
|
|
921 |
#define KEYV_L (0x0002) /* Flash Key violation flag */
|
|
|
922 |
#define ACCVIFG_L (0x0004) /* Flash Access violation flag */
|
|
|
923 |
#define WAIT_L (0x0008) /* Wait flag for segment write */
|
|
|
924 |
#define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
925 |
#define EMEX_L (0x0020) /* Flash Emergency Exit */
|
|
|
926 |
#define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
|
|
|
927 |
//#define RESERVED (0x0080) /* Reserved */
|
|
|
928 |
|
|
|
929 |
/* FCTL3 Control Bits */
|
|
|
930 |
//#define RESERVED (0x0080) /* Reserved */
|
|
|
931 |
|
|
|
932 |
/* FCTL4 Control Bits */
|
|
|
933 |
#define VPE (0x0001) /* Voltage Changed during Program Error Flag */
|
|
|
934 |
#define MGR0 (0x0010) /* Marginal read 0 mode. */
|
|
|
935 |
#define MGR1 (0x0020) /* Marginal read 1 mode. */
|
|
|
936 |
#define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
|
|
|
937 |
|
|
|
938 |
/* FCTL4 Control Bits */
|
|
|
939 |
#define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */
|
|
|
940 |
#define MGR0_L (0x0010) /* Marginal read 0 mode. */
|
|
|
941 |
#define MGR1_L (0x0020) /* Marginal read 1 mode. */
|
|
|
942 |
#define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
|
|
|
943 |
|
|
|
944 |
/* FCTL4 Control Bits */
|
|
|
945 |
|
|
|
946 |
/************************************************************
|
|
|
947 |
* HARDWARE MULTIPLIER 32Bit
|
|
|
948 |
************************************************************/
|
|
|
949 |
#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
|
|
|
950 |
#define __MSP430_BASEADDRESS_MPY32__ 0x04C0
|
|
|
951 |
|
|
|
952 |
SFR_16BIT(MPY); /* Multiply Unsigned/Operand 1 */
|
|
|
953 |
SFR_8BIT(MPY_L); /* Multiply Unsigned/Operand 1 */
|
|
|
954 |
SFR_8BIT(MPY_H); /* Multiply Unsigned/Operand 1 */
|
|
|
955 |
SFR_16BIT(MPYS); /* Multiply Signed/Operand 1 */
|
|
|
956 |
SFR_8BIT(MPYS_L); /* Multiply Signed/Operand 1 */
|
|
|
957 |
SFR_8BIT(MPYS_H); /* Multiply Signed/Operand 1 */
|
|
|
958 |
SFR_16BIT(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */
|
|
|
959 |
SFR_8BIT(MAC_L); /* Multiply Unsigned and Accumulate/Operand 1 */
|
|
|
960 |
SFR_8BIT(MAC_H); /* Multiply Unsigned and Accumulate/Operand 1 */
|
|
|
961 |
SFR_16BIT(MACS); /* Multiply Signed and Accumulate/Operand 1 */
|
|
|
962 |
SFR_8BIT(MACS_L); /* Multiply Signed and Accumulate/Operand 1 */
|
|
|
963 |
SFR_8BIT(MACS_H); /* Multiply Signed and Accumulate/Operand 1 */
|
|
|
964 |
SFR_16BIT(OP2); /* Operand 2 */
|
|
|
965 |
SFR_8BIT(OP2_L); /* Operand 2 */
|
|
|
966 |
SFR_8BIT(OP2_H); /* Operand 2 */
|
|
|
967 |
SFR_16BIT(RESLO); /* Result Low Word */
|
|
|
968 |
SFR_8BIT(RESLO_L); /* Result Low Word */
|
|
|
969 |
SFR_8BIT(RESLO_H); /* Result Low Word */
|
|
|
970 |
SFR_16BIT(RESHI); /* Result High Word */
|
|
|
971 |
SFR_8BIT(RESHI_L); /* Result High Word */
|
|
|
972 |
SFR_8BIT(RESHI_H); /* Result High Word */
|
|
|
973 |
SFR_16BIT(SUMEXT); /* Sum Extend */
|
|
|
974 |
SFR_8BIT(SUMEXT_L); /* Sum Extend */
|
|
|
975 |
SFR_8BIT(SUMEXT_H); /* Sum Extend */
|
|
|
976 |
|
|
|
977 |
SFR_16BIT(MPY32L); /* 32-bit operand 1 - multiply - low word */
|
|
|
978 |
SFR_8BIT(MPY32L_L); /* 32-bit operand 1 - multiply - low word */
|
|
|
979 |
SFR_8BIT(MPY32L_H); /* 32-bit operand 1 - multiply - low word */
|
|
|
980 |
SFR_16BIT(MPY32H); /* 32-bit operand 1 - multiply - high word */
|
|
|
981 |
SFR_8BIT(MPY32H_L); /* 32-bit operand 1 - multiply - high word */
|
|
|
982 |
SFR_8BIT(MPY32H_H); /* 32-bit operand 1 - multiply - high word */
|
|
|
983 |
SFR_16BIT(MPYS32L); /* 32-bit operand 1 - signed multiply - low word */
|
|
|
984 |
SFR_8BIT(MPYS32L_L); /* 32-bit operand 1 - signed multiply - low word */
|
|
|
985 |
SFR_8BIT(MPYS32L_H); /* 32-bit operand 1 - signed multiply - low word */
|
|
|
986 |
SFR_16BIT(MPYS32H); /* 32-bit operand 1 - signed multiply - high word */
|
|
|
987 |
SFR_8BIT(MPYS32H_L); /* 32-bit operand 1 - signed multiply - high word */
|
|
|
988 |
SFR_8BIT(MPYS32H_H); /* 32-bit operand 1 - signed multiply - high word */
|
|
|
989 |
SFR_16BIT(MAC32L); /* 32-bit operand 1 - multiply accumulate - low word */
|
|
|
990 |
SFR_8BIT(MAC32L_L); /* 32-bit operand 1 - multiply accumulate - low word */
|
|
|
991 |
SFR_8BIT(MAC32L_H); /* 32-bit operand 1 - multiply accumulate - low word */
|
|
|
992 |
SFR_16BIT(MAC32H); /* 32-bit operand 1 - multiply accumulate - high word */
|
|
|
993 |
SFR_8BIT(MAC32H_L); /* 32-bit operand 1 - multiply accumulate - high word */
|
|
|
994 |
SFR_8BIT(MAC32H_H); /* 32-bit operand 1 - multiply accumulate - high word */
|
|
|
995 |
SFR_16BIT(MACS32L); /* 32-bit operand 1 - signed multiply accumulate - low word */
|
|
|
996 |
SFR_8BIT(MACS32L_L); /* 32-bit operand 1 - signed multiply accumulate - low word */
|
|
|
997 |
SFR_8BIT(MACS32L_H); /* 32-bit operand 1 - signed multiply accumulate - low word */
|
|
|
998 |
SFR_16BIT(MACS32H); /* 32-bit operand 1 - signed multiply accumulate - high word */
|
|
|
999 |
SFR_8BIT(MACS32H_L); /* 32-bit operand 1 - signed multiply accumulate - high word */
|
|
|
1000 |
SFR_8BIT(MACS32H_H); /* 32-bit operand 1 - signed multiply accumulate - high word */
|
|
|
1001 |
SFR_16BIT(OP2L); /* 32-bit operand 2 - low word */
|
|
|
1002 |
SFR_8BIT(OP2L_L); /* 32-bit operand 2 - low word */
|
|
|
1003 |
SFR_8BIT(OP2L_H); /* 32-bit operand 2 - low word */
|
|
|
1004 |
SFR_16BIT(OP2H); /* 32-bit operand 2 - high word */
|
|
|
1005 |
SFR_8BIT(OP2H_L); /* 32-bit operand 2 - high word */
|
|
|
1006 |
SFR_8BIT(OP2H_H); /* 32-bit operand 2 - high word */
|
|
|
1007 |
SFR_16BIT(RES0); /* 32x32-bit result 0 - least significant word */
|
|
|
1008 |
SFR_8BIT(RES0_L); /* 32x32-bit result 0 - least significant word */
|
|
|
1009 |
SFR_8BIT(RES0_H); /* 32x32-bit result 0 - least significant word */
|
|
|
1010 |
SFR_16BIT(RES1); /* 32x32-bit result 1 */
|
|
|
1011 |
SFR_8BIT(RES1_L); /* 32x32-bit result 1 */
|
|
|
1012 |
SFR_8BIT(RES1_H); /* 32x32-bit result 1 */
|
|
|
1013 |
SFR_16BIT(RES2); /* 32x32-bit result 2 */
|
|
|
1014 |
SFR_8BIT(RES2_L); /* 32x32-bit result 2 */
|
|
|
1015 |
SFR_8BIT(RES2_H); /* 32x32-bit result 2 */
|
|
|
1016 |
SFR_16BIT(RES3); /* 32x32-bit result 3 - most significant word */
|
|
|
1017 |
SFR_8BIT(RES3_L); /* 32x32-bit result 3 - most significant word */
|
|
|
1018 |
SFR_8BIT(RES3_H); /* 32x32-bit result 3 - most significant word */
|
|
|
1019 |
SFR_16BIT(MPY32CTL0); /* MPY32 Control Register 0 */
|
|
|
1020 |
SFR_8BIT(MPY32CTL0_L); /* MPY32 Control Register 0 */
|
|
|
1021 |
SFR_8BIT(MPY32CTL0_H); /* MPY32 Control Register 0 */
|
|
|
1022 |
|
|
|
1023 |
#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
|
|
|
1024 |
#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
|
|
|
1025 |
#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
|
|
|
1026 |
#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
|
|
|
1027 |
#define OP2_B OP2_L /* Operand 2 (Byte Access) */
|
|
|
1028 |
#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
|
|
|
1029 |
#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
|
|
|
1030 |
#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
|
|
|
1031 |
#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
|
|
|
1032 |
#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
|
|
|
1033 |
#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
|
|
|
1034 |
#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
|
|
|
1035 |
#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
|
|
|
1036 |
#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
|
|
|
1037 |
#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
|
|
|
1038 |
|
|
|
1039 |
/* MPY32CTL0 Control Bits */
|
|
|
1040 |
#define MPYC (0x0001) /* Carry of the multiplier */
|
|
|
1041 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
1042 |
#define MPYFRAC (0x0004) /* Fractional mode */
|
|
|
1043 |
#define MPYSAT (0x0008) /* Saturation mode */
|
|
|
1044 |
#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */
|
|
|
1045 |
#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */
|
|
|
1046 |
#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
|
|
|
1047 |
#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
|
|
|
1048 |
#define MPYDLYWRTEN (0x0100) /* Delayed write enable */
|
|
|
1049 |
#define MPYDLY32 (0x0200) /* Delayed write mode */
|
|
|
1050 |
|
|
|
1051 |
/* MPY32CTL0 Control Bits */
|
|
|
1052 |
#define MPYC_L (0x0001) /* Carry of the multiplier */
|
|
|
1053 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
1054 |
#define MPYFRAC_L (0x0004) /* Fractional mode */
|
|
|
1055 |
#define MPYSAT_L (0x0008) /* Saturation mode */
|
|
|
1056 |
#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */
|
|
|
1057 |
#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */
|
|
|
1058 |
#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
|
|
|
1059 |
#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
|
|
|
1060 |
|
|
|
1061 |
/* MPY32CTL0 Control Bits */
|
|
|
1062 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
1063 |
#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */
|
|
|
1064 |
#define MPYDLY32_H (0x0002) /* Delayed write mode */
|
|
|
1065 |
|
|
|
1066 |
#define MPYM_0 (0x0000) /* Multiplier mode: MPY */
|
|
|
1067 |
#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */
|
|
|
1068 |
#define MPYM_2 (0x0020) /* Multiplier mode: MAC */
|
|
|
1069 |
#define MPYM_3 (0x0030) /* Multiplier mode: MACS */
|
|
|
1070 |
#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */
|
|
|
1071 |
#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */
|
|
|
1072 |
#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */
|
|
|
1073 |
#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */
|
|
|
1074 |
|
|
|
1075 |
/************************************************************
|
|
|
1076 |
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
|
|
|
1077 |
************************************************************/
|
|
|
1078 |
#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
|
|
|
1079 |
#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
|
|
|
1080 |
#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
|
|
|
1081 |
#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
|
|
|
1082 |
#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
|
|
|
1083 |
#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
|
|
|
1084 |
|
|
|
1085 |
SFR_16BIT(PAIN); /* Port A Input */
|
|
|
1086 |
SFR_8BIT(PAIN_L); /* Port A Input */
|
|
|
1087 |
SFR_8BIT(PAIN_H); /* Port A Input */
|
|
|
1088 |
SFR_16BIT(PAOUT); /* Port A Output */
|
|
|
1089 |
SFR_8BIT(PAOUT_L); /* Port A Output */
|
|
|
1090 |
SFR_8BIT(PAOUT_H); /* Port A Output */
|
|
|
1091 |
SFR_16BIT(PADIR); /* Port A Direction */
|
|
|
1092 |
SFR_8BIT(PADIR_L); /* Port A Direction */
|
|
|
1093 |
SFR_8BIT(PADIR_H); /* Port A Direction */
|
|
|
1094 |
SFR_16BIT(PAREN); /* Port A Resistor Enable */
|
|
|
1095 |
SFR_8BIT(PAREN_L); /* Port A Resistor Enable */
|
|
|
1096 |
SFR_8BIT(PAREN_H); /* Port A Resistor Enable */
|
|
|
1097 |
SFR_16BIT(PADS); /* Port A Resistor Drive Strenght */
|
|
|
1098 |
SFR_8BIT(PADS_L); /* Port A Resistor Drive Strenght */
|
|
|
1099 |
SFR_8BIT(PADS_H); /* Port A Resistor Drive Strenght */
|
|
|
1100 |
SFR_16BIT(PASEL); /* Port A Selection */
|
|
|
1101 |
SFR_8BIT(PASEL_L); /* Port A Selection */
|
|
|
1102 |
SFR_8BIT(PASEL_H); /* Port A Selection */
|
|
|
1103 |
SFR_16BIT(PAIES); /* Port A Interrupt Edge Select */
|
|
|
1104 |
SFR_8BIT(PAIES_L); /* Port A Interrupt Edge Select */
|
|
|
1105 |
SFR_8BIT(PAIES_H); /* Port A Interrupt Edge Select */
|
|
|
1106 |
SFR_16BIT(PAIE); /* Port A Interrupt Enable */
|
|
|
1107 |
SFR_8BIT(PAIE_L); /* Port A Interrupt Enable */
|
|
|
1108 |
SFR_8BIT(PAIE_H); /* Port A Interrupt Enable */
|
|
|
1109 |
SFR_16BIT(PAIFG); /* Port A Interrupt Flag */
|
|
|
1110 |
SFR_8BIT(PAIFG_L); /* Port A Interrupt Flag */
|
|
|
1111 |
SFR_8BIT(PAIFG_H); /* Port A Interrupt Flag */
|
|
|
1112 |
|
|
|
1113 |
|
|
|
1114 |
SFR_16BIT(P1IV); /* Port 1 Interrupt Vector Word */
|
|
|
1115 |
SFR_16BIT(P2IV); /* Port 2 Interrupt Vector Word */
|
|
|
1116 |
#define P1IN (PAIN_L) /* Port 1 Input */
|
|
|
1117 |
#define P1OUT (PAOUT_L) /* Port 1 Output */
|
|
|
1118 |
#define P1DIR (PADIR_L) /* Port 1 Direction */
|
|
|
1119 |
#define P1REN (PAREN_L) /* Port 1 Resistor Enable */
|
|
|
1120 |
#define P1DS (PADS_L) /* Port 1 Resistor Drive Strenght */
|
|
|
1121 |
#define P1SEL (PASEL_L) /* Port 1 Selection */
|
|
|
1122 |
#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
|
|
|
1123 |
#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
|
|
|
1124 |
#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
|
|
|
1125 |
|
|
|
1126 |
//Definitions for P1IV
|
|
|
1127 |
#define P1IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1128 |
#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */
|
|
|
1129 |
#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */
|
|
|
1130 |
#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */
|
|
|
1131 |
#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */
|
|
|
1132 |
#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */
|
|
|
1133 |
#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */
|
|
|
1134 |
#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */
|
|
|
1135 |
#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */
|
|
|
1136 |
|
|
|
1137 |
#define P2IN (PAIN_H) /* Port 2 Input */
|
|
|
1138 |
#define P2OUT (PAOUT_H) /* Port 2 Output */
|
|
|
1139 |
#define P2DIR (PADIR_H) /* Port 2 Direction */
|
|
|
1140 |
#define P2REN (PAREN_H) /* Port 2 Resistor Enable */
|
|
|
1141 |
#define P2DS (PADS_H) /* Port 2 Resistor Drive Strenght */
|
|
|
1142 |
#define P2SEL (PASEL_H) /* Port 2 Selection */
|
|
|
1143 |
#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
|
|
|
1144 |
#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
|
|
|
1145 |
#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
|
|
|
1146 |
|
|
|
1147 |
//Definitions for P2IV
|
|
|
1148 |
#define P2IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1149 |
#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */
|
|
|
1150 |
#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */
|
|
|
1151 |
#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */
|
|
|
1152 |
#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */
|
|
|
1153 |
#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */
|
|
|
1154 |
#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */
|
|
|
1155 |
#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */
|
|
|
1156 |
#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */
|
|
|
1157 |
|
|
|
1158 |
|
|
|
1159 |
/************************************************************
|
|
|
1160 |
* DIGITAL I/O Port3 Pull up / Pull down Resistors
|
|
|
1161 |
************************************************************/
|
|
|
1162 |
#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
|
|
|
1163 |
#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220
|
|
|
1164 |
#define __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */
|
|
|
1165 |
#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220
|
|
|
1166 |
|
|
|
1167 |
SFR_16BIT(PBIN); /* Port B Input */
|
|
|
1168 |
SFR_8BIT(PBIN_L); /* Port B Input */
|
|
|
1169 |
SFR_8BIT(PBIN_H); /* Port B Input */
|
|
|
1170 |
SFR_16BIT(PBOUT); /* Port B Output */
|
|
|
1171 |
SFR_8BIT(PBOUT_L); /* Port B Output */
|
|
|
1172 |
SFR_8BIT(PBOUT_H); /* Port B Output */
|
|
|
1173 |
SFR_16BIT(PBDIR); /* Port B Direction */
|
|
|
1174 |
SFR_8BIT(PBDIR_L); /* Port B Direction */
|
|
|
1175 |
SFR_8BIT(PBDIR_H); /* Port B Direction */
|
|
|
1176 |
SFR_16BIT(PBREN); /* Port B Resistor Enable */
|
|
|
1177 |
SFR_8BIT(PBREN_L); /* Port B Resistor Enable */
|
|
|
1178 |
SFR_8BIT(PBREN_H); /* Port B Resistor Enable */
|
|
|
1179 |
SFR_16BIT(PBDS); /* Port B Resistor Drive Strenght */
|
|
|
1180 |
SFR_8BIT(PBDS_L); /* Port B Resistor Drive Strenght */
|
|
|
1181 |
SFR_8BIT(PBDS_H); /* Port B Resistor Drive Strenght */
|
|
|
1182 |
SFR_16BIT(PBSEL); /* Port B Selection */
|
|
|
1183 |
SFR_8BIT(PBSEL_L); /* Port B Selection */
|
|
|
1184 |
SFR_8BIT(PBSEL_H); /* Port B Selection */
|
|
|
1185 |
|
|
|
1186 |
|
|
|
1187 |
#define P3IN (PBIN_L) /* Port 3 Input */
|
|
|
1188 |
#define P3OUT (PBOUT_L) /* Port 3 Output */
|
|
|
1189 |
#define P3DIR (PBDIR_L) /* Port 3 Direction */
|
|
|
1190 |
#define P3REN (PBREN_L) /* Port 3 Resistor Enable */
|
|
|
1191 |
#define P3DS (PBDS_L) /* Port 3 Resistor Drive Strenght */
|
|
|
1192 |
#define P3SEL (PBSEL_L) /* Port 3 Selection */
|
|
|
1193 |
|
|
|
1194 |
|
|
|
1195 |
/************************************************************
|
|
|
1196 |
* DIGITAL I/O PortJ Pull up / Pull down Resistors
|
|
|
1197 |
************************************************************/
|
|
|
1198 |
#define __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */
|
|
|
1199 |
#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320
|
|
|
1200 |
|
|
|
1201 |
SFR_16BIT(PJIN); /* Port J Input */
|
|
|
1202 |
SFR_8BIT(PJIN_L); /* Port J Input */
|
|
|
1203 |
SFR_8BIT(PJIN_H); /* Port J Input */
|
|
|
1204 |
SFR_16BIT(PJOUT); /* Port J Output */
|
|
|
1205 |
SFR_8BIT(PJOUT_L); /* Port J Output */
|
|
|
1206 |
SFR_8BIT(PJOUT_H); /* Port J Output */
|
|
|
1207 |
SFR_16BIT(PJDIR); /* Port J Direction */
|
|
|
1208 |
SFR_8BIT(PJDIR_L); /* Port J Direction */
|
|
|
1209 |
SFR_8BIT(PJDIR_H); /* Port J Direction */
|
|
|
1210 |
SFR_16BIT(PJREN); /* Port J Resistor Enable */
|
|
|
1211 |
SFR_8BIT(PJREN_L); /* Port J Resistor Enable */
|
|
|
1212 |
SFR_8BIT(PJREN_H); /* Port J Resistor Enable */
|
|
|
1213 |
SFR_16BIT(PJDS); /* Port J Resistor Drive Strenght */
|
|
|
1214 |
SFR_8BIT(PJDS_L); /* Port J Resistor Drive Strenght */
|
|
|
1215 |
SFR_8BIT(PJDS_H); /* Port J Resistor Drive Strenght */
|
|
|
1216 |
SFR_16BIT(PJSEL); /* Port J Selection */
|
|
|
1217 |
SFR_8BIT(PJSEL_L); /* Port J Selection */
|
|
|
1218 |
SFR_8BIT(PJSEL_H); /* Port J Selection */
|
|
|
1219 |
|
|
|
1220 |
/************************************************************
|
|
|
1221 |
* PORT MAPPING CONTROLLER
|
|
|
1222 |
************************************************************/
|
|
|
1223 |
#define __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */
|
|
|
1224 |
#define __MSP430_BASEADDRESS_PORT_MAPPING__ 0x01C0
|
|
|
1225 |
|
|
|
1226 |
SFR_16BIT(PMAPKEYID); /* Port Mapping Key register */
|
|
|
1227 |
SFR_8BIT(PMAPKEYID_L); /* Port Mapping Key register */
|
|
|
1228 |
SFR_8BIT(PMAPKEYID_H); /* Port Mapping Key register */
|
|
|
1229 |
SFR_16BIT(PMAPCTL); /* Port Mapping control register */
|
|
|
1230 |
SFR_8BIT(PMAPCTL_L); /* Port Mapping control register */
|
|
|
1231 |
SFR_8BIT(PMAPCTL_H); /* Port Mapping control register */
|
|
|
1232 |
|
|
|
1233 |
#define PMAPKEY (0x2D52) /* Port Mapping Key */
|
|
|
1234 |
#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */
|
|
|
1235 |
#define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */
|
|
|
1236 |
|
|
|
1237 |
/* PMAPCTL Control Bits */
|
|
|
1238 |
#define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */
|
|
|
1239 |
#define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */
|
|
|
1240 |
|
|
|
1241 |
/* PMAPCTL Control Bits */
|
|
|
1242 |
#define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */
|
|
|
1243 |
#define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */
|
|
|
1244 |
|
|
|
1245 |
/* PMAPCTL Control Bits */
|
|
|
1246 |
|
|
|
1247 |
/************************************************************
|
|
|
1248 |
* PORT 1 MAPPING CONTROLLER
|
|
|
1249 |
************************************************************/
|
|
|
1250 |
#define __MSP430_HAS_PORT1_MAPPING__ /* Definition to show that Module is available */
|
|
|
1251 |
#define __MSP430_BASEADDRESS_PORT1_MAPPING__ 0x01C8
|
|
|
1252 |
|
|
|
1253 |
SFR_16BIT(P1MAP01); /* Port P1.0/1 mapping register */
|
|
|
1254 |
SFR_8BIT(P1MAP01_L); /* Port P1.0/1 mapping register */
|
|
|
1255 |
SFR_8BIT(P1MAP01_H); /* Port P1.0/1 mapping register */
|
|
|
1256 |
SFR_16BIT(P1MAP23); /* Port P1.2/3 mapping register */
|
|
|
1257 |
SFR_8BIT(P1MAP23_L); /* Port P1.2/3 mapping register */
|
|
|
1258 |
SFR_8BIT(P1MAP23_H); /* Port P1.2/3 mapping register */
|
|
|
1259 |
SFR_16BIT(P1MAP45); /* Port P1.4/5 mapping register */
|
|
|
1260 |
SFR_8BIT(P1MAP45_L); /* Port P1.4/5 mapping register */
|
|
|
1261 |
SFR_8BIT(P1MAP45_H); /* Port P1.4/5 mapping register */
|
|
|
1262 |
SFR_16BIT(P1MAP67); /* Port P1.6/7 mapping register */
|
|
|
1263 |
SFR_8BIT(P1MAP67_L); /* Port P1.6/7 mapping register */
|
|
|
1264 |
SFR_8BIT(P1MAP67_H); /* Port P1.6/7 mapping register */
|
|
|
1265 |
|
|
|
1266 |
#define P1MAP0 P1MAP01_L /* Port P1.0 mapping register */
|
|
|
1267 |
#define P1MAP1 P1MAP01_H /* Port P1.1 mapping register */
|
|
|
1268 |
#define P1MAP2 P1MAP23_L /* Port P1.2 mapping register */
|
|
|
1269 |
#define P1MAP3 P1MAP23_H /* Port P1.3 mapping register */
|
|
|
1270 |
#define P1MAP4 P1MAP45_L /* Port P1.4 mapping register */
|
|
|
1271 |
#define P1MAP5 P1MAP45_H /* Port P1.5 mapping register */
|
|
|
1272 |
#define P1MAP6 P1MAP67_L /* Port P1.6 mapping register */
|
|
|
1273 |
#define P1MAP7 P1MAP67_H /* Port P1.7 mapping register */
|
|
|
1274 |
|
|
|
1275 |
/************************************************************
|
|
|
1276 |
* PORT 2 MAPPING CONTROLLER
|
|
|
1277 |
************************************************************/
|
|
|
1278 |
#define __MSP430_HAS_PORT2_MAPPING__ /* Definition to show that Module is available */
|
|
|
1279 |
#define __MSP430_BASEADDRESS_PORT2_MAPPING__ 0x01D0
|
|
|
1280 |
|
|
|
1281 |
SFR_16BIT(P2MAP01); /* Port P2.0/1 mapping register */
|
|
|
1282 |
SFR_8BIT(P2MAP01_L); /* Port P2.0/1 mapping register */
|
|
|
1283 |
SFR_8BIT(P2MAP01_H); /* Port P2.0/1 mapping register */
|
|
|
1284 |
SFR_16BIT(P2MAP23); /* Port P2.2/3 mapping register */
|
|
|
1285 |
SFR_8BIT(P2MAP23_L); /* Port P2.2/3 mapping register */
|
|
|
1286 |
SFR_8BIT(P2MAP23_H); /* Port P2.2/3 mapping register */
|
|
|
1287 |
SFR_16BIT(P2MAP45); /* Port P2.4/5 mapping register */
|
|
|
1288 |
SFR_8BIT(P2MAP45_L); /* Port P2.4/5 mapping register */
|
|
|
1289 |
SFR_8BIT(P2MAP45_H); /* Port P2.4/5 mapping register */
|
|
|
1290 |
SFR_16BIT(P2MAP67); /* Port P2.6/7 mapping register */
|
|
|
1291 |
SFR_8BIT(P2MAP67_L); /* Port P2.6/7 mapping register */
|
|
|
1292 |
SFR_8BIT(P2MAP67_H); /* Port P2.6/7 mapping register */
|
|
|
1293 |
|
|
|
1294 |
#define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */
|
|
|
1295 |
#define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */
|
|
|
1296 |
#define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */
|
|
|
1297 |
#define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */
|
|
|
1298 |
#define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */
|
|
|
1299 |
#define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */
|
|
|
1300 |
#define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */
|
|
|
1301 |
#define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */
|
|
|
1302 |
|
|
|
1303 |
/************************************************************
|
|
|
1304 |
* PORT 3 MAPPING CONTROLLER
|
|
|
1305 |
************************************************************/
|
|
|
1306 |
#define __MSP430_HAS_PORT3_MAPPING__ /* Definition to show that Module is available */
|
|
|
1307 |
#define __MSP430_BASEADDRESS_PORT3_MAPPING__ 0x01D8
|
|
|
1308 |
|
|
|
1309 |
SFR_16BIT(P3MAP01); /* Port P3.0/1 mapping register */
|
|
|
1310 |
SFR_8BIT(P3MAP01_L); /* Port P3.0/1 mapping register */
|
|
|
1311 |
SFR_8BIT(P3MAP01_H); /* Port P3.0/1 mapping register */
|
|
|
1312 |
SFR_16BIT(P3MAP23); /* Port P3.2/3 mapping register */
|
|
|
1313 |
SFR_8BIT(P3MAP23_L); /* Port P3.2/3 mapping register */
|
|
|
1314 |
SFR_8BIT(P3MAP23_H); /* Port P3.2/3 mapping register */
|
|
|
1315 |
SFR_16BIT(P3MAP45); /* Port P3.4/5 mapping register */
|
|
|
1316 |
SFR_8BIT(P3MAP45_L); /* Port P3.4/5 mapping register */
|
|
|
1317 |
SFR_8BIT(P3MAP45_H); /* Port P3.4/5 mapping register */
|
|
|
1318 |
SFR_16BIT(P3MAP67); /* Port P3.6/7 mapping register */
|
|
|
1319 |
SFR_8BIT(P3MAP67_L); /* Port P3.6/7 mapping register */
|
|
|
1320 |
SFR_8BIT(P3MAP67_H); /* Port P3.6/7 mapping register */
|
|
|
1321 |
|
|
|
1322 |
#define P3MAP0 P3MAP01_L /* Port P3.0 mapping register */
|
|
|
1323 |
#define P3MAP1 P3MAP01_H /* Port P3.1 mapping register */
|
|
|
1324 |
#define P3MAP2 P3MAP23_L /* Port P3.2 mapping register */
|
|
|
1325 |
#define P3MAP3 P3MAP23_H /* Port P3.3 mapping register */
|
|
|
1326 |
#define P3MAP4 P3MAP45_L /* Port P3.4 mapping register */
|
|
|
1327 |
#define P3MAP5 P3MAP45_H /* Port P3.5 mapping register */
|
|
|
1328 |
#define P3MAP6 P3MAP67_L /* Port P3.6 mapping register */
|
|
|
1329 |
#define P3MAP7 P3MAP67_H /* Port P3.7 mapping register */
|
|
|
1330 |
|
|
|
1331 |
|
|
|
1332 |
#define PM_NONE 0
|
|
|
1333 |
#define PM_UCA0CLK 1
|
|
|
1334 |
#define PM_UCB0STE 1
|
|
|
1335 |
#define PM_UCA0TXD 2
|
|
|
1336 |
#define PM_UCA0SIMO 2
|
|
|
1337 |
#define PM_UCB0SOMO 3
|
|
|
1338 |
#define PM_UCB0SCL 3
|
|
|
1339 |
#define PM_UCA0RXD 4
|
|
|
1340 |
#define PM_UCA0SOMI 4
|
|
|
1341 |
#define PM_UCB0SIMO 5
|
|
|
1342 |
#define PM_UCB0SDA 5
|
|
|
1343 |
#define PM_UCB0CLK 6
|
|
|
1344 |
#define PM_UCA0STE 6
|
|
|
1345 |
#define PM_TD0_0 7
|
|
|
1346 |
#define PM_TD0_1 8
|
|
|
1347 |
#define PM_TD0_2 9
|
|
|
1348 |
#define PM_TD1_0 10
|
|
|
1349 |
#define PM_TD1_1 11
|
|
|
1350 |
#define PM_TD1_2 12
|
|
|
1351 |
#define PM_CLR1TD0_0 13
|
|
|
1352 |
#define PM_FLT1_2TD0_0 13
|
|
|
1353 |
#define PM_FLT1_0TD0_1 14
|
|
|
1354 |
#define PM_FLT1_1TD0_2 15
|
|
|
1355 |
#define PM_CLR2TD1_0 16
|
|
|
1356 |
#define PM_FLT2_1TD1_0 16
|
|
|
1357 |
#define PM_FLT2_2TD1_1 17
|
|
|
1358 |
#define PM_FLT2_0TD1_2 18
|
|
|
1359 |
#define PM_TD0_0SMCLK 19
|
|
|
1360 |
#define PM_TA0CLKCBOUT 20
|
|
|
1361 |
#define PM_TD0CLKMCLK 21
|
|
|
1362 |
#define PM_TA0_0 22
|
|
|
1363 |
#define PM_TA0_1 23
|
|
|
1364 |
#define PM_TA0_2 24
|
|
|
1365 |
#define PM_DMAE0SMCLK 25
|
|
|
1366 |
#define PM_DMAE1MCLK 26
|
|
|
1367 |
#define PM_DMAE2SVM 27
|
|
|
1368 |
#define PM_TD0OUTH 28
|
|
|
1369 |
#define PM_TD1OUTH 29
|
|
|
1370 |
#define PM_ANALOG 31
|
|
|
1371 |
|
|
|
1372 |
/************************************************************
|
|
|
1373 |
* PMM - Power Management System
|
|
|
1374 |
************************************************************/
|
|
|
1375 |
#define __MSP430_HAS_PMM__ /* Definition to show that Module is available */
|
|
|
1376 |
#define __MSP430_BASEADDRESS_PMM__ 0x0120
|
|
|
1377 |
|
|
|
1378 |
SFR_16BIT(PMMCTL0); /* PMM Control 0 */
|
|
|
1379 |
SFR_8BIT(PMMCTL0_L); /* PMM Control 0 */
|
|
|
1380 |
SFR_8BIT(PMMCTL0_H); /* PMM Control 0 */
|
|
|
1381 |
SFR_16BIT(PMMCTL1); /* PMM Control 1 */
|
|
|
1382 |
SFR_8BIT(PMMCTL1_L); /* PMM Control 1 */
|
|
|
1383 |
SFR_8BIT(PMMCTL1_H); /* PMM Control 1 */
|
|
|
1384 |
SFR_16BIT(SVSMHCTL); /* SVS and SVM high side control register */
|
|
|
1385 |
SFR_8BIT(SVSMHCTL_L); /* SVS and SVM high side control register */
|
|
|
1386 |
SFR_8BIT(SVSMHCTL_H); /* SVS and SVM high side control register */
|
|
|
1387 |
SFR_16BIT(SVSMLCTL); /* SVS and SVM low side control register */
|
|
|
1388 |
SFR_8BIT(SVSMLCTL_L); /* SVS and SVM low side control register */
|
|
|
1389 |
SFR_8BIT(SVSMLCTL_H); /* SVS and SVM low side control register */
|
|
|
1390 |
SFR_16BIT(SVSMIO); /* SVSIN and SVSOUT control register */
|
|
|
1391 |
SFR_8BIT(SVSMIO_L); /* SVSIN and SVSOUT control register */
|
|
|
1392 |
SFR_8BIT(SVSMIO_H); /* SVSIN and SVSOUT control register */
|
|
|
1393 |
SFR_16BIT(PMMIFG); /* PMM Interrupt Flag */
|
|
|
1394 |
SFR_8BIT(PMMIFG_L); /* PMM Interrupt Flag */
|
|
|
1395 |
SFR_8BIT(PMMIFG_H); /* PMM Interrupt Flag */
|
|
|
1396 |
SFR_16BIT(PMMRIE); /* PMM and RESET Interrupt Enable */
|
|
|
1397 |
SFR_8BIT(PMMRIE_L); /* PMM and RESET Interrupt Enable */
|
|
|
1398 |
SFR_8BIT(PMMRIE_H); /* PMM and RESET Interrupt Enable */
|
|
|
1399 |
SFR_16BIT(PM5CTL0); /* PMM Power Mode 5 Control Register 0 */
|
|
|
1400 |
SFR_8BIT(PM5CTL0_L); /* PMM Power Mode 5 Control Register 0 */
|
|
|
1401 |
SFR_8BIT(PM5CTL0_H); /* PMM Power Mode 5 Control Register 0 */
|
|
|
1402 |
|
|
|
1403 |
#define PMMPW (0xA500) /* PMM Register Write Password */
|
|
|
1404 |
#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
|
|
|
1405 |
|
|
|
1406 |
/* PMMCTL0 Control Bits */
|
|
|
1407 |
#define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */
|
|
|
1408 |
#define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */
|
|
|
1409 |
#define PMMSWBOR (0x0004) /* PMM Software BOR */
|
|
|
1410 |
#define PMMSWPOR (0x0008) /* PMM Software POR */
|
|
|
1411 |
#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */
|
|
|
1412 |
#define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */
|
|
|
1413 |
|
|
|
1414 |
/* PMMCTL0 Control Bits */
|
|
|
1415 |
#define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */
|
|
|
1416 |
#define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */
|
|
|
1417 |
#define PMMSWBOR_L (0x0004) /* PMM Software BOR */
|
|
|
1418 |
#define PMMSWPOR_L (0x0008) /* PMM Software POR */
|
|
|
1419 |
#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */
|
|
|
1420 |
#define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */
|
|
|
1421 |
|
|
|
1422 |
/* PMMCTL0 Control Bits */
|
|
|
1423 |
|
|
|
1424 |
#define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */
|
|
|
1425 |
#define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */
|
|
|
1426 |
#define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */
|
|
|
1427 |
#define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */
|
|
|
1428 |
|
|
|
1429 |
/* PMMCTL1 Control Bits */
|
|
|
1430 |
#define PMMREFMD (0x0001) /* PMM Reference Mode */
|
|
|
1431 |
#define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */
|
|
|
1432 |
#define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */
|
|
|
1433 |
|
|
|
1434 |
/* PMMCTL1 Control Bits */
|
|
|
1435 |
#define PMMREFMD_L (0x0001) /* PMM Reference Mode */
|
|
|
1436 |
#define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */
|
|
|
1437 |
#define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */
|
|
|
1438 |
|
|
|
1439 |
/* PMMCTL1 Control Bits */
|
|
|
1440 |
|
|
|
1441 |
/* SVSMHCTL Control Bits */
|
|
|
1442 |
#define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
|
|
|
1443 |
#define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
|
|
|
1444 |
#define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
|
|
|
1445 |
#define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */
|
|
|
1446 |
#define SVSHMD (0x0010) /* SVS high side mode */
|
|
|
1447 |
#define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */
|
|
|
1448 |
#define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */
|
|
|
1449 |
#define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */
|
|
|
1450 |
#define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */
|
|
|
1451 |
#define SVSHE (0x0400) /* SVS high side enable */
|
|
|
1452 |
#define SVSHFP (0x0800) /* SVS high side full performace mode */
|
|
|
1453 |
#define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */
|
|
|
1454 |
#define SVMHE (0x4000) /* SVM high side enable */
|
|
|
1455 |
#define SVMHFP (0x8000) /* SVM high side full performace mode */
|
|
|
1456 |
|
|
|
1457 |
/* SVSMHCTL Control Bits */
|
|
|
1458 |
#define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
|
|
|
1459 |
#define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
|
|
|
1460 |
#define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
|
|
|
1461 |
#define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */
|
|
|
1462 |
#define SVSHMD_L (0x0010) /* SVS high side mode */
|
|
|
1463 |
#define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */
|
|
|
1464 |
#define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */
|
|
|
1465 |
|
|
|
1466 |
/* SVSMHCTL Control Bits */
|
|
|
1467 |
#define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */
|
|
|
1468 |
#define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */
|
|
|
1469 |
#define SVSHE_H (0x0004) /* SVS high side enable */
|
|
|
1470 |
#define SVSHFP_H (0x0008) /* SVS high side full performace mode */
|
|
|
1471 |
#define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */
|
|
|
1472 |
#define SVMHE_H (0x0040) /* SVM high side enable */
|
|
|
1473 |
#define SVMHFP_H (0x0080) /* SVM high side full performace mode */
|
|
|
1474 |
|
|
|
1475 |
#define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */
|
|
|
1476 |
#define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */
|
|
|
1477 |
#define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */
|
|
|
1478 |
#define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */
|
|
|
1479 |
#define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */
|
|
|
1480 |
#define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */
|
|
|
1481 |
#define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */
|
|
|
1482 |
#define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */
|
|
|
1483 |
|
|
|
1484 |
#define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */
|
|
|
1485 |
#define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */
|
|
|
1486 |
#define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */
|
|
|
1487 |
#define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */
|
|
|
1488 |
|
|
|
1489 |
/* SVSMLCTL Control Bits */
|
|
|
1490 |
#define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
|
|
|
1491 |
#define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
|
|
|
1492 |
#define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
|
|
|
1493 |
#define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */
|
|
|
1494 |
#define SVSLMD (0x0010) /* SVS low side mode */
|
|
|
1495 |
#define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */
|
|
|
1496 |
#define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */
|
|
|
1497 |
#define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */
|
|
|
1498 |
#define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */
|
|
|
1499 |
#define SVSLE (0x0400) /* SVS low side enable */
|
|
|
1500 |
#define SVSLFP (0x0800) /* SVS low side full performace mode */
|
|
|
1501 |
#define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */
|
|
|
1502 |
#define SVMLE (0x4000) /* SVM low side enable */
|
|
|
1503 |
#define SVMLFP (0x8000) /* SVM low side full performace mode */
|
|
|
1504 |
|
|
|
1505 |
/* SVSMLCTL Control Bits */
|
|
|
1506 |
#define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
|
|
|
1507 |
#define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
|
|
|
1508 |
#define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
|
|
|
1509 |
#define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */
|
|
|
1510 |
#define SVSLMD_L (0x0010) /* SVS low side mode */
|
|
|
1511 |
#define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */
|
|
|
1512 |
#define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */
|
|
|
1513 |
|
|
|
1514 |
/* SVSMLCTL Control Bits */
|
|
|
1515 |
#define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */
|
|
|
1516 |
#define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */
|
|
|
1517 |
#define SVSLE_H (0x0004) /* SVS low side enable */
|
|
|
1518 |
#define SVSLFP_H (0x0008) /* SVS low side full performace mode */
|
|
|
1519 |
#define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */
|
|
|
1520 |
#define SVMLE_H (0x0040) /* SVM low side enable */
|
|
|
1521 |
#define SVMLFP_H (0x0080) /* SVM low side full performace mode */
|
|
|
1522 |
|
|
|
1523 |
#define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */
|
|
|
1524 |
#define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */
|
|
|
1525 |
#define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */
|
|
|
1526 |
#define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */
|
|
|
1527 |
#define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */
|
|
|
1528 |
#define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */
|
|
|
1529 |
#define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */
|
|
|
1530 |
#define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */
|
|
|
1531 |
|
|
|
1532 |
#define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */
|
|
|
1533 |
#define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */
|
|
|
1534 |
#define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */
|
|
|
1535 |
#define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */
|
|
|
1536 |
|
|
|
1537 |
/* SVSMIO Control Bits */
|
|
|
1538 |
#define SVMLOE (0x0008) /* SVM low side output enable */
|
|
|
1539 |
#define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */
|
|
|
1540 |
#define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */
|
|
|
1541 |
#define SVMHOE (0x0800) /* SVM high side output enable */
|
|
|
1542 |
#define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */
|
|
|
1543 |
|
|
|
1544 |
/* SVSMIO Control Bits */
|
|
|
1545 |
#define SVMLOE_L (0x0008) /* SVM low side output enable */
|
|
|
1546 |
#define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */
|
|
|
1547 |
#define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */
|
|
|
1548 |
|
|
|
1549 |
/* SVSMIO Control Bits */
|
|
|
1550 |
#define SVMHOE_H (0x0008) /* SVM high side output enable */
|
|
|
1551 |
#define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */
|
|
|
1552 |
|
|
|
1553 |
/* PMMIFG Control Bits */
|
|
|
1554 |
#define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */
|
|
|
1555 |
#define SVMLIFG (0x0002) /* SVM low side interrupt flag */
|
|
|
1556 |
#define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */
|
|
|
1557 |
#define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */
|
|
|
1558 |
#define SVMHIFG (0x0020) /* SVM high side interrupt flag */
|
|
|
1559 |
#define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */
|
|
|
1560 |
#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */
|
|
|
1561 |
#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */
|
|
|
1562 |
#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */
|
|
|
1563 |
#define SVSHIFG (0x1000) /* SVS low side interrupt flag */
|
|
|
1564 |
#define SVSLIFG (0x2000) /* SVS high side interrupt flag */
|
|
|
1565 |
#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */
|
|
|
1566 |
|
|
|
1567 |
/* PMMIFG Control Bits */
|
|
|
1568 |
#define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */
|
|
|
1569 |
#define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */
|
|
|
1570 |
#define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */
|
|
|
1571 |
#define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */
|
|
|
1572 |
#define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */
|
|
|
1573 |
#define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */
|
|
|
1574 |
|
|
|
1575 |
/* PMMIFG Control Bits */
|
|
|
1576 |
#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */
|
|
|
1577 |
#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */
|
|
|
1578 |
#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */
|
|
|
1579 |
#define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */
|
|
|
1580 |
#define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */
|
|
|
1581 |
#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */
|
|
|
1582 |
|
|
|
1583 |
#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */
|
|
|
1584 |
|
|
|
1585 |
/* PMMIE and RESET Control Bits */
|
|
|
1586 |
#define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */
|
|
|
1587 |
#define SVMLIE (0x0002) /* SVM low side interrupt enable */
|
|
|
1588 |
#define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */
|
|
|
1589 |
#define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */
|
|
|
1590 |
#define SVMHIE (0x0020) /* SVM high side interrupt enable */
|
|
|
1591 |
#define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */
|
|
|
1592 |
#define SVSLPE (0x0100) /* SVS low side POR enable */
|
|
|
1593 |
#define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */
|
|
|
1594 |
#define SVSHPE (0x1000) /* SVS high side POR enable */
|
|
|
1595 |
#define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */
|
|
|
1596 |
|
|
|
1597 |
/* PMMIE and RESET Control Bits */
|
|
|
1598 |
#define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */
|
|
|
1599 |
#define SVMLIE_L (0x0002) /* SVM low side interrupt enable */
|
|
|
1600 |
#define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */
|
|
|
1601 |
#define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */
|
|
|
1602 |
#define SVMHIE_L (0x0020) /* SVM high side interrupt enable */
|
|
|
1603 |
#define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */
|
|
|
1604 |
|
|
|
1605 |
/* PMMIE and RESET Control Bits */
|
|
|
1606 |
#define SVSLPE_H (0x0001) /* SVS low side POR enable */
|
|
|
1607 |
#define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */
|
|
|
1608 |
#define SVSHPE_H (0x0010) /* SVS high side POR enable */
|
|
|
1609 |
#define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */
|
|
|
1610 |
|
|
|
1611 |
/* PM5CTL0 Power Mode 5 Control Bits */
|
|
|
1612 |
#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
|
|
|
1613 |
|
|
|
1614 |
/* PM5CTL0 Power Mode 5 Control Bits */
|
|
|
1615 |
#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
|
|
|
1616 |
|
|
|
1617 |
/* PM5CTL0 Power Mode 5 Control Bits */
|
|
|
1618 |
#define LOCKIO LOCKLPM5 /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
|
|
|
1619 |
|
|
|
1620 |
/*************************************************************
|
|
|
1621 |
* RAM Control Module
|
|
|
1622 |
*************************************************************/
|
|
|
1623 |
#define __MSP430_HAS_RC__ /* Definition to show that Module is available */
|
|
|
1624 |
#define __MSP430_BASEADDRESS_RC__ 0x0158
|
|
|
1625 |
|
|
|
1626 |
SFR_16BIT(RCCTL0); /* Ram Controller Control Register */
|
|
|
1627 |
SFR_8BIT(RCCTL0_L); /* Ram Controller Control Register */
|
|
|
1628 |
SFR_8BIT(RCCTL0_H); /* Ram Controller Control Register */
|
|
|
1629 |
|
|
|
1630 |
/* RCCTL0 Control Bits */
|
|
|
1631 |
#define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */
|
|
|
1632 |
#define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */
|
|
|
1633 |
#define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */
|
|
|
1634 |
#define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */
|
|
|
1635 |
|
|
|
1636 |
/* RCCTL0 Control Bits */
|
|
|
1637 |
#define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */
|
|
|
1638 |
#define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */
|
|
|
1639 |
#define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */
|
|
|
1640 |
#define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */
|
|
|
1641 |
|
|
|
1642 |
/* RCCTL0 Control Bits */
|
|
|
1643 |
|
|
|
1644 |
#define RCKEY (0x5A00)
|
|
|
1645 |
|
|
|
1646 |
/************************************************************
|
|
|
1647 |
* Shared Reference
|
|
|
1648 |
************************************************************/
|
|
|
1649 |
#define __MSP430_HAS_REF__ /* Definition to show that Module is available */
|
|
|
1650 |
#define __MSP430_BASEADDRESS_REF__ 0x01B0
|
|
|
1651 |
|
|
|
1652 |
SFR_16BIT(REFCTL0); /* REF Shared Reference control register 0 */
|
|
|
1653 |
SFR_8BIT(REFCTL0_L); /* REF Shared Reference control register 0 */
|
|
|
1654 |
SFR_8BIT(REFCTL0_H); /* REF Shared Reference control register 0 */
|
|
|
1655 |
|
|
|
1656 |
/* REFCTL0 Control Bits */
|
|
|
1657 |
#define REFON (0x0001) /* REF Reference On */
|
|
|
1658 |
#define REFOUT (0x0002) /* REF Reference output Buffer On */
|
|
|
1659 |
//#define RESERVED (0x0004) /* Reserved */
|
|
|
1660 |
#define REFTCOFF (0x0008) /* REF Temp.Sensor off */
|
|
|
1661 |
#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
|
|
|
1662 |
#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
|
|
|
1663 |
//#define RESERVED (0x0040) /* Reserved */
|
|
|
1664 |
#define REFMSTR (0x0080) /* REF Master Control */
|
|
|
1665 |
#define REFGENACT (0x0100) /* REF Reference generator active */
|
|
|
1666 |
#define REFBGACT (0x0200) /* REF Reference bandgap active */
|
|
|
1667 |
#define REFGENBUSY (0x0400) /* REF Reference generator busy */
|
|
|
1668 |
#define BGMODE (0x0800) /* REF Bandgap mode */
|
|
|
1669 |
//#define RESERVED (0x1000) /* Reserved */
|
|
|
1670 |
//#define RESERVED (0x2000) /* Reserved */
|
|
|
1671 |
//#define RESERVED (0x4000) /* Reserved */
|
|
|
1672 |
//#define RESERVED (0x8000) /* Reserved */
|
|
|
1673 |
|
|
|
1674 |
/* REFCTL0 Control Bits */
|
|
|
1675 |
#define REFON_L (0x0001) /* REF Reference On */
|
|
|
1676 |
#define REFOUT_L (0x0002) /* REF Reference output Buffer On */
|
|
|
1677 |
//#define RESERVED (0x0004) /* Reserved */
|
|
|
1678 |
#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
|
|
|
1679 |
#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
|
|
|
1680 |
#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
|
|
|
1681 |
//#define RESERVED (0x0040) /* Reserved */
|
|
|
1682 |
#define REFMSTR_L (0x0080) /* REF Master Control */
|
|
|
1683 |
//#define RESERVED (0x1000) /* Reserved */
|
|
|
1684 |
//#define RESERVED (0x2000) /* Reserved */
|
|
|
1685 |
//#define RESERVED (0x4000) /* Reserved */
|
|
|
1686 |
//#define RESERVED (0x8000) /* Reserved */
|
|
|
1687 |
|
|
|
1688 |
/* REFCTL0 Control Bits */
|
|
|
1689 |
//#define RESERVED (0x0004) /* Reserved */
|
|
|
1690 |
//#define RESERVED (0x0040) /* Reserved */
|
|
|
1691 |
#define REFGENACT_H (0x0001) /* REF Reference generator active */
|
|
|
1692 |
#define REFBGACT_H (0x0002) /* REF Reference bandgap active */
|
|
|
1693 |
#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
|
|
|
1694 |
#define BGMODE_H (0x0008) /* REF Bandgap mode */
|
|
|
1695 |
//#define RESERVED (0x1000) /* Reserved */
|
|
|
1696 |
//#define RESERVED (0x2000) /* Reserved */
|
|
|
1697 |
//#define RESERVED (0x4000) /* Reserved */
|
|
|
1698 |
//#define RESERVED (0x8000) /* Reserved */
|
|
|
1699 |
|
|
|
1700 |
#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */
|
|
|
1701 |
#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
|
|
|
1702 |
#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
|
|
|
1703 |
#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
|
|
|
1704 |
|
|
|
1705 |
/************************************************************
|
|
|
1706 |
* SFR - Special Function Register Module
|
|
|
1707 |
************************************************************/
|
|
|
1708 |
#define __MSP430_HAS_SFR__ /* Definition to show that Module is available */
|
|
|
1709 |
#define __MSP430_BASEADDRESS_SFR__ 0x0100
|
|
|
1710 |
|
|
|
1711 |
SFR_16BIT(SFRIE1); /* Interrupt Enable 1 */
|
|
|
1712 |
SFR_8BIT(SFRIE1_L); /* Interrupt Enable 1 */
|
|
|
1713 |
SFR_8BIT(SFRIE1_H); /* Interrupt Enable 1 */
|
|
|
1714 |
|
|
|
1715 |
/* SFRIE1 Control Bits */
|
|
|
1716 |
#define WDTIE (0x0001) /* WDT Interrupt Enable */
|
|
|
1717 |
#define OFIE (0x0002) /* Osc Fault Enable */
|
|
|
1718 |
//#define Reserved (0x0004)
|
|
|
1719 |
#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */
|
|
|
1720 |
#define NMIIE (0x0010) /* NMI Interrupt Enable */
|
|
|
1721 |
#define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */
|
|
|
1722 |
#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */
|
|
|
1723 |
#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */
|
|
|
1724 |
|
|
|
1725 |
#define WDTIE_L (0x0001) /* WDT Interrupt Enable */
|
|
|
1726 |
#define OFIE_L (0x0002) /* Osc Fault Enable */
|
|
|
1727 |
//#define Reserved (0x0004)
|
|
|
1728 |
#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */
|
|
|
1729 |
#define NMIIE_L (0x0010) /* NMI Interrupt Enable */
|
|
|
1730 |
#define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */
|
|
|
1731 |
#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */
|
|
|
1732 |
#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */
|
|
|
1733 |
|
|
|
1734 |
//#define Reserved (0x0004)
|
|
|
1735 |
|
|
|
1736 |
SFR_16BIT(SFRIFG1); /* Interrupt Flag 1 */
|
|
|
1737 |
SFR_8BIT(SFRIFG1_L); /* Interrupt Flag 1 */
|
|
|
1738 |
SFR_8BIT(SFRIFG1_H); /* Interrupt Flag 1 */
|
|
|
1739 |
/* SFRIFG1 Control Bits */
|
|
|
1740 |
#define WDTIFG (0x0001) /* WDT Interrupt Flag */
|
|
|
1741 |
#define OFIFG (0x0002) /* Osc Fault Flag */
|
|
|
1742 |
//#define Reserved (0x0004)
|
|
|
1743 |
#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */
|
|
|
1744 |
#define NMIIFG (0x0010) /* NMI Interrupt Flag */
|
|
|
1745 |
//#define Reserved (0x0020)
|
|
|
1746 |
#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */
|
|
|
1747 |
#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */
|
|
|
1748 |
|
|
|
1749 |
#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */
|
|
|
1750 |
#define OFIFG_L (0x0002) /* Osc Fault Flag */
|
|
|
1751 |
//#define Reserved (0x0004)
|
|
|
1752 |
#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */
|
|
|
1753 |
#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */
|
|
|
1754 |
//#define Reserved (0x0020)
|
|
|
1755 |
#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */
|
|
|
1756 |
#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */
|
|
|
1757 |
|
|
|
1758 |
//#define Reserved (0x0004)
|
|
|
1759 |
//#define Reserved (0x0020)
|
|
|
1760 |
|
|
|
1761 |
SFR_16BIT(SFRRPCR); /* RESET Pin Control Register */
|
|
|
1762 |
SFR_8BIT(SFRRPCR_L); /* RESET Pin Control Register */
|
|
|
1763 |
SFR_8BIT(SFRRPCR_H); /* RESET Pin Control Register */
|
|
|
1764 |
/* SFRRPCR Control Bits */
|
|
|
1765 |
#define SYSNMI (0x0001) /* NMI select */
|
|
|
1766 |
#define SYSNMIIES (0x0002) /* NMI edge select */
|
|
|
1767 |
#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */
|
|
|
1768 |
#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */
|
|
|
1769 |
|
|
|
1770 |
#define SYSNMI_L (0x0001) /* NMI select */
|
|
|
1771 |
#define SYSNMIIES_L (0x0002) /* NMI edge select */
|
|
|
1772 |
#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */
|
|
|
1773 |
#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */
|
|
|
1774 |
|
|
|
1775 |
/************************************************************
|
|
|
1776 |
* SYS - System Module
|
|
|
1777 |
************************************************************/
|
|
|
1778 |
#define __MSP430_HAS_SYS__ /* Definition to show that Module is available */
|
|
|
1779 |
#define __MSP430_BASEADDRESS_SYS__ 0x0180
|
|
|
1780 |
|
|
|
1781 |
SFR_16BIT(SYSCTL); /* System control */
|
|
|
1782 |
SFR_8BIT(SYSCTL_L); /* System control */
|
|
|
1783 |
SFR_8BIT(SYSCTL_H); /* System control */
|
|
|
1784 |
SFR_16BIT(SYSBSLC); /* Boot strap configuration area */
|
|
|
1785 |
SFR_8BIT(SYSBSLC_L); /* Boot strap configuration area */
|
|
|
1786 |
SFR_8BIT(SYSBSLC_H); /* Boot strap configuration area */
|
|
|
1787 |
SFR_16BIT(SYSJMBC); /* JTAG mailbox control */
|
|
|
1788 |
SFR_8BIT(SYSJMBC_L); /* JTAG mailbox control */
|
|
|
1789 |
SFR_8BIT(SYSJMBC_H); /* JTAG mailbox control */
|
|
|
1790 |
SFR_16BIT(SYSJMBI0); /* JTAG mailbox input 0 */
|
|
|
1791 |
SFR_8BIT(SYSJMBI0_L); /* JTAG mailbox input 0 */
|
|
|
1792 |
SFR_8BIT(SYSJMBI0_H); /* JTAG mailbox input 0 */
|
|
|
1793 |
SFR_16BIT(SYSJMBI1); /* JTAG mailbox input 1 */
|
|
|
1794 |
SFR_8BIT(SYSJMBI1_L); /* JTAG mailbox input 1 */
|
|
|
1795 |
SFR_8BIT(SYSJMBI1_H); /* JTAG mailbox input 1 */
|
|
|
1796 |
SFR_16BIT(SYSJMBO0); /* JTAG mailbox output 0 */
|
|
|
1797 |
SFR_8BIT(SYSJMBO0_L); /* JTAG mailbox output 0 */
|
|
|
1798 |
SFR_8BIT(SYSJMBO0_H); /* JTAG mailbox output 0 */
|
|
|
1799 |
SFR_16BIT(SYSJMBO1); /* JTAG mailbox output 1 */
|
|
|
1800 |
SFR_8BIT(SYSJMBO1_L); /* JTAG mailbox output 1 */
|
|
|
1801 |
SFR_8BIT(SYSJMBO1_H); /* JTAG mailbox output 1 */
|
|
|
1802 |
|
|
|
1803 |
SFR_16BIT(SYSBERRIV); /* Bus Error vector generator */
|
|
|
1804 |
SFR_8BIT(SYSBERRIV_L); /* Bus Error vector generator */
|
|
|
1805 |
SFR_8BIT(SYSBERRIV_H); /* Bus Error vector generator */
|
|
|
1806 |
SFR_16BIT(SYSUNIV); /* User NMI vector generator */
|
|
|
1807 |
SFR_8BIT(SYSUNIV_L); /* User NMI vector generator */
|
|
|
1808 |
SFR_8BIT(SYSUNIV_H); /* User NMI vector generator */
|
|
|
1809 |
SFR_16BIT(SYSSNIV); /* System NMI vector generator */
|
|
|
1810 |
SFR_8BIT(SYSSNIV_L); /* System NMI vector generator */
|
|
|
1811 |
SFR_8BIT(SYSSNIV_H); /* System NMI vector generator */
|
|
|
1812 |
SFR_16BIT(SYSRSTIV); /* Reset vector generator */
|
|
|
1813 |
SFR_8BIT(SYSRSTIV_L); /* Reset vector generator */
|
|
|
1814 |
SFR_8BIT(SYSRSTIV_H); /* Reset vector generator */
|
|
|
1815 |
|
|
|
1816 |
/* SYSCTL Control Bits */
|
|
|
1817 |
#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */
|
|
|
1818 |
//#define RESERVED (0x0002) /* SYS - Reserved */
|
|
|
1819 |
#define SYSPMMPE (0x0004) /* SYS - PMM access protect */
|
|
|
1820 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
1821 |
#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */
|
|
|
1822 |
#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */
|
|
|
1823 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
1824 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
1825 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
1826 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
1827 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
1828 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
1829 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
1830 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
1831 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
1832 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
1833 |
|
|
|
1834 |
/* SYSCTL Control Bits */
|
|
|
1835 |
#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */
|
|
|
1836 |
//#define RESERVED (0x0002) /* SYS - Reserved */
|
|
|
1837 |
#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */
|
|
|
1838 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
1839 |
#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */
|
|
|
1840 |
#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */
|
|
|
1841 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
1842 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
1843 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
1844 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
1845 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
1846 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
1847 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
1848 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
1849 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
1850 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
1851 |
|
|
|
1852 |
/* SYSCTL Control Bits */
|
|
|
1853 |
//#define RESERVED (0x0002) /* SYS - Reserved */
|
|
|
1854 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
1855 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
1856 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
1857 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
1858 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
1859 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
1860 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
1861 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
1862 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
1863 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
1864 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
1865 |
|
|
|
1866 |
/* SYSBSLC Control Bits */
|
|
|
1867 |
#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */
|
|
|
1868 |
#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */
|
|
|
1869 |
#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */
|
|
|
1870 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
1871 |
//#define RESERVED (0x0010) /* SYS - Reserved */
|
|
|
1872 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
1873 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
1874 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
1875 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
1876 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
1877 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
1878 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
1879 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
1880 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
1881 |
#define SYSBSLOFF (0x4000) /* SYS - BSL Memeory disabled */
|
|
|
1882 |
#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */
|
|
|
1883 |
|
|
|
1884 |
/* SYSBSLC Control Bits */
|
|
|
1885 |
#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */
|
|
|
1886 |
#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */
|
|
|
1887 |
#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */
|
|
|
1888 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
1889 |
//#define RESERVED (0x0010) /* SYS - Reserved */
|
|
|
1890 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
1891 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
1892 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
1893 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
1894 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
1895 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
1896 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
1897 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
1898 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
1899 |
|
|
|
1900 |
/* SYSBSLC Control Bits */
|
|
|
1901 |
//#define RESERVED (0x0008) /* SYS - Reserved */
|
|
|
1902 |
//#define RESERVED (0x0010) /* SYS - Reserved */
|
|
|
1903 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
1904 |
//#define RESERVED (0x0040) /* SYS - Reserved */
|
|
|
1905 |
//#define RESERVED (0x0080) /* SYS - Reserved */
|
|
|
1906 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
1907 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
1908 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
1909 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
1910 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
1911 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
1912 |
#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memeory disabled */
|
|
|
1913 |
#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */
|
|
|
1914 |
|
|
|
1915 |
/* SYSJMBC Control Bits */
|
|
|
1916 |
#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
|
|
|
1917 |
#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
|
|
|
1918 |
#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
|
|
|
1919 |
#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
|
|
|
1920 |
#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */
|
|
|
1921 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
1922 |
#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
|
|
|
1923 |
#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
|
|
|
1924 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
1925 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
1926 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
1927 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
1928 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
1929 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
1930 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
1931 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
1932 |
|
|
|
1933 |
/* SYSJMBC Control Bits */
|
|
|
1934 |
#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
|
|
|
1935 |
#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
|
|
|
1936 |
#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
|
|
|
1937 |
#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
|
|
|
1938 |
#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */
|
|
|
1939 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
1940 |
#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
|
|
|
1941 |
#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
|
|
|
1942 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
1943 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
1944 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
1945 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
1946 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
1947 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
1948 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
1949 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
1950 |
|
|
|
1951 |
/* SYSJMBC Control Bits */
|
|
|
1952 |
//#define RESERVED (0x0020) /* SYS - Reserved */
|
|
|
1953 |
//#define RESERVED (0x0100) /* SYS - Reserved */
|
|
|
1954 |
//#define RESERVED (0x0200) /* SYS - Reserved */
|
|
|
1955 |
//#define RESERVED (0x0400) /* SYS - Reserved */
|
|
|
1956 |
//#define RESERVED (0x0800) /* SYS - Reserved */
|
|
|
1957 |
//#define RESERVED (0x1000) /* SYS - Reserved */
|
|
|
1958 |
//#define RESERVED (0x2000) /* SYS - Reserved */
|
|
|
1959 |
//#define RESERVED (0x4000) /* SYS - Reserved */
|
|
|
1960 |
//#define RESERVED (0x8000) /* SYS - Reserved */
|
|
|
1961 |
|
|
|
1962 |
/* SYSUNIV Definitions */
|
|
|
1963 |
#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1964 |
#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */
|
|
|
1965 |
#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */
|
|
|
1966 |
#define SYSUNIV_ACCVIFG (0x0006) /* SYSUNIV : Access Violation - ACCVIFG */
|
|
|
1967 |
#define SYSUNIV_SYSBERRIV (0x0008) /* SYSUNIV : Bus Error - SYSBERRIV */
|
|
|
1968 |
|
|
|
1969 |
/* SYSSNIV Definitions */
|
|
|
1970 |
#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1971 |
#define SYSSNIV_SVMLIFG (0x0002) /* SYSSNIV : SVMLIFG */
|
|
|
1972 |
#define SYSSNIV_SVMHIFG (0x0004) /* SYSSNIV : SVMHIFG */
|
|
|
1973 |
#define SYSSNIV_DLYLIFG (0x0006) /* SYSSNIV : DLYLIFG */
|
|
|
1974 |
#define SYSSNIV_DLYHIFG (0x0008) /* SYSSNIV : DLYHIFG */
|
|
|
1975 |
#define SYSSNIV_VMAIFG (0x000A) /* SYSSNIV : VMAIFG */
|
|
|
1976 |
#define SYSSNIV_JMBINIFG (0x000C) /* SYSSNIV : JMBINIFG */
|
|
|
1977 |
#define SYSSNIV_JMBOUTIFG (0x000E) /* SYSSNIV : JMBOUTIFG */
|
|
|
1978 |
#define SYSSNIV_VLRLIFG (0x0010) /* SYSSNIV : VLRLIFG */
|
|
|
1979 |
#define SYSSNIV_VLRHIFG (0x0012) /* SYSSNIV : VLRHIFG */
|
|
|
1980 |
|
|
|
1981 |
/* SYSRSTIV Definitions */
|
|
|
1982 |
#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1983 |
#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */
|
|
|
1984 |
#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */
|
|
|
1985 |
#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */
|
|
|
1986 |
#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */
|
|
|
1987 |
#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */
|
|
|
1988 |
#define SYSRSTIV_SVSL (0x000C) /* SYSRSTIV : SVSL */
|
|
|
1989 |
#define SYSRSTIV_SVSH (0x000E) /* SYSRSTIV : SVSH */
|
|
|
1990 |
#define SYSRSTIV_SVML_OVP (0x0010) /* SYSRSTIV : SVML_OVP */
|
|
|
1991 |
#define SYSRSTIV_SVMH_OVP (0x0012) /* SYSRSTIV : SVMH_OVP */
|
|
|
1992 |
#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */
|
|
|
1993 |
#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */
|
|
|
1994 |
#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */
|
|
|
1995 |
#define SYSRSTIV_KEYV (0x001A) /* SYSRSTIV : Flash Key violation */
|
|
|
1996 |
#define SYSRSTIV_PLLUL (0x001C) /* SYSRSTIV : PLL unlock */
|
|
|
1997 |
#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */
|
|
|
1998 |
#define SYSRSTIV_PMMKEY (0x0020) /* SYSRSTIV : PMMKEY violation */
|
|
|
1999 |
|
|
|
2000 |
/************************************************************
|
|
|
2001 |
* Timer0_A3
|
|
|
2002 |
************************************************************/
|
|
|
2003 |
#define __MSP430_HAS_T0A3__ /* Definition to show that Module is available */
|
|
|
2004 |
#define __MSP430_BASEADDRESS_T0A3__ 0x03C0
|
|
|
2005 |
|
|
|
2006 |
SFR_16BIT(TA0CTL); /* Timer0_A3 Control */
|
|
|
2007 |
SFR_16BIT(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */
|
|
|
2008 |
SFR_16BIT(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */
|
|
|
2009 |
SFR_16BIT(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */
|
|
|
2010 |
SFR_16BIT(TA0R); /* Timer0_A3 */
|
|
|
2011 |
SFR_16BIT(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */
|
|
|
2012 |
SFR_16BIT(TA0CCR1); /* Timer0_A3 Capture/Compare 1 */
|
|
|
2013 |
SFR_16BIT(TA0CCR2); /* Timer0_A3 Capture/Compare 2 */
|
|
|
2014 |
SFR_16BIT(TA0IV); /* Timer0_A3 Interrupt Vector Word */
|
|
|
2015 |
SFR_16BIT(TA0EX0); /* Timer0_A3 Expansion Register 0 */
|
|
|
2016 |
|
|
|
2017 |
/* TAxCTL Control Bits */
|
|
|
2018 |
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
|
|
|
2019 |
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
|
|
|
2020 |
#define ID1 (0x0080) /* Timer A clock input divider 1 */
|
|
|
2021 |
#define ID0 (0x0040) /* Timer A clock input divider 0 */
|
|
|
2022 |
#define MC1 (0x0020) /* Timer A mode control 1 */
|
|
|
2023 |
#define MC0 (0x0010) /* Timer A mode control 0 */
|
|
|
2024 |
#define TACLR (0x0004) /* Timer A counter clear */
|
|
|
2025 |
#define TAIE (0x0002) /* Timer A counter interrupt enable */
|
|
|
2026 |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
|
|
|
2027 |
|
|
|
2028 |
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
2029 |
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
2030 |
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
2031 |
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
2032 |
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
2033 |
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
2034 |
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
2035 |
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
2036 |
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
2037 |
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
2038 |
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
2039 |
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
2040 |
#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
2041 |
#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
2042 |
#define MC__CONTINOUS (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
2043 |
#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
2044 |
#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
2045 |
#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
2046 |
#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
2047 |
#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
2048 |
#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
2049 |
#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
2050 |
#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
2051 |
#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
2052 |
|
|
|
2053 |
/* TAxCCTLx Control Bits */
|
|
|
2054 |
#define CM1 (0x8000) /* Capture mode 1 */
|
|
|
2055 |
#define CM0 (0x4000) /* Capture mode 0 */
|
|
|
2056 |
#define CCIS1 (0x2000) /* Capture input select 1 */
|
|
|
2057 |
#define CCIS0 (0x1000) /* Capture input select 0 */
|
|
|
2058 |
#define SCS (0x0800) /* Capture sychronize */
|
|
|
2059 |
#define SCCI (0x0400) /* Latched capture signal (read) */
|
|
|
2060 |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
|
|
|
2061 |
#define OUTMOD2 (0x0080) /* Output mode 2 */
|
|
|
2062 |
#define OUTMOD1 (0x0040) /* Output mode 1 */
|
|
|
2063 |
#define OUTMOD0 (0x0020) /* Output mode 0 */
|
|
|
2064 |
#define CCIE (0x0010) /* Capture/compare interrupt enable */
|
|
|
2065 |
#define CCI (0x0008) /* Capture input signal (read) */
|
|
|
2066 |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
|
|
|
2067 |
#define COV (0x0002) /* Capture/compare overflow flag */
|
|
|
2068 |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
|
|
|
2069 |
|
|
|
2070 |
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
|
|
|
2071 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
|
|
|
2072 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
|
|
|
2073 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
|
|
|
2074 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
|
|
|
2075 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
|
|
|
2076 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
|
|
|
2077 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
|
|
|
2078 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
|
|
|
2079 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
|
|
|
2080 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
|
|
|
2081 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
|
|
|
2082 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
|
|
|
2083 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
|
|
|
2084 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
|
|
|
2085 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
|
|
|
2086 |
|
|
|
2087 |
/* TAxEX0 Control Bits */
|
|
|
2088 |
#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */
|
|
|
2089 |
#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */
|
|
|
2090 |
#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */
|
|
|
2091 |
|
|
|
2092 |
#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */
|
|
|
2093 |
#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */
|
|
|
2094 |
#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */
|
|
|
2095 |
#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */
|
|
|
2096 |
#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */
|
|
|
2097 |
#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */
|
|
|
2098 |
#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */
|
|
|
2099 |
#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */
|
|
|
2100 |
|
|
|
2101 |
/* T0A3IV Definitions */
|
|
|
2102 |
#define TA0IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2103 |
#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */
|
|
|
2104 |
#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */
|
|
|
2105 |
#define TA0IV_3 (0x0006) /* Reserved */
|
|
|
2106 |
#define TA0IV_4 (0x0008) /* Reserved */
|
|
|
2107 |
#define TA0IV_5 (0x000A) /* Reserved */
|
|
|
2108 |
#define TA0IV_6 (0x000C) /* Reserved */
|
|
|
2109 |
#define TA0IV_TA0IFG (0x000E) /* TA0IFG */
|
|
|
2110 |
|
|
|
2111 |
/************************************************************
|
|
|
2112 |
* Timer0_D3
|
|
|
2113 |
************************************************************/
|
|
|
2114 |
#define __MSP430_HAS_T0D3__ /* Definition to show that Module is available */
|
|
|
2115 |
#define __MSP430_BASEADDRESS_T0D3__ 0x0B00
|
|
|
2116 |
|
|
|
2117 |
SFR_16BIT(TD0CTL0); /* Timer0_D3 Control 0 */
|
|
|
2118 |
SFR_16BIT(TD0CTL1); /* Timer0_D3 Control 1 */
|
|
|
2119 |
SFR_16BIT(TD0CTL2); /* Timer0_D3 Control 2 */
|
|
|
2120 |
SFR_16BIT(TD0R); /* Timer0_D3 Counter */
|
|
|
2121 |
SFR_16BIT(TD0CCTL0); /* Timer0_D3 Capture/Compare Control 0 */
|
|
|
2122 |
SFR_16BIT(TD0CCR0); /* Timer0_D3 Capture/Compare 0 */
|
|
|
2123 |
SFR_16BIT(TD0CL0); /* Timer0_D3 Capture/Compare Latch 0 */
|
|
|
2124 |
SFR_16BIT(TD0CCTL1); /* Timer0_D3 Capture/Compare Control 1 */
|
|
|
2125 |
SFR_16BIT(TD0CCR1); /* Timer0_D3 Capture/Compare 1 */
|
|
|
2126 |
SFR_16BIT(TD0CL1); /* Timer0_D3 Capture/Compare Latch 1 */
|
|
|
2127 |
SFR_16BIT(TD0CCTL2); /* Timer0_D3 Capture/Compare Control 2 */
|
|
|
2128 |
SFR_16BIT(TD0CCR2); /* Timer0_D3 Capture/Compare 2 */
|
|
|
2129 |
SFR_16BIT(TD0CL2); /* Timer0_D3 Capture/Compare Latch 2 */
|
|
|
2130 |
SFR_16BIT(TD0HCTL0); /* Timer0_D3 High-resolution Control Register 0 */
|
|
|
2131 |
SFR_16BIT(TD0HCTL1); /* Timer0_D3 High-resolution Control Register 1 */
|
|
|
2132 |
SFR_16BIT(TD0HINT); /* Timer0_D3 High-resolution Interrupt Register */
|
|
|
2133 |
SFR_16BIT(TD0IV); /* Timer0_D3 Interrupt Vector Word */
|
|
|
2134 |
|
|
|
2135 |
/* TDxCTL0 Control Bits */
|
|
|
2136 |
#define TDCLGRP1 (0x4000) /* Timer0_D3 Compare latch load group 1 */
|
|
|
2137 |
#define TDCLGRP0 (0x2000) /* Timer0_D3 Compare latch load group 0 */
|
|
|
2138 |
#define CNTL1 (0x1000) /* Counter lenght 1 */
|
|
|
2139 |
#define CNTL0 (0x0800) /* Counter lenght 0 */
|
|
|
2140 |
#define TDSSEL1 (0x0200) /* Clock source 1 */
|
|
|
2141 |
#define TDSSEL0 (0x0100) /* Clock source 0 */
|
|
|
2142 |
#define TDCLR (0x0004) /* Timer0_D3 counter clear */
|
|
|
2143 |
#define TDIE (0x0002) /* Timer0_D3 interrupt enable */
|
|
|
2144 |
#define TDIFG (0x0001) /* Timer0_D3 interrupt flag */
|
|
|
2145 |
|
|
|
2146 |
#define SHR1 (0x4000) /* Timer0_D3 Compare latch load group 1 */
|
|
|
2147 |
#define SHR0 (0x2000) /* Timer0_D3 Compare latch load group 0 */
|
|
|
2148 |
|
|
|
2149 |
#define TDSSEL_0 (0*0x0100u) /* Clock Source: TDCLK */
|
|
|
2150 |
#define TDSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
|
|
|
2151 |
#define TDSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
|
|
|
2152 |
#define TDSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
|
|
|
2153 |
#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
|
|
|
2154 |
#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
|
|
|
2155 |
#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
|
|
|
2156 |
#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
|
|
|
2157 |
#define SHR_0 (0*0x2000u) /* Timer0_D3 Group: 0 - individually */
|
|
|
2158 |
#define SHR_1 (1*0x2000u) /* Timer0_D3 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
2159 |
#define SHR_2 (2*0x2000u) /* Timer0_D3 Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
2160 |
#define SHR_3 (3*0x2000u) /* Timer0_D3 Group: 3 - 1 group (all) */
|
|
|
2161 |
#define TDCLGRP_0 (0*0x2000u) /* Timer0_D3 Group: 0 - individually */
|
|
|
2162 |
#define TDCLGRP_1 (1*0x2000u) /* Timer0_D3 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
2163 |
#define TDCLGRP_2 (2*0x2000u) /* Timer0_D3 Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
2164 |
#define TDCLGRP_3 (3*0x2000u) /* Timer0_D3 Group: 3 - 1 group (all) */
|
|
|
2165 |
#define TDSSEL__TACLK (0*0x0100u) /* Timer0_D3 clock source select: 0 - TACLK */
|
|
|
2166 |
#define TDSSEL__ACLK (1*0x0100u) /* Timer0_D3 clock source select: 1 - ACLK */
|
|
|
2167 |
#define TDSSEL__SMCLK (2*0x0100u) /* Timer0_D3 clock source select: 2 - SMCLK */
|
|
|
2168 |
#define TDSSEL__INCLK (3*0x0100u) /* Timer0_D3 clock source select: 3 - INCLK */
|
|
|
2169 |
#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */
|
|
|
2170 |
#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */
|
|
|
2171 |
#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */
|
|
|
2172 |
#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */
|
|
|
2173 |
|
|
|
2174 |
/* Additional Timer B Control Register bits are defined in Timer A */
|
|
|
2175 |
|
|
|
2176 |
/* TDxCTL1 Control Bits */
|
|
|
2177 |
#define TDCLKM0 (0x0001) /* Timer0_D3 Clocking Mode Bit: 0 */
|
|
|
2178 |
#define TDCLKM1 (0x0002) /* Timer0_D3 Clocking Mode Bit: 1 */
|
|
|
2179 |
#define TD2CMB (0x0010) /* Timer0_D3 TD0CCR Combination in TD2 */
|
|
|
2180 |
#define TD4CMB (0x0020) /* Timer0_D3 TD0CCR Combination in TD4 */
|
|
|
2181 |
#define TD6CMB (0x0040) /* Timer0_D3 TD0CCR Combination in TD6 */
|
|
|
2182 |
#define TDIDEX0 (0x0100) /* Timer0_D3 Input divider expansion Bit: 0 */
|
|
|
2183 |
#define TDIDEX1 (0x0200) /* Timer0_D3 Input divider expansion Bit: 1 */
|
|
|
2184 |
#define TDIDEX2 (0x0400) /* Timer0_D3 Input divider expansion Bit: 2 */
|
|
|
2185 |
|
|
|
2186 |
#define TDCLKM_0 (0x0000) /* Timer0_D3 Clocking Mode: External */
|
|
|
2187 |
#define TDCLKM_1 (0x0001) /* Timer0_D3 Clocking Mode: High-Res. local clock */
|
|
|
2188 |
#define TDCLKM_2 (0x0002) /* Timer0_D3 Clocking Mode: Aux Clock */
|
|
|
2189 |
#define TDCLKM__EXT (0x0000) /* Timer0_D3 Clocking Mode: External */
|
|
|
2190 |
#define TDCLKM__HIGHRES (0x0001) /* Timer0_D3 Clocking Mode: High-Res. local clock */
|
|
|
2191 |
#define TDCLKM__AUX (0x0002) /* Timer0_D3 Clocking Mode: Aux Clock */
|
|
|
2192 |
|
|
|
2193 |
#define TDIDEX_0 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */
|
|
|
2194 |
#define TDIDEX_1 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */
|
|
|
2195 |
#define TDIDEX_2 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */
|
|
|
2196 |
#define TDIDEX_3 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */
|
|
|
2197 |
#define TDIDEX_4 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */
|
|
|
2198 |
#define TDIDEX_5 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */
|
|
|
2199 |
#define TDIDEX_6 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */
|
|
|
2200 |
#define TDIDEX_7 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */
|
|
|
2201 |
#define TDIDEX__1 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */
|
|
|
2202 |
#define TDIDEX__2 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */
|
|
|
2203 |
#define TDIDEX__3 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */
|
|
|
2204 |
#define TDIDEX__4 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */
|
|
|
2205 |
#define TDIDEX__5 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */
|
|
|
2206 |
#define TDIDEX__6 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */
|
|
|
2207 |
#define TDIDEX__7 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */
|
|
|
2208 |
#define TDIDEX__8 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */
|
|
|
2209 |
|
|
|
2210 |
/* TDxCTL2 Control Bits */
|
|
|
2211 |
#define TDCAPM0 (0x0001) /* Timer0_D3 Capture Mode of Channel 0 */
|
|
|
2212 |
#define TDCAPM1 (0x0002) /* Timer0_D3 Capture Mode of Channel 1 */
|
|
|
2213 |
#define TDCAPM2 (0x0004) /* Timer0_D3 Capture Mode of Channel 2 */
|
|
|
2214 |
#define TDCAPM3 (0x0008) /* Timer0_D3 Capture Mode of Channel 3 */
|
|
|
2215 |
#define TDCAPM4 (0x0010) /* Timer0_D3 Capture Mode of Channel 4 */
|
|
|
2216 |
#define TDCAPM5 (0x0020) /* Timer0_D3 Capture Mode of Channel 5 */
|
|
|
2217 |
#define TDCAPM6 (0x0040) /* Timer0_D3 Capture Mode of Channel 6 */
|
|
|
2218 |
|
|
|
2219 |
/* TDxCCTLx Control Bits */
|
|
|
2220 |
#define CLLD1 (0x0400) /* Compare latch load source 1 */
|
|
|
2221 |
#define CLLD0 (0x0200) /* Compare latch load source 0 */
|
|
|
2222 |
|
|
|
2223 |
#define SLSHR1 (0x0400) /* Compare latch load source 1 */
|
|
|
2224 |
#define SLSHR0 (0x0200) /* Compare latch load source 0 */
|
|
|
2225 |
|
|
|
2226 |
#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
2227 |
#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */
|
|
|
2228 |
#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
2229 |
#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */
|
|
|
2230 |
|
|
|
2231 |
#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
2232 |
#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */
|
|
|
2233 |
#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
2234 |
#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */
|
|
|
2235 |
|
|
|
2236 |
/* TDxHCTL0 Control Bits */
|
|
|
2237 |
#define TDHEN (0x0001) /* Timer0_D3 High-Resolution Enable */
|
|
|
2238 |
#define TDHREGEN (0x0002) /* Timer0_D3 High-Resolution Regulated Mode */
|
|
|
2239 |
#define TDHEAEN (0x0004) /* Timer0_D3 High-Resolution clock error accum. enable */
|
|
|
2240 |
#define TDHRON (0x0008) /* Timer0_D3 High-Resolution Generator forced on*/
|
|
|
2241 |
#define TDHM0 (0x0010) /* Timer0_D3 High-Resoltuion Clock Mult. Bit: 0 */
|
|
|
2242 |
#define TDHM1 (0x0020) /* Timer0_D3 High-Resoltuion Clock Mult. Bit: 1 */
|
|
|
2243 |
#define TDHD0 (0x0040) /* Timer0_D3 High-Resolution clock divider Bit: 0 */
|
|
|
2244 |
#define TDHD1 (0x0080) /* Timer0_D3 High-Resolution clock divider Bit: 1 */
|
|
|
2245 |
#define TDHFW (0x0100) /* Timer0_D7 High-resolution generator fast wakeup enable */
|
|
|
2246 |
|
|
|
2247 |
#define TDHCALEN TDHREGEN /* Timer0_D3 Lagacy Definition */
|
|
|
2248 |
|
|
|
2249 |
#define TDHM_0 (0x0000) /* Timer0_D3 High-Resoltuion Clock Mult.: 8x TimerD clock */
|
|
|
2250 |
#define TDHM_1 (0x0010) /* Timer0_D3 High-Resoltuion Clock Mult.: 16x TimerD clock */
|
|
|
2251 |
#define TDHM__8 (0x0000) /* Timer0_D3 High-Resoltuion Clock Mult.: 8x TimerD clock */
|
|
|
2252 |
#define TDHM__16 (0x0010) /* Timer0_D3 High-Resoltuion Clock Mult.: 16x TimerD clock */
|
|
|
2253 |
#define TDHD_0 (0x0000) /* Timer0_D3 High-Resolution clock divider: /1 */
|
|
|
2254 |
#define TDHD_1 (0x0040) /* Timer0_D3 High-Resolution clock divider: /2 */
|
|
|
2255 |
#define TDHD_2 (0x0080) /* Timer0_D3 High-Resolution clock divider: /4 */
|
|
|
2256 |
#define TDHD_3 (0x00C0) /* Timer0_D3 High-Resolution clock divider: /8 */
|
|
|
2257 |
#define TDHD__1 (0x0000) /* Timer0_D3 High-Resolution clock divider: /1 */
|
|
|
2258 |
#define TDHD__2 (0x0040) /* Timer0_D3 High-Resolution clock divider: /2 */
|
|
|
2259 |
#define TDHD__4 (0x0080) /* Timer0_D3 High-Resolution clock divider: /4 */
|
|
|
2260 |
#define TDHD__8 (0x00C0) /* Timer0_D3 High-Resolution clock divider: /8 */
|
|
|
2261 |
|
|
|
2262 |
/* TDxHCTL1 Control Bits */
|
|
|
2263 |
#define TDHCLKTRIM0 (0x0002) /* Timer0_D3 High-Resolution Clock Trim Bit: 0 */
|
|
|
2264 |
#define TDHCLKTRIM1 (0x0004) /* Timer0_D3 High-Resolution Clock Trim Bit: 1 */
|
|
|
2265 |
#define TDHCLKTRIM2 (0x0008) /* Timer0_D3 High-Resolution Clock Trim Bit: 2 */
|
|
|
2266 |
#define TDHCLKTRIM3 (0x0010) /* Timer0_D3 High-Resolution Clock Trim Bit: 3 */
|
|
|
2267 |
#define TDHCLKTRIM4 (0x0020) /* Timer0_D3 High-Resolution Clock Trim Bit: 4 */
|
|
|
2268 |
#define TDHCLKTRIM5 (0x0040) /* Timer0_D3 High-Resolution Clock Trim Bit: 5 */
|
|
|
2269 |
#define TDHCLKTRIM6 (0x0080) /* Timer0_D3 High-Resolution Clock Trim Bit: 6 */
|
|
|
2270 |
#define TDHCLKSR0 (0x0100) /* Timer0_D3 High-Resolution Clock Sub-Range Bit: 0 */
|
|
|
2271 |
#define TDHCLKSR1 (0x0200) /* Timer0_D3 High-Resolution Clock Sub-Range Bit: 1 */
|
|
|
2272 |
#define TDHCLKSR2 (0x0400) /* Timer0_D3 High-Resolution Clock Sub-Range Bit: 2 */
|
|
|
2273 |
#define TDHCLKSR3 (0x0800) /* Timer0_D3 High-Resolution Clock Sub-Range Bit: 3 */
|
|
|
2274 |
#define TDHCLKSR4 (0x1000) /* Timer0_D3 High-Resolution Clock Sub-Range Bit: 4 */
|
|
|
2275 |
#define TDHCLKR0 (0x2000) /* Timer0_D3 High-Resolution Clock Range Bit: 0 */
|
|
|
2276 |
#define TDHCLKR1 (0x4000) /* Timer0_D3 High-Resolution Clock Range Bit: 1 */
|
|
|
2277 |
#define TDHCLKCR (0x8000) /* Timer0_D3 High-Resolution Coarse Clock Range */
|
|
|
2278 |
|
|
|
2279 |
/* TDxHINT Control Bits */
|
|
|
2280 |
#define TDHFLIFG (0x0001) /* Timer0_D3 High-Res. fail low Interrupt Flag */
|
|
|
2281 |
#define TDHFHIFG (0x0002) /* Timer0_D3 High-Res. fail high Interrupt Flag */
|
|
|
2282 |
#define TDHLKIFG (0x0004) /* Timer0_D3 High-Res. frequency lock Interrupt Flag */
|
|
|
2283 |
#define TDHUNLKIFG (0x0008) /* Timer0_D3 High-Res. frequency unlock Interrupt Flag */
|
|
|
2284 |
#define TDHFLIE (0x0100) /* Timer0_D3 High-Res. fail low Interrupt Enable */
|
|
|
2285 |
#define TDHFHIE (0x0200) /* Timer0_D3 High-Res. fail high Interrupt Enable */
|
|
|
2286 |
#define TDHLKIE (0x0400) /* Timer0_D3 High-Res. frequency lock Interrupt Enable */
|
|
|
2287 |
#define TDHUNLKIE (0x0800) /* Timer0_D3 High-Res. frequency unlock Interrupt Enable */
|
|
|
2288 |
|
|
|
2289 |
/* TD0IV Definitions */
|
|
|
2290 |
#define TD0IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2291 |
#define TD0IV_TD0CCR1 (0x0002) /* TD0CCR1_CCIFG */
|
|
|
2292 |
#define TD0IV_TD0CCR2 (0x0004) /* TD0CCR2_CCIFG */
|
|
|
2293 |
#define TD0IV_TD0CCR3 (0x0006) /* TD0CCR3_CCIFG */
|
|
|
2294 |
#define TD0IV_TD0CCR4 (0x0008) /* TD0CCR4_CCIFG */
|
|
|
2295 |
#define TD0IV_TD0CCR5 (0x000A) /* TD0CCR5_CCIFG */
|
|
|
2296 |
#define TD0IV_TD0CCR6 (0x000C) /* TD0CCR6_CCIFG */
|
|
|
2297 |
#define TD0IV_RES_14 (0x000E) /* Reserverd */
|
|
|
2298 |
#define TD0IV_TD0IFG (0x0010) /* TD0IFG */
|
|
|
2299 |
#define TD0IV_TDHFLIFG (0x0012) /* TDHFLIFG Clock fail low */
|
|
|
2300 |
#define TD0IV_TDHFHIFG (0x0014) /* TDHFLIFG Clock fail high */
|
|
|
2301 |
#define TD0IV_TDHLKIFG (0x0016) /* TDHLKIE Clock lock*/
|
|
|
2302 |
#define TD0IV_TDHUNLKIFG (0x0018) /* TDHUNLKIE Clock unlock */
|
|
|
2303 |
|
|
|
2304 |
|
|
|
2305 |
/************************************************************
|
|
|
2306 |
* Timer1_D3
|
|
|
2307 |
************************************************************/
|
|
|
2308 |
#define __MSP430_HAS_T1D3__ /* Definition to show that Module is available */
|
|
|
2309 |
#define __MSP430_BASEADDRESS_T1D3__ 0x0B40
|
|
|
2310 |
|
|
|
2311 |
SFR_16BIT(TD1CTL0); /* Timer1_D3 Control 0 */
|
|
|
2312 |
SFR_16BIT(TD1CTL1); /* Timer1_D3 Control 1 */
|
|
|
2313 |
SFR_16BIT(TD1CTL2); /* Timer1_D3 Control 2 */
|
|
|
2314 |
SFR_16BIT(TD1R); /* Timer1_D3 Counter */
|
|
|
2315 |
SFR_16BIT(TD1CCTL0); /* Timer1_D3 Capture/Compare Control 0 */
|
|
|
2316 |
SFR_16BIT(TD1CCR0); /* Timer1_D3 Capture/Compare 0 */
|
|
|
2317 |
SFR_16BIT(TD1CL0); /* Timer1_D3 Capture/Compare Latch 0 */
|
|
|
2318 |
SFR_16BIT(TD1CCTL1); /* Timer1_D3 Capture/Compare Control 1 */
|
|
|
2319 |
SFR_16BIT(TD1CCR1); /* Timer1_D3 Capture/Compare 1 */
|
|
|
2320 |
SFR_16BIT(TD1CL1); /* Timer1_D3 Capture/Compare Latch 1 */
|
|
|
2321 |
SFR_16BIT(TD1CCTL2); /* Timer1_D3 Capture/Compare Control 2 */
|
|
|
2322 |
SFR_16BIT(TD1CCR2); /* Timer1_D3 Capture/Compare 2 */
|
|
|
2323 |
SFR_16BIT(TD1CL2); /* Timer1_D3 Capture/Compare Latch 2 */
|
|
|
2324 |
SFR_16BIT(TD1HCTL0); /* Timer1_D3 High-resolution Control Register 0 */
|
|
|
2325 |
SFR_16BIT(TD1HCTL1); /* Timer1_D3 High-resolution Control Register 1 */
|
|
|
2326 |
SFR_16BIT(TD1HINT); /* Timer1_D3 High-resolution Interrupt Register */
|
|
|
2327 |
SFR_16BIT(TD1IV); /* Timer1_D3 Interrupt Vector Word */
|
|
|
2328 |
|
|
|
2329 |
/* Bits are already defined within the Timer0_Dx */
|
|
|
2330 |
|
|
|
2331 |
/* TD1IV Definitions */
|
|
|
2332 |
#define TD1IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2333 |
#define TD1IV_TD1CCR1 (0x0002) /* TD1CCR1_CCIFG */
|
|
|
2334 |
#define TD1IV_TD1CCR2 (0x0004) /* TD1CCR2_CCIFG */
|
|
|
2335 |
#define TD1IV_TD1CCR3 (0x0006) /* TD1CCR3_CCIFG */
|
|
|
2336 |
#define TD1IV_TD1CCR4 (0x0008) /* TD1CCR4_CCIFG */
|
|
|
2337 |
#define TD1IV_TD1CCR5 (0x000A) /* TD1CCR5_CCIFG */
|
|
|
2338 |
#define TD1IV_TD1CCR6 (0x000C) /* TD1CCR6_CCIFG */
|
|
|
2339 |
#define TD1IV_RES_14 (0x000E) /* Reserverd */
|
|
|
2340 |
#define TD1IV_TD1IFG (0x0010) /* TD1IFG */
|
|
|
2341 |
#define TD1IV_TDHFLIFG (0x0012) /* TDHFLIFG Clock fail low */
|
|
|
2342 |
#define TD1IV_TDHFHIFG (0x0014) /* TDHFLIFG Clock fail high */
|
|
|
2343 |
#define TD1IV_TDHLKIFG (0x0016) /* TDHLKIE Clock lock*/
|
|
|
2344 |
#define TD1IV_TDHUNLKIFG (0x0018) /* TDHUNLKIE Clock unlock */
|
|
|
2345 |
|
|
|
2346 |
/************************************************************
|
|
|
2347 |
* Timer Event Control 0
|
|
|
2348 |
************************************************************/
|
|
|
2349 |
#define __MSP430_HAS_TEV0__ /* Definition to show that Module is available */
|
|
|
2350 |
#define __MSP430_BASEADDRESS_TEV0__ 0x0C00
|
|
|
2351 |
|
|
|
2352 |
SFR_16BIT(TEC0XCTL0); /* Timer Event Control 0 External Control 0 */
|
|
|
2353 |
SFR_8BIT(TEC0XCTL0_L); /* Timer Event Control 0 External Control 0 */
|
|
|
2354 |
SFR_8BIT(TEC0XCTL0_H); /* Timer Event Control 0 External Control 0 */
|
|
|
2355 |
SFR_16BIT(TEC0XCTL1); /* Timer Event Control 0 External Control 1 */
|
|
|
2356 |
SFR_8BIT(TEC0XCTL1_L); /* Timer Event Control 0 External Control 1 */
|
|
|
2357 |
SFR_8BIT(TEC0XCTL1_H); /* Timer Event Control 0 External Control 1 */
|
|
|
2358 |
SFR_16BIT(TEC0XCTL2); /* Timer Event Control 0 External Control 2 */
|
|
|
2359 |
SFR_8BIT(TEC0XCTL2_L); /* Timer Event Control 0 External Control 2 */
|
|
|
2360 |
SFR_8BIT(TEC0XCTL2_H); /* Timer Event Control 0 External Control 2 */
|
|
|
2361 |
SFR_16BIT(TEC0STA); /* Timer Event Control 0 Status */
|
|
|
2362 |
SFR_8BIT(TEC0STA_L); /* Timer Event Control 0 Status */
|
|
|
2363 |
SFR_8BIT(TEC0STA_H); /* Timer Event Control 0 Status */
|
|
|
2364 |
SFR_16BIT(TEC0XINT); /* Timer Event Control 0 External Interrupt */
|
|
|
2365 |
SFR_8BIT(TEC0XINT_L); /* Timer Event Control 0 External Interrupt */
|
|
|
2366 |
SFR_8BIT(TEC0XINT_H); /* Timer Event Control 0 External Interrupt */
|
|
|
2367 |
SFR_16BIT(TEC0IV); /* Timer Event Control 0 Interrupt Vector */
|
|
|
2368 |
SFR_8BIT(TEC0IV_L); /* Timer Event Control 0 Interrupt Vector */
|
|
|
2369 |
SFR_8BIT(TEC0IV_H); /* Timer Event Control 0 Interrupt Vector */
|
|
|
2370 |
|
|
|
2371 |
/* TECxXCTL0 Control Bits */
|
|
|
2372 |
#define TECXFLTHLD0 (0x0001) /* TEV Ext. fault signal hold for CE0 */
|
|
|
2373 |
#define TECXFLTHLD1 (0x0002) /* TEV Ext. fault signal hold for CE1 */
|
|
|
2374 |
#define TECXFLTHLD2 (0x0004) /* TEV Ext. fault signal hold for CE2 */
|
|
|
2375 |
#define TECXFLTHLD3 (0x0008) /* TEV Ext. fault signal hold for CE3 */
|
|
|
2376 |
#define TECXFLTHLD4 (0x0010) /* TEV Ext. fault signal hold for CE4 */
|
|
|
2377 |
#define TECXFLTHLD5 (0x0020) /* TEV Ext. fault signal hold for CE5 */
|
|
|
2378 |
#define TECXFLTHLD6 (0x0040) /* TEV Ext. fault signal hold for CE6 */
|
|
|
2379 |
#define TECXFLTEN0 (0x0100) /* TEV Ext. fault signal enable for CE0 */
|
|
|
2380 |
#define TECXFLTEN1 (0x0200) /* TEV Ext. fault signal enable for CE1 */
|
|
|
2381 |
#define TECXFLTEN2 (0x0400) /* TEV Ext. fault signal enable for CE2 */
|
|
|
2382 |
#define TECXFLTEN3 (0x0800) /* TEV Ext. fault signal enable for CE3 */
|
|
|
2383 |
#define TECXFLTEN4 (0x1000) /* TEV Ext. fault signal enable for CE4 */
|
|
|
2384 |
#define TECXFLTEN5 (0x2000) /* TEV Ext. fault signal enable for CE5 */
|
|
|
2385 |
#define TECXFLTEN6 (0x4000) /* TEV Ext. fault signal enable for CE6 */
|
|
|
2386 |
|
|
|
2387 |
/* TECxXCTL0 Control Bits */
|
|
|
2388 |
#define TECXFLTHLD0_L (0x0001) /* TEV Ext. fault signal hold for CE0 */
|
|
|
2389 |
#define TECXFLTHLD1_L (0x0002) /* TEV Ext. fault signal hold for CE1 */
|
|
|
2390 |
#define TECXFLTHLD2_L (0x0004) /* TEV Ext. fault signal hold for CE2 */
|
|
|
2391 |
#define TECXFLTHLD3_L (0x0008) /* TEV Ext. fault signal hold for CE3 */
|
|
|
2392 |
#define TECXFLTHLD4_L (0x0010) /* TEV Ext. fault signal hold for CE4 */
|
|
|
2393 |
#define TECXFLTHLD5_L (0x0020) /* TEV Ext. fault signal hold for CE5 */
|
|
|
2394 |
#define TECXFLTHLD6_L (0x0040) /* TEV Ext. fault signal hold for CE6 */
|
|
|
2395 |
|
|
|
2396 |
/* TECxXCTL0 Control Bits */
|
|
|
2397 |
#define TECXFLTEN0_H (0x0001) /* TEV Ext. fault signal enable for CE0 */
|
|
|
2398 |
#define TECXFLTEN1_H (0x0002) /* TEV Ext. fault signal enable for CE1 */
|
|
|
2399 |
#define TECXFLTEN2_H (0x0004) /* TEV Ext. fault signal enable for CE2 */
|
|
|
2400 |
#define TECXFLTEN3_H (0x0008) /* TEV Ext. fault signal enable for CE3 */
|
|
|
2401 |
#define TECXFLTEN4_H (0x0010) /* TEV Ext. fault signal enable for CE4 */
|
|
|
2402 |
#define TECXFLTEN5_H (0x0020) /* TEV Ext. fault signal enable for CE5 */
|
|
|
2403 |
#define TECXFLTEN6_H (0x0040) /* TEV Ext. fault signal enable for CE6 */
|
|
|
2404 |
|
|
|
2405 |
/* TECxXCTL1 Control Bits */
|
|
|
2406 |
#define TECXFLTPOL0 (0x0001) /* TEV Polarity Bit of ext. fault 0 */
|
|
|
2407 |
#define TECXFLTPOL1 (0x0002) /* TEV Polarity Bit of ext. fault 1 */
|
|
|
2408 |
#define TECXFLTPOL2 (0x0004) /* TEV Polarity Bit of ext. fault 2 */
|
|
|
2409 |
#define TECXFLTPOL3 (0x0008) /* TEV Polarity Bit of ext. fault 3 */
|
|
|
2410 |
#define TECXFLTPOL4 (0x0010) /* TEV Polarity Bit of ext. fault 4 */
|
|
|
2411 |
#define TECXFLTPOL5 (0x0020) /* TEV Polarity Bit of ext. fault 5 */
|
|
|
2412 |
#define TECXFLTPOL6 (0x0040) /* TEV Polarity Bit of ext. fault 6 */
|
|
|
2413 |
#define TECXFLTLVS0 (0x0100) /* TEV Signal Type of Ext. fault 0 */
|
|
|
2414 |
#define TECXFLTLVS1 (0x0200) /* TEV Signal Type of Ext. fault 1 */
|
|
|
2415 |
#define TECXFLTLVS2 (0x0400) /* TEV Signal Type of Ext. fault 2 */
|
|
|
2416 |
#define TECXFLTLVS3 (0x0800) /* TEV Signal Type of Ext. fault 3 */
|
|
|
2417 |
#define TECXFLTLVS4 (0x1000) /* TEV Signal Type of Ext. fault 4 */
|
|
|
2418 |
#define TECXFLTLVS5 (0x2000) /* TEV Signal Type of Ext. fault 5 */
|
|
|
2419 |
#define TECXFLTLVS6 (0x4000) /* TEV Signal Type of Ext. fault 6 */
|
|
|
2420 |
|
|
|
2421 |
/* TECxXCTL1 Control Bits */
|
|
|
2422 |
#define TECXFLTPOL0_L (0x0001) /* TEV Polarity Bit of ext. fault 0 */
|
|
|
2423 |
#define TECXFLTPOL1_L (0x0002) /* TEV Polarity Bit of ext. fault 1 */
|
|
|
2424 |
#define TECXFLTPOL2_L (0x0004) /* TEV Polarity Bit of ext. fault 2 */
|
|
|
2425 |
#define TECXFLTPOL3_L (0x0008) /* TEV Polarity Bit of ext. fault 3 */
|
|
|
2426 |
#define TECXFLTPOL4_L (0x0010) /* TEV Polarity Bit of ext. fault 4 */
|
|
|
2427 |
#define TECXFLTPOL5_L (0x0020) /* TEV Polarity Bit of ext. fault 5 */
|
|
|
2428 |
#define TECXFLTPOL6_L (0x0040) /* TEV Polarity Bit of ext. fault 6 */
|
|
|
2429 |
|
|
|
2430 |
/* TECxXCTL1 Control Bits */
|
|
|
2431 |
#define TECXFLTLVS0_H (0x0001) /* TEV Signal Type of Ext. fault 0 */
|
|
|
2432 |
#define TECXFLTLVS1_H (0x0002) /* TEV Signal Type of Ext. fault 1 */
|
|
|
2433 |
#define TECXFLTLVS2_H (0x0004) /* TEV Signal Type of Ext. fault 2 */
|
|
|
2434 |
#define TECXFLTLVS3_H (0x0008) /* TEV Signal Type of Ext. fault 3 */
|
|
|
2435 |
#define TECXFLTLVS4_H (0x0010) /* TEV Signal Type of Ext. fault 4 */
|
|
|
2436 |
#define TECXFLTLVS5_H (0x0020) /* TEV Signal Type of Ext. fault 5 */
|
|
|
2437 |
#define TECXFLTLVS6_H (0x0040) /* TEV Signal Type of Ext. fault 6 */
|
|
|
2438 |
|
|
|
2439 |
/* TECxXCTL2 Control Bits */
|
|
|
2440 |
#define TECCLKSEL0 (0x0001) /* TEV Aux. Clock Select Bit: 0 */
|
|
|
2441 |
#define TECCLKSEL1 (0x0002) /* TEV Aux. Clock Select Bit: 1 */
|
|
|
2442 |
#define TECAXCLREN (0x0004) /* TEV Auxilary clear signal control */
|
|
|
2443 |
#define TECEXCLREN (0x0008) /* TEV Ext. clear signal control */
|
|
|
2444 |
#define TECEXCLRHLD (0x0010) /* TEV External clear signal hold bit */
|
|
|
2445 |
#define TECEXCLRPOL (0x0020) /* TEV Polarity Bit of ext. clear */
|
|
|
2446 |
#define TECEXCLRLVS (0x0040) /* TEV Signal Type of Ext. clear */
|
|
|
2447 |
|
|
|
2448 |
/* TECxXCTL2 Control Bits */
|
|
|
2449 |
#define TECCLKSEL0_L (0x0001) /* TEV Aux. Clock Select Bit: 0 */
|
|
|
2450 |
#define TECCLKSEL1_L (0x0002) /* TEV Aux. Clock Select Bit: 1 */
|
|
|
2451 |
#define TECAXCLREN_L (0x0004) /* TEV Auxilary clear signal control */
|
|
|
2452 |
#define TECEXCLREN_L (0x0008) /* TEV Ext. clear signal control */
|
|
|
2453 |
#define TECEXCLRHLD_L (0x0010) /* TEV External clear signal hold bit */
|
|
|
2454 |
#define TECEXCLRPOL_L (0x0020) /* TEV Polarity Bit of ext. clear */
|
|
|
2455 |
#define TECEXCLRLVS_L (0x0040) /* TEV Signal Type of Ext. clear */
|
|
|
2456 |
|
|
|
2457 |
/* TECxXCTL2 Control Bits */
|
|
|
2458 |
|
|
|
2459 |
#define TECCLKSEL_0 (0x0000) /* TEV Aux. Clock Select: CLK0 */
|
|
|
2460 |
#define TECCLKSEL_1 (0x0001) /* TEV Aux. Clock Select: CLK1 */
|
|
|
2461 |
#define TECCLKSEL_2 (0x0002) /* TEV Aux. Clock Select: CLK2 */
|
|
|
2462 |
#define TECCLKSEL_3 (0x0003) /* TEV Aux. Clock Select: CLK3 */
|
|
|
2463 |
|
|
|
2464 |
/* TECxSTA Control Bits */
|
|
|
2465 |
#define TECXFLT0STA (0x0001) /* TEV External fault status flag for CE0 */
|
|
|
2466 |
#define TECXFLT1STA (0x0002) /* TEV External fault status flag for CE1 */
|
|
|
2467 |
#define TECXFLT2STA (0x0004) /* TEV External fault status flag for CE2 */
|
|
|
2468 |
#define TECXFLT3STA (0x0008) /* TEV External fault status flag for CE3 */
|
|
|
2469 |
#define TECXFLT4STA (0x0010) /* TEV External fault status flag for CE4 */
|
|
|
2470 |
#define TECXFLT5STA (0x0020) /* TEV External fault status flag for CE5 */
|
|
|
2471 |
#define TECXFLT6STA (0x0040) /* TEV External fault status flag for CE6 */
|
|
|
2472 |
#define TECXCLRSTA (0x0100) /* TEC External clear status flag */
|
|
|
2473 |
|
|
|
2474 |
/* TECxSTA Control Bits */
|
|
|
2475 |
#define TECXFLT0STA_L (0x0001) /* TEV External fault status flag for CE0 */
|
|
|
2476 |
#define TECXFLT1STA_L (0x0002) /* TEV External fault status flag for CE1 */
|
|
|
2477 |
#define TECXFLT2STA_L (0x0004) /* TEV External fault status flag for CE2 */
|
|
|
2478 |
#define TECXFLT3STA_L (0x0008) /* TEV External fault status flag for CE3 */
|
|
|
2479 |
#define TECXFLT4STA_L (0x0010) /* TEV External fault status flag for CE4 */
|
|
|
2480 |
#define TECXFLT5STA_L (0x0020) /* TEV External fault status flag for CE5 */
|
|
|
2481 |
#define TECXFLT6STA_L (0x0040) /* TEV External fault status flag for CE6 */
|
|
|
2482 |
|
|
|
2483 |
/* TECxSTA Control Bits */
|
|
|
2484 |
#define TECXCLRSTA_H (0x0001) /* TEC External clear status flag */
|
|
|
2485 |
|
|
|
2486 |
/* TECxXINT Control Bits */
|
|
|
2487 |
#define TECAXCLRIFG (0x0001) /* TEC Aux. Clear Interrupt Flag */
|
|
|
2488 |
#define TECEXCLRIFG (0x0002) /* TEC External Clear Interrupt Flag */
|
|
|
2489 |
#define TECXFLTIFG (0x0004) /* TEC External Fault Interrupt Flag */
|
|
|
2490 |
#define TECAXCLRIE (0x0100) /* TEC Aux. Clear Interrupt Enable */
|
|
|
2491 |
#define TECEXCLRIE (0x0200) /* TEC External Clear Interrupt Enable */
|
|
|
2492 |
#define TECXFLTIE (0x0400) /* TEC External Fault Interrupt Enable */
|
|
|
2493 |
|
|
|
2494 |
/* TECxXINT Control Bits */
|
|
|
2495 |
#define TECAXCLRIFG_L (0x0001) /* TEC Aux. Clear Interrupt Flag */
|
|
|
2496 |
#define TECEXCLRIFG_L (0x0002) /* TEC External Clear Interrupt Flag */
|
|
|
2497 |
#define TECXFLTIFG_L (0x0004) /* TEC External Fault Interrupt Flag */
|
|
|
2498 |
|
|
|
2499 |
/* TECxXINT Control Bits */
|
|
|
2500 |
#define TECAXCLRIE_H (0x0001) /* TEC Aux. Clear Interrupt Enable */
|
|
|
2501 |
#define TECEXCLRIE_H (0x0002) /* TEC External Clear Interrupt Enable */
|
|
|
2502 |
#define TECXFLTIE_H (0x0004) /* TEC External Fault Interrupt Enable */
|
|
|
2503 |
|
|
|
2504 |
/* TEC0IV Definitions */
|
|
|
2505 |
#define TEC0IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2506 |
#define TEC0IV_TECXFLTIFG (0x0002) /* TEC0XFLTIFG */
|
|
|
2507 |
#define TEC0IV_TECEXCLRIFG (0x0004) /* TEC0EXCLRIFG */
|
|
|
2508 |
#define TEC0IV_TECAXCLRIFG (0x0006) /* TEC0AXCLRIFG */
|
|
|
2509 |
|
|
|
2510 |
/************************************************************
|
|
|
2511 |
* Timer Event Control 1
|
|
|
2512 |
************************************************************/
|
|
|
2513 |
#define __MSP430_HAS_TEV1__ /* Definition to show that Module is available */
|
|
|
2514 |
#define __MSP430_BASEADDRESS_TEV1__ 0x0C20
|
|
|
2515 |
|
|
|
2516 |
SFR_16BIT(TEC1XCTL0); /* Timer Event Control 1 External Control 0 */
|
|
|
2517 |
SFR_8BIT(TEC1XCTL0_L); /* Timer Event Control 1 External Control 0 */
|
|
|
2518 |
SFR_8BIT(TEC1XCTL0_H); /* Timer Event Control 1 External Control 0 */
|
|
|
2519 |
SFR_16BIT(TEC1XCTL1); /* Timer Event Control 1 External Control 1 */
|
|
|
2520 |
SFR_8BIT(TEC1XCTL1_L); /* Timer Event Control 1 External Control 1 */
|
|
|
2521 |
SFR_8BIT(TEC1XCTL1_H); /* Timer Event Control 1 External Control 1 */
|
|
|
2522 |
SFR_16BIT(TEC1XCTL2); /* Timer Event Control 1 External Control 2 */
|
|
|
2523 |
SFR_8BIT(TEC1XCTL2_L); /* Timer Event Control 1 External Control 2 */
|
|
|
2524 |
SFR_8BIT(TEC1XCTL2_H); /* Timer Event Control 1 External Control 2 */
|
|
|
2525 |
SFR_16BIT(TEC1STA); /* Timer Event Control 1 Status */
|
|
|
2526 |
SFR_8BIT(TEC1STA_L); /* Timer Event Control 1 Status */
|
|
|
2527 |
SFR_8BIT(TEC1STA_H); /* Timer Event Control 1 Status */
|
|
|
2528 |
SFR_16BIT(TEC1XINT); /* Timer Event Control 1 External Interrupt */
|
|
|
2529 |
SFR_8BIT(TEC1XINT_L); /* Timer Event Control 1 External Interrupt */
|
|
|
2530 |
SFR_8BIT(TEC1XINT_H); /* Timer Event Control 1 External Interrupt */
|
|
|
2531 |
SFR_16BIT(TEC1IV); /* Timer Event Control 1 Interrupt Vector */
|
|
|
2532 |
SFR_8BIT(TEC1IV_L); /* Timer Event Control 1 Interrupt Vector */
|
|
|
2533 |
SFR_8BIT(TEC1IV_H); /* Timer Event Control 1 Interrupt Vector */
|
|
|
2534 |
|
|
|
2535 |
/* TECIV Definitions */
|
|
|
2536 |
#define TEC1IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
2537 |
#define TEC1IV_TECXFLTIFG (0x0002) /* TEC1XFLTIFG */
|
|
|
2538 |
#define TEC1IV_TECEXCLRIFG (0x0004) /* TEC1EXCLRIFG */
|
|
|
2539 |
#define TEC1IV_TECAXCLRIFG (0x0006) /* TEC1AXCLRIFG */
|
|
|
2540 |
|
|
|
2541 |
|
|
|
2542 |
/************************************************************
|
|
|
2543 |
* UNIFIED CLOCK SYSTEM
|
|
|
2544 |
************************************************************/
|
|
|
2545 |
#define __MSP430_HAS_UCS__ /* Definition to show that Module is available */
|
|
|
2546 |
#define __MSP430_BASEADDRESS_UCS__ 0x0160
|
|
|
2547 |
|
|
|
2548 |
SFR_16BIT(UCSCTL0); /* UCS Control Register 0 */
|
|
|
2549 |
SFR_8BIT(UCSCTL0_L); /* UCS Control Register 0 */
|
|
|
2550 |
SFR_8BIT(UCSCTL0_H); /* UCS Control Register 0 */
|
|
|
2551 |
SFR_16BIT(UCSCTL1); /* UCS Control Register 1 */
|
|
|
2552 |
SFR_8BIT(UCSCTL1_L); /* UCS Control Register 1 */
|
|
|
2553 |
SFR_8BIT(UCSCTL1_H); /* UCS Control Register 1 */
|
|
|
2554 |
SFR_16BIT(UCSCTL2); /* UCS Control Register 2 */
|
|
|
2555 |
SFR_8BIT(UCSCTL2_L); /* UCS Control Register 2 */
|
|
|
2556 |
SFR_8BIT(UCSCTL2_H); /* UCS Control Register 2 */
|
|
|
2557 |
SFR_16BIT(UCSCTL3); /* UCS Control Register 3 */
|
|
|
2558 |
SFR_8BIT(UCSCTL3_L); /* UCS Control Register 3 */
|
|
|
2559 |
SFR_8BIT(UCSCTL3_H); /* UCS Control Register 3 */
|
|
|
2560 |
SFR_16BIT(UCSCTL4); /* UCS Control Register 4 */
|
|
|
2561 |
SFR_8BIT(UCSCTL4_L); /* UCS Control Register 4 */
|
|
|
2562 |
SFR_8BIT(UCSCTL4_H); /* UCS Control Register 4 */
|
|
|
2563 |
SFR_16BIT(UCSCTL5); /* UCS Control Register 5 */
|
|
|
2564 |
SFR_8BIT(UCSCTL5_L); /* UCS Control Register 5 */
|
|
|
2565 |
SFR_8BIT(UCSCTL5_H); /* UCS Control Register 5 */
|
|
|
2566 |
SFR_16BIT(UCSCTL6); /* UCS Control Register 6 */
|
|
|
2567 |
SFR_8BIT(UCSCTL6_L); /* UCS Control Register 6 */
|
|
|
2568 |
SFR_8BIT(UCSCTL6_H); /* UCS Control Register 6 */
|
|
|
2569 |
SFR_16BIT(UCSCTL7); /* UCS Control Register 7 */
|
|
|
2570 |
SFR_8BIT(UCSCTL7_L); /* UCS Control Register 7 */
|
|
|
2571 |
SFR_8BIT(UCSCTL7_H); /* UCS Control Register 7 */
|
|
|
2572 |
SFR_16BIT(UCSCTL8); /* UCS Control Register 8 */
|
|
|
2573 |
SFR_8BIT(UCSCTL8_L); /* UCS Control Register 8 */
|
|
|
2574 |
SFR_8BIT(UCSCTL8_H); /* UCS Control Register 8 */
|
|
|
2575 |
|
|
|
2576 |
/* UCSCTL0 Control Bits */
|
|
|
2577 |
//#define RESERVED (0x0001) /* RESERVED */
|
|
|
2578 |
//#define RESERVED (0x0002) /* RESERVED */
|
|
|
2579 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
2580 |
#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */
|
|
|
2581 |
#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */
|
|
|
2582 |
#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */
|
|
|
2583 |
#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */
|
|
|
2584 |
#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */
|
|
|
2585 |
#define DCO0 (0x0100) /* DCO TAP Bit : 0 */
|
|
|
2586 |
#define DCO1 (0x0200) /* DCO TAP Bit : 1 */
|
|
|
2587 |
#define DCO2 (0x0400) /* DCO TAP Bit : 2 */
|
|
|
2588 |
#define DCO3 (0x0800) /* DCO TAP Bit : 3 */
|
|
|
2589 |
#define DCO4 (0x1000) /* DCO TAP Bit : 4 */
|
|
|
2590 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2591 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2592 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2593 |
|
|
|
2594 |
/* UCSCTL0 Control Bits */
|
|
|
2595 |
//#define RESERVED (0x0001) /* RESERVED */
|
|
|
2596 |
//#define RESERVED (0x0002) /* RESERVED */
|
|
|
2597 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
2598 |
#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */
|
|
|
2599 |
#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */
|
|
|
2600 |
#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */
|
|
|
2601 |
#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */
|
|
|
2602 |
#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */
|
|
|
2603 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2604 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2605 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2606 |
|
|
|
2607 |
/* UCSCTL0 Control Bits */
|
|
|
2608 |
//#define RESERVED (0x0001) /* RESERVED */
|
|
|
2609 |
//#define RESERVED (0x0002) /* RESERVED */
|
|
|
2610 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
2611 |
#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */
|
|
|
2612 |
#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */
|
|
|
2613 |
#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */
|
|
|
2614 |
#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */
|
|
|
2615 |
#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */
|
|
|
2616 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2617 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2618 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2619 |
|
|
|
2620 |
/* UCSCTL1 Control Bits */
|
|
|
2621 |
#define DISMOD (0x0001) /* Disable Modulation */
|
|
|
2622 |
//#define RESERVED (0x0002) /* RESERVED */
|
|
|
2623 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
2624 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2625 |
#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */
|
|
|
2626 |
#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */
|
|
|
2627 |
#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */
|
|
|
2628 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2629 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
2630 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
2631 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2632 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2633 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
2634 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2635 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2636 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2637 |
|
|
|
2638 |
/* UCSCTL1 Control Bits */
|
|
|
2639 |
#define DISMOD_L (0x0001) /* Disable Modulation */
|
|
|
2640 |
//#define RESERVED (0x0002) /* RESERVED */
|
|
|
2641 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
2642 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2643 |
#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */
|
|
|
2644 |
#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */
|
|
|
2645 |
#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */
|
|
|
2646 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2647 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
2648 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
2649 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2650 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2651 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
2652 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2653 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2654 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2655 |
|
|
|
2656 |
/* UCSCTL1 Control Bits */
|
|
|
2657 |
//#define RESERVED (0x0002) /* RESERVED */
|
|
|
2658 |
//#define RESERVED (0x0004) /* RESERVED */
|
|
|
2659 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2660 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2661 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
2662 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
2663 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2664 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2665 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
2666 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2667 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2668 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2669 |
|
|
|
2670 |
#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */
|
|
|
2671 |
#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */
|
|
|
2672 |
#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */
|
|
|
2673 |
#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */
|
|
|
2674 |
#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */
|
|
|
2675 |
#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */
|
|
|
2676 |
#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */
|
|
|
2677 |
#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */
|
|
|
2678 |
|
|
|
2679 |
/* UCSCTL2 Control Bits */
|
|
|
2680 |
#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */
|
|
|
2681 |
#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */
|
|
|
2682 |
#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */
|
|
|
2683 |
#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */
|
|
|
2684 |
#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */
|
|
|
2685 |
#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */
|
|
|
2686 |
#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */
|
|
|
2687 |
#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */
|
|
|
2688 |
#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */
|
|
|
2689 |
#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */
|
|
|
2690 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2691 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2692 |
#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */
|
|
|
2693 |
#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */
|
|
|
2694 |
#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */
|
|
|
2695 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2696 |
|
|
|
2697 |
/* UCSCTL2 Control Bits */
|
|
|
2698 |
#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */
|
|
|
2699 |
#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */
|
|
|
2700 |
#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */
|
|
|
2701 |
#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */
|
|
|
2702 |
#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */
|
|
|
2703 |
#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */
|
|
|
2704 |
#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */
|
|
|
2705 |
#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */
|
|
|
2706 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2707 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2708 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2709 |
|
|
|
2710 |
/* UCSCTL2 Control Bits */
|
|
|
2711 |
#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */
|
|
|
2712 |
#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */
|
|
|
2713 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2714 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2715 |
#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */
|
|
|
2716 |
#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */
|
|
|
2717 |
#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */
|
|
|
2718 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2719 |
|
|
|
2720 |
#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */
|
|
|
2721 |
#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */
|
|
|
2722 |
#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */
|
|
|
2723 |
#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */
|
|
|
2724 |
#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */
|
|
|
2725 |
#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */
|
|
|
2726 |
#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */
|
|
|
2727 |
#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */
|
|
|
2728 |
#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */
|
|
|
2729 |
#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */
|
|
|
2730 |
#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */
|
|
|
2731 |
#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */
|
|
|
2732 |
#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */
|
|
|
2733 |
#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */
|
|
|
2734 |
|
|
|
2735 |
/* UCSCTL3 Control Bits */
|
|
|
2736 |
#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */
|
|
|
2737 |
#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */
|
|
|
2738 |
#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */
|
|
|
2739 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2740 |
#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */
|
|
|
2741 |
#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */
|
|
|
2742 |
#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */
|
|
|
2743 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2744 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
2745 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
2746 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2747 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2748 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
2749 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2750 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2751 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2752 |
|
|
|
2753 |
/* UCSCTL3 Control Bits */
|
|
|
2754 |
#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */
|
|
|
2755 |
#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */
|
|
|
2756 |
#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */
|
|
|
2757 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2758 |
#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */
|
|
|
2759 |
#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */
|
|
|
2760 |
#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */
|
|
|
2761 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2762 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
2763 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
2764 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2765 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2766 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
2767 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2768 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2769 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2770 |
|
|
|
2771 |
/* UCSCTL3 Control Bits */
|
|
|
2772 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2773 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2774 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
2775 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
2776 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
2777 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2778 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
2779 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2780 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2781 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2782 |
|
|
|
2783 |
#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */
|
|
|
2784 |
#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */
|
|
|
2785 |
#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */
|
|
|
2786 |
#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */
|
|
|
2787 |
#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */
|
|
|
2788 |
#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */
|
|
|
2789 |
#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */
|
|
|
2790 |
#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */
|
|
|
2791 |
#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */
|
|
|
2792 |
#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */
|
|
|
2793 |
#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */
|
|
|
2794 |
#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */
|
|
|
2795 |
#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */
|
|
|
2796 |
#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */
|
|
|
2797 |
#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */
|
|
|
2798 |
#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */
|
|
|
2799 |
#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */
|
|
|
2800 |
#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */
|
|
|
2801 |
#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */
|
|
|
2802 |
#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */
|
|
|
2803 |
#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */
|
|
|
2804 |
#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */
|
|
|
2805 |
#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */
|
|
|
2806 |
#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */
|
|
|
2807 |
|
|
|
2808 |
/* UCSCTL4 Control Bits */
|
|
|
2809 |
#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
|
|
|
2810 |
#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
|
|
|
2811 |
#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
|
|
|
2812 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2813 |
#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
|
|
|
2814 |
#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
|
|
|
2815 |
#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
|
|
|
2816 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2817 |
#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
|
|
|
2818 |
#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
|
|
|
2819 |
#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
|
|
|
2820 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2821 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
2822 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2823 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2824 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2825 |
|
|
|
2826 |
/* UCSCTL4 Control Bits */
|
|
|
2827 |
#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
|
|
|
2828 |
#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
|
|
|
2829 |
#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
|
|
|
2830 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2831 |
#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
|
|
|
2832 |
#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
|
|
|
2833 |
#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
|
|
|
2834 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2835 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2836 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
2837 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2838 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2839 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2840 |
|
|
|
2841 |
/* UCSCTL4 Control Bits */
|
|
|
2842 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2843 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2844 |
#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
|
|
|
2845 |
#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
|
|
|
2846 |
#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
|
|
|
2847 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2848 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
2849 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
2850 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
2851 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2852 |
|
|
|
2853 |
#define SELM_0 (0x0000) /* MCLK Source Select 0 */
|
|
|
2854 |
#define SELM_1 (0x0001) /* MCLK Source Select 1 */
|
|
|
2855 |
#define SELM_2 (0x0002) /* MCLK Source Select 2 */
|
|
|
2856 |
#define SELM_3 (0x0003) /* MCLK Source Select 3 */
|
|
|
2857 |
#define SELM_4 (0x0004) /* MCLK Source Select 4 */
|
|
|
2858 |
#define SELM_5 (0x0005) /* MCLK Source Select 5 */
|
|
|
2859 |
#define SELM_6 (0x0006) /* MCLK Source Select 6 */
|
|
|
2860 |
#define SELM_7 (0x0007) /* MCLK Source Select 7 */
|
|
|
2861 |
#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */
|
|
|
2862 |
#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
|
|
|
2863 |
#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */
|
|
|
2864 |
#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
|
|
|
2865 |
#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */
|
|
|
2866 |
|
|
|
2867 |
#define SELS_0 (0x0000) /* SMCLK Source Select 0 */
|
|
|
2868 |
#define SELS_1 (0x0010) /* SMCLK Source Select 1 */
|
|
|
2869 |
#define SELS_2 (0x0020) /* SMCLK Source Select 2 */
|
|
|
2870 |
#define SELS_3 (0x0030) /* SMCLK Source Select 3 */
|
|
|
2871 |
#define SELS_4 (0x0040) /* SMCLK Source Select 4 */
|
|
|
2872 |
#define SELS_5 (0x0050) /* SMCLK Source Select 5 */
|
|
|
2873 |
#define SELS_6 (0x0060) /* SMCLK Source Select 6 */
|
|
|
2874 |
#define SELS_7 (0x0070) /* SMCLK Source Select 7 */
|
|
|
2875 |
#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */
|
|
|
2876 |
#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
|
|
|
2877 |
#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */
|
|
|
2878 |
#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
|
|
|
2879 |
#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */
|
|
|
2880 |
|
|
|
2881 |
#define SELA_0 (0x0000) /* ACLK Source Select 0 */
|
|
|
2882 |
#define SELA_1 (0x0100) /* ACLK Source Select 1 */
|
|
|
2883 |
#define SELA_2 (0x0200) /* ACLK Source Select 2 */
|
|
|
2884 |
#define SELA_3 (0x0300) /* ACLK Source Select 3 */
|
|
|
2885 |
#define SELA_4 (0x0400) /* ACLK Source Select 4 */
|
|
|
2886 |
#define SELA_5 (0x0500) /* ACLK Source Select 5 */
|
|
|
2887 |
#define SELA_6 (0x0600) /* ACLK Source Select 6 */
|
|
|
2888 |
#define SELA_7 (0x0700) /* ACLK Source Select 7 */
|
|
|
2889 |
#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */
|
|
|
2890 |
#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
|
|
|
2891 |
#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */
|
|
|
2892 |
#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */
|
|
|
2893 |
#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */
|
|
|
2894 |
|
|
|
2895 |
/* UCSCTL5 Control Bits */
|
|
|
2896 |
#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
|
|
|
2897 |
#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
|
|
|
2898 |
#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
|
|
|
2899 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2900 |
#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
|
|
|
2901 |
#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
|
|
|
2902 |
#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
|
|
|
2903 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2904 |
#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
|
|
|
2905 |
#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
|
|
|
2906 |
#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
|
|
|
2907 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2908 |
#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */
|
|
|
2909 |
#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */
|
|
|
2910 |
#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */
|
|
|
2911 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2912 |
|
|
|
2913 |
/* UCSCTL5 Control Bits */
|
|
|
2914 |
#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
|
|
|
2915 |
#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
|
|
|
2916 |
#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
|
|
|
2917 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2918 |
#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
|
|
|
2919 |
#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
|
|
|
2920 |
#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
|
|
|
2921 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2922 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2923 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2924 |
|
|
|
2925 |
/* UCSCTL5 Control Bits */
|
|
|
2926 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
2927 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
2928 |
#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
|
|
|
2929 |
#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
|
|
|
2930 |
#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
|
|
|
2931 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
2932 |
#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */
|
|
|
2933 |
#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */
|
|
|
2934 |
#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */
|
|
|
2935 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
2936 |
|
|
|
2937 |
#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
|
|
|
2938 |
#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
|
|
|
2939 |
#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
|
|
|
2940 |
#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
|
|
|
2941 |
#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
|
|
|
2942 |
#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
|
|
|
2943 |
#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */
|
|
|
2944 |
#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */
|
|
|
2945 |
#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
|
|
|
2946 |
#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
|
|
|
2947 |
#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
|
|
|
2948 |
#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
|
|
|
2949 |
#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
|
|
|
2950 |
#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
|
|
|
2951 |
|
|
|
2952 |
#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
|
|
|
2953 |
#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
|
|
|
2954 |
#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
|
|
|
2955 |
#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
|
|
|
2956 |
#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
|
|
|
2957 |
#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
|
|
|
2958 |
#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */
|
|
|
2959 |
#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */
|
|
|
2960 |
#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
|
|
|
2961 |
#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
|
|
|
2962 |
#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
|
|
|
2963 |
#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
|
|
|
2964 |
#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
|
|
|
2965 |
#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
|
|
|
2966 |
|
|
|
2967 |
#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
|
|
|
2968 |
#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
|
|
|
2969 |
#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
|
|
|
2970 |
#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
|
|
|
2971 |
#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
|
|
|
2972 |
#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
|
|
|
2973 |
#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */
|
|
|
2974 |
#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */
|
|
|
2975 |
#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
|
|
|
2976 |
#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
|
|
|
2977 |
#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
|
|
|
2978 |
#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
|
|
|
2979 |
#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
|
|
|
2980 |
#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
|
|
|
2981 |
|
|
|
2982 |
#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */
|
|
|
2983 |
#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */
|
|
|
2984 |
#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */
|
|
|
2985 |
#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */
|
|
|
2986 |
#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */
|
|
|
2987 |
#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */
|
|
|
2988 |
#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */
|
|
|
2989 |
#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */
|
|
|
2990 |
#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */
|
|
|
2991 |
#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */
|
|
|
2992 |
#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */
|
|
|
2993 |
#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */
|
|
|
2994 |
#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */
|
|
|
2995 |
#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */
|
|
|
2996 |
|
|
|
2997 |
/* UCSCTL6 Control Bits */
|
|
|
2998 |
#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
|
|
|
2999 |
#define SMCLKOFF (0x0002) /* SMCLK Off */
|
|
|
3000 |
#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */
|
|
|
3001 |
#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */
|
|
|
3002 |
#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
|
|
|
3003 |
#define XTS (0x0020) /* 1: Selects high-freq. oscillator */
|
|
|
3004 |
#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */
|
|
|
3005 |
#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */
|
|
|
3006 |
#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */
|
|
|
3007 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
3008 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
3009 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
3010 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
3011 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
3012 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
3013 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
3014 |
|
|
|
3015 |
/* UCSCTL6 Control Bits */
|
|
|
3016 |
#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
|
|
|
3017 |
#define SMCLKOFF_L (0x0002) /* SMCLK Off */
|
|
|
3018 |
#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */
|
|
|
3019 |
#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */
|
|
|
3020 |
#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
|
|
|
3021 |
#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */
|
|
|
3022 |
#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */
|
|
|
3023 |
#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */
|
|
|
3024 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
3025 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
3026 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
3027 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
3028 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
3029 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
3030 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
3031 |
|
|
|
3032 |
/* UCSCTL6 Control Bits */
|
|
|
3033 |
#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */
|
|
|
3034 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
3035 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
3036 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
3037 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
3038 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
3039 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
3040 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
3041 |
|
|
|
3042 |
#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */
|
|
|
3043 |
#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */
|
|
|
3044 |
#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */
|
|
|
3045 |
#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */
|
|
|
3046 |
#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */
|
|
|
3047 |
#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */
|
|
|
3048 |
#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */
|
|
|
3049 |
#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */
|
|
|
3050 |
|
|
|
3051 |
/* UCSCTL7 Control Bits */
|
|
|
3052 |
#define DCOFFG (0x0001) /* DCO Fault Flag */
|
|
|
3053 |
#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
|
|
|
3054 |
#define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
|
|
|
3055 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
3056 |
//#define RESERVED (0x0010) /* RESERVED */
|
|
|
3057 |
//#define RESERVED (0x0020) /* RESERVED */
|
|
|
3058 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
3059 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
3060 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
3061 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
3062 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
3063 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
3064 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
3065 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
3066 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
3067 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
3068 |
|
|
|
3069 |
/* UCSCTL7 Control Bits */
|
|
|
3070 |
#define DCOFFG_L (0x0001) /* DCO Fault Flag */
|
|
|
3071 |
#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
|
|
|
3072 |
#define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
|
|
|
3073 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
3074 |
//#define RESERVED (0x0010) /* RESERVED */
|
|
|
3075 |
//#define RESERVED (0x0020) /* RESERVED */
|
|
|
3076 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
3077 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
3078 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
3079 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
3080 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
3081 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
3082 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
3083 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
3084 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
3085 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
3086 |
|
|
|
3087 |
/* UCSCTL7 Control Bits */
|
|
|
3088 |
//#define RESERVED (0x0008) /* RESERVED */
|
|
|
3089 |
//#define RESERVED (0x0010) /* RESERVED */
|
|
|
3090 |
//#define RESERVED (0x0020) /* RESERVED */
|
|
|
3091 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
3092 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
3093 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
3094 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
3095 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
3096 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
3097 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
3098 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
3099 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
3100 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
3101 |
|
|
|
3102 |
/* UCSCTL8 Control Bits */
|
|
|
3103 |
#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
|
|
|
3104 |
#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
|
|
|
3105 |
#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
|
|
|
3106 |
#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */
|
|
|
3107 |
//#define RESERVED (0x0010) /* RESERVED */
|
|
|
3108 |
//#define RESERVED (0x0020) /* RESERVED */
|
|
|
3109 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
3110 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
3111 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
3112 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
3113 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
3114 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
3115 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
3116 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
3117 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
3118 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
3119 |
|
|
|
3120 |
/* UCSCTL8 Control Bits */
|
|
|
3121 |
#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
|
|
|
3122 |
#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
|
|
|
3123 |
#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
|
|
|
3124 |
#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */
|
|
|
3125 |
//#define RESERVED (0x0010) /* RESERVED */
|
|
|
3126 |
//#define RESERVED (0x0020) /* RESERVED */
|
|
|
3127 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
3128 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
3129 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
3130 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
3131 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
3132 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
3133 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
3134 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
3135 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
3136 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
3137 |
|
|
|
3138 |
/* UCSCTL8 Control Bits */
|
|
|
3139 |
//#define RESERVED (0x0010) /* RESERVED */
|
|
|
3140 |
//#define RESERVED (0x0020) /* RESERVED */
|
|
|
3141 |
//#define RESERVED (0x0040) /* RESERVED */
|
|
|
3142 |
//#define RESERVED (0x0080) /* RESERVED */
|
|
|
3143 |
//#define RESERVED (0x0100) /* RESERVED */
|
|
|
3144 |
//#define RESERVED (0x0200) /* RESERVED */
|
|
|
3145 |
//#define RESERVED (0x0400) /* RESERVED */
|
|
|
3146 |
//#define RESERVED (0x0800) /* RESERVED */
|
|
|
3147 |
//#define RESERVED (0x1000) /* RESERVED */
|
|
|
3148 |
//#define RESERVED (0x2000) /* RESERVED */
|
|
|
3149 |
//#define RESERVED (0x4000) /* RESERVED */
|
|
|
3150 |
//#define RESERVED (0x8000) /* RESERVED */
|
|
|
3151 |
|
|
|
3152 |
/************************************************************
|
|
|
3153 |
* USCI A0
|
|
|
3154 |
************************************************************/
|
|
|
3155 |
#define __MSP430_HAS_USCI_A0__ /* Definition to show that Module is available */
|
|
|
3156 |
#define __MSP430_BASEADDRESS_USCI_A0__ 0x05C0
|
|
|
3157 |
|
|
|
3158 |
SFR_16BIT(UCA0CTLW0); /* USCI A0 Control Word Register 0 */
|
|
|
3159 |
SFR_8BIT(UCA0CTLW0_L); /* USCI A0 Control Word Register 0 */
|
|
|
3160 |
SFR_8BIT(UCA0CTLW0_H); /* USCI A0 Control Word Register 0 */
|
|
|
3161 |
#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */
|
|
|
3162 |
#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */
|
|
|
3163 |
SFR_16BIT(UCA0BRW); /* USCI A0 Baud Word Rate 0 */
|
|
|
3164 |
SFR_8BIT(UCA0BRW_L); /* USCI A0 Baud Word Rate 0 */
|
|
|
3165 |
SFR_8BIT(UCA0BRW_H); /* USCI A0 Baud Word Rate 0 */
|
|
|
3166 |
#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */
|
|
|
3167 |
#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */
|
|
|
3168 |
SFR_8BIT(UCA0MCTL); /* USCI A0 Modulation Control */
|
|
|
3169 |
SFR_8BIT(UCA0STAT); /* USCI A0 Status Register */
|
|
|
3170 |
SFR_8BIT(UCA0RXBUF); /* USCI A0 Receive Buffer */
|
|
|
3171 |
SFR_8BIT(UCA0TXBUF); /* USCI A0 Transmit Buffer */
|
|
|
3172 |
SFR_8BIT(UCA0ABCTL); /* USCI A0 LIN Control */
|
|
|
3173 |
SFR_16BIT(UCA0IRCTL); /* USCI A0 IrDA Transmit Control */
|
|
|
3174 |
SFR_8BIT(UCA0IRCTL_L); /* USCI A0 IrDA Transmit Control */
|
|
|
3175 |
SFR_8BIT(UCA0IRCTL_H); /* USCI A0 IrDA Transmit Control */
|
|
|
3176 |
#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */
|
|
|
3177 |
#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */
|
|
|
3178 |
SFR_16BIT(UCA0ICTL); /* USCI A0 Interrupt Enable Register */
|
|
|
3179 |
SFR_8BIT(UCA0ICTL_L); /* USCI A0 Interrupt Enable Register */
|
|
|
3180 |
SFR_8BIT(UCA0ICTL_H); /* USCI A0 Interrupt Enable Register */
|
|
|
3181 |
#define UCA0IE UCA0ICTL_L /* USCI A0 Interrupt Enable Register */
|
|
|
3182 |
#define UCA0IFG UCA0ICTL_H /* USCI A0 Interrupt Flags Register */
|
|
|
3183 |
SFR_16BIT(UCA0IV); /* USCI A0 Interrupt Vector Register */
|
|
|
3184 |
|
|
|
3185 |
|
|
|
3186 |
/************************************************************
|
|
|
3187 |
* USCI B0
|
|
|
3188 |
************************************************************/
|
|
|
3189 |
#define __MSP430_HAS_USCI_B0__ /* Definition to show that Module is available */
|
|
|
3190 |
#define __MSP430_BASEADDRESS_USCI_B0__ 0x05E0
|
|
|
3191 |
|
|
|
3192 |
|
|
|
3193 |
SFR_16BIT(UCB0CTLW0); /* USCI B0 Control Word Register 0 */
|
|
|
3194 |
SFR_8BIT(UCB0CTLW0_L); /* USCI B0 Control Word Register 0 */
|
|
|
3195 |
SFR_8BIT(UCB0CTLW0_H); /* USCI B0 Control Word Register 0 */
|
|
|
3196 |
#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */
|
|
|
3197 |
#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */
|
|
|
3198 |
SFR_16BIT(UCB0BRW); /* USCI B0 Baud Word Rate 0 */
|
|
|
3199 |
SFR_8BIT(UCB0BRW_L); /* USCI B0 Baud Word Rate 0 */
|
|
|
3200 |
SFR_8BIT(UCB0BRW_H); /* USCI B0 Baud Word Rate 0 */
|
|
|
3201 |
#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */
|
|
|
3202 |
#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */
|
|
|
3203 |
SFR_8BIT(UCB0STAT); /* USCI B0 Status Register */
|
|
|
3204 |
SFR_8BIT(UCB0RXBUF); /* USCI B0 Receive Buffer */
|
|
|
3205 |
SFR_8BIT(UCB0TXBUF); /* USCI B0 Transmit Buffer */
|
|
|
3206 |
SFR_16BIT(UCB0I2COA); /* USCI B0 I2C Own Address */
|
|
|
3207 |
SFR_8BIT(UCB0I2COA_L); /* USCI B0 I2C Own Address */
|
|
|
3208 |
SFR_8BIT(UCB0I2COA_H); /* USCI B0 I2C Own Address */
|
|
|
3209 |
SFR_16BIT(UCB0I2CSA); /* USCI B0 I2C Slave Address */
|
|
|
3210 |
SFR_8BIT(UCB0I2CSA_L); /* USCI B0 I2C Slave Address */
|
|
|
3211 |
SFR_8BIT(UCB0I2CSA_H); /* USCI B0 I2C Slave Address */
|
|
|
3212 |
SFR_16BIT(UCB0ICTL); /* USCI B0 Interrupt Enable Register */
|
|
|
3213 |
SFR_8BIT(UCB0ICTL_L); /* USCI B0 Interrupt Enable Register */
|
|
|
3214 |
SFR_8BIT(UCB0ICTL_H); /* USCI B0 Interrupt Enable Register */
|
|
|
3215 |
#define UCB0IE UCB0ICTL_L /* USCI B0 Interrupt Enable Register */
|
|
|
3216 |
#define UCB0IFG UCB0ICTL_H /* USCI B0 Interrupt Flags Register */
|
|
|
3217 |
SFR_16BIT(UCB0IV); /* USCI B0 Interrupt Vector Register */
|
|
|
3218 |
|
|
|
3219 |
// UCAxCTL0 UART-Mode Control Bits
|
|
|
3220 |
#define UCPEN (0x80) /* Async. Mode: Parity enable */
|
|
|
3221 |
#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
|
|
|
3222 |
#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
|
|
|
3223 |
#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
|
|
|
3224 |
#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
|
|
|
3225 |
#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
|
|
|
3226 |
#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
|
|
|
3227 |
#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
|
|
|
3228 |
|
|
|
3229 |
// UCxxCTL0 SPI-Mode Control Bits
|
|
|
3230 |
#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
|
|
|
3231 |
#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
|
|
|
3232 |
#define UCMST (0x08) /* Sync. Mode: Master Select */
|
|
|
3233 |
|
|
|
3234 |
// UCBxCTL0 I2C-Mode Control Bits
|
|
|
3235 |
#define UCA10 (0x80) /* 10-bit Address Mode */
|
|
|
3236 |
#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
|
|
|
3237 |
#define UCMM (0x20) /* Multi-Master Environment */
|
|
|
3238 |
//#define res (0x10) /* reserved */
|
|
|
3239 |
#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
|
|
|
3240 |
#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
|
|
|
3241 |
#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
|
|
|
3242 |
#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
|
|
|
3243 |
|
|
|
3244 |
// UCAxCTL1 UART-Mode Control Bits
|
|
|
3245 |
#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
|
|
|
3246 |
#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
|
|
|
3247 |
#define UCRXEIE (0x20) /* RX Error interrupt enable */
|
|
|
3248 |
#define UCBRKIE (0x10) /* Break interrupt enable */
|
|
|
3249 |
#define UCDORM (0x08) /* Dormant (Sleep) Mode */
|
|
|
3250 |
#define UCTXADDR (0x04) /* Send next Data as Address */
|
|
|
3251 |
#define UCTXBRK (0x02) /* Send next Data as Break */
|
|
|
3252 |
#define UCSWRST (0x01) /* USCI Software Reset */
|
|
|
3253 |
|
|
|
3254 |
// UCxxCTL1 SPI-Mode Control Bits
|
|
|
3255 |
//#define res (0x20) /* reserved */
|
|
|
3256 |
//#define res (0x10) /* reserved */
|
|
|
3257 |
//#define res (0x08) /* reserved */
|
|
|
3258 |
//#define res (0x04) /* reserved */
|
|
|
3259 |
//#define res (0x02) /* reserved */
|
|
|
3260 |
|
|
|
3261 |
// UCBxCTL1 I2C-Mode Control Bits
|
|
|
3262 |
//#define res (0x20) /* reserved */
|
|
|
3263 |
#define UCTR (0x10) /* Transmit/Receive Select/Flag */
|
|
|
3264 |
#define UCTXNACK (0x08) /* Transmit NACK */
|
|
|
3265 |
#define UCTXSTP (0x04) /* Transmit STOP */
|
|
|
3266 |
#define UCTXSTT (0x02) /* Transmit START */
|
|
|
3267 |
#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
|
|
|
3268 |
#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
|
|
|
3269 |
#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
|
|
|
3270 |
#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
|
|
|
3271 |
#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */
|
|
|
3272 |
#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */
|
|
|
3273 |
#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */
|
|
|
3274 |
|
|
|
3275 |
/* UCAxMCTL Control Bits */
|
|
|
3276 |
#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
|
|
|
3277 |
#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
|
|
|
3278 |
#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
|
|
|
3279 |
#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
|
|
|
3280 |
#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
|
|
|
3281 |
#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
|
|
|
3282 |
#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
|
|
|
3283 |
#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
|
|
|
3284 |
|
|
|
3285 |
#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
|
|
|
3286 |
#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
|
|
|
3287 |
#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
|
|
|
3288 |
#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
|
|
|
3289 |
#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
|
|
|
3290 |
#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
|
|
|
3291 |
#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
|
|
|
3292 |
#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
|
|
|
3293 |
#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
|
|
|
3294 |
#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
|
|
|
3295 |
#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
|
|
|
3296 |
#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
|
|
|
3297 |
#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
|
|
|
3298 |
#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
|
|
|
3299 |
#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
|
|
|
3300 |
#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
|
|
|
3301 |
|
|
|
3302 |
#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
|
|
|
3303 |
#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
|
|
|
3304 |
#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
|
|
|
3305 |
#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
|
|
|
3306 |
#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
|
|
|
3307 |
#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
|
|
|
3308 |
#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
|
|
|
3309 |
#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
|
|
|
3310 |
|
|
|
3311 |
/* UCAxSTAT Control Bits */
|
|
|
3312 |
#define UCLISTEN (0x80) /* USCI Listen mode */
|
|
|
3313 |
#define UCFE (0x40) /* USCI Frame Error Flag */
|
|
|
3314 |
#define UCOE (0x20) /* USCI Overrun Error Flag */
|
|
|
3315 |
#define UCPE (0x10) /* USCI Parity Error Flag */
|
|
|
3316 |
#define UCBRK (0x08) /* USCI Break received */
|
|
|
3317 |
#define UCRXERR (0x04) /* USCI RX Error Flag */
|
|
|
3318 |
#define UCADDR (0x02) /* USCI Address received Flag */
|
|
|
3319 |
#define UCBUSY (0x01) /* USCI Busy Flag */
|
|
|
3320 |
#define UCIDLE (0x02) /* USCI Idle line detected Flag */
|
|
|
3321 |
|
|
|
3322 |
/* UCBxSTAT Control Bits */
|
|
|
3323 |
#define UCSCLLOW (0x40) /* SCL low */
|
|
|
3324 |
#define UCGC (0x20) /* General Call address received Flag */
|
|
|
3325 |
#define UCBBUSY (0x10) /* Bus Busy Flag */
|
|
|
3326 |
|
|
|
3327 |
/* UCAxIRTCTL Control Bits */
|
|
|
3328 |
#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
|
|
|
3329 |
#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
|
|
|
3330 |
#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
|
|
|
3331 |
#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
|
|
|
3332 |
#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
|
|
|
3333 |
#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
|
|
|
3334 |
#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
|
|
|
3335 |
#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
|
|
|
3336 |
|
|
|
3337 |
/* UCAxIRRCTL Control Bits */
|
|
|
3338 |
#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
|
|
|
3339 |
#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
|
|
|
3340 |
#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
|
|
|
3341 |
#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
|
|
|
3342 |
#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
|
|
|
3343 |
#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
|
|
|
3344 |
#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
|
|
|
3345 |
#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
|
|
|
3346 |
|
|
|
3347 |
/* UCAxABCTL Control Bits */
|
|
|
3348 |
//#define res (0x80) /* reserved */
|
|
|
3349 |
//#define res (0x40) /* reserved */
|
|
|
3350 |
#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
|
|
|
3351 |
#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
|
|
|
3352 |
#define UCSTOE (0x08) /* Sync-Field Timeout error */
|
|
|
3353 |
#define UCBTOE (0x04) /* Break Timeout error */
|
|
|
3354 |
//#define res (0x02) /* reserved */
|
|
|
3355 |
#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
|
|
|
3356 |
|
|
|
3357 |
/* UCBxI2COA Control Bits */
|
|
|
3358 |
#define UCGCEN (0x8000) /* I2C General Call enable */
|
|
|
3359 |
#define UCOA9 (0x0200) /* I2C Own Address 9 */
|
|
|
3360 |
#define UCOA8 (0x0100) /* I2C Own Address 8 */
|
|
|
3361 |
#define UCOA7 (0x0080) /* I2C Own Address 7 */
|
|
|
3362 |
#define UCOA6 (0x0040) /* I2C Own Address 6 */
|
|
|
3363 |
#define UCOA5 (0x0020) /* I2C Own Address 5 */
|
|
|
3364 |
#define UCOA4 (0x0010) /* I2C Own Address 4 */
|
|
|
3365 |
#define UCOA3 (0x0008) /* I2C Own Address 3 */
|
|
|
3366 |
#define UCOA2 (0x0004) /* I2C Own Address 2 */
|
|
|
3367 |
#define UCOA1 (0x0002) /* I2C Own Address 1 */
|
|
|
3368 |
#define UCOA0 (0x0001) /* I2C Own Address 0 */
|
|
|
3369 |
|
|
|
3370 |
/* UCBxI2COA Control Bits */
|
|
|
3371 |
#define UCOA7_L (0x0080) /* I2C Own Address 7 */
|
|
|
3372 |
#define UCOA6_L (0x0040) /* I2C Own Address 6 */
|
|
|
3373 |
#define UCOA5_L (0x0020) /* I2C Own Address 5 */
|
|
|
3374 |
#define UCOA4_L (0x0010) /* I2C Own Address 4 */
|
|
|
3375 |
#define UCOA3_L (0x0008) /* I2C Own Address 3 */
|
|
|
3376 |
#define UCOA2_L (0x0004) /* I2C Own Address 2 */
|
|
|
3377 |
#define UCOA1_L (0x0002) /* I2C Own Address 1 */
|
|
|
3378 |
#define UCOA0_L (0x0001) /* I2C Own Address 0 */
|
|
|
3379 |
|
|
|
3380 |
/* UCBxI2COA Control Bits */
|
|
|
3381 |
#define UCGCEN_H (0x0080) /* I2C General Call enable */
|
|
|
3382 |
#define UCOA9_H (0x0002) /* I2C Own Address 9 */
|
|
|
3383 |
#define UCOA8_H (0x0001) /* I2C Own Address 8 */
|
|
|
3384 |
|
|
|
3385 |
/* UCBxI2CSA Control Bits */
|
|
|
3386 |
#define UCSA9 (0x0200) /* I2C Slave Address 9 */
|
|
|
3387 |
#define UCSA8 (0x0100) /* I2C Slave Address 8 */
|
|
|
3388 |
#define UCSA7 (0x0080) /* I2C Slave Address 7 */
|
|
|
3389 |
#define UCSA6 (0x0040) /* I2C Slave Address 6 */
|
|
|
3390 |
#define UCSA5 (0x0020) /* I2C Slave Address 5 */
|
|
|
3391 |
#define UCSA4 (0x0010) /* I2C Slave Address 4 */
|
|
|
3392 |
#define UCSA3 (0x0008) /* I2C Slave Address 3 */
|
|
|
3393 |
#define UCSA2 (0x0004) /* I2C Slave Address 2 */
|
|
|
3394 |
#define UCSA1 (0x0002) /* I2C Slave Address 1 */
|
|
|
3395 |
#define UCSA0 (0x0001) /* I2C Slave Address 0 */
|
|
|
3396 |
|
|
|
3397 |
/* UCBxI2CSA Control Bits */
|
|
|
3398 |
#define UCSA7_L (0x0080) /* I2C Slave Address 7 */
|
|
|
3399 |
#define UCSA6_L (0x0040) /* I2C Slave Address 6 */
|
|
|
3400 |
#define UCSA5_L (0x0020) /* I2C Slave Address 5 */
|
|
|
3401 |
#define UCSA4_L (0x0010) /* I2C Slave Address 4 */
|
|
|
3402 |
#define UCSA3_L (0x0008) /* I2C Slave Address 3 */
|
|
|
3403 |
#define UCSA2_L (0x0004) /* I2C Slave Address 2 */
|
|
|
3404 |
#define UCSA1_L (0x0002) /* I2C Slave Address 1 */
|
|
|
3405 |
#define UCSA0_L (0x0001) /* I2C Slave Address 0 */
|
|
|
3406 |
|
|
|
3407 |
/* UCBxI2CSA Control Bits */
|
|
|
3408 |
#define UCSA9_H (0x0002) /* I2C Slave Address 9 */
|
|
|
3409 |
#define UCSA8_H (0x0001) /* I2C Slave Address 8 */
|
|
|
3410 |
|
|
|
3411 |
/* UCAxIE Control Bits */
|
|
|
3412 |
#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */
|
|
|
3413 |
#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */
|
|
|
3414 |
|
|
|
3415 |
/* UCBxIE Control Bits */
|
|
|
3416 |
#define UCNACKIE (0x0020) /* NACK Condition interrupt enable */
|
|
|
3417 |
#define UCALIE (0x0010) /* Arbitration Lost interrupt enable */
|
|
|
3418 |
#define UCSTPIE (0x0008) /* STOP Condition interrupt enable */
|
|
|
3419 |
#define UCSTTIE (0x0004) /* START Condition interrupt enable */
|
|
|
3420 |
#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */
|
|
|
3421 |
#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */
|
|
|
3422 |
|
|
|
3423 |
/* UCAxIFG Control Bits */
|
|
|
3424 |
#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */
|
|
|
3425 |
#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */
|
|
|
3426 |
|
|
|
3427 |
/* UCBxIFG Control Bits */
|
|
|
3428 |
#define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */
|
|
|
3429 |
#define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */
|
|
|
3430 |
#define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */
|
|
|
3431 |
#define UCSTTIFG (0x0004) /* START Condition interrupt Flag */
|
|
|
3432 |
#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */
|
|
|
3433 |
#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */
|
|
|
3434 |
|
|
|
3435 |
/* USCI Definitions */
|
|
|
3436 |
#define USCI_NONE (0x0000) /* No Interrupt pending */
|
|
|
3437 |
#define USCI_UCRXIFG (0x0002) /* USCI UCRXIFG */
|
|
|
3438 |
#define USCI_UCTXIFG (0x0004) /* USCI UCTXIFG */
|
|
|
3439 |
#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */
|
|
|
3440 |
#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */
|
|
|
3441 |
#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/
|
|
|
3442 |
#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/
|
|
|
3443 |
#define USCI_I2C_UCRXIFG (0x000A) /* USCI I2C Mode: UCRXIFG */
|
|
|
3444 |
#define USCI_I2C_UCTXIFG (0x000C) /* USCI I2C Mode: UCTXIFG */
|
|
|
3445 |
|
|
|
3446 |
/************************************************************
|
|
|
3447 |
* WATCHDOG TIMER A
|
|
|
3448 |
************************************************************/
|
|
|
3449 |
#define __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */
|
|
|
3450 |
#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
|
|
|
3451 |
|
|
|
3452 |
SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
|
|
|
3453 |
SFR_8BIT(WDTCTL_L); /* Watchdog Timer Control */
|
|
|
3454 |
SFR_8BIT(WDTCTL_H); /* Watchdog Timer Control */
|
|
|
3455 |
/* The bit names have been prefixed with "WDT" */
|
|
|
3456 |
/* WDTCTL Control Bits */
|
|
|
3457 |
#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */
|
|
|
3458 |
#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */
|
|
|
3459 |
#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */
|
|
|
3460 |
#define WDTCNTCL (0x0008) /* WDT - Timer Clear */
|
|
|
3461 |
#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */
|
|
|
3462 |
#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */
|
|
|
3463 |
#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */
|
|
|
3464 |
#define WDTHOLD (0x0080) /* WDT - Timer hold */
|
|
|
3465 |
|
|
|
3466 |
/* WDTCTL Control Bits */
|
|
|
3467 |
#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */
|
|
|
3468 |
#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */
|
|
|
3469 |
#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */
|
|
|
3470 |
#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */
|
|
|
3471 |
#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */
|
|
|
3472 |
#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */
|
|
|
3473 |
#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */
|
|
|
3474 |
#define WDTHOLD_L (0x0080) /* WDT - Timer hold */
|
|
|
3475 |
|
|
|
3476 |
/* WDTCTL Control Bits */
|
|
|
3477 |
|
|
|
3478 |
#define WDTPW (0x5A00)
|
|
|
3479 |
|
|
|
3480 |
#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */
|
|
|
3481 |
#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */
|
|
|
3482 |
#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
|
|
|
3483 |
#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */
|
|
|
3484 |
#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */
|
|
|
3485 |
#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
|
|
|
3486 |
#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
|
|
|
3487 |
#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
|
|
|
3488 |
#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */
|
|
|
3489 |
#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */
|
|
|
3490 |
#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
|
|
|
3491 |
#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */
|
|
|
3492 |
#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */
|
|
|
3493 |
#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
|
|
|
3494 |
#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
|
|
|
3495 |
#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
|
|
|
3496 |
|
|
|
3497 |
#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
|
|
|
3498 |
#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
|
|
|
3499 |
#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
|
|
|
3500 |
#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */
|
|
|
3501 |
#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
|
|
|
3502 |
#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
|
|
|
3503 |
#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
|
|
|
3504 |
|
|
|
3505 |
/* WDT-interval times [1ms] coded with Bits 0-2 */
|
|
|
3506 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
3507 |
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
|
|
|
3508 |
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
|
|
|
3509 |
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
|
|
|
3510 |
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
3511 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
3512 |
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
|
|
|
3513 |
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
|
|
|
3514 |
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
|
|
|
3515 |
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
3516 |
/* Watchdog mode -> reset after expired time */
|
|
|
3517 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
3518 |
#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
|
|
|
3519 |
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
|
|
|
3520 |
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
|
|
|
3521 |
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
3522 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
3523 |
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
|
|
|
3524 |
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
|
|
|
3525 |
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
|
|
|
3526 |
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
3527 |
|
|
|
3528 |
|
|
|
3529 |
/************************************************************
|
|
|
3530 |
* TLV Descriptors
|
|
|
3531 |
************************************************************/
|
|
|
3532 |
#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */
|
|
|
3533 |
|
|
|
3534 |
#define TLV_START (0x1A08) /* Start Address of the TLV structure */
|
|
|
3535 |
#define TLV_END (0x1AFF) /* End Address of the TLV structure */
|
|
|
3536 |
|
|
|
3537 |
#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
|
|
|
3538 |
#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
|
|
|
3539 |
#define TLV_Reserved3 (0x03) /* Future usage */
|
|
|
3540 |
#define TLV_Reserved4 (0x04) /* Future usage */
|
|
|
3541 |
#define TLV_BLANK (0x05) /* Blank descriptor */
|
|
|
3542 |
#define TLV_Reserved6 (0x06) /* Future usage */
|
|
|
3543 |
#define TLV_Reserved7 (0x07) /* Serial Number */
|
|
|
3544 |
#define TLV_DIERECORD (0x08) /* Die Record */
|
|
|
3545 |
#define TLV_ADCCAL (0x11) /* ADC12 calibration */
|
|
|
3546 |
#define TLV_ADC12CAL (0x11) /* ADC12 calibration */
|
|
|
3547 |
#define TLV_ADC10CAL (0x13) /* ADC10 calibration */
|
|
|
3548 |
#define TLV_REFCAL (0x12) /* REF calibration */
|
|
|
3549 |
#define TLV_TAGEXT (0xFE) /* Tag extender */
|
|
|
3550 |
#define TLV_TAGEND (0xFF) // Tag End of Table
|
|
|
3551 |
|
|
|
3552 |
/************************************************************
|
|
|
3553 |
* Interrupt Vectors (offset from 0xFF80)
|
|
|
3554 |
************************************************************/
|
|
|
3555 |
|
|
|
3556 |
#pragma diag_suppress 1107
|
|
|
3557 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
3558 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
3559 |
#define CREATE_VECTOR(name) void * const VECTOR_NAME(name) = (void *)(long)&name
|
|
|
3560 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
3561 |
#define PLACE_INTERRUPT(func) EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
|
|
|
3562 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
3563 |
PLACE_VECTOR(VECTOR_NAME(func), offset) \
|
|
|
3564 |
PLACE_INTERRUPT(func)
|
|
|
3565 |
|
|
|
3566 |
|
|
|
3567 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3568 |
#define PORT2_VECTOR ".int45" /* 0xFFDA Port 2 */
|
|
|
3569 |
#else
|
|
|
3570 |
#define PORT2_VECTOR (45 * 1u) /* 0xFFDA Port 2 */
|
|
|
3571 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int45") */ /* 0xFFDA Port 2 */ /* CCE V2 Style */
|
|
|
3572 |
#endif
|
|
|
3573 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3574 |
#define PORT1_VECTOR ".int46" /* 0xFFDC Port 1 */
|
|
|
3575 |
#else
|
|
|
3576 |
#define PORT1_VECTOR (46 * 1u) /* 0xFFDC Port 1 */
|
|
|
3577 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int46") */ /* 0xFFDC Port 1 */ /* CCE V2 Style */
|
|
|
3578 |
#endif
|
|
|
3579 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3580 |
#define TIMER1_D1_VECTOR ".int47" /* 0xFFDE Timer1_D3 CC1-2, TA1 */
|
|
|
3581 |
#else
|
|
|
3582 |
#define TIMER1_D1_VECTOR (47 * 1u) /* 0xFFDE Timer1_D3 CC1-2, TA1 */
|
|
|
3583 |
/*#define TIMER1_D1_ISR(func) ISR_VECTOR(func, ".int47") */ /* 0xFFDE Timer1_D3 CC1-2, TA1 */ /* CCE V2 Style */
|
|
|
3584 |
#endif
|
|
|
3585 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3586 |
#define TIMER1_D0_VECTOR ".int48" /* 0xFFE0 Timer1_D3 CC0 */
|
|
|
3587 |
#else
|
|
|
3588 |
#define TIMER1_D0_VECTOR (48 * 1u) /* 0xFFE0 Timer1_D3 CC0 */
|
|
|
3589 |
/*#define TIMER1_D0_ISR(func) ISR_VECTOR(func, ".int48") */ /* 0xFFE0 Timer1_D3 CC0 */ /* CCE V2 Style */
|
|
|
3590 |
#endif
|
|
|
3591 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3592 |
#define TEC1_VECTOR ".int49" /* 0xFFF2 Timer Event Controller 1 */
|
|
|
3593 |
#else
|
|
|
3594 |
#define TEC1_VECTOR (49 * 1u) /* 0xFFF2 Timer Event Controller 1 */
|
|
|
3595 |
/*#define TEC1_ISR(func) ISR_VECTOR(func, ".int49") */ /* 0xFFF2 Timer Event Controller 1 */ /* CCE V2 Style */
|
|
|
3596 |
#endif
|
|
|
3597 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3598 |
#define DMA_VECTOR ".int50" /* 0xFFE4 DMA */
|
|
|
3599 |
#else
|
|
|
3600 |
#define DMA_VECTOR (50 * 1u) /* 0xFFE4 DMA */
|
|
|
3601 |
/*#define DMA_ISR(func) ISR_VECTOR(func, ".int50") */ /* 0xFFE4 DMA */ /* CCE V2 Style */
|
|
|
3602 |
#endif
|
|
|
3603 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3604 |
#define TIMER0_A1_VECTOR ".int51" /* 0xFFE6 Timer0_A3 CC1-2, TA */
|
|
|
3605 |
#else
|
|
|
3606 |
#define TIMER0_A1_VECTOR (51 * 1u) /* 0xFFE6 Timer0_A3 CC1-2, TA */
|
|
|
3607 |
/*#define TIMER0_A1_ISR(func) ISR_VECTOR(func, ".int51") */ /* 0xFFE6 Timer0_A3 CC1-2, TA */ /* CCE V2 Style */
|
|
|
3608 |
#endif
|
|
|
3609 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3610 |
#define TIMER0_A0_VECTOR ".int52" /* 0xFFE8 Timer0_A3 CC0 */
|
|
|
3611 |
#else
|
|
|
3612 |
#define TIMER0_A0_VECTOR (52 * 1u) /* 0xFFE8 Timer0_A3 CC0 */
|
|
|
3613 |
/*#define TIMER0_A0_ISR(func) ISR_VECTOR(func, ".int52") */ /* 0xFFE8 Timer0_A3 CC0 */ /* CCE V2 Style */
|
|
|
3614 |
#endif
|
|
|
3615 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3616 |
#define USCI_B0_VECTOR ".int54" /* 0xFFEC USCI B0 Receive/Transmit */
|
|
|
3617 |
#else
|
|
|
3618 |
#define USCI_B0_VECTOR (54 * 1u) /* 0xFFEC USCI B0 Receive/Transmit */
|
|
|
3619 |
/*#define USCI_B0_ISR(func) ISR_VECTOR(func, ".int54") */ /* 0xFFEC USCI B0 Receive/Transmit */ /* CCE V2 Style */
|
|
|
3620 |
#endif
|
|
|
3621 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3622 |
#define USCI_A0_VECTOR ".int55" /* 0xFFEE USCI A0 Receive/Transmit */
|
|
|
3623 |
#else
|
|
|
3624 |
#define USCI_A0_VECTOR (55 * 1u) /* 0xFFEE USCI A0 Receive/Transmit */
|
|
|
3625 |
/*#define USCI_A0_ISR(func) ISR_VECTOR(func, ".int55") */ /* 0xFFEE USCI A0 Receive/Transmit */ /* CCE V2 Style */
|
|
|
3626 |
#endif
|
|
|
3627 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3628 |
#define WDT_VECTOR ".int56" /* 0xFFF0 Watchdog Timer */
|
|
|
3629 |
#else
|
|
|
3630 |
#define WDT_VECTOR (56 * 1u) /* 0xFFF0 Watchdog Timer */
|
|
|
3631 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int56") */ /* 0xFFF0 Watchdog Timer */ /* CCE V2 Style */
|
|
|
3632 |
#endif
|
|
|
3633 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3634 |
#define TIMER0_D1_VECTOR ".int57" /* 0xFFE2 Timer0_D3 CC1-2, TA */
|
|
|
3635 |
#else
|
|
|
3636 |
#define TIMER0_D1_VECTOR (57 * 1u) /* 0xFFE2 Timer0_D3 CC1-2, TA */
|
|
|
3637 |
/*#define TIMER0_D1_ISR(func) ISR_VECTOR(func, ".int57") */ /* 0xFFE2 Timer0_D3 CC1-2, TA */ /* CCE V2 Style */
|
|
|
3638 |
#endif
|
|
|
3639 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3640 |
#define TIMER0_D0_VECTOR ".int58" /* 0xFFE4 Timer0_D3 CC0 */
|
|
|
3641 |
#else
|
|
|
3642 |
#define TIMER0_D0_VECTOR (58 * 1u) /* 0xFFE4 Timer0_D3 CC0 */
|
|
|
3643 |
/*#define TIMER0_D0_ISR(func) ISR_VECTOR(func, ".int58") */ /* 0xFFE4 Timer0_D3 CC0 */ /* CCE V2 Style */
|
|
|
3644 |
#endif
|
|
|
3645 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3646 |
#define TEC0_VECTOR ".int59" /* 0xFFF6 Timer Event Controller 0 */
|
|
|
3647 |
#else
|
|
|
3648 |
#define TEC0_VECTOR (59 * 1u) /* 0xFFF6 Timer Event Controller 0 */
|
|
|
3649 |
/*#define TEC0_ISR(func) ISR_VECTOR(func, ".int59") */ /* 0xFFF6 Timer Event Controller 0 */ /* CCE V2 Style */
|
|
|
3650 |
#endif
|
|
|
3651 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3652 |
#define COMP_B_VECTOR ".int60" /* 0xFFF8 Watchdog Timer */
|
|
|
3653 |
#else
|
|
|
3654 |
#define COMP_B_VECTOR (60 * 1u) /* 0xFFF8 Watchdog Timer */
|
|
|
3655 |
/*#define COMP_B_ISR(func) ISR_VECTOR(func, ".int60") */ /* 0xFFF8 Watchdog Timer */ /* CCE V2 Style */
|
|
|
3656 |
#endif
|
|
|
3657 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3658 |
#define UNMI_VECTOR ".int61" /* 0xFFFA User Non-maskable */
|
|
|
3659 |
#else
|
|
|
3660 |
#define UNMI_VECTOR (61 * 1u) /* 0xFFFA User Non-maskable */
|
|
|
3661 |
/*#define UNMI_ISR(func) ISR_VECTOR(func, ".int61") */ /* 0xFFFA User Non-maskable */ /* CCE V2 Style */
|
|
|
3662 |
#endif
|
|
|
3663 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3664 |
#define SYSNMI_VECTOR ".int62" /* 0xFFFC System Non-maskable */
|
|
|
3665 |
#else
|
|
|
3666 |
#define SYSNMI_VECTOR (62 * 1u) /* 0xFFFC System Non-maskable */
|
|
|
3667 |
/*#define SYSNMI_ISR(func) ISR_VECTOR(func, ".int62") */ /* 0xFFFC System Non-maskable */ /* CCE V2 Style */
|
|
|
3668 |
#endif
|
|
|
3669 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
3670 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
3671 |
#else
|
|
|
3672 |
#define RESET_VECTOR (63 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
3673 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int63") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
3674 |
#endif
|
|
|
3675 |
|
|
|
3676 |
/************************************************************
|
|
|
3677 |
* End of Modules
|
|
|
3678 |
************************************************************/
|
|
|
3679 |
|
|
|
3680 |
#ifdef __cplusplus
|
|
|
3681 |
}
|
|
|
3682 |
#endif /* extern "C" */
|
|
|
3683 |
|
|
|
3684 |
#endif /* #ifndef __MSP430F5131 */
|
|
|
3685 |
|