| 2850 |
dpurdie |
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/******************************************************************************/
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2 |
/* msp430f5131.cmd */
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/* - Linker Command File for defintions in the header file */
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4 |
/* Please do not change ! */
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/* */
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/******************************************************************************/
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/************************************************************
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* STANDARD BITS
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11 |
************************************************************/
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/************************************************************
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* STATUS REGISTER BITS
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14 |
************************************************************/
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/************************************************************
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* CPU
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17 |
************************************************************/
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/************************************************************
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19 |
* PERIPHERAL FILE MAP
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20 |
************************************************************/
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21 |
/************************************************************
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22 |
* Comparator B
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23 |
************************************************************/
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24 |
CBCTL0 = 0x08C0;
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25 |
CBCTL0_L = 0x08C0;
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26 |
CBCTL0_H = 0x08C1;
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27 |
CBCTL1 = 0x08C2;
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28 |
CBCTL1_L = 0x08C2;
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29 |
CBCTL1_H = 0x08C3;
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30 |
CBCTL2 = 0x08C4;
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31 |
CBCTL2_L = 0x08C4;
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32 |
CBCTL2_H = 0x08C5;
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33 |
CBCTL3 = 0x08C6;
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34 |
CBCTL3_L = 0x08C6;
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35 |
CBCTL3_H = 0x08C7;
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36 |
CBINT = 0x08CC;
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37 |
CBINT_L = 0x08CC;
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38 |
CBINT_H = 0x08CD;
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39 |
CBIV = 0x08CE;
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/*************************************************************
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* CRC Module
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42 |
*************************************************************/
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CRCDI = 0x0150;
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44 |
CRCDI_L = 0x0150;
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45 |
CRCDI_H = 0x0151;
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CRCDIRB = 0x0152;
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47 |
CRCDIRB_L = 0x0152;
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48 |
CRCDIRB_H = 0x0153;
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49 |
CRCINIRES = 0x0154;
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50 |
CRCINIRES_L = 0x0154;
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51 |
CRCINIRES_H = 0x0155;
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CRCRESR = 0x0156;
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53 |
CRCRESR_L = 0x0156;
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CRCRESR_H = 0x0157;
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/************************************************************
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* DMA_X
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************************************************************/
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58 |
DMACTL0 = 0x0500;
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59 |
DMACTL0_L = 0x0500;
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DMACTL0_H = 0x0501;
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61 |
DMACTL1 = 0x0502;
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DMACTL1_L = 0x0502;
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DMACTL1_H = 0x0503;
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DMACTL2 = 0x0504;
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DMACTL2_L = 0x0504;
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DMACTL2_H = 0x0505;
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67 |
DMACTL3 = 0x0506;
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68 |
DMACTL3_L = 0x0506;
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DMACTL3_H = 0x0507;
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70 |
DMACTL4 = 0x0508;
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71 |
DMACTL4_L = 0x0508;
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72 |
DMACTL4_H = 0x0509;
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DMAIV = 0x050E;
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DMAIV_L = 0x050E;
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DMAIV_H = 0x050F;
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DMA0CTL = 0x0510;
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DMA0CTL_L = 0x0510;
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DMA0CTL_H = 0x0511;
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DMA0SA = 0x0512;
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DMA0SAL = 0x0512;
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81 |
DMA0DA = 0x0516;
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82 |
DMA0DAL = 0x0516;
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DMA0SZ = 0x051A;
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DMA1CTL = 0x0520;
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DMA1CTL_L = 0x0520;
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DMA1CTL_H = 0x0521;
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DMA1SA = 0x0522;
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DMA1SAL = 0x0522;
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DMA1DA = 0x0526;
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DMA1DAL = 0x0526;
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DMA1SZ = 0x052A;
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DMA2CTL = 0x0530;
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DMA2CTL_L = 0x0530;
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DMA2CTL_H = 0x0531;
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DMA2SA = 0x0532;
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DMA2SAL = 0x0532;
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DMA2DA = 0x0536;
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DMA2DAL = 0x0536;
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DMA2SZ = 0x053A;
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/*************************************************************
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101 |
* Flash Memory
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102 |
*************************************************************/
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103 |
FCTL1 = 0x0140;
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104 |
FCTL1_L = 0x0140;
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105 |
FCTL1_H = 0x0141;
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FCTL3 = 0x0144;
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107 |
FCTL3_L = 0x0144;
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108 |
FCTL3_H = 0x0145;
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109 |
FCTL4 = 0x0146;
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110 |
FCTL4_L = 0x0146;
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111 |
FCTL4_H = 0x0147;
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112 |
/************************************************************
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* HARDWARE MULTIPLIER 32Bit
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114 |
************************************************************/
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MPY = 0x04C0;
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116 |
MPY_L = 0x04C0;
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117 |
MPY_H = 0x04C1;
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118 |
MPYS = 0x04C2;
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119 |
MPYS_L = 0x04C2;
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120 |
MPYS_H = 0x04C3;
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121 |
MAC = 0x04C4;
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122 |
MAC_L = 0x04C4;
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123 |
MAC_H = 0x04C5;
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124 |
MACS = 0x04C6;
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MACS_L = 0x04C6;
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126 |
MACS_H = 0x04C7;
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127 |
OP2 = 0x04C8;
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128 |
OP2_L = 0x04C8;
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129 |
OP2_H = 0x04C9;
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RESLO = 0x04CA;
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131 |
RESLO_L = 0x04CA;
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132 |
RESLO_H = 0x04CB;
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RESHI = 0x04CC;
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134 |
RESHI_L = 0x04CC;
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RESHI_H = 0x04CD;
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SUMEXT = 0x04CE;
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137 |
SUMEXT_L = 0x04CE;
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138 |
SUMEXT_H = 0x04CF;
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139 |
MPY32L = 0x04D0;
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140 |
MPY32L_L = 0x04D0;
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141 |
MPY32L_H = 0x04D1;
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142 |
MPY32H = 0x04D2;
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143 |
MPY32H_L = 0x04D2;
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144 |
MPY32H_H = 0x04D3;
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145 |
MPYS32L = 0x04D4;
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146 |
MPYS32L_L = 0x04D4;
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147 |
MPYS32L_H = 0x04D5;
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148 |
MPYS32H = 0x04D6;
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149 |
MPYS32H_L = 0x04D6;
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150 |
MPYS32H_H = 0x04D7;
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151 |
MAC32L = 0x04D8;
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152 |
MAC32L_L = 0x04D8;
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153 |
MAC32L_H = 0x04D9;
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154 |
MAC32H = 0x04DA;
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155 |
MAC32H_L = 0x04DA;
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156 |
MAC32H_H = 0x04DB;
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MACS32L = 0x04DC;
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158 |
MACS32L_L = 0x04DC;
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MACS32L_H = 0x04DD;
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160 |
MACS32H = 0x04DE;
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161 |
MACS32H_L = 0x04DE;
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162 |
MACS32H_H = 0x04DF;
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OP2L = 0x04E0;
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164 |
OP2L_L = 0x04E0;
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OP2L_H = 0x04E1;
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166 |
OP2H = 0x04E2;
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167 |
OP2H_L = 0x04E2;
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168 |
OP2H_H = 0x04E3;
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169 |
RES0 = 0x04E4;
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170 |
RES0_L = 0x04E4;
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171 |
RES0_H = 0x04E5;
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172 |
RES1 = 0x04E6;
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173 |
RES1_L = 0x04E6;
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174 |
RES1_H = 0x04E7;
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175 |
RES2 = 0x04E8;
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176 |
RES2_L = 0x04E8;
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177 |
RES2_H = 0x04E9;
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178 |
RES3 = 0x04EA;
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179 |
RES3_L = 0x04EA;
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180 |
RES3_H = 0x04EB;
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181 |
MPY32CTL0 = 0x04EC;
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182 |
MPY32CTL0_L = 0x04EC;
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183 |
MPY32CTL0_H = 0x04ED;
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184 |
/************************************************************
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185 |
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
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186 |
************************************************************/
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187 |
PAIN = 0x0200;
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188 |
PAIN_L = 0x0200;
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189 |
PAIN_H = 0x0201;
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190 |
PAOUT = 0x0202;
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191 |
PAOUT_L = 0x0202;
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192 |
PAOUT_H = 0x0203;
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PADIR = 0x0204;
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194 |
PADIR_L = 0x0204;
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195 |
PADIR_H = 0x0205;
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196 |
PAREN = 0x0206;
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197 |
PAREN_L = 0x0206;
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198 |
PAREN_H = 0x0207;
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199 |
PADS = 0x0208;
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200 |
PADS_L = 0x0208;
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201 |
PADS_H = 0x0209;
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202 |
PASEL = 0x020A;
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203 |
PASEL_L = 0x020A;
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204 |
PASEL_H = 0x020B;
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205 |
PAIES = 0x0218;
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206 |
PAIES_L = 0x0218;
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207 |
PAIES_H = 0x0219;
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208 |
PAIE = 0x021A;
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209 |
PAIE_L = 0x021A;
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210 |
PAIE_H = 0x021B;
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211 |
PAIFG = 0x021C;
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212 |
PAIFG_L = 0x021C;
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213 |
PAIFG_H = 0x021D;
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214 |
P1IV = 0x020E;
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215 |
P2IV = 0x021E;
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216 |
/************************************************************
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* DIGITAL I/O Port3 Pull up / Pull down Resistors
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218 |
************************************************************/
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219 |
PBIN = 0x0220;
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220 |
PBIN_L = 0x0220;
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221 |
PBIN_H = 0x0221;
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222 |
PBOUT = 0x0222;
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223 |
PBOUT_L = 0x0222;
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224 |
PBOUT_H = 0x0223;
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225 |
PBDIR = 0x0224;
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226 |
PBDIR_L = 0x0224;
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227 |
PBDIR_H = 0x0225;
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228 |
PBREN = 0x0226;
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229 |
PBREN_L = 0x0226;
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230 |
PBREN_H = 0x0227;
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231 |
PBDS = 0x0228;
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232 |
PBDS_L = 0x0228;
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233 |
PBDS_H = 0x0229;
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234 |
PBSEL = 0x022A;
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235 |
PBSEL_L = 0x022A;
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236 |
PBSEL_H = 0x022B;
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237 |
/************************************************************
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238 |
* DIGITAL I/O PortJ Pull up / Pull down Resistors
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239 |
************************************************************/
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240 |
PJIN = 0x0320;
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241 |
PJIN_L = 0x0320;
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242 |
PJIN_H = 0x0321;
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243 |
PJOUT = 0x0322;
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244 |
PJOUT_L = 0x0322;
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245 |
PJOUT_H = 0x0323;
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246 |
PJDIR = 0x0324;
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247 |
PJDIR_L = 0x0324;
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248 |
PJDIR_H = 0x0325;
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249 |
PJREN = 0x0326;
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250 |
PJREN_L = 0x0326;
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251 |
PJREN_H = 0x0327;
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252 |
PJDS = 0x0328;
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253 |
PJDS_L = 0x0328;
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254 |
PJDS_H = 0x0329;
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255 |
PJSEL = 0x032A;
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256 |
PJSEL_L = 0x032A;
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257 |
PJSEL_H = 0x032B;
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258 |
/************************************************************
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259 |
* PORT MAPPING CONTROLLER
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260 |
************************************************************/
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261 |
PMAPKEYID = 0x01C0;
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262 |
PMAPKEYID_L = 0x01C0;
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263 |
PMAPKEYID_H = 0x01C1;
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264 |
PMAPCTL = 0x01C2;
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265 |
PMAPCTL_L = 0x01C2;
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266 |
PMAPCTL_H = 0x01C3;
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267 |
/************************************************************
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268 |
* PORT 1 MAPPING CONTROLLER
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269 |
************************************************************/
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270 |
P1MAP01 = 0x01C8;
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271 |
P1MAP01_L = 0x01C8;
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272 |
P1MAP01_H = 0x01C9;
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273 |
P1MAP23 = 0x01CA;
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274 |
P1MAP23_L = 0x01CA;
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275 |
P1MAP23_H = 0x01CB;
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276 |
P1MAP45 = 0x01CC;
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277 |
P1MAP45_L = 0x01CC;
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278 |
P1MAP45_H = 0x01CD;
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279 |
P1MAP67 = 0x01CE;
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280 |
P1MAP67_L = 0x01CE;
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281 |
P1MAP67_H = 0x01CF;
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282 |
/************************************************************
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283 |
* PORT 2 MAPPING CONTROLLER
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284 |
************************************************************/
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285 |
P2MAP01 = 0x01D0;
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286 |
P2MAP01_L = 0x01D0;
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287 |
P2MAP01_H = 0x01D1;
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288 |
P2MAP23 = 0x01D2;
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289 |
P2MAP23_L = 0x01D2;
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290 |
P2MAP23_H = 0x01D3;
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291 |
P2MAP45 = 0x01D4;
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292 |
P2MAP45_L = 0x01D4;
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293 |
P2MAP45_H = 0x01D5;
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294 |
P2MAP67 = 0x01D6;
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295 |
P2MAP67_L = 0x01D6;
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296 |
P2MAP67_H = 0x01D7;
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297 |
/************************************************************
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298 |
* PORT 3 MAPPING CONTROLLER
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299 |
************************************************************/
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300 |
P3MAP01 = 0x01D8;
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301 |
P3MAP01_L = 0x01D8;
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302 |
P3MAP01_H = 0x01D9;
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303 |
P3MAP23 = 0x01DA;
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304 |
P3MAP23_L = 0x01DA;
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305 |
P3MAP23_H = 0x01DB;
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306 |
P3MAP45 = 0x01DC;
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307 |
P3MAP45_L = 0x01DC;
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308 |
P3MAP45_H = 0x01DD;
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309 |
P3MAP67 = 0x01DE;
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310 |
P3MAP67_L = 0x01DE;
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311 |
P3MAP67_H = 0x01DF;
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312 |
/************************************************************
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313 |
* PMM - Power Management System
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314 |
************************************************************/
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315 |
PMMCTL0 = 0x0120;
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316 |
PMMCTL0_L = 0x0120;
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317 |
PMMCTL0_H = 0x0121;
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318 |
PMMCTL1 = 0x0122;
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319 |
PMMCTL1_L = 0x0122;
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320 |
PMMCTL1_H = 0x0123;
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321 |
SVSMHCTL = 0x0124;
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322 |
SVSMHCTL_L = 0x0124;
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323 |
SVSMHCTL_H = 0x0125;
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324 |
SVSMLCTL = 0x0126;
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325 |
SVSMLCTL_L = 0x0126;
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326 |
SVSMLCTL_H = 0x0127;
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327 |
SVSMIO = 0x0128;
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328 |
SVSMIO_L = 0x0128;
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329 |
SVSMIO_H = 0x0129;
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330 |
PMMIFG = 0x012C;
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331 |
PMMIFG_L = 0x012C;
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332 |
PMMIFG_H = 0x012D;
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|
|
333 |
PMMRIE = 0x012E;
|
|
|
334 |
PMMRIE_L = 0x012E;
|
|
|
335 |
PMMRIE_H = 0x012F;
|
|
|
336 |
PM5CTL0 = 0x0130;
|
|
|
337 |
PM5CTL0_L = 0x0130;
|
|
|
338 |
PM5CTL0_H = 0x0131;
|
|
|
339 |
/*************************************************************
|
|
|
340 |
* RAM Control Module
|
|
|
341 |
*************************************************************/
|
|
|
342 |
RCCTL0 = 0x0158;
|
|
|
343 |
RCCTL0_L = 0x0158;
|
|
|
344 |
RCCTL0_H = 0x0159;
|
|
|
345 |
/************************************************************
|
|
|
346 |
* Shared Reference
|
|
|
347 |
************************************************************/
|
|
|
348 |
REFCTL0 = 0x01B0;
|
|
|
349 |
REFCTL0_L = 0x01B0;
|
|
|
350 |
REFCTL0_H = 0x01B1;
|
|
|
351 |
/************************************************************
|
|
|
352 |
* SFR - Special Function Register Module
|
|
|
353 |
************************************************************/
|
|
|
354 |
SFRIE1 = 0x0100;
|
|
|
355 |
SFRIE1_L = 0x0100;
|
|
|
356 |
SFRIE1_H = 0x0101;
|
|
|
357 |
SFRIFG1 = 0x0102;
|
|
|
358 |
SFRIFG1_L = 0x0102;
|
|
|
359 |
SFRIFG1_H = 0x0103;
|
|
|
360 |
SFRRPCR = 0x0104;
|
|
|
361 |
SFRRPCR_L = 0x0104;
|
|
|
362 |
SFRRPCR_H = 0x0105;
|
|
|
363 |
/************************************************************
|
|
|
364 |
* SYS - System Module
|
|
|
365 |
************************************************************/
|
|
|
366 |
SYSCTL = 0x0180;
|
|
|
367 |
SYSCTL_L = 0x0180;
|
|
|
368 |
SYSCTL_H = 0x0181;
|
|
|
369 |
SYSBSLC = 0x0182;
|
|
|
370 |
SYSBSLC_L = 0x0182;
|
|
|
371 |
SYSBSLC_H = 0x0183;
|
|
|
372 |
SYSJMBC = 0x0186;
|
|
|
373 |
SYSJMBC_L = 0x0186;
|
|
|
374 |
SYSJMBC_H = 0x0187;
|
|
|
375 |
SYSJMBI0 = 0x0188;
|
|
|
376 |
SYSJMBI0_L = 0x0188;
|
|
|
377 |
SYSJMBI0_H = 0x0189;
|
|
|
378 |
SYSJMBI1 = 0x018A;
|
|
|
379 |
SYSJMBI1_L = 0x018A;
|
|
|
380 |
SYSJMBI1_H = 0x018B;
|
|
|
381 |
SYSJMBO0 = 0x018C;
|
|
|
382 |
SYSJMBO0_L = 0x018C;
|
|
|
383 |
SYSJMBO0_H = 0x018D;
|
|
|
384 |
SYSJMBO1 = 0x018E;
|
|
|
385 |
SYSJMBO1_L = 0x018E;
|
|
|
386 |
SYSJMBO1_H = 0x018F;
|
|
|
387 |
SYSBERRIV = 0x0198;
|
|
|
388 |
SYSBERRIV_L = 0x0198;
|
|
|
389 |
SYSBERRIV_H = 0x0199;
|
|
|
390 |
SYSUNIV = 0x019A;
|
|
|
391 |
SYSUNIV_L = 0x019A;
|
|
|
392 |
SYSUNIV_H = 0x019B;
|
|
|
393 |
SYSSNIV = 0x019C;
|
|
|
394 |
SYSSNIV_L = 0x019C;
|
|
|
395 |
SYSSNIV_H = 0x019D;
|
|
|
396 |
SYSRSTIV = 0x019E;
|
|
|
397 |
SYSRSTIV_L = 0x019E;
|
|
|
398 |
SYSRSTIV_H = 0x019F;
|
|
|
399 |
/************************************************************
|
|
|
400 |
* Timer0_A3
|
|
|
401 |
************************************************************/
|
|
|
402 |
TA0CTL = 0x03C0;
|
|
|
403 |
TA0CCTL0 = 0x03C2;
|
|
|
404 |
TA0CCTL1 = 0x03C4;
|
|
|
405 |
TA0CCTL2 = 0x03C6;
|
|
|
406 |
TA0R = 0x03D0;
|
|
|
407 |
TA0CCR0 = 0x03D2;
|
|
|
408 |
TA0CCR1 = 0x03D4;
|
|
|
409 |
TA0CCR2 = 0x03D6;
|
|
|
410 |
TA0IV = 0x03EE;
|
|
|
411 |
TA0EX0 = 0x03E0;
|
|
|
412 |
/************************************************************
|
|
|
413 |
* Timer0_D3
|
|
|
414 |
************************************************************/
|
|
|
415 |
TD0CTL0 = 0x0B00;
|
|
|
416 |
TD0CTL1 = 0x0B02;
|
|
|
417 |
TD0CTL2 = 0x0B04;
|
|
|
418 |
TD0R = 0x0B06;
|
|
|
419 |
TD0CCTL0 = 0x0B08;
|
|
|
420 |
TD0CCR0 = 0x0B0A;
|
|
|
421 |
TD0CL0 = 0x0B0C;
|
|
|
422 |
TD0CCTL1 = 0x0B0E;
|
|
|
423 |
TD0CCR1 = 0x0B10;
|
|
|
424 |
TD0CL1 = 0x0B12;
|
|
|
425 |
TD0CCTL2 = 0x0B14;
|
|
|
426 |
TD0CCR2 = 0x0B16;
|
|
|
427 |
TD0CL2 = 0x0B18;
|
|
|
428 |
TD0HCTL0 = 0x0B38;
|
|
|
429 |
TD0HCTL1 = 0x0B3A;
|
|
|
430 |
TD0HINT = 0x0B3C;
|
|
|
431 |
TD0IV = 0x0B3E;
|
|
|
432 |
/************************************************************
|
|
|
433 |
* Timer1_D3
|
|
|
434 |
************************************************************/
|
|
|
435 |
TD1CTL0 = 0x0B40;
|
|
|
436 |
TD1CTL1 = 0x0B42;
|
|
|
437 |
TD1CTL2 = 0x0B44;
|
|
|
438 |
TD1R = 0x0B46;
|
|
|
439 |
TD1CCTL0 = 0x0B48;
|
|
|
440 |
TD1CCR0 = 0x0B4A;
|
|
|
441 |
TD1CL0 = 0x0B4C;
|
|
|
442 |
TD1CCTL1 = 0x0B4E;
|
|
|
443 |
TD1CCR1 = 0x0B50;
|
|
|
444 |
TD1CL1 = 0x0B52;
|
|
|
445 |
TD1CCTL2 = 0x0B54;
|
|
|
446 |
TD1CCR2 = 0x0B56;
|
|
|
447 |
TD1CL2 = 0x0B58;
|
|
|
448 |
TD1HCTL0 = 0x0B78;
|
|
|
449 |
TD1HCTL1 = 0x0B7A;
|
|
|
450 |
TD1HINT = 0x0B7C;
|
|
|
451 |
TD1IV = 0x0B7E;
|
|
|
452 |
/************************************************************
|
|
|
453 |
* Timer Event Control 0
|
|
|
454 |
************************************************************/
|
|
|
455 |
TEC0XCTL0 = 0x0C00;
|
|
|
456 |
TEC0XCTL0_L = 0x0C00;
|
|
|
457 |
TEC0XCTL0_H = 0x0C01;
|
|
|
458 |
TEC0XCTL1 = 0x0C02;
|
|
|
459 |
TEC0XCTL1_L = 0x0C02;
|
|
|
460 |
TEC0XCTL1_H = 0x0C03;
|
|
|
461 |
TEC0XCTL2 = 0x0C04;
|
|
|
462 |
TEC0XCTL2_L = 0x0C04;
|
|
|
463 |
TEC0XCTL2_H = 0x0C05;
|
|
|
464 |
TEC0STA = 0x0C06;
|
|
|
465 |
TEC0STA_L = 0x0C06;
|
|
|
466 |
TEC0STA_H = 0x0C07;
|
|
|
467 |
TEC0XINT = 0x0C08;
|
|
|
468 |
TEC0XINT_L = 0x0C08;
|
|
|
469 |
TEC0XINT_H = 0x0C09;
|
|
|
470 |
TEC0IV = 0x0C0A;
|
|
|
471 |
TEC0IV_L = 0x0C0A;
|
|
|
472 |
TEC0IV_H = 0x0C0B;
|
|
|
473 |
/************************************************************
|
|
|
474 |
* Timer Event Control 1
|
|
|
475 |
************************************************************/
|
|
|
476 |
TEC1XCTL0 = 0x0C20;
|
|
|
477 |
TEC1XCTL0_L = 0x0C20;
|
|
|
478 |
TEC1XCTL0_H = 0x0C21;
|
|
|
479 |
TEC1XCTL1 = 0x0C22;
|
|
|
480 |
TEC1XCTL1_L = 0x0C22;
|
|
|
481 |
TEC1XCTL1_H = 0x0C23;
|
|
|
482 |
TEC1XCTL2 = 0x0C24;
|
|
|
483 |
TEC1XCTL2_L = 0x0C24;
|
|
|
484 |
TEC1XCTL2_H = 0x0C25;
|
|
|
485 |
TEC1STA = 0x0C26;
|
|
|
486 |
TEC1STA_L = 0x0C26;
|
|
|
487 |
TEC1STA_H = 0x0C27;
|
|
|
488 |
TEC1XINT = 0x0C28;
|
|
|
489 |
TEC1XINT_L = 0x0C28;
|
|
|
490 |
TEC1XINT_H = 0x0C29;
|
|
|
491 |
TEC1IV = 0x0C2A;
|
|
|
492 |
TEC1IV_L = 0x0C2A;
|
|
|
493 |
TEC1IV_H = 0x0C2B;
|
|
|
494 |
/************************************************************
|
|
|
495 |
* UNIFIED CLOCK SYSTEM
|
|
|
496 |
************************************************************/
|
|
|
497 |
UCSCTL0 = 0x0160;
|
|
|
498 |
UCSCTL0_L = 0x0160;
|
|
|
499 |
UCSCTL0_H = 0x0161;
|
|
|
500 |
UCSCTL1 = 0x0162;
|
|
|
501 |
UCSCTL1_L = 0x0162;
|
|
|
502 |
UCSCTL1_H = 0x0163;
|
|
|
503 |
UCSCTL2 = 0x0164;
|
|
|
504 |
UCSCTL2_L = 0x0164;
|
|
|
505 |
UCSCTL2_H = 0x0165;
|
|
|
506 |
UCSCTL3 = 0x0166;
|
|
|
507 |
UCSCTL3_L = 0x0166;
|
|
|
508 |
UCSCTL3_H = 0x0167;
|
|
|
509 |
UCSCTL4 = 0x0168;
|
|
|
510 |
UCSCTL4_L = 0x0168;
|
|
|
511 |
UCSCTL4_H = 0x0169;
|
|
|
512 |
UCSCTL5 = 0x016A;
|
|
|
513 |
UCSCTL5_L = 0x016A;
|
|
|
514 |
UCSCTL5_H = 0x016B;
|
|
|
515 |
UCSCTL6 = 0x016C;
|
|
|
516 |
UCSCTL6_L = 0x016C;
|
|
|
517 |
UCSCTL6_H = 0x016D;
|
|
|
518 |
UCSCTL7 = 0x016E;
|
|
|
519 |
UCSCTL7_L = 0x016E;
|
|
|
520 |
UCSCTL7_H = 0x016F;
|
|
|
521 |
UCSCTL8 = 0x0170;
|
|
|
522 |
UCSCTL8_L = 0x0170;
|
|
|
523 |
UCSCTL8_H = 0x0171;
|
|
|
524 |
/************************************************************
|
|
|
525 |
* USCI A0
|
|
|
526 |
************************************************************/
|
|
|
527 |
UCA0CTLW0 = 0x05C0;
|
|
|
528 |
UCA0CTLW0_L = 0x05C0;
|
|
|
529 |
UCA0CTLW0_H = 0x05C1;
|
|
|
530 |
UCA0BRW = 0x05C6;
|
|
|
531 |
UCA0BRW_L = 0x05C6;
|
|
|
532 |
UCA0BRW_H = 0x05C7;
|
|
|
533 |
UCA0MCTL = 0x05C8;
|
|
|
534 |
UCA0STAT = 0x05CA;
|
|
|
535 |
UCA0RXBUF = 0x05CC;
|
|
|
536 |
UCA0TXBUF = 0x05CE;
|
|
|
537 |
UCA0ABCTL = 0x05D0;
|
|
|
538 |
UCA0IRCTL = 0x05D2;
|
|
|
539 |
UCA0IRCTL_L = 0x05D2;
|
|
|
540 |
UCA0IRCTL_H = 0x05D3;
|
|
|
541 |
UCA0ICTL = 0x05DC;
|
|
|
542 |
UCA0ICTL_L = 0x05DC;
|
|
|
543 |
UCA0ICTL_H = 0x05DD;
|
|
|
544 |
UCA0IV = 0x05DE;
|
|
|
545 |
/************************************************************
|
|
|
546 |
* USCI B0
|
|
|
547 |
************************************************************/
|
|
|
548 |
UCB0CTLW0 = 0x05E0;
|
|
|
549 |
UCB0CTLW0_L = 0x05E0;
|
|
|
550 |
UCB0CTLW0_H = 0x05E1;
|
|
|
551 |
UCB0BRW = 0x05E6;
|
|
|
552 |
UCB0BRW_L = 0x05E6;
|
|
|
553 |
UCB0BRW_H = 0x05E7;
|
|
|
554 |
UCB0STAT = 0x05EA;
|
|
|
555 |
UCB0RXBUF = 0x05EC;
|
|
|
556 |
UCB0TXBUF = 0x05EE;
|
|
|
557 |
UCB0I2COA = 0x05F0;
|
|
|
558 |
UCB0I2COA_L = 0x05F0;
|
|
|
559 |
UCB0I2COA_H = 0x05F1;
|
|
|
560 |
UCB0I2CSA = 0x05F2;
|
|
|
561 |
UCB0I2CSA_L = 0x05F2;
|
|
|
562 |
UCB0I2CSA_H = 0x05F3;
|
|
|
563 |
UCB0ICTL = 0x05FC;
|
|
|
564 |
UCB0ICTL_L = 0x05FC;
|
|
|
565 |
UCB0ICTL_H = 0x05FD;
|
|
|
566 |
UCB0IV = 0x05FE;
|
|
|
567 |
/************************************************************
|
|
|
568 |
* WATCHDOG TIMER A
|
|
|
569 |
************************************************************/
|
|
|
570 |
WDTCTL = 0x015C;
|
|
|
571 |
WDTCTL_L = 0x015C;
|
|
|
572 |
WDTCTL_H = 0x015D;
|
|
|
573 |
/************************************************************
|
|
|
574 |
* TLV Descriptors
|
|
|
575 |
************************************************************/
|
|
|
576 |
/************************************************************
|
|
|
577 |
* Interrupt Vectors (offset from 0xFF80)
|
|
|
578 |
************************************************************/
|
|
|
579 |
/************************************************************
|
|
|
580 |
* End of Modules
|
|
|
581 |
************************************************************/
|