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dpurdie |
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/********************************************************************
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*
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* Standard register and bit definitions for the Texas Instruments
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* MSP430 microcontroller.
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*
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* This file supports assembler and C development for
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* MSP430x471x6 devices.
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*
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* Texas Instruments, Version 1.1
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*
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* Rev. 1.0, First Release
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* Rev. 1.1, Corrected OSCCAP settings
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*
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*
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********************************************************************/
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#ifndef __msp430x471x6
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#define __msp430x471x6
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* PERIPHERAL FILE MAP */
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/*----------------------------------------------------------------------------*/
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/* External references resolved by a device-specific linker command file */
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#define SFR_8BIT(address) extern volatile unsigned char address
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#define SFR_16BIT(address) extern volatile unsigned int address
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//#define SFR_20BIT(address) extern volatile unsigned int address
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typedef void (* __SFR_FARPTR)();
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#define SFR_20BIT(address) extern __SFR_FARPTR address
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#define SFR_32BIT(address) extern volatile unsigned long address
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/************************************************************
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* STANDARD BITS
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************************************************************/
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#define BIT0 (0x0001)
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#define BIT1 (0x0002)
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#define BIT2 (0x0004)
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#define BIT3 (0x0008)
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#define BIT4 (0x0010)
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#define BIT5 (0x0020)
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#define BIT6 (0x0040)
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#define BIT7 (0x0080)
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#define BIT8 (0x0100)
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#define BIT9 (0x0200)
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#define BITA (0x0400)
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#define BITB (0x0800)
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#define BITC (0x1000)
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#define BITD (0x2000)
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#define BITE (0x4000)
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#define BITF (0x8000)
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/************************************************************
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* STATUS REGISTER BITS
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************************************************************/
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#define C (0x0001)
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#define Z (0x0002)
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#define N (0x0004)
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#define V (0x0100)
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#define GIE (0x0008)
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#define CPUOFF (0x0010)
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#define OSCOFF (0x0020)
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#define SCG0 (0x0040)
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#define SCG1 (0x0080)
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/* Low Power Modes coded with Bits 4-7 in SR */
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#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
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#define LPM0 (CPUOFF)
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#define LPM1 (SCG0+CPUOFF)
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#define LPM2 (SCG1+CPUOFF)
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#define LPM3 (SCG1+SCG0+CPUOFF)
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#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
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/* End #defines for assembler */
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#else /* Begin #defines for C */
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#define LPM0_bits (CPUOFF)
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#define LPM1_bits (SCG0+CPUOFF)
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#define LPM2_bits (SCG1+CPUOFF)
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#define LPM3_bits (SCG1+SCG0+CPUOFF)
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#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
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#include "in430.h"
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#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
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#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
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#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
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#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
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#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
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#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
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#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
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#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
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#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
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#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
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#endif /* End #defines for C */
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/************************************************************
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* CPU
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************************************************************/
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#define __MSP430_HAS_MSP430X_CPU__ /* Definition to show that it has MSP430X CPU */
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/************************************************************
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* PERIPHERAL FILE MAP
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************************************************************/
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/************************************************************
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* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
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************************************************************/
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SFR_8BIT(IE1); /* Interrupt Enable 1 */
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#define WDTIE (0x01) /* Watchdog Interrupt Enable */
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#define OFIE (0x02) /* Osc. Fault Interrupt Enable */
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#define NMIIE (0x10) /* NMI Interrupt Enable */
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#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */
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SFR_8BIT(IFG1); /* Interrupt Flag 1 */
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#define WDTIFG (0x01) /* WDT Interrupt Flag */
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#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */
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#define PORIFG (0x04) /* Power On Interrupt Flag */
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#define RSTIFG (0x08) /* Reset Interrupt Flag */
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#define NMIIFG (0x10) /* NMI Interrupt Flag */
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SFR_8BIT(IE2); /* Interrupt Enable 2 */
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#define UC0IE IE2
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#define UCA0RXIE (0x01)
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#define UCA0TXIE (0x02)
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#define UCB0RXIE (0x04)
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#define UCB0TXIE (0x08)
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#define BTIE (0x80)
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SFR_8BIT(IFG2); /* Interrupt Flag 2 */
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#define UC0IFG IFG2
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#define UCA0RXIFG (0x01)
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#define UCA0TXIFG (0x02)
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#define UCB0RXIFG (0x04)
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#define UCB0TXIFG (0x08)
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#define BTIFG (0x80)
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SFR_8BIT(UC1IE); /* USCI 1 Interrupt Enable */
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#define UCA1RXIE (0x01)
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#define UCA1TXIE (0x02)
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#define UCB1RXIE (0x04)
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#define UCB1TXIE (0x08)
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SFR_8BIT(UC1IFG); /* ISCI 1 Interrupt Flags */
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#define UCA1RXIFG (0x01)
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#define UCA1TXIFG (0x02)
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#define UCB1RXIFG (0x04)
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#define UCB1TXIFG (0x08)
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/************************************************************
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* BASIC TIMER with Real Time Clock
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************************************************************/
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#define __MSP430_HAS_BT_RTC__ /* Definition to show that Module is available */
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SFR_8BIT(BTCTL); /* Basic Timer Control */
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SFR_8BIT(RTCCTL); /* Real Time Clock Control */
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SFR_8BIT(RTCNT1); /* Real Time Counter 1 */
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SFR_8BIT(RTCNT2); /* Real Time Counter 2 */
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SFR_8BIT(RTCNT3); /* Real Time Counter 3 */
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SFR_8BIT(RTCNT4); /* Real Time Counter 4 */
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SFR_8BIT(BTCNT1); /* Basic Timer Count 1 */
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SFR_8BIT(BTCNT2); /* Basic Timer Count 2 */
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SFR_8BIT(RTCDAY); /* Real Time Clock Day */
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SFR_8BIT(RTCMON); /* Real Time Clock Month */
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SFR_8BIT(RTCYEARL); /* Real Time Clock Year (Low Byte) */
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SFR_8BIT(RTCYEARH); /* Real Time Clock Year (High Byte) */
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#define RTCSEC RTCNT1
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#define RTCMIN RTCNT2
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#define RTCHOUR RTCNT3
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#define RTCDOW RTCNT4
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SFR_16BIT(RTCTL); /* Basic/Real Timer Control */
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SFR_16BIT(RTCTIM0); /* Real Time Clock Time 0 */
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SFR_16BIT(RTCTIM1); /* Real Time Clock Time 1 */
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SFR_16BIT(BTCNT12); /* Basic Timer Count 1/2 */
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SFR_16BIT(RTCDATE); /* Real Time Clock Date */
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SFR_16BIT(RTCYEAR); /* Real Time Clock Year */
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#define RTCNT12 RTCTIM0
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#define RTCNT34 RTCTIM1
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#define BTSSEL (0x80) /* fBT = fMCLK (main clock) */
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#define BTHOLD (0x40) /* BT1 is held if this bit is set */
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#define BTDIV (0x20) /* fCLK2 = ACLK:256 */
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//#define res (0x10)
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//#define res (0x08)
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#define BTIP2 (0x04)
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#define BTIP1 (0x02)
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#define BTIP0 (0x01)
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#define RTCBCD (0x80) /* RTC BCD Select */
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#define RTCHOLD (0x40) /* RTC Hold */
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#define RTCMODE1 (0x20) /* RTC Mode 1 */
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#define RTCMODE0 (0x10) /* RTC Mode 0 */
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#define RTCTEV1 (0x08) /* RTC Time Event 1 */
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#define RTCTEV0 (0x04) /* RTC Time Event 0 */
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#define RTCIE (0x02) /* RTC Interrupt Enable */
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#define RTCFG (0x01) /* RTC Event Flag */
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#define RTCTEV_0 (0x00) /* RTC Time Event: 0 */
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#define RTCTEV_1 (0x04) /* RTC Time Event: 1 */
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#define RTCTEV_2 (0x08) /* RTC Time Event: 2 */
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#define RTCTEV_3 (0x0C) /* RTC Time Event: 3 */
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#define RTCMODE_0 (0x00) /* RTC Mode: 0 */
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#define RTCMODE_1 (0x10) /* RTC Mode: 1 */
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#define RTCMODE_2 (0x20) /* RTC Mode: 2 */
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#define RTCMODE_3 (0x30) /* RTC Mode: 3 */
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/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
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#define BT_fCLK2_ACLK (0x00)
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#define BT_fCLK2_ACLK_DIV256 (BTDIV)
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#define BT_fCLK2_MCLK (BTSSEL)
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/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
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#define BT_fCLK2_DIV2 (0x00) /* fINT = fCLK2:2 (default) */
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#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */
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#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */
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#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT = fCLK2:16 */
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#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */
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#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT = fCLK2:64 */
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#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT = fCLK2:128 */
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#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 */
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/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
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/* fBT=fACLK is thought for longer interval times */
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#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */
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#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */
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#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */
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#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms " */
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#define BT_ADLY_1 (BTIP2) /* 1ms " */
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#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms " */
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#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms " */
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#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms " */
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#define BT_ADLY_16 (BTDIV) /* 16ms " */
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#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms " */
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#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms " */
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#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms " */
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#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms " */
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#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms " */
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#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms " */
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#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms " */
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/* fCLK2=fMCLK (1MHz) is thought for short interval times */
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/* the timing for short intervals is more precise than ACLK */
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/* NOTE */
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/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
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/* Too low interval time results in interrupts too frequent for the processor to handle! */
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#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
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#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms " *** too short for */
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#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms " *** interrupt */
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#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms " *** handling */
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#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms " */
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#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms " */
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#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms " */
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#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms " */
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/* Hold coded with Bits 6-7 in BT(1)CTL */
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/* this is for BT */
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#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
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#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
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/* INTERRUPT CONTROL BITS */
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/* #define BTIE 0x80 */
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/* #define BTIFG 0x80 */
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/************************************************************
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* Comparator A
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************************************************************/
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#define __MSP430_HAS_COMPA__ /* Definition to show that Module is available */
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SFR_8BIT(CACTL1); /* Comparator A Control 1 */
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SFR_8BIT(CACTL2); /* Comparator A Control 2 */
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SFR_8BIT(CAPD); /* Comparator A Port Disable */
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#define CAIFG (0x01) /* Comp. A Interrupt Flag */
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#define CAIE (0x02) /* Comp. A Interrupt Enable */
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#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
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#define CAON (0x08) /* Comp. A enable */
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#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
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#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
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#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
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#define CAEX (0x80) /* Comp. A Exchange Inputs */
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#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
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#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
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#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
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#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
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296 |
#define CAOUT (0x01) /* Comp. A Output */
|
|
|
297 |
#define CAF (0x02) /* Comp. A Enable Output Filter */
|
|
|
298 |
#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */
|
|
|
299 |
#define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */
|
|
|
300 |
#define CACTL24 (0x10)
|
|
|
301 |
#define CACTL25 (0x20)
|
|
|
302 |
#define CACTL26 (0x40)
|
|
|
303 |
#define CACTL27 (0x80)
|
|
|
304 |
|
|
|
305 |
#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
|
|
|
306 |
#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
|
|
|
307 |
#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
|
|
|
308 |
#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
|
|
|
309 |
#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
|
|
|
310 |
#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
|
|
|
311 |
#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
|
|
|
312 |
#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
|
|
|
313 |
|
|
|
314 |
/************************************************************
|
|
|
315 |
* DMA_X
|
|
|
316 |
************************************************************/
|
|
|
317 |
#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
|
|
|
318 |
|
|
|
319 |
SFR_16BIT(DMACTL0); /* DMA Module Control 0 */
|
|
|
320 |
#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
|
|
|
321 |
#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
|
|
|
322 |
#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
|
|
|
323 |
#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
|
|
|
324 |
#define DMA1TSEL0 (0x0010) /* DMA channel 1 transfer select bit 0 */
|
|
|
325 |
#define DMA1TSEL1 (0x0020) /* DMA channel 1 transfer select bit 1 */
|
|
|
326 |
#define DMA1TSEL2 (0x0040) /* DMA channel 1 transfer select bit 2 */
|
|
|
327 |
#define DMA1TSEL3 (0x0080) /* DMA channel 1 transfer select bit 3 */
|
|
|
328 |
#define DMA2TSEL0 (0x0100) /* DMA channel 2 transfer select bit 0 */
|
|
|
329 |
#define DMA2TSEL1 (0x0200) /* DMA channel 2 transfer select bit 1 */
|
|
|
330 |
#define DMA2TSEL2 (0x0400) /* DMA channel 2 transfer select bit 2 */
|
|
|
331 |
#define DMA2TSEL3 (0x0800) /* DMA channel 2 transfer select bit 3 */
|
|
|
332 |
|
|
|
333 |
#define DMA0TSEL_0 (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw)*/
|
|
|
334 |
#define DMA0TSEL_1 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer_A (TACCR2.IFG) */
|
|
|
335 |
#define DMA0TSEL_2 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer_B (TBCCR2.IFG) */
|
|
|
336 |
#define DMA0TSEL_3 (3*0x0001u) /* DMA channel 0 transfer select 3: USCIA0 receive */
|
|
|
337 |
#define DMA0TSEL_4 (4*0x0001u) /* DMA channel 0 transfer select 4: USCIA0 transmit */
|
|
|
338 |
#define DMA0TSEL_5 (5*0x0001u) /* DMA channel 0 transfer select 5: Reserved */
|
|
|
339 |
#define DMA0TSEL_6 (6*0x0001u) /* DMA channel 0 transfer select 6: SD16 (SD16IFG) */
|
|
|
340 |
#define DMA0TSEL_7 (7*0x0001u) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */
|
|
|
341 |
#define DMA0TSEL_8 (8*0x0001u) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */
|
|
|
342 |
#define DMA0TSEL_9 (9*0x0001u) /* DMA channel 0 transfer select 9: USCIA1 receive */
|
|
|
343 |
#define DMA0TSEL_10 (10*0x0001u) /* DMA channel 0 transfer select 10: USCIA1 transmit */
|
|
|
344 |
#define DMA0TSEL_11 (11*0x0001u) /* DMA channel 0 transfer select 11: Multiplier ready */
|
|
|
345 |
#define DMA0TSEL_12 (12*0x0001u) /* DMA channel 0 transfer select 12: USCIB0 receive */
|
|
|
346 |
#define DMA0TSEL_13 (13*0x0001u) /* DMA channel 0 transfer select 13: USCIB0 transmit */
|
|
|
347 |
#define DMA0TSEL_14 (14*0x0001u) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */
|
|
|
348 |
#define DMA0TSEL_15 (15*0x0001u) /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */
|
|
|
349 |
|
|
|
350 |
#define DMA1TSEL_0 (0*0x0010u) /* DMA channel 1 transfer select 0: DMA_REQ */
|
|
|
351 |
#define DMA1TSEL_1 (1*0x0010u) /* DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */
|
|
|
352 |
#define DMA1TSEL_2 (2*0x0010u) /* DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */
|
|
|
353 |
#define DMA1TSEL_3 (3*0x0010u) /* DMA channel 1 transfer select 3: USCIA0 receive */
|
|
|
354 |
#define DMA1TSEL_4 (4*0x0010u) /* DMA channel 1 transfer select 4: USCIA0 transmit */
|
|
|
355 |
#define DMA1TSEL_5 (5*0x0010u) /* DMA channel 1 transfer select 5: Reserved */
|
|
|
356 |
#define DMA1TSEL_6 (6*0x0010u) /* DMA channel 1 transfer select 6: SD16 (SD16IFG) */
|
|
|
357 |
#define DMA1TSEL_7 (7*0x0010u) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */
|
|
|
358 |
#define DMA1TSEL_8 (8*0x0010u) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */
|
|
|
359 |
#define DMA1TSEL_9 (9*0x0010u) /* DMA channel 1 transfer select 9: USCIA1 receive */
|
|
|
360 |
#define DMA1TSEL_10 (10*0x0010u) /* DMA channel 1 transfer select 10: USCIA1 transmit */
|
|
|
361 |
#define DMA1TSEL_11 (11*0x0010u) /* DMA channel 1 transfer select 11: Multiplier ready */
|
|
|
362 |
#define DMA1TSEL_12 (12*0x0010u) /* DMA channel 1 transfer select 12: USCIB0 receive */
|
|
|
363 |
#define DMA1TSEL_13 (13*0x0010u) /* DMA channel 1 transfer select 13: USCIB0 transmit */
|
|
|
364 |
#define DMA1TSEL_14 (14*0x0010u) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */
|
|
|
365 |
#define DMA1TSEL_15 (15*0x0010u) /* DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */
|
|
|
366 |
|
|
|
367 |
#define DMA2TSEL_0 (0*0x0100u) /* DMA channel 2 transfer select 0: DMA_REQ */
|
|
|
368 |
#define DMA2TSEL_1 (1*0x0100u) /* DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */
|
|
|
369 |
#define DMA2TSEL_2 (2*0x0100u) /* DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */
|
|
|
370 |
#define DMA2TSEL_3 (3*0x0100u) /* DMA channel 2 transfer select 3: USCIA0 receive */
|
|
|
371 |
#define DMA2TSEL_4 (4*0x0100u) /* DMA channel 2 transfer select 4: USCIA0 transmit */
|
|
|
372 |
#define DMA2TSEL_5 (5*0x0100u) /* DMA channel 2 transfer select 5: Reserved */
|
|
|
373 |
#define DMA2TSEL_6 (6*0x0100u) /* DMA channel 2 transfer select 6: SD16 (SD16IFG) */
|
|
|
374 |
#define DMA2TSEL_7 (7*0x0100u) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */
|
|
|
375 |
#define DMA2TSEL_8 (8*0x0100u) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */
|
|
|
376 |
#define DMA2TSEL_9 (9*0x0100u) /* DMA channel 2 transfer select 9: USCIA1 receive */
|
|
|
377 |
#define DMA2TSEL_10 (10*0x0100u) /* DMA channel 2 transfer select 10: USCIA1 transmit */
|
|
|
378 |
#define DMA2TSEL_11 (11*0x0100u) /* DMA channel 2 transfer select 11: Multiplier ready */
|
|
|
379 |
#define DMA2TSEL_12 (12*0x0100u) /* DMA channel 2 transfer select 12: USCIB0 receive */
|
|
|
380 |
#define DMA2TSEL_13 (13*0x0100u) /* DMA channel 2 transfer select 13: USCIB0 transmit */
|
|
|
381 |
#define DMA2TSEL_14 (14*0x0100u) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */
|
|
|
382 |
#define DMA2TSEL_15 (15*0x0100u) /* DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */
|
|
|
383 |
|
|
|
384 |
SFR_16BIT(DMACTL1); /* DMA Module Control 1 */
|
|
|
385 |
#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
|
|
|
386 |
#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
|
|
|
387 |
#define DMAONFETCH (0x0004) /* DMA transfer on instruction fetch */
|
|
|
388 |
|
|
|
389 |
SFR_16BIT(DMAIV); /* DMA Interrupt Vector Word */
|
|
|
390 |
SFR_16BIT(DMA0CTL); /* DMA Channel 0 Control */
|
|
|
391 |
SFR_16BIT(DMA1CTL); /* DMA Channel 1 Control */
|
|
|
392 |
SFR_16BIT(DMA2CTL); /* DMA Channel 2 Control */
|
|
|
393 |
|
|
|
394 |
#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
|
|
|
395 |
#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
|
|
|
396 |
#define DMAIE (0x0004) /* DMA interrupt enable */
|
|
|
397 |
#define DMAIFG (0x0008) /* DMA interrupt flag */
|
|
|
398 |
#define DMAEN (0x0010) /* DMA enable */
|
|
|
399 |
#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
|
|
|
400 |
#define DMASRCBYTE (0x0040) /* DMA source byte */
|
|
|
401 |
#define DMADSTBYTE (0x0080) /* DMA destination byte */
|
|
|
402 |
#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
|
|
|
403 |
#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
|
|
|
404 |
#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
|
|
|
405 |
#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
|
|
|
406 |
#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
|
|
|
407 |
#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
|
|
|
408 |
#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
|
|
|
409 |
|
|
|
410 |
#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
|
|
|
411 |
#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
|
|
|
412 |
#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
|
|
|
413 |
#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
|
|
|
414 |
|
|
|
415 |
#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
|
|
|
416 |
#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
|
|
|
417 |
#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
|
|
|
418 |
#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
|
|
|
419 |
|
|
|
420 |
#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
|
|
|
421 |
#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
|
|
|
422 |
#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
|
|
|
423 |
#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
|
|
|
424 |
|
|
|
425 |
#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: single */
|
|
|
426 |
#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: block */
|
|
|
427 |
#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: interleaved */
|
|
|
428 |
#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: interleaved */
|
|
|
429 |
#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: single, repeat */
|
|
|
430 |
#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: block, repeat */
|
|
|
431 |
#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: interleaved, repeat */
|
|
|
432 |
#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: interleaved, repeat */
|
|
|
433 |
|
|
|
434 |
SFR_20BIT(DMA0SA); /* DMA Channel 0 Source Address */
|
|
|
435 |
SFR_16BIT(DMA0SAL); /* DMA Channel 0 Source Address */
|
|
|
436 |
SFR_20BIT(DMA0DA); /* DMA Channel 0 Destination Address */
|
|
|
437 |
SFR_16BIT(DMA0DAL); /* DMA Channel 0 Destination Address */
|
|
|
438 |
SFR_16BIT(DMA0SZ); /* DMA Channel 0 Transfer Size */
|
|
|
439 |
SFR_20BIT(DMA1SA); /* DMA Channel 1 Source Address */
|
|
|
440 |
SFR_16BIT(DMA1SAL); /* DMA Channel 1 Source Address */
|
|
|
441 |
SFR_20BIT(DMA1DA); /* DMA Channel 1 Destination Address */
|
|
|
442 |
SFR_16BIT(DMA1DAL); /* DMA Channel 1 Destination Address */
|
|
|
443 |
SFR_16BIT(DMA1SZ); /* DMA Channel 1 Transfer Size */
|
|
|
444 |
SFR_20BIT(DMA2SA); /* DMA Channel 2 Source Address */
|
|
|
445 |
SFR_16BIT(DMA2SAL); /* DMA Channel 2 Source Address */
|
|
|
446 |
SFR_20BIT(DMA2DA); /* DMA Channel 2 Destination Address */
|
|
|
447 |
SFR_16BIT(DMA2DAL); /* DMA Channel 2 Destination Address */
|
|
|
448 |
SFR_16BIT(DMA2SZ); /* DMA Channel 2 Transfer Size */
|
|
|
449 |
|
|
|
450 |
/* DMAIV Definitions */
|
|
|
451 |
#define DMAIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
452 |
#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG */
|
|
|
453 |
#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG */
|
|
|
454 |
#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG */
|
|
|
455 |
|
|
|
456 |
/*************************************************************
|
|
|
457 |
* Flash Memory
|
|
|
458 |
*************************************************************/
|
|
|
459 |
#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */
|
|
|
460 |
|
|
|
461 |
SFR_16BIT(FCTL1); /* FLASH Control 1 */
|
|
|
462 |
SFR_16BIT(FCTL2); /* FLASH Control 2 */
|
|
|
463 |
SFR_16BIT(FCTL3); /* FLASH Control 3 */
|
|
|
464 |
SFR_16BIT(FCTL4); /* FLASH Control 4 */
|
|
|
465 |
|
|
|
466 |
#define FRKEY (0x9600) /* Flash key returned by read */
|
|
|
467 |
#define FWKEY (0xA500) /* Flash key for write */
|
|
|
468 |
#define FXKEY (0x3300) /* for use with XOR instruction */
|
|
|
469 |
|
|
|
470 |
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
|
|
|
471 |
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
|
|
|
472 |
#define EEI (0x0008) /* Enable Erase Interrupts */
|
|
|
473 |
#define EEIEX (0x0010) /* Enable Emergency Interrupt Exit */
|
|
|
474 |
#define WRT (0x0040) /* Enable bit for Flash write */
|
|
|
475 |
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
|
|
|
476 |
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
|
|
|
477 |
|
|
|
478 |
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
|
|
|
479 |
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
|
|
|
480 |
#ifndef FN2
|
|
|
481 |
#define FN2 (0x0004)
|
|
|
482 |
#endif
|
|
|
483 |
#ifndef FN3
|
|
|
484 |
#define FN3 (0x0008)
|
|
|
485 |
#endif
|
|
|
486 |
#ifndef FN4
|
|
|
487 |
#define FN4 (0x0010)
|
|
|
488 |
#endif
|
|
|
489 |
#define FN5 (0x0020)
|
|
|
490 |
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
|
|
|
491 |
#define FSSEL1 (0x0080) /* Flash clock select 1 */
|
|
|
492 |
|
|
|
493 |
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
|
|
|
494 |
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
|
|
|
495 |
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
|
|
|
496 |
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
|
|
|
497 |
|
|
|
498 |
#define BUSY (0x0001) /* Flash busy: 1 */
|
|
|
499 |
#define KEYV (0x0002) /* Flash Key violation flag */
|
|
|
500 |
#define ACCVIFG (0x0004) /* Flash Access violation flag */
|
|
|
501 |
#define WAIT (0x0008) /* Wait flag for segment write */
|
|
|
502 |
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
503 |
#define EMEX (0x0020) /* Flash Emergency Exit */
|
|
|
504 |
#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
|
|
|
505 |
#define FAIL (0x0080) /* Last Program or Erase failed */
|
|
|
506 |
|
|
|
507 |
#define MGR0 (0x0010) /* Marginal read 0 mode. */
|
|
|
508 |
#define MGR1 (0x0020) /* Marginal read 1 mode. */
|
|
|
509 |
|
|
|
510 |
/************************************************************
|
|
|
511 |
* SYSTEM CLOCK, FLL+
|
|
|
512 |
************************************************************/
|
|
|
513 |
#define __MSP430_HAS_FLLPLUS__ /* Definition to show that Module is available */
|
|
|
514 |
|
|
|
515 |
SFR_8BIT(SCFI0); /* System Clock Frequency Integrator 0 */
|
|
|
516 |
#define FN_2 (0x04) /* fDCOCLK = 1.4-12MHz*/
|
|
|
517 |
#define FN_3 (0x08) /* fDCOCLK = 2.2-17Mhz*/
|
|
|
518 |
#define FN_4 (0x10) /* fDCOCLK = 3.2-25Mhz*/
|
|
|
519 |
#define FN_8 (0x20) /* fDCOCLK = 5-40Mhz*/
|
|
|
520 |
#define FLLD0 (0x40) /* Loop Divider Bit : 0 */
|
|
|
521 |
#define FLLD1 (0x80) /* Loop Divider Bit : 1 */
|
|
|
522 |
|
|
|
523 |
#define FLLD_1 (0x00) /* Multiply Selected Loop Freq. By 1 */
|
|
|
524 |
#define FLLD_2 (0x40) /* Multiply Selected Loop Freq. By 2 */
|
|
|
525 |
#define FLLD_4 (0x80) /* Multiply Selected Loop Freq. By 4 */
|
|
|
526 |
#define FLLD_8 (0xC0) /* Multiply Selected Loop Freq. By 8 */
|
|
|
527 |
|
|
|
528 |
SFR_8BIT(SCFI1); /* System Clock Frequency Integrator 1 */
|
|
|
529 |
SFR_8BIT(SCFQCTL); /* System Clock Frequency Control */
|
|
|
530 |
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
|
|
|
531 |
/* #define SCFQ_32K 0x00 fMCLK=1*fACLK only a range from */
|
|
|
532 |
#define SCFQ_64K (0x01) /* fMCLK=2*fACLK 1+1 to 127+1 is possible */
|
|
|
533 |
#define SCFQ_128K (0x03) /* fMCLK=4*fACLK */
|
|
|
534 |
#define SCFQ_256K (0x07) /* fMCLK=8*fACLK */
|
|
|
535 |
#define SCFQ_512K (0x0F) /* fMCLK=16*fACLK */
|
|
|
536 |
#define SCFQ_1M (0x1F) /* fMCLK=32*fACLK */
|
|
|
537 |
#define SCFQ_2M (0x3F) /* fMCLK=64*fACLK */
|
|
|
538 |
#define SCFQ_4M (0x7F) /* fMCLK=128*fACLK */
|
|
|
539 |
#define SCFQ_M (0x80) /* Modulation Disable */
|
|
|
540 |
|
|
|
541 |
SFR_8BIT(FLL_CTL0); /* FLL+ Control 0 */
|
|
|
542 |
#define DCOF (0x01) /* DCO Fault Flag */
|
|
|
543 |
#define LFOF (0x02) /* Low Frequency Oscillator Fault Flag */
|
|
|
544 |
#define XT1OF (0x04) /* High Frequency Oscillator 1 Fault Flag */
|
|
|
545 |
#define XT2OF (0x08) /* High Frequency Oscillator 2 Fault Flag */
|
|
|
546 |
#define OSCCAP0 (0x10) /* XIN/XOUT Cap 0 */
|
|
|
547 |
#define OSCCAP1 (0x20) /* XIN/XOUT Cap 1 */
|
|
|
548 |
#define XTS_FLL (0x40) /* 1: Selects high-freq. oscillator */
|
|
|
549 |
#define DCOPLUS (0x80) /* DCO+ Enable */
|
|
|
550 |
|
|
|
551 |
#define XCAP0PF (0x00) /* XIN Cap = XOUT Cap = 0pf */
|
|
|
552 |
#define XCAP5_5F (0x10) /* XIN Cap = XOUT Cap = 5.5pf */
|
|
|
553 |
#define XCAP8_5PF (0x20) /* XIN Cap = XOUT Cap = 8.5pf */
|
|
|
554 |
#define XCAP11PF (0x30) /* XIN Cap = XOUT Cap = 11pf */
|
|
|
555 |
#define OSCCAP_0 (0x00) /* XIN Cap = XOUT Cap: 0 */
|
|
|
556 |
#define OSCCAP_1 (0x10) /* XIN Cap = XOUT Cap: 1 */
|
|
|
557 |
#define OSCCAP_2 (0x20) /* XIN Cap = XOUT Cap: 2 */
|
|
|
558 |
#define OSCCAP_3 (0x30) /* XIN Cap = XOUT Cap: 3 */
|
|
|
559 |
|
|
|
560 |
SFR_8BIT(FLL_CTL1); /* FLL+ Control 1 */
|
|
|
561 |
#define FLL_DIV0 (0x01) /* FLL+ Divide Px.x/ACLK 0 */
|
|
|
562 |
#define FLL_DIV1 (0x02) /* FLL+ Divide Px.x/ACLK 1 */
|
|
|
563 |
#define SELS (0x04) /* Peripheral Module Clock Source (0: DCO, 1: XT2) */
|
|
|
564 |
#define SELM0 (0x08) /* MCLK Source Select 0 */
|
|
|
565 |
#define SELM1 (0x10) /* MCLK Source Select 1 */
|
|
|
566 |
#define XT2OFF (0x20) /* High Frequency Oscillator 2 (XT2) disable */
|
|
|
567 |
#define SMCLKOFF (0x40) /* Peripheral Module Clock (SMCLK) disable */
|
|
|
568 |
#define LFXT1DIG (0x80) /* Enable Digital input for LF clock */
|
|
|
569 |
|
|
|
570 |
#define FLL_DIV_1 (0x00) /* FLL+ Divide Px.x/ACLK By 1 */
|
|
|
571 |
#define FLL_DIV_2 (0x01) /* FLL+ Divide Px.x/ACLK By 2 */
|
|
|
572 |
#define FLL_DIV_4 (0x02) /* FLL+ Divide Px.x/ACLK By 4 */
|
|
|
573 |
#define FLL_DIV_8 (0x03) /* FLL+ Divide Px.x/ACLK By 8 */
|
|
|
574 |
|
|
|
575 |
#define SELM_DCO (0x00) /* Select DCO for CPU MCLK */
|
|
|
576 |
#define SELM_XT2 (0x10) /* Select XT2 for CPU MCLK */
|
|
|
577 |
#define SELM_A (0x18) /* Select A (from LFXT1) for CPU MCLK */
|
|
|
578 |
|
|
|
579 |
SFR_8BIT(FLL_CTL2); /* FLL+ Control 2 */
|
|
|
580 |
|
|
|
581 |
#define XT2S0 (0x40) /* Mode 0 for XT2 */
|
|
|
582 |
#define XT2S1 (0x80) /* Mode 1 for XT2 */
|
|
|
583 |
|
|
|
584 |
#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */
|
|
|
585 |
#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */
|
|
|
586 |
#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */
|
|
|
587 |
#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */
|
|
|
588 |
|
|
|
589 |
/* INTERRUPT CONTROL BITS */
|
|
|
590 |
/* These two bits are defined in the Special Function Registers */
|
|
|
591 |
/* #define OFIFG 0x02 */
|
|
|
592 |
/* #define OFIE 0x02 */
|
|
|
593 |
|
|
|
594 |
/************************************************************
|
|
|
595 |
* LCD_A
|
|
|
596 |
************************************************************/
|
|
|
597 |
#define __MSP430_HAS_LCD_A__ /* Definition to show that Module is available */
|
|
|
598 |
|
|
|
599 |
SFR_8BIT(LCDACTL); /* LCD_A Control Register */
|
|
|
600 |
#define LCDON (0x01)
|
|
|
601 |
#define LCDSON (0x04)
|
|
|
602 |
#define LCDMX0 (0x08)
|
|
|
603 |
#define LCDMX1 (0x10)
|
|
|
604 |
#define LCDFREQ0 (0x20)
|
|
|
605 |
#define LCDFREQ1 (0x40)
|
|
|
606 |
#define LCDFREQ2 (0x80)
|
|
|
607 |
/* Display modes coded with Bits 2-4 */
|
|
|
608 |
#define LCDSTATIC (LCDSON)
|
|
|
609 |
#define LCD2MUX (LCDMX0+LCDSON)
|
|
|
610 |
#define LCD3MUX (LCDMX1+LCDSON)
|
|
|
611 |
#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
|
|
|
612 |
/* Frequency select code with Bits 5-7 */
|
|
|
613 |
#define LCDFREQ_32 (0x00) /* LCD Freq: ACLK divided by 32 */
|
|
|
614 |
#define LCDFREQ_64 (0x20) /* LCD Freq: ACLK divided by 64 */
|
|
|
615 |
#define LCDFREQ_96 (0x40) /* LCD Freq: ACLK divided by 96 */
|
|
|
616 |
#define LCDFREQ_128 (0x60) /* LCD Freq: ACLK divided by 128 */
|
|
|
617 |
#define LCDFREQ_192 (0x80) /* LCD Freq: ACLK divided by 192 */
|
|
|
618 |
#define LCDFREQ_256 (0xA0) /* LCD Freq: ACLK divided by 256 */
|
|
|
619 |
#define LCDFREQ_384 (0xC0) /* LCD Freq: ACLK divided by 384 */
|
|
|
620 |
#define LCDFREQ_512 (0xE0) /* LCD Freq: ACLK divided by 512 */
|
|
|
621 |
|
|
|
622 |
SFR_8BIT(LCDAPCTL0); /* LCD_A Port Control Register 0 */
|
|
|
623 |
#define LCDS0 (0x01) /* LCD Segment 0 to 3 Enable. */
|
|
|
624 |
#define LCDS4 (0x02) /* LCD Segment 4 to 7 Enable. */
|
|
|
625 |
#define LCDS8 (0x04) /* LCD Segment 8 to 11 Enable. */
|
|
|
626 |
#define LCDS12 (0x08) /* LCD Segment 12 to 15 Enable. */
|
|
|
627 |
#define LCDS16 (0x10) /* LCD Segment 16 to 19 Enable. */
|
|
|
628 |
#define LCDS20 (0x20) /* LCD Segment 20 to 23 Enable. */
|
|
|
629 |
#define LCDS24 (0x40) /* LCD Segment 24 to 27 Enable. */
|
|
|
630 |
#define LCDS28 (0x80) /* LCD Segment 28 to 31 Enable. */
|
|
|
631 |
|
|
|
632 |
SFR_8BIT(LCDAPCTL1); /* LCD_A Port Control Register 1 */
|
|
|
633 |
#define LCDS32 (0x01) /* LCD Segment 32 to 35 Enable. */
|
|
|
634 |
#define LCDS36 (0x02) /* LCD Segment 36 to 39 Enable. */
|
|
|
635 |
|
|
|
636 |
SFR_8BIT(LCDAVCTL0); /* LCD_A Voltage Control Register 0 */
|
|
|
637 |
#define LCD2B (0x01) /* Selects 1/2 bias. */
|
|
|
638 |
#define VLCDREF0 (0x02) /* Selects reference voltage for regulated charge pump: 0 */
|
|
|
639 |
#define VLCDREF1 (0x04) /* Selects reference voltage for regulated charge pump: 1 */
|
|
|
640 |
#define LCDCPEN (0x08) /* LCD Voltage Charge Pump Enable. */
|
|
|
641 |
#define VLCDEXT (0x10) /* Select external source for VLCD. */
|
|
|
642 |
#define LCDREXT (0x20) /* Selects external connections for LCD mid voltages. */
|
|
|
643 |
#define LCDR03EXT (0x40) /* Selects external connection for lowest LCD voltage. */
|
|
|
644 |
|
|
|
645 |
/* Reference voltage source select for the regulated charge pump */
|
|
|
646 |
#define VLCDREF_0 (0<<1) /* Internal */
|
|
|
647 |
#define VLCDREF_1 (1<<1) /* External */
|
|
|
648 |
#define VLCDREF_2 (2<<1) /* Reserved */
|
|
|
649 |
#define VLCDREF_3 (3<<1) /* Reserved */
|
|
|
650 |
|
|
|
651 |
SFR_8BIT(LCDAVCTL1); /* LCD_A Voltage Control Register 1 */
|
|
|
652 |
#define VLCD0 (0x02) /* VLCD select: 0 */
|
|
|
653 |
#define VLCD1 (0x04) /* VLCD select: 1 */
|
|
|
654 |
#define VLCD2 (0x08) /* VLCD select: 2 */
|
|
|
655 |
#define VLCD3 (0x10) /* VLCD select: 3 */
|
|
|
656 |
|
|
|
657 |
/* Charge pump voltage selections */
|
|
|
658 |
#define VLCD_0 (0<<1) /* Charge pump disabled */
|
|
|
659 |
#define VLCD_1 (1<<1) /* VLCD = 2.60V */
|
|
|
660 |
#define VLCD_2 (2<<1) /* VLCD = 2.66V */
|
|
|
661 |
#define VLCD_3 (3<<1) /* VLCD = 2.72V */
|
|
|
662 |
#define VLCD_4 (4<<1) /* VLCD = 2.78V */
|
|
|
663 |
#define VLCD_5 (5<<1) /* VLCD = 2.84V */
|
|
|
664 |
#define VLCD_6 (6<<1) /* VLCD = 2.90V */
|
|
|
665 |
#define VLCD_7 (7<<1) /* VLCD = 2.96V */
|
|
|
666 |
#define VLCD_8 (8<<1) /* VLCD = 3.02V */
|
|
|
667 |
#define VLCD_9 (9<<1) /* VLCD = 3.08V */
|
|
|
668 |
#define VLCD_10 (10<<1) /* VLCD = 3.14V */
|
|
|
669 |
#define VLCD_11 (11<<1) /* VLCD = 3.20V */
|
|
|
670 |
#define VLCD_12 (12<<1) /* VLCD = 3.26V */
|
|
|
671 |
#define VLCD_13 (12<<1) /* VLCD = 3.32V */
|
|
|
672 |
#define VLCD_14 (13<<1) /* VLCD = 3.38V */
|
|
|
673 |
#define VLCD_15 (15<<1) /* VLCD = 3.44V */
|
|
|
674 |
|
|
|
675 |
#define VLCD_DISABLED (0<<1) /* Charge pump disabled */
|
|
|
676 |
#define VLCD_2_60 (1<<1) /* VLCD = 2.60V */
|
|
|
677 |
#define VLCD_2_66 (2<<1) /* VLCD = 2.66V */
|
|
|
678 |
#define VLCD_2_72 (3<<1) /* VLCD = 2.72V */
|
|
|
679 |
#define VLCD_2_78 (4<<1) /* VLCD = 2.78V */
|
|
|
680 |
#define VLCD_2_84 (5<<1) /* VLCD = 2.84V */
|
|
|
681 |
#define VLCD_2_90 (6<<1) /* VLCD = 2.90V */
|
|
|
682 |
#define VLCD_2_96 (7<<1) /* VLCD = 2.96V */
|
|
|
683 |
#define VLCD_3_02 (8<<1) /* VLCD = 3.02V */
|
|
|
684 |
#define VLCD_3_08 (9<<1) /* VLCD = 3.08V */
|
|
|
685 |
#define VLCD_3_14 (10<<1) /* VLCD = 3.14V */
|
|
|
686 |
#define VLCD_3_20 (11<<1) /* VLCD = 3.20V */
|
|
|
687 |
#define VLCD_3_26 (12<<1) /* VLCD = 3.26V */
|
|
|
688 |
#define VLCD_3_32 (12<<1) /* VLCD = 3.32V */
|
|
|
689 |
#define VLCD_3_38 (13<<1) /* VLCD = 3.38V */
|
|
|
690 |
#define VLCD_3_44 (15<<1) /* VLCD = 3.44V */
|
|
|
691 |
|
|
|
692 |
#define LCDMEM_ (0x0091) /* LCD Memory */
|
|
|
693 |
#ifdef __ASM_HEADER__
|
|
|
694 |
#define LCDMEM (LCDMEM_) /* LCD Memory (for assembler) */
|
|
|
695 |
#else
|
|
|
696 |
#define LCDMEM ((char*) LCDMEM_) /* LCD Memory (for C) */
|
|
|
697 |
#endif
|
|
|
698 |
SFR_8BIT(LCDM1); /* LCD Memory 1 */
|
|
|
699 |
SFR_8BIT(LCDM2); /* LCD Memory 2 */
|
|
|
700 |
SFR_8BIT(LCDM3); /* LCD Memory 3 */
|
|
|
701 |
SFR_8BIT(LCDM4); /* LCD Memory 4 */
|
|
|
702 |
SFR_8BIT(LCDM5); /* LCD Memory 5 */
|
|
|
703 |
SFR_8BIT(LCDM6); /* LCD Memory 6 */
|
|
|
704 |
SFR_8BIT(LCDM7); /* LCD Memory 7 */
|
|
|
705 |
SFR_8BIT(LCDM8); /* LCD Memory 8 */
|
|
|
706 |
SFR_8BIT(LCDM9); /* LCD Memory 9 */
|
|
|
707 |
SFR_8BIT(LCDM10); /* LCD Memory 10 */
|
|
|
708 |
SFR_8BIT(LCDM11); /* LCD Memory 11 */
|
|
|
709 |
SFR_8BIT(LCDM12); /* LCD Memory 12 */
|
|
|
710 |
SFR_8BIT(LCDM13); /* LCD Memory 13 */
|
|
|
711 |
SFR_8BIT(LCDM14); /* LCD Memory 14 */
|
|
|
712 |
SFR_8BIT(LCDM15); /* LCD Memory 15 */
|
|
|
713 |
SFR_8BIT(LCDM16); /* LCD Memory 16 */
|
|
|
714 |
SFR_8BIT(LCDM17); /* LCD Memory 17 */
|
|
|
715 |
SFR_8BIT(LCDM18); /* LCD Memory 18 */
|
|
|
716 |
SFR_8BIT(LCDM19); /* LCD Memory 19 */
|
|
|
717 |
SFR_8BIT(LCDM20); /* LCD Memory 20 */
|
|
|
718 |
|
|
|
719 |
#define LCDMA (LCDM10) /* LCD Memory A */
|
|
|
720 |
#define LCDMB (LCDM11) /* LCD Memory B */
|
|
|
721 |
#define LCDMC (LCDM12) /* LCD Memory C */
|
|
|
722 |
#define LCDMD (LCDM13) /* LCD Memory D */
|
|
|
723 |
#define LCDME (LCDM14) /* LCD Memory E */
|
|
|
724 |
#define LCDMF (LCDM15) /* LCD Memory F */
|
|
|
725 |
|
|
|
726 |
/************************************************************
|
|
|
727 |
* HARDWARE MULTIPLIER 32Bit
|
|
|
728 |
************************************************************/
|
|
|
729 |
#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
|
|
|
730 |
|
|
|
731 |
SFR_8BIT(MPY_B); /* Multiply Unsigned/Operand 1 (Byte Access) */
|
|
|
732 |
SFR_8BIT(MPYS_B); /* Multiply Signed/Operand 1 (Byte Access) */
|
|
|
733 |
SFR_8BIT(MAC_B); /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
|
|
|
734 |
SFR_8BIT(MACS_B); /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
|
|
|
735 |
SFR_8BIT(OP2_B); /* Operand 2 (Byte Access) */
|
|
|
736 |
SFR_16BIT(MPY); /* Multiply Unsigned/Operand 1 */
|
|
|
737 |
SFR_16BIT(MPYS); /* Multiply Signed/Operand 1 */
|
|
|
738 |
SFR_16BIT(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */
|
|
|
739 |
SFR_16BIT(MACS); /* Multiply Signed and Accumulate/Operand 1 */
|
|
|
740 |
SFR_16BIT(OP2); /* Operand 2 */
|
|
|
741 |
SFR_16BIT(RESLO); /* Result Low Word */
|
|
|
742 |
SFR_16BIT(RESHI); /* Result High Word */
|
|
|
743 |
SFR_16BIT(SUMEXT); /* Sum Extend */
|
|
|
744 |
|
|
|
745 |
SFR_8BIT(MPY32L_B); /* 32-bit operand 1 - multiply - low word (Byte Access) */
|
|
|
746 |
SFR_8BIT(MPY32H_B); /* 32-bit operand 1 - multiply - high word (Byte Access) */
|
|
|
747 |
SFR_8BIT(MPYS32L_B); /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
|
|
|
748 |
SFR_8BIT(MPYS32H_B); /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
|
|
|
749 |
SFR_8BIT(MAC32L_B); /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
|
|
|
750 |
SFR_8BIT(MAC32H_B); /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
|
|
|
751 |
SFR_8BIT(MACS32L_B); /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
|
|
|
752 |
SFR_8BIT(MACS32H_B); /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
|
|
|
753 |
SFR_8BIT(OP2L_B); /* 32-bit operand 2 - low word (Byte Access) */
|
|
|
754 |
SFR_8BIT(OP2H_B); /* 32-bit operand 2 - high word (Byte Access) */
|
|
|
755 |
SFR_16BIT(MPY32L); /* 32-bit operand 1 - multiply - low word */
|
|
|
756 |
SFR_16BIT(MPY32H); /* 32-bit operand 1 - multiply - high word */
|
|
|
757 |
SFR_16BIT(MPYS32L); /* 32-bit operand 1 - signed multiply - low word */
|
|
|
758 |
SFR_16BIT(MPYS32H); /* 32-bit operand 1 - signed multiply - high word */
|
|
|
759 |
SFR_16BIT(MAC32L); /* 32-bit operand 1 - multiply accumulate - low word */
|
|
|
760 |
SFR_16BIT(MAC32H); /* 32-bit operand 1 - multiply accumulate - high word */
|
|
|
761 |
SFR_16BIT(MACS32L); /* 32-bit operand 1 - signed multiply accumulate - low word */
|
|
|
762 |
SFR_16BIT(MACS32H); /* 32-bit operand 1 - signed multiply accumulate - high word */
|
|
|
763 |
SFR_16BIT(OP2L); /* 32-bit operand 2 - low word */
|
|
|
764 |
SFR_16BIT(OP2H); /* 32-bit operand 2 - high word */
|
|
|
765 |
SFR_16BIT(RES0); /* 32x32-bit result 0 - least significant word */
|
|
|
766 |
SFR_16BIT(RES1); /* 32x32-bit result 1 */
|
|
|
767 |
SFR_16BIT(RES2); /* 32x32-bit result 2 */
|
|
|
768 |
SFR_16BIT(RES3); /* 32x32-bit result 3 - most significant word */
|
|
|
769 |
SFR_16BIT(MPY32CTL0); /* MPY32 Control Register 0 */
|
|
|
770 |
|
|
|
771 |
#define MPYC (0x0001) /* Carry of the multiplier */
|
|
|
772 |
//#define RESERVED (0x0002) /* Reserved */
|
|
|
773 |
#define MPYFRAC (0x0004) /* Fractional mode */
|
|
|
774 |
#define MPYSAT (0x0008) /* Saturation mode */
|
|
|
775 |
#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */
|
|
|
776 |
#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */
|
|
|
777 |
#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
|
|
|
778 |
#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
|
|
|
779 |
#define MPYDLYWRTEN (0x0100) /* Delayed write enable */
|
|
|
780 |
#define MPYDLY32 (0x0200) /* Delayed write mode */
|
|
|
781 |
|
|
|
782 |
#define MPYM_0 (0x0000) /* Multiplier mode: MPY */
|
|
|
783 |
#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */
|
|
|
784 |
#define MPYM_2 (0x0020) /* Multiplier mode: MAC */
|
|
|
785 |
#define MPYM_3 (0x0030) /* Multiplier mode: MACS */
|
|
|
786 |
#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */
|
|
|
787 |
#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */
|
|
|
788 |
#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */
|
|
|
789 |
#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */
|
|
|
790 |
|
|
|
791 |
/************************************************************
|
|
|
792 |
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
|
|
|
793 |
************************************************************/
|
|
|
794 |
#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
|
|
|
795 |
#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
|
|
|
796 |
|
|
|
797 |
SFR_8BIT(P1IN); /* Port 1 Input */
|
|
|
798 |
SFR_8BIT(P1OUT); /* Port 1 Output */
|
|
|
799 |
SFR_8BIT(P1DIR); /* Port 1 Direction */
|
|
|
800 |
SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */
|
|
|
801 |
SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */
|
|
|
802 |
SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */
|
|
|
803 |
SFR_8BIT(P1SEL); /* Port 1 Selection */
|
|
|
804 |
SFR_8BIT(P1REN); /* Port 1 Resistor Enable */
|
|
|
805 |
|
|
|
806 |
SFR_8BIT(P2IN); /* Port 2 Input */
|
|
|
807 |
SFR_8BIT(P2OUT); /* Port 2 Output */
|
|
|
808 |
SFR_8BIT(P2DIR); /* Port 2 Direction */
|
|
|
809 |
SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */
|
|
|
810 |
SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */
|
|
|
811 |
SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */
|
|
|
812 |
SFR_8BIT(P2SEL); /* Port 2 Selection */
|
|
|
813 |
SFR_8BIT(P2REN); /* Port 2 Resistor Enable */
|
|
|
814 |
|
|
|
815 |
/************************************************************
|
|
|
816 |
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
|
|
|
817 |
************************************************************/
|
|
|
818 |
#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
|
|
|
819 |
#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
|
|
|
820 |
|
|
|
821 |
SFR_8BIT(P3IN); /* Port 3 Input */
|
|
|
822 |
SFR_8BIT(P3OUT); /* Port 3 Output */
|
|
|
823 |
SFR_8BIT(P3DIR); /* Port 3 Direction */
|
|
|
824 |
SFR_8BIT(P3SEL); /* Port 3 Selection */
|
|
|
825 |
SFR_8BIT(P3REN); /* Port 3 Resistor Enable */
|
|
|
826 |
|
|
|
827 |
SFR_8BIT(P4IN); /* Port 4 Input */
|
|
|
828 |
SFR_8BIT(P4OUT); /* Port 4 Output */
|
|
|
829 |
SFR_8BIT(P4DIR); /* Port 4 Direction */
|
|
|
830 |
SFR_8BIT(P4SEL); /* Port 4 Selection */
|
|
|
831 |
SFR_8BIT(P4REN); /* Port 4 Resistor Enable */
|
|
|
832 |
|
|
|
833 |
/************************************************************
|
|
|
834 |
* DIGITAL I/O Port5 Pull up / Pull down Resistors
|
|
|
835 |
************************************************************/
|
|
|
836 |
#define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */
|
|
|
837 |
|
|
|
838 |
SFR_8BIT(P5IN); /* Port 5 Input */
|
|
|
839 |
SFR_8BIT(P5OUT); /* Port 5 Output */
|
|
|
840 |
SFR_8BIT(P5DIR); /* Port 5 Direction */
|
|
|
841 |
SFR_8BIT(P5SEL); /* Port 5 Selection */
|
|
|
842 |
SFR_8BIT(P5REN); /* Port 5 Resistor Enable */
|
|
|
843 |
|
|
|
844 |
/************************************************************
|
|
|
845 |
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
|
|
|
846 |
************************************************************/
|
|
|
847 |
#define __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */
|
|
|
848 |
#define __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */
|
|
|
849 |
#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
|
|
|
850 |
|
|
|
851 |
SFR_8BIT(P7IN); /* Port 7 Input */
|
|
|
852 |
SFR_8BIT(P7OUT); /* Port 7 Output */
|
|
|
853 |
SFR_8BIT(P7DIR); /* Port 7 Direction */
|
|
|
854 |
SFR_8BIT(P7SEL); /* Port 7 Selection */
|
|
|
855 |
SFR_8BIT(P7REN); /* Port 7 Resistor Enable */
|
|
|
856 |
|
|
|
857 |
SFR_8BIT(P8IN); /* Port 8 Input */
|
|
|
858 |
SFR_8BIT(P8OUT); /* Port 8 Output */
|
|
|
859 |
SFR_8BIT(P8DIR); /* Port 8 Direction */
|
|
|
860 |
SFR_8BIT(P8SEL); /* Port 8 Selection */
|
|
|
861 |
SFR_8BIT(P8REN); /* Port 8 Resistor Enable */
|
|
|
862 |
|
|
|
863 |
SFR_16BIT(PAIN); /* Port A Input */
|
|
|
864 |
SFR_16BIT(PAOUT); /* Port A Output */
|
|
|
865 |
SFR_16BIT(PADIR); /* Port A Direction */
|
|
|
866 |
SFR_16BIT(PASEL); /* Port A Selection */
|
|
|
867 |
SFR_16BIT(PAREN); /* Port A Resistor Enable */
|
|
|
868 |
|
|
|
869 |
/************************************************************
|
|
|
870 |
* DIGITAL I/O Port9/10 Pull up / Pull down Resistors
|
|
|
871 |
************************************************************/
|
|
|
872 |
#define __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */
|
|
|
873 |
#define __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */
|
|
|
874 |
#define __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */
|
|
|
875 |
|
|
|
876 |
SFR_8BIT(P9IN); /* Port 9 Input */
|
|
|
877 |
SFR_8BIT(P9OUT); /* Port 9 Output */
|
|
|
878 |
SFR_8BIT(P9DIR); /* Port 9 Direction */
|
|
|
879 |
SFR_8BIT(P9SEL); /* Port 9 Selection */
|
|
|
880 |
SFR_8BIT(P9REN); /* Port 9 Resistor Enable */
|
|
|
881 |
|
|
|
882 |
SFR_8BIT(P10IN); /* Port 10 Input */
|
|
|
883 |
SFR_8BIT(P10OUT); /* Port 10 Output */
|
|
|
884 |
SFR_8BIT(P10DIR); /* Port 10 Direction */
|
|
|
885 |
SFR_8BIT(P10SEL); /* Port 10 Selection */
|
|
|
886 |
SFR_8BIT(P10REN); /* Port 10 Resistor Enable */
|
|
|
887 |
|
|
|
888 |
SFR_16BIT(PBIN); /* Port B Input */
|
|
|
889 |
SFR_16BIT(PBOUT); /* Port B Output */
|
|
|
890 |
SFR_16BIT(PBDIR); /* Port B Direction */
|
|
|
891 |
SFR_16BIT(PBSEL); /* Port B Selection */
|
|
|
892 |
SFR_16BIT(PBREN); /* Port B Resistor Enable */
|
|
|
893 |
|
|
|
894 |
/************************************************************
|
|
|
895 |
* Brown-Out, Supply Voltage Supervision (SVS)
|
|
|
896 |
************************************************************/
|
|
|
897 |
#define __MSP430_HAS_SVS__ /* Definition to show that Module is available */
|
|
|
898 |
|
|
|
899 |
SFR_8BIT(SVSCTL); /* SVS Control */
|
|
|
900 |
#define SVSFG (0x01) /* SVS Flag */
|
|
|
901 |
#define SVSOP (0x02) /* SVS output (read only) */
|
|
|
902 |
#define SVSON (0x04) /* Switches the SVS on/off */
|
|
|
903 |
#define PORON (0x08) /* Enable POR Generation if Low Voltage */
|
|
|
904 |
#define VLD0 (0x10)
|
|
|
905 |
#define VLD1 (0x20)
|
|
|
906 |
#define VLD2 (0x40)
|
|
|
907 |
#define VLD3 (0x80)
|
|
|
908 |
|
|
|
909 |
#define VLDON (0x10)
|
|
|
910 |
#define VLDOFF (0x00)
|
|
|
911 |
#define VLD_1_8V (0x10)
|
|
|
912 |
|
|
|
913 |
/************************************************************
|
|
|
914 |
* SD16_A6 - Sigma Delta 16 Bit
|
|
|
915 |
************************************************************/
|
|
|
916 |
#define __MSP430_HAS_SD16_A6__ /* Definition to show that Module is available */
|
|
|
917 |
|
|
|
918 |
SFR_8BIT(SD16INCTL0); /* SD16 Input Control Register Channel 0 */
|
|
|
919 |
SFR_8BIT(SD16INCTL1); /* SD16 Input Control Register Channel 1 */
|
|
|
920 |
SFR_8BIT(SD16INCTL2); /* SD16 Input Control Register Channel 2 */
|
|
|
921 |
SFR_8BIT(SD16INCTL3); /* SD16 Input Control Register Channel 3 */
|
|
|
922 |
SFR_8BIT(SD16INCTL4); /* SD16 Input Control Register Channel 4 */
|
|
|
923 |
SFR_8BIT(SD16INCTL5); /* SD16 Input Control Register Channel 5 */
|
|
|
924 |
SFR_8BIT(SD16PRE0); /* SD16 Preload Register Channel 0 */
|
|
|
925 |
SFR_8BIT(SD16PRE1); /* SD16 Preload Register Channel 1 */
|
|
|
926 |
SFR_8BIT(SD16PRE2); /* SD16 Preload Register Channel 2 */
|
|
|
927 |
SFR_8BIT(SD16PRE3); /* SD16 Preload Register Channel 3 */
|
|
|
928 |
SFR_8BIT(SD16PRE4); /* SD16 Preload Register Channel 4 */
|
|
|
929 |
SFR_8BIT(SD16PRE5); /* SD16 Preload Register Channel 5 */
|
|
|
930 |
SFR_8BIT(SD16CONF0); /* SD16 Internal Configuration Register 0 */
|
|
|
931 |
SFR_8BIT(SD16CONF1); /* SD16 Internal Configuration Register 1 */
|
|
|
932 |
/* Please use only the recommended settings */
|
|
|
933 |
|
|
|
934 |
SFR_16BIT(SD16CTL); /* Sigma Delta ADC 16 Control Register */
|
|
|
935 |
SFR_16BIT(SD16CCTL0); /* SD16 Channel 0 Control Register */
|
|
|
936 |
SFR_16BIT(SD16CCTL1); /* SD16 Channel 1 Control Register */
|
|
|
937 |
SFR_16BIT(SD16CCTL2); /* SD16 Channel 2 Control Register */
|
|
|
938 |
SFR_16BIT(SD16CCTL3); /* SD16 Channel 3 Control Register */
|
|
|
939 |
SFR_16BIT(SD16CCTL4); /* SD16 Channel 4 Control Register */
|
|
|
940 |
SFR_16BIT(SD16CCTL5); /* SD16 Channel 5 Control Register */
|
|
|
941 |
SFR_16BIT(SD16MEM0); /* SD16 Channel 0 Conversion Memory */
|
|
|
942 |
SFR_16BIT(SD16MEM1); /* SD16 Channel 1 Conversion Memory */
|
|
|
943 |
SFR_16BIT(SD16MEM2); /* SD16 Channel 2 Conversion Memory */
|
|
|
944 |
SFR_16BIT(SD16MEM3); /* SD16 Channel 3 Conversion Memory */
|
|
|
945 |
SFR_16BIT(SD16MEM4); /* SD16 Channel 4 Conversion Memory */
|
|
|
946 |
SFR_16BIT(SD16MEM5); /* SD16 Channel 5 Conversion Memory */
|
|
|
947 |
SFR_16BIT(SD16IV); /* SD16 Interrupt Vector Register */
|
|
|
948 |
|
|
|
949 |
/* SD16INCTLx */
|
|
|
950 |
#define SD16INCH0 (0x0001) /* SD16 Input Channel select 0 */
|
|
|
951 |
#define SD16INCH1 (0x0002) /* SD16 Input Channel select 1 */
|
|
|
952 |
#define SD16INCH2 (0x0004) /* SD16 Input Channel select 2 */
|
|
|
953 |
#define SD16GAIN0 (0x0008) /* SD16 Input Pre-Amplifier Gain Select 0 */
|
|
|
954 |
#define SD16GAIN1 (0x0010) /* SD16 Input Pre-Amplifier Gain Select 1 */
|
|
|
955 |
#define SD16GAIN2 (0x0020) /* SD16 Input Pre-Amplifier Gain Select 2 */
|
|
|
956 |
#define SD16INTDLY0 (0x0040) /* SD16 Interrupt Delay after 1.Conversion 0 */
|
|
|
957 |
#define SD16INTDLY1 (0x0080) /* SD16 Interrupt Delay after 1.Conversion 1 */
|
|
|
958 |
|
|
|
959 |
#define SD16GAIN_1 (0x0000) /* SD16 Input Pre-Amplifier Gain Select *1 */
|
|
|
960 |
#define SD16GAIN_2 (0x0008) /* SD16 Input Pre-Amplifier Gain Select *2 */
|
|
|
961 |
#define SD16GAIN_4 (0x0010) /* SD16 Input Pre-Amplifier Gain Select *4 */
|
|
|
962 |
#define SD16GAIN_8 (0x0018) /* SD16 Input Pre-Amplifier Gain Select *8 */
|
|
|
963 |
#define SD16GAIN_16 (0x0020) /* SD16 Input Pre-Amplifier Gain Select *16 */
|
|
|
964 |
#define SD16GAIN_32 (0x0028) /* SD16 Input Pre-Amplifier Gain Select *32 */
|
|
|
965 |
|
|
|
966 |
#define SD16INCH_0 (0x0000) /* SD16 Input Channel select input */
|
|
|
967 |
#define SD16INCH_1 (0x0001) /* SD16 Input Channel select input */
|
|
|
968 |
#define SD16INCH_2 (0x0002) /* SD16 Input Channel select input */
|
|
|
969 |
#define SD16INCH_3 (0x0003) /* SD16 Input Channel select input */
|
|
|
970 |
#define SD16INCH_4 (0x0004) /* SD16 Input Channel select input */
|
|
|
971 |
#define SD16INCH_5 (0x0005) /* SD16 Input Channel select Vcc divider */
|
|
|
972 |
#define SD16INCH_6 (0x0006) /* SD16 Input Channel select Temp */
|
|
|
973 |
#define SD16INCH_7 (0x0007) /* SD16 Input Channel select Offset */
|
|
|
974 |
|
|
|
975 |
#define SD16INTDLY_0 (0x0000) /* SD16 Interrupt Delay: Int. after 4.Conversion */
|
|
|
976 |
#define SD16INTDLY_1 (0x0040) /* SD16 Interrupt Delay: Int. after 3.Conversion */
|
|
|
977 |
#define SD16INTDLY_2 (0x0080) /* SD16 Interrupt Delay: Int. after 2.Conversion */
|
|
|
978 |
#define SD16INTDLY_3 (0x00C0) /* SD16 Interrupt Delay: Int. after 1.Conversion */
|
|
|
979 |
|
|
|
980 |
/* SD16CTL */
|
|
|
981 |
#define SD16OVIE (0x0002) /* SD16 Overflow Interupt Enable */
|
|
|
982 |
#define SD16REFON (0x0004) /* SD16 Switch internal Reference on */
|
|
|
983 |
#define SD16VMIDON (0x0008) /* SD16 Switch Vmid Buffer on */
|
|
|
984 |
#define SD16SSEL0 (0x0010) /* SD16 Clock Source Select 0 */
|
|
|
985 |
#define SD16SSEL1 (0x0020) /* SD16 Clock Source Select 1 */
|
|
|
986 |
#define SD16DIV0 (0x0040) /* SD16 Clock Divider Select 0 */
|
|
|
987 |
#define SD16DIV1 (0x0080) /* SD16 Clock Divider Select 1 */
|
|
|
988 |
#define SD16LP (0x0100) /* SD16 Low Power Mode Enable */
|
|
|
989 |
#define SD16XDIV0 (0x0200) /* SD16 2.Clock Divider Select 0 */
|
|
|
990 |
#define SD16XDIV1 (0x0400) /* SD16 2.Clock Divider Select 1 */
|
|
|
991 |
//#define SD16XDIV2 (0x0800) /* SD16 2.Clock Divider Select 2 */
|
|
|
992 |
|
|
|
993 |
#define SD16DIV_0 (0x0000) /* SD16 Clock Divider Select /1 */
|
|
|
994 |
#define SD16DIV_1 (SD16DIV0) /* SD16 Clock Divider Select /2 */
|
|
|
995 |
#define SD16DIV_2 (SD16DIV1) /* SD16 Clock Divider Select /4 */
|
|
|
996 |
#define SD16DIV_3 (SD16DIV0+SD16DIV1) /* SD16 Clock Divider Select /8 */
|
|
|
997 |
|
|
|
998 |
#define SD16XDIV_0 (0x0000) /* SD16 2.Clock Divider Select /1 */
|
|
|
999 |
#define SD16XDIV_1 (SD16XDIV0) /* SD16 2.Clock Divider Select /3 */
|
|
|
1000 |
#define SD16XDIV_2 (SD16XDIV1) /* SD16 2.Clock Divider Select /16 */
|
|
|
1001 |
#define SD16XDIV_3 (SD16XDIV0+SD16XDIV1) /* SD16 2.Clock Divider Select /48 */
|
|
|
1002 |
|
|
|
1003 |
#define SD16SSEL_0 (0x0000) /* SD16 Clock Source Select MCLK */
|
|
|
1004 |
#define SD16SSEL_1 (SD16SSEL0) /* SD16 Clock Source Select SMCLK */
|
|
|
1005 |
#define SD16SSEL_2 (SD16SSEL1) /* SD16 Clock Source Select ACLK */
|
|
|
1006 |
#define SD16SSEL_3 (SD16SSEL0+SD16SSEL1) /* SD16 Clock Source Select TACLK */
|
|
|
1007 |
|
|
|
1008 |
/* SD16CCTLx */
|
|
|
1009 |
#define SD16GRP (0x0001) /* SD16 Grouping of Channels: 0:Off/1:On */
|
|
|
1010 |
#define SD16SC (0x0002) /* SD16 Start Conversion */
|
|
|
1011 |
#define SD16IFG (0x0004) /* SD16 Channel x Interrupt Flag */
|
|
|
1012 |
#define SD16IE (0x0008) /* SD16 Channel x Interrupt Enable */
|
|
|
1013 |
#define SD16DF (0x0010) /* SD16 Channel x Data Format: 0:Unipolar/1:Bipolar */
|
|
|
1014 |
#define SD16OVIFG (0x0020) /* SD16 Channel x Overflow Interrupt Flag */
|
|
|
1015 |
#define SD16LSBACC (0x0040) /* SD16 Channel x Access LSB of ADC */
|
|
|
1016 |
#define SD16LSBTOG (0x0080) /* SD16 Channel x Toggle LSB Output of ADC */
|
|
|
1017 |
#define SD16OSR0 (0x0100) /* SD16 Channel x OverSampling Ratio 0 */
|
|
|
1018 |
#define SD16OSR1 (0x0200) /* SD16 Channel x OverSampling Ratio 1 */
|
|
|
1019 |
#define SD16SNGL (0x0400) /* SD16 Channel x Single Conversion On/Off */
|
|
|
1020 |
#define SD16XOSR (0x0800) /* SD16 Channel x Extended OverSampling Ratio */
|
|
|
1021 |
#define SD16UNI (0x1000) /* SD16 Channel x Bipolar(0) / Unipolar(1) Mode */
|
|
|
1022 |
|
|
|
1023 |
#define SD16OSR_1024 (SD16OSR0+SD16XOSR) /* SD16 Channel x OverSampling Ratio 1024 */
|
|
|
1024 |
#define SD16OSR_512 (SD16XOSR) /* SD16 Channel x OverSampling Ratio 512 */
|
|
|
1025 |
#define SD16OSR_256 (0x0000) /* SD16 Channel x OverSampling Ratio 256 */
|
|
|
1026 |
#define SD16OSR_128 (0x0100) /* SD16 Channel x OverSampling Ratio 128 */
|
|
|
1027 |
#define SD16OSR_64 (0x0200) /* SD16 Channel x OverSampling Ratio 64 */
|
|
|
1028 |
#define SD16OSR_32 (0x0300) /* SD16 Channel x OverSampling Ratio 32 */
|
|
|
1029 |
|
|
|
1030 |
/* SD16IV Definitions */
|
|
|
1031 |
#define SD16IV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1032 |
#define SD16IV_SD16OVIFG (0x0002) /* SD16OVIFG */
|
|
|
1033 |
#define SD16IV_SD16MEM0 (0x0004) /* SD16MEM0 SD16IFG */
|
|
|
1034 |
#define SD16IV_SD16MEM1 (0x0006) /* SD16MEM1 SD16IFG */
|
|
|
1035 |
#define SD16IV_SD16MEM2 (0x0008) /* SD16MEM2 SD16IFG */
|
|
|
1036 |
#define SD16IV_SD16MEM3 (0x000A) /* SD16MEM3 SD16IFG */
|
|
|
1037 |
#define SD16IV_SD16MEM4 (0x000C) /* SD16MEM4 SD16IFG */
|
|
|
1038 |
#define SD16IV_SD16MEM5 (0x000E) /* SD16MEM5 SD16IFG */
|
|
|
1039 |
|
|
|
1040 |
/************************************************************
|
|
|
1041 |
* Timer A3
|
|
|
1042 |
************************************************************/
|
|
|
1043 |
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
|
|
|
1044 |
|
|
|
1045 |
SFR_16BIT(TAIV); /* Timer A Interrupt Vector Word */
|
|
|
1046 |
SFR_16BIT(TACTL); /* Timer A Control */
|
|
|
1047 |
SFR_16BIT(TACCTL0); /* Timer A Capture/Compare Control 0 */
|
|
|
1048 |
SFR_16BIT(TACCTL1); /* Timer A Capture/Compare Control 1 */
|
|
|
1049 |
SFR_16BIT(TACCTL2); /* Timer A Capture/Compare Control 2 */
|
|
|
1050 |
SFR_16BIT(TAR); /* Timer A Counter Register */
|
|
|
1051 |
SFR_16BIT(TACCR0); /* Timer A Capture/Compare 0 */
|
|
|
1052 |
SFR_16BIT(TACCR1); /* Timer A Capture/Compare 1 */
|
|
|
1053 |
SFR_16BIT(TACCR2); /* Timer A Capture/Compare 2 */
|
|
|
1054 |
|
|
|
1055 |
/* Alternate register names */
|
|
|
1056 |
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
1057 |
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
1058 |
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
1059 |
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
1060 |
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
1061 |
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
1062 |
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
1063 |
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
1064 |
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
1065 |
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
1066 |
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
1067 |
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
1068 |
/* Alternate register names - 5xx style */
|
|
|
1069 |
#define TA0IV TAIV /* Timer A Interrupt Vector Word */
|
|
|
1070 |
#define TA0CTL TACTL /* Timer A Control */
|
|
|
1071 |
#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
1072 |
#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
1073 |
#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
|
|
|
1074 |
#define TA0R TAR /* Timer A Counter Register */
|
|
|
1075 |
#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
1076 |
#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
1077 |
#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */
|
|
|
1078 |
#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */
|
|
|
1079 |
#define TA0CTL_ TACTL_ /* Timer A Control */
|
|
|
1080 |
#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
1081 |
#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
1082 |
#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
|
|
|
1083 |
#define TA0R_ TAR_ /* Timer A Counter Register */
|
|
|
1084 |
#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
1085 |
#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
1086 |
#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
|
|
|
1087 |
|
|
|
1088 |
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
|
|
|
1089 |
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
|
|
|
1090 |
#define ID1 (0x0080) /* Timer A clock input divider 1 */
|
|
|
1091 |
#define ID0 (0x0040) /* Timer A clock input divider 0 */
|
|
|
1092 |
#define MC1 (0x0020) /* Timer A mode control 1 */
|
|
|
1093 |
#define MC0 (0x0010) /* Timer A mode control 0 */
|
|
|
1094 |
#define TACLR (0x0004) /* Timer A counter clear */
|
|
|
1095 |
#define TAIE (0x0002) /* Timer A counter interrupt enable */
|
|
|
1096 |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
|
|
|
1097 |
|
|
|
1098 |
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
1099 |
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
1100 |
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
1101 |
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
1102 |
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
1103 |
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
1104 |
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
1105 |
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
1106 |
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
1107 |
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
1108 |
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
1109 |
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
1110 |
|
|
|
1111 |
#define CM1 (0x8000) /* Capture mode 1 */
|
|
|
1112 |
#define CM0 (0x4000) /* Capture mode 0 */
|
|
|
1113 |
#define CCIS1 (0x2000) /* Capture input select 1 */
|
|
|
1114 |
#define CCIS0 (0x1000) /* Capture input select 0 */
|
|
|
1115 |
#define SCS (0x0800) /* Capture sychronize */
|
|
|
1116 |
#define SCCI (0x0400) /* Latched capture signal (read) */
|
|
|
1117 |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
|
|
|
1118 |
#define OUTMOD2 (0x0080) /* Output mode 2 */
|
|
|
1119 |
#define OUTMOD1 (0x0040) /* Output mode 1 */
|
|
|
1120 |
#define OUTMOD0 (0x0020) /* Output mode 0 */
|
|
|
1121 |
#define CCIE (0x0010) /* Capture/compare interrupt enable */
|
|
|
1122 |
#define CCI (0x0008) /* Capture input signal (read) */
|
|
|
1123 |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
|
|
|
1124 |
#define COV (0x0002) /* Capture/compare overflow flag */
|
|
|
1125 |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
|
|
|
1126 |
|
|
|
1127 |
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
|
|
|
1128 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
|
|
|
1129 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
|
|
|
1130 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
|
|
|
1131 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
|
|
|
1132 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
|
|
|
1133 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
|
|
|
1134 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
|
|
|
1135 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
|
|
|
1136 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
|
|
|
1137 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
|
|
|
1138 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
|
|
|
1139 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
|
|
|
1140 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
|
|
|
1141 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
|
|
|
1142 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
|
|
|
1143 |
|
|
|
1144 |
/* TA3IV Definitions */
|
|
|
1145 |
#define TAIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1146 |
#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */
|
|
|
1147 |
#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */
|
|
|
1148 |
#define TAIV_6 (0x0006) /* Reserved */
|
|
|
1149 |
#define TAIV_8 (0x0008) /* Reserved */
|
|
|
1150 |
#define TAIV_TAIFG (0x000A) /* TAIFG */
|
|
|
1151 |
|
|
|
1152 |
/************************************************************
|
|
|
1153 |
* Timer B3
|
|
|
1154 |
************************************************************/
|
|
|
1155 |
#define __MSP430_HAS_TB3__ /* Definition to show that Module is available */
|
|
|
1156 |
|
|
|
1157 |
SFR_16BIT(TBIV); /* Timer B Interrupt Vector Word */
|
|
|
1158 |
SFR_16BIT(TBCTL); /* Timer B Control */
|
|
|
1159 |
SFR_16BIT(TBCCTL0); /* Timer B Capture/Compare Control 0 */
|
|
|
1160 |
SFR_16BIT(TBCCTL1); /* Timer B Capture/Compare Control 1 */
|
|
|
1161 |
SFR_16BIT(TBCCTL2); /* Timer B Capture/Compare Control 2 */
|
|
|
1162 |
SFR_16BIT(TBR); /* Timer B Counter Register */
|
|
|
1163 |
SFR_16BIT(TBCCR0); /* Timer B Capture/Compare 0 */
|
|
|
1164 |
SFR_16BIT(TBCCR1); /* Timer B Capture/Compare 1 */
|
|
|
1165 |
SFR_16BIT(TBCCR2); /* Timer B Capture/Compare 2 */
|
|
|
1166 |
|
|
|
1167 |
/* Alternate register names - 5xx style */
|
|
|
1168 |
#define TB0IV TBIV /* Timer B Interrupt Vector Word */
|
|
|
1169 |
#define TB0CTL TBCTL /* Timer B Control */
|
|
|
1170 |
#define TB0CCTL0 TBCCTL0 /* Timer B Capture/Compare Control 0 */
|
|
|
1171 |
#define TB0CCTL1 TBCCTL1 /* Timer B Capture/Compare Control 1 */
|
|
|
1172 |
#define TB0CCTL2 TBCCTL2 /* Timer B Capture/Compare Control 2 */
|
|
|
1173 |
#define TB0R TBR /* Timer B Counter Register */
|
|
|
1174 |
#define TB0CCR0 TBCCR0 /* Timer B Capture/Compare 0 */
|
|
|
1175 |
#define TB0CCR1 TBCCR1 /* Timer B Capture/Compare 1 */
|
|
|
1176 |
#define TB0CCR2 TBCCR2 /* Timer B Capture/Compare 2 */
|
|
|
1177 |
#define TB0IV_ TBIV_ /* Timer B Interrupt Vector Word */
|
|
|
1178 |
#define TB0CTL_ TBCTL_ /* Timer B Control */
|
|
|
1179 |
#define TB0CCTL0_ TBCCTL0_ /* Timer B Capture/Compare Control 0 */
|
|
|
1180 |
#define TB0CCTL1_ TBCCTL1_ /* Timer B Capture/Compare Control 1 */
|
|
|
1181 |
#define TB0CCTL2_ TBCCTL2_ /* Timer B Capture/Compare Control 2 */
|
|
|
1182 |
#define TB0R_ TBR_ /* Timer B Counter Register */
|
|
|
1183 |
#define TB0CCR0_ TBCCR0_ /* Timer B Capture/Compare 0 */
|
|
|
1184 |
#define TB0CCR1_ TBCCR1_ /* Timer B Capture/Compare 1 */
|
|
|
1185 |
#define TB0CCR2_ TBCCR2_ /* Timer B Capture/Compare 2 */
|
|
|
1186 |
|
|
|
1187 |
#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */
|
|
|
1188 |
#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */
|
|
|
1189 |
#define CNTL1 (0x1000) /* Counter lenght 1 */
|
|
|
1190 |
#define CNTL0 (0x0800) /* Counter lenght 0 */
|
|
|
1191 |
#define TBSSEL1 (0x0200) /* Clock source 1 */
|
|
|
1192 |
#define TBSSEL0 (0x0100) /* Clock source 0 */
|
|
|
1193 |
#define TBCLR (0x0004) /* Timer B counter clear */
|
|
|
1194 |
#define TBIE (0x0002) /* Timer B interrupt enable */
|
|
|
1195 |
#define TBIFG (0x0001) /* Timer B interrupt flag */
|
|
|
1196 |
|
|
|
1197 |
#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */
|
|
|
1198 |
#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */
|
|
|
1199 |
|
|
|
1200 |
#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
|
|
|
1201 |
#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
|
|
|
1202 |
#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
|
|
|
1203 |
#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
|
|
|
1204 |
#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
|
|
|
1205 |
#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
|
|
|
1206 |
#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
|
|
|
1207 |
#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
|
|
|
1208 |
#define SHR_0 (0*0x2000u) /* Timer B Group: 0 - individually */
|
|
|
1209 |
#define SHR_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
1210 |
#define SHR_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
1211 |
#define SHR_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
|
|
|
1212 |
#define TBCLGRP_0 (0*0x2000u) /* Timer B Group: 0 - individually */
|
|
|
1213 |
#define TBCLGRP_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
|
|
|
1214 |
#define TBCLGRP_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
|
|
|
1215 |
#define TBCLGRP_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
|
|
|
1216 |
|
|
|
1217 |
/* Additional Timer B Control Register bits are defined in Timer A */
|
|
|
1218 |
|
|
|
1219 |
#define CLLD1 (0x0400) /* Compare latch load source 1 */
|
|
|
1220 |
#define CLLD0 (0x0200) /* Compare latch load source 0 */
|
|
|
1221 |
|
|
|
1222 |
#define SLSHR1 (0x0400) /* Compare latch load source 1 */
|
|
|
1223 |
#define SLSHR0 (0x0200) /* Compare latch load source 0 */
|
|
|
1224 |
|
|
|
1225 |
#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
1226 |
#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
|
|
|
1227 |
#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
1228 |
#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
|
|
|
1229 |
|
|
|
1230 |
#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
|
|
|
1231 |
#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
|
|
|
1232 |
#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
|
|
|
1233 |
#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
|
|
|
1234 |
|
|
|
1235 |
/* TB3IV Definitions */
|
|
|
1236 |
#define TBIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
1237 |
#define TBIV_TBCCR1 (0x0002) /* TBCCR1_CCIFG */
|
|
|
1238 |
#define TBIV_TBCCR2 (0x0004) /* TBCCR2_CCIFG */
|
|
|
1239 |
#define TBIV_3 (0x0006) /* Reserved */
|
|
|
1240 |
#define TBIV_4 (0x0008) /* Reserved */
|
|
|
1241 |
#define TBIV_5 (0x000A) /* Reserved */
|
|
|
1242 |
#define TBIV_6 (0x000C) /* Reserved */
|
|
|
1243 |
#define TBIV_TBIFG (0x000E) /* TBIFG */
|
|
|
1244 |
|
|
|
1245 |
/************************************************************
|
|
|
1246 |
* USCI
|
|
|
1247 |
************************************************************/
|
|
|
1248 |
#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */
|
|
|
1249 |
#define __MSP430_HAS_USCI_AB0__ /* Definition to show that Module is available */
|
|
|
1250 |
#define __MSP430_HAS_USCI_AB1__ /* Definition to show that Module is available */
|
|
|
1251 |
|
|
|
1252 |
SFR_8BIT(UCA0CTL0); /* USCI A0 Control Register 0 */
|
|
|
1253 |
SFR_8BIT(UCA0CTL1); /* USCI A0 Control Register 1 */
|
|
|
1254 |
SFR_8BIT(UCA0BR0); /* USCI A0 Baud Rate 0 */
|
|
|
1255 |
SFR_8BIT(UCA0BR1); /* USCI A0 Baud Rate 1 */
|
|
|
1256 |
SFR_8BIT(UCA0MCTL); /* USCI A0 Modulation Control */
|
|
|
1257 |
SFR_8BIT(UCA0STAT); /* USCI A0 Status Register */
|
|
|
1258 |
SFR_8BIT(UCA0RXBUF); /* USCI A0 Receive Buffer */
|
|
|
1259 |
SFR_8BIT(UCA0TXBUF); /* USCI A0 Transmit Buffer */
|
|
|
1260 |
SFR_8BIT(UCA0ABCTL); /* USCI A0 LIN Control */
|
|
|
1261 |
SFR_8BIT(UCA0IRTCTL); /* USCI A0 IrDA Transmit Control */
|
|
|
1262 |
SFR_8BIT(UCA0IRRCTL); /* USCI A0 IrDA Receive Control */
|
|
|
1263 |
|
|
|
1264 |
|
|
|
1265 |
|
|
|
1266 |
SFR_8BIT(UCB0CTL0); /* USCI B0 Control Register 0 */
|
|
|
1267 |
SFR_8BIT(UCB0CTL1); /* USCI B0 Control Register 1 */
|
|
|
1268 |
SFR_8BIT(UCB0BR0); /* USCI B0 Baud Rate 0 */
|
|
|
1269 |
SFR_8BIT(UCB0BR1); /* USCI B0 Baud Rate 1 */
|
|
|
1270 |
SFR_8BIT(UCB0I2CIE); /* USCI B0 I2C Interrupt Enable Register */
|
|
|
1271 |
SFR_8BIT(UCB0STAT); /* USCI B0 Status Register */
|
|
|
1272 |
SFR_8BIT(UCB0RXBUF); /* USCI B0 Receive Buffer */
|
|
|
1273 |
SFR_8BIT(UCB0TXBUF); /* USCI B0 Transmit Buffer */
|
|
|
1274 |
/* Note: Devices with SD16 have the next two registers on a different address */
|
|
|
1275 |
SFR_16BIT(UCB0I2COA); /* USCI B0 I2C Own Address */
|
|
|
1276 |
SFR_16BIT(UCB0I2CSA); /* USCI B0 I2C Slave Address */
|
|
|
1277 |
|
|
|
1278 |
SFR_8BIT(UCA1CTL0); /* USCI A1 Control Register 0 */
|
|
|
1279 |
SFR_8BIT(UCA1CTL1); /* USCI A1 Control Register 1 */
|
|
|
1280 |
SFR_8BIT(UCA1BR0); /* USCI A1 Baud Rate 0 */
|
|
|
1281 |
SFR_8BIT(UCA1BR1); /* USCI A1 Baud Rate 1 */
|
|
|
1282 |
SFR_8BIT(UCA1MCTL); /* USCI A1 Modulation Control */
|
|
|
1283 |
SFR_8BIT(UCA1STAT); /* USCI A1 Status Register */
|
|
|
1284 |
SFR_8BIT(UCA1RXBUF); /* USCI A1 Receive Buffer */
|
|
|
1285 |
SFR_8BIT(UCA1TXBUF); /* USCI A1 Transmit Buffer */
|
|
|
1286 |
SFR_8BIT(UCA1ABCTL); /* USCI A1 LIN Control */
|
|
|
1287 |
SFR_8BIT(UCA1IRTCTL); /* USCI A1 IrDA Transmit Control */
|
|
|
1288 |
SFR_8BIT(UCA1IRRCTL); /* USCI A1 IrDA Receive Control */
|
|
|
1289 |
|
|
|
1290 |
|
|
|
1291 |
|
|
|
1292 |
SFR_8BIT(UCB1CTL0); /* USCI B1 Control Register 0 */
|
|
|
1293 |
SFR_8BIT(UCB1CTL1); /* USCI B1 Control Register 1 */
|
|
|
1294 |
SFR_8BIT(UCB1BR0); /* USCI B1 Baud Rate 0 */
|
|
|
1295 |
SFR_8BIT(UCB1BR1); /* USCI B1 Baud Rate 1 */
|
|
|
1296 |
SFR_8BIT(UCB1I2CIE); /* USCI B1 I2C Interrupt Enable Register */
|
|
|
1297 |
SFR_8BIT(UCB1STAT); /* USCI B1 Status Register */
|
|
|
1298 |
SFR_8BIT(UCB1RXBUF); /* USCI B1 Receive Buffer */
|
|
|
1299 |
SFR_8BIT(UCB1TXBUF); /* USCI B1 Transmit Buffer */
|
|
|
1300 |
SFR_16BIT(UCB1I2COA); /* USCI B1 I2C Own Address */
|
|
|
1301 |
SFR_16BIT(UCB1I2CSA); /* USCI B1 I2C Slave Address */
|
|
|
1302 |
|
|
|
1303 |
// UART-Mode Bits
|
|
|
1304 |
#define UCPEN (0x80) /* Async. Mode: Parity enable */
|
|
|
1305 |
#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
|
|
|
1306 |
#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
|
|
|
1307 |
#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
|
|
|
1308 |
#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
|
|
|
1309 |
#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
|
|
|
1310 |
#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
|
|
|
1311 |
#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
|
|
|
1312 |
|
|
|
1313 |
// SPI-Mode Bits
|
|
|
1314 |
#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
|
|
|
1315 |
#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
|
|
|
1316 |
#define UCMST (0x08) /* Sync. Mode: Master Select */
|
|
|
1317 |
|
|
|
1318 |
// I2C-Mode Bits
|
|
|
1319 |
#define UCA10 (0x80) /* 10-bit Address Mode */
|
|
|
1320 |
#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
|
|
|
1321 |
#define UCMM (0x20) /* Multi-Master Environment */
|
|
|
1322 |
//#define res (0x10) /* reserved */
|
|
|
1323 |
#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
|
|
|
1324 |
#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
|
|
|
1325 |
#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
|
|
|
1326 |
#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
|
|
|
1327 |
|
|
|
1328 |
// UART-Mode Bits
|
|
|
1329 |
#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
|
|
|
1330 |
#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
|
|
|
1331 |
#define UCRXEIE (0x20) /* RX Error interrupt enable */
|
|
|
1332 |
#define UCBRKIE (0x10) /* Break interrupt enable */
|
|
|
1333 |
#define UCDORM (0x08) /* Dormant (Sleep) Mode */
|
|
|
1334 |
#define UCTXADDR (0x04) /* Send next Data as Address */
|
|
|
1335 |
#define UCTXBRK (0x02) /* Send next Data as Break */
|
|
|
1336 |
#define UCSWRST (0x01) /* USCI Software Reset */
|
|
|
1337 |
|
|
|
1338 |
// SPI-Mode Bits
|
|
|
1339 |
//#define res (0x20) /* reserved */
|
|
|
1340 |
//#define res (0x10) /* reserved */
|
|
|
1341 |
//#define res (0x08) /* reserved */
|
|
|
1342 |
//#define res (0x04) /* reserved */
|
|
|
1343 |
//#define res (0x02) /* reserved */
|
|
|
1344 |
|
|
|
1345 |
// I2C-Mode Bits
|
|
|
1346 |
//#define res (0x20) /* reserved */
|
|
|
1347 |
#define UCTR (0x10) /* Transmit/Receive Select/Flag */
|
|
|
1348 |
#define UCTXNACK (0x08) /* Transmit NACK */
|
|
|
1349 |
#define UCTXSTP (0x04) /* Transmit STOP */
|
|
|
1350 |
#define UCTXSTT (0x02) /* Transmit START */
|
|
|
1351 |
#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
|
|
|
1352 |
#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
|
|
|
1353 |
#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
|
|
|
1354 |
#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
|
|
|
1355 |
|
|
|
1356 |
#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
|
|
|
1357 |
#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
|
|
|
1358 |
#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
|
|
|
1359 |
#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
|
|
|
1360 |
#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
|
|
|
1361 |
#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
|
|
|
1362 |
#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
|
|
|
1363 |
#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
|
|
|
1364 |
|
|
|
1365 |
#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
|
|
|
1366 |
#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
|
|
|
1367 |
#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
|
|
|
1368 |
#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
|
|
|
1369 |
#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
|
|
|
1370 |
#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
|
|
|
1371 |
#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
|
|
|
1372 |
#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
|
|
|
1373 |
#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
|
|
|
1374 |
#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
|
|
|
1375 |
#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
|
|
|
1376 |
#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
|
|
|
1377 |
#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
|
|
|
1378 |
#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
|
|
|
1379 |
#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
|
|
|
1380 |
#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
|
|
|
1381 |
|
|
|
1382 |
#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
|
|
|
1383 |
#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
|
|
|
1384 |
#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
|
|
|
1385 |
#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
|
|
|
1386 |
#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
|
|
|
1387 |
#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
|
|
|
1388 |
#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
|
|
|
1389 |
#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
|
|
|
1390 |
|
|
|
1391 |
#define UCLISTEN (0x80) /* USCI Listen mode */
|
|
|
1392 |
#define UCFE (0x40) /* USCI Frame Error Flag */
|
|
|
1393 |
#define UCOE (0x20) /* USCI Overrun Error Flag */
|
|
|
1394 |
#define UCPE (0x10) /* USCI Parity Error Flag */
|
|
|
1395 |
#define UCBRK (0x08) /* USCI Break received */
|
|
|
1396 |
#define UCRXERR (0x04) /* USCI RX Error Flag */
|
|
|
1397 |
#define UCADDR (0x02) /* USCI Address received Flag */
|
|
|
1398 |
#define UCBUSY (0x01) /* USCI Busy Flag */
|
|
|
1399 |
#define UCIDLE (0x02) /* USCI Idle line detected Flag */
|
|
|
1400 |
|
|
|
1401 |
//#define res (0x80) /* reserved */
|
|
|
1402 |
//#define res (0x40) /* reserved */
|
|
|
1403 |
//#define res (0x20) /* reserved */
|
|
|
1404 |
//#define res (0x10) /* reserved */
|
|
|
1405 |
#define UCNACKIE (0x08) /* NACK Condition interrupt enable */
|
|
|
1406 |
#define UCSTPIE (0x04) /* STOP Condition interrupt enable */
|
|
|
1407 |
#define UCSTTIE (0x02) /* START Condition interrupt enable */
|
|
|
1408 |
#define UCALIE (0x01) /* Arbitration Lost interrupt enable */
|
|
|
1409 |
|
|
|
1410 |
#define UCSCLLOW (0x40) /* SCL low */
|
|
|
1411 |
#define UCGC (0x20) /* General Call address received Flag */
|
|
|
1412 |
#define UCBBUSY (0x10) /* Bus Busy Flag */
|
|
|
1413 |
#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */
|
|
|
1414 |
#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */
|
|
|
1415 |
#define UCSTTIFG (0x02) /* START Condition interrupt Flag */
|
|
|
1416 |
#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */
|
|
|
1417 |
|
|
|
1418 |
#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
|
|
|
1419 |
#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
|
|
|
1420 |
#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
|
|
|
1421 |
#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
|
|
|
1422 |
#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
|
|
|
1423 |
#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
|
|
|
1424 |
#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
|
|
|
1425 |
#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
|
|
|
1426 |
|
|
|
1427 |
#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
|
|
|
1428 |
#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
|
|
|
1429 |
#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
|
|
|
1430 |
#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
|
|
|
1431 |
#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
|
|
|
1432 |
#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
|
|
|
1433 |
#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
|
|
|
1434 |
#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
|
|
|
1435 |
|
|
|
1436 |
//#define res (0x80) /* reserved */
|
|
|
1437 |
//#define res (0x40) /* reserved */
|
|
|
1438 |
#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
|
|
|
1439 |
#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
|
|
|
1440 |
#define UCSTOE (0x08) /* Sync-Field Timeout error */
|
|
|
1441 |
#define UCBTOE (0x04) /* Break Timeout error */
|
|
|
1442 |
//#define res (0x02) /* reserved */
|
|
|
1443 |
#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
|
|
|
1444 |
|
|
|
1445 |
#define UCGCEN (0x8000) /* I2C General Call enable */
|
|
|
1446 |
#define UCOA9 (0x0200) /* I2C Own Address 9 */
|
|
|
1447 |
#define UCOA8 (0x0100) /* I2C Own Address 8 */
|
|
|
1448 |
#define UCOA7 (0x0080) /* I2C Own Address 7 */
|
|
|
1449 |
#define UCOA6 (0x0040) /* I2C Own Address 6 */
|
|
|
1450 |
#define UCOA5 (0x0020) /* I2C Own Address 5 */
|
|
|
1451 |
#define UCOA4 (0x0010) /* I2C Own Address 4 */
|
|
|
1452 |
#define UCOA3 (0x0008) /* I2C Own Address 3 */
|
|
|
1453 |
#define UCOA2 (0x0004) /* I2C Own Address 2 */
|
|
|
1454 |
#define UCOA1 (0x0002) /* I2C Own Address 1 */
|
|
|
1455 |
#define UCOA0 (0x0001) /* I2C Own Address 0 */
|
|
|
1456 |
|
|
|
1457 |
#define UCSA9 (0x0200) /* I2C Slave Address 9 */
|
|
|
1458 |
#define UCSA8 (0x0100) /* I2C Slave Address 8 */
|
|
|
1459 |
#define UCSA7 (0x0080) /* I2C Slave Address 7 */
|
|
|
1460 |
#define UCSA6 (0x0040) /* I2C Slave Address 6 */
|
|
|
1461 |
#define UCSA5 (0x0020) /* I2C Slave Address 5 */
|
|
|
1462 |
#define UCSA4 (0x0010) /* I2C Slave Address 4 */
|
|
|
1463 |
#define UCSA3 (0x0008) /* I2C Slave Address 3 */
|
|
|
1464 |
#define UCSA2 (0x0004) /* I2C Slave Address 2 */
|
|
|
1465 |
#define UCSA1 (0x0002) /* I2C Slave Address 1 */
|
|
|
1466 |
#define UCSA0 (0x0001) /* I2C Slave Address 0 */
|
|
|
1467 |
|
|
|
1468 |
/************************************************************
|
|
|
1469 |
* WATCHDOG TIMER
|
|
|
1470 |
************************************************************/
|
|
|
1471 |
#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
|
|
|
1472 |
|
|
|
1473 |
SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
|
|
|
1474 |
/* The bit names have been prefixed with "WDT" */
|
|
|
1475 |
#define WDTIS0 (0x0001)
|
|
|
1476 |
#define WDTIS1 (0x0002)
|
|
|
1477 |
#define WDTSSEL (0x0004)
|
|
|
1478 |
#define WDTCNTCL (0x0008)
|
|
|
1479 |
#define WDTTMSEL (0x0010)
|
|
|
1480 |
#define WDTNMI (0x0020)
|
|
|
1481 |
#define WDTNMIES (0x0040)
|
|
|
1482 |
#define WDTHOLD (0x0080)
|
|
|
1483 |
|
|
|
1484 |
#define WDTPW (0x5A00)
|
|
|
1485 |
|
|
|
1486 |
/* WDT-interval times [1ms] coded with Bits 0-2 */
|
|
|
1487 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
1488 |
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
|
|
|
1489 |
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
|
|
|
1490 |
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
|
|
|
1491 |
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
1492 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
1493 |
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
|
|
|
1494 |
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
|
|
|
1495 |
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
|
|
|
1496 |
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
1497 |
/* Watchdog mode -> reset after expired time */
|
|
|
1498 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
1499 |
#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
|
|
|
1500 |
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
|
|
|
1501 |
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
|
|
|
1502 |
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
1503 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
1504 |
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
|
|
|
1505 |
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
|
|
|
1506 |
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
|
|
|
1507 |
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
1508 |
|
|
|
1509 |
/* INTERRUPT CONTROL */
|
|
|
1510 |
/* These two bits are defined in the Special Function Registers */
|
|
|
1511 |
/* #define WDTIE 0x01 */
|
|
|
1512 |
/* #define WDTIFG 0x01 */
|
|
|
1513 |
|
|
|
1514 |
/************************************************************
|
|
|
1515 |
* Interrupt Vectors (offset from 0xFFC0)
|
|
|
1516 |
************************************************************/
|
|
|
1517 |
|
|
|
1518 |
#pragma diag_suppress 1107
|
|
|
1519 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
1520 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
1521 |
#define CREATE_VECTOR(name) void * const VECTOR_NAME(name) = (void *)(long)&name
|
|
|
1522 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
1523 |
#define PLACE_INTERRUPT(func) EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
|
|
|
1524 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
1525 |
PLACE_VECTOR(VECTOR_NAME(func), offset) \
|
|
|
1526 |
PLACE_INTERRUPT(func)
|
|
|
1527 |
|
|
|
1528 |
|
|
|
1529 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1530 |
#define DMA_VECTOR ".int15" /* 0xFFDE DMA */
|
|
|
1531 |
#else
|
|
|
1532 |
#define DMA_VECTOR (15 * 1u) /* 0xFFDE DMA */
|
|
|
1533 |
/*#define DMA_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFDE DMA */ /* CCE V2 Style */
|
|
|
1534 |
#endif
|
|
|
1535 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1536 |
#define BASICTIMER_VECTOR ".int16" /* 0xFFE0 Basic Timer / RTC */
|
|
|
1537 |
#else
|
|
|
1538 |
#define BASICTIMER_VECTOR (16 * 1u) /* 0xFFE0 Basic Timer / RTC */
|
|
|
1539 |
/*#define BASICTIMER_ISR(func) ISR_VECTOR(func, ".int16") */ /* 0xFFE0 Basic Timer / RTC */ /* CCE V2 Style */
|
|
|
1540 |
#endif
|
|
|
1541 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1542 |
#define PORT2_VECTOR ".int17" /* 0xFFE2 Port 2 */
|
|
|
1543 |
#else
|
|
|
1544 |
#define PORT2_VECTOR (17 * 1u) /* 0xFFE2 Port 2 */
|
|
|
1545 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int17") */ /* 0xFFE2 Port 2 */ /* CCE V2 Style */
|
|
|
1546 |
#endif
|
|
|
1547 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1548 |
#define USCIAB1TX_VECTOR ".int18" /* 0xFFE4 USCI A1/B1 Transmit */
|
|
|
1549 |
#else
|
|
|
1550 |
#define USCIAB1TX_VECTOR (18 * 1u) /* 0xFFE4 USCI A1/B1 Transmit */
|
|
|
1551 |
/*#define USCIAB1TX_ISR(func) ISR_VECTOR(func, ".int18") */ /* 0xFFE4 USCI A1/B1 Transmit */ /* CCE V2 Style */
|
|
|
1552 |
#endif
|
|
|
1553 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1554 |
#define USCIAB1RX_VECTOR ".int19" /* 0xFFE6 USCI A1/B1 Receive */
|
|
|
1555 |
#else
|
|
|
1556 |
#define USCIAB1RX_VECTOR (19 * 1u) /* 0xFFE6 USCI A1/B1 Receive */
|
|
|
1557 |
/*#define USCIAB1RX_ISR(func) ISR_VECTOR(func, ".int19") */ /* 0xFFE6 USCI A1/B1 Receive */ /* CCE V2 Style */
|
|
|
1558 |
#endif
|
|
|
1559 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1560 |
#define PORT1_VECTOR ".int20" /* 0xFFE8 Port 1 */
|
|
|
1561 |
#else
|
|
|
1562 |
#define PORT1_VECTOR (20 * 1u) /* 0xFFE8 Port 1 */
|
|
|
1563 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int20") */ /* 0xFFE8 Port 1 */ /* CCE V2 Style */
|
|
|
1564 |
#endif
|
|
|
1565 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1566 |
#define TIMERA1_VECTOR ".int21" /* 0xFFEA Timer A CC1-2, TA */
|
|
|
1567 |
#else
|
|
|
1568 |
#define TIMERA1_VECTOR (21 * 1u) /* 0xFFEA Timer A CC1-2, TA */
|
|
|
1569 |
/*#define TIMERA1_ISR(func) ISR_VECTOR(func, ".int21") */ /* 0xFFEA Timer A CC1-2, TA */ /* CCE V2 Style */
|
|
|
1570 |
#endif
|
|
|
1571 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1572 |
#define TIMERA0_VECTOR ".int22" /* 0xFFEC Timer A CC0 */
|
|
|
1573 |
#else
|
|
|
1574 |
#define TIMERA0_VECTOR (22 * 1u) /* 0xFFEC Timer A CC0 */
|
|
|
1575 |
/*#define TIMERA0_ISR(func) ISR_VECTOR(func, ".int22") */ /* 0xFFEC Timer A CC0 */ /* CCE V2 Style */
|
|
|
1576 |
#endif
|
|
|
1577 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1578 |
#define SD16A_VECTOR ".int23" /* 0xFFEE ADC */
|
|
|
1579 |
#else
|
|
|
1580 |
#define SD16A_VECTOR (23 * 1u) /* 0xFFEE ADC */
|
|
|
1581 |
/*#define SD16A_ISR(func) ISR_VECTOR(func, ".int23") */ /* 0xFFEE ADC */ /* CCE V2 Style */
|
|
|
1582 |
#endif
|
|
|
1583 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1584 |
#define USCIAB0TX_VECTOR ".int24" /* 0xFFF0 USCI A0/B0 Transmit */
|
|
|
1585 |
#else
|
|
|
1586 |
#define USCIAB0TX_VECTOR (24 * 1u) /* 0xFFF0 USCI A0/B0 Transmit */
|
|
|
1587 |
/*#define USCIAB0TX_ISR(func) ISR_VECTOR(func, ".int24") */ /* 0xFFF0 USCI A0/B0 Transmit */ /* CCE V2 Style */
|
|
|
1588 |
#endif
|
|
|
1589 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1590 |
#define USCIAB0RX_VECTOR ".int25" /* 0xFFF2 USCI A0/B0 Receive */
|
|
|
1591 |
#else
|
|
|
1592 |
#define USCIAB0RX_VECTOR (25 * 1u) /* 0xFFF2 USCI A0/B0 Receive */
|
|
|
1593 |
/*#define USCIAB0RX_ISR(func) ISR_VECTOR(func, ".int25") */ /* 0xFFF2 USCI A0/B0 Receive */ /* CCE V2 Style */
|
|
|
1594 |
#endif
|
|
|
1595 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1596 |
#define WDT_VECTOR ".int26" /* 0xFFF4 Watchdog Timer */
|
|
|
1597 |
#else
|
|
|
1598 |
#define WDT_VECTOR (26 * 1u) /* 0xFFF4 Watchdog Timer */
|
|
|
1599 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int26") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
|
|
|
1600 |
#endif
|
|
|
1601 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1602 |
#define COMPARATORA_VECTOR ".int27" /* 0xFFF6 Comparator A */
|
|
|
1603 |
#else
|
|
|
1604 |
#define COMPARATORA_VECTOR (27 * 1u) /* 0xFFF6 Comparator A */
|
|
|
1605 |
/*#define COMPARATORA_ISR(func) ISR_VECTOR(func, ".int27") */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */
|
|
|
1606 |
#endif
|
|
|
1607 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1608 |
#define TIMERB1_VECTOR ".int28" /* 0xFFF8 Timer B CC1-2, TB */
|
|
|
1609 |
#else
|
|
|
1610 |
#define TIMERB1_VECTOR (28 * 1u) /* 0xFFF8 Timer B CC1-2, TB */
|
|
|
1611 |
/*#define TIMERB1_ISR(func) ISR_VECTOR(func, ".int28") */ /* 0xFFF8 Timer B CC1-2, TB */ /* CCE V2 Style */
|
|
|
1612 |
#endif
|
|
|
1613 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1614 |
#define TIMERB0_VECTOR ".int29" /* 0xFFFA Timer B CC0 */
|
|
|
1615 |
#else
|
|
|
1616 |
#define TIMERB0_VECTOR (29 * 1u) /* 0xFFFA Timer B CC0 */
|
|
|
1617 |
/*#define TIMERB0_ISR(func) ISR_VECTOR(func, ".int29") */ /* 0xFFFA Timer B CC0 */ /* CCE V2 Style */
|
|
|
1618 |
#endif
|
|
|
1619 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1620 |
#define NMI_VECTOR ".int30" /* 0xFFFC Non-maskable */
|
|
|
1621 |
#else
|
|
|
1622 |
#define NMI_VECTOR (30 * 1u) /* 0xFFFC Non-maskable */
|
|
|
1623 |
/*#define NMI_ISR(func) ISR_VECTOR(func, ".int30") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
|
|
|
1624 |
#endif
|
|
|
1625 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
1626 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
1627 |
#else
|
|
|
1628 |
#define RESET_VECTOR (31 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
1629 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int31") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
1630 |
#endif
|
|
|
1631 |
|
|
|
1632 |
/************************************************************
|
|
|
1633 |
* End of Modules
|
|
|
1634 |
************************************************************/
|
|
|
1635 |
|
|
|
1636 |
#ifdef __cplusplus
|
|
|
1637 |
}
|
|
|
1638 |
#endif /* extern "C" */
|
|
|
1639 |
|
|
|
1640 |
#endif /* #ifndef __msp430x471x6 */
|
|
|
1641 |
|