WebSVN – DevTools – Blame – /TexasInstrumentsMsp430/trunk/src/ccsv4/msp430/include/msp430f2617.h

Rev	Author	Line No.	Line
2850	dpurdie	1	`/********************************************************************`
		2	`*`
		3	`* Standard register and bit definitions for the Texas Instruments`
		4	`* MSP430 microcontroller.`
		5	`*`
		6	`* This file supports assembler and C development for`
		7	`* MSP430x26x devices.`
		8	`*`
		9	`* Texas Instruments, Version 1.5`
		10	`*`
		11	`* Rev. 1.0, Initial Version`
		12	`* Rev. 1.1, changed PAREN from sfrb to sfrw`
		13	`* Rev. 1.2 added TLV in INFO Memory`
		14	`* Rev. 1.3, added definitions for Interrupt Vectors xxIV`
		15	`* Rev. 1.4, changed 'void __data20 * volatile' definition`
		16	`* Rev. 1.5, fixed define: TAG_ADC12_1 to 0x08`
		17	`*`
		18	`********************************************************************/`
		19
		20	`#ifndef __msp430x26x`
		21	`#define __msp430x26x`
		22
		23	`#ifdef __cplusplus`
		24	`extern "C" {`
		25	`#endif`
		26
		27
		28	`/----------------------------------------------------------------------------/`
		29	`/* PERIPHERAL FILE MAP */`
		30	`/----------------------------------------------------------------------------/`
		31
		32	`/* External references resolved by a device-specific linker command file */`
		33	`#define SFR_8BIT(address) extern volatile unsigned char address`
		34	`#define SFR_16BIT(address) extern volatile unsigned int address`
		35	`//#define SFR_20BIT(address) extern volatile unsigned int address`
		36	`typedef void (* __SFR_FARPTR)();`
		37	`#define SFR_20BIT(address) extern __SFR_FARPTR address`
		38	`#define SFR_32BIT(address) extern volatile unsigned long address`
		39
		40
		41
		42	`/************************************************************`
		43	`* STANDARD BITS`
		44	`************************************************************/`
		45
		46	`#define BIT0 (0x0001)`
		47	`#define BIT1 (0x0002)`
		48	`#define BIT2 (0x0004)`
		49	`#define BIT3 (0x0008)`
		50	`#define BIT4 (0x0010)`
		51	`#define BIT5 (0x0020)`
		52	`#define BIT6 (0x0040)`
		53	`#define BIT7 (0x0080)`
		54	`#define BIT8 (0x0100)`
		55	`#define BIT9 (0x0200)`
		56	`#define BITA (0x0400)`
		57	`#define BITB (0x0800)`
		58	`#define BITC (0x1000)`
		59	`#define BITD (0x2000)`
		60	`#define BITE (0x4000)`
		61	`#define BITF (0x8000)`
		62
		63	`/************************************************************`
		64	`* STATUS REGISTER BITS`
		65	`************************************************************/`
		66
		67	`#define C (0x0001)`
		68	`#define Z (0x0002)`
		69	`#define N (0x0004)`
		70	`#define V (0x0100)`
		71	`#define GIE (0x0008)`
		72	`#define CPUOFF (0x0010)`
		73	`#define OSCOFF (0x0020)`
		74	`#define SCG0 (0x0040)`
		75	`#define SCG1 (0x0080)`
		76
		77	`/* Low Power Modes coded with Bits 4-7 in SR */`
		78
		79	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		80	`#define LPM0 (CPUOFF)`
		81	`#define LPM1 (SCG0+CPUOFF)`
		82	`#define LPM2 (SCG1+CPUOFF)`
		83	`#define LPM3 (SCG1+SCG0+CPUOFF)`
		84	`#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)`
		85	`/* End #defines for assembler */`
		86
		87	`#else /* Begin #defines for C */`
		88	`#define LPM0_bits (CPUOFF)`
		89	`#define LPM1_bits (SCG0+CPUOFF)`
		90	`#define LPM2_bits (SCG1+CPUOFF)`
		91	`#define LPM3_bits (SCG1+SCG0+CPUOFF)`
		92	`#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)`
		93
		94	`#include "in430.h"`
		95
		96	`#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */`
		97	`#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */`
		98	`#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */`
		99	`#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */`
		100	`#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */`
		101	`#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */`
		102	`#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */`
		103	`#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */`
		104	`#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */`
		105	`#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */`
		106	`#endif /* End #defines for C */`
		107
		108	`/************************************************************`
		109	`* CPU`
		110	`************************************************************/`
		111	`#define __MSP430_HAS_MSP430X_CPU__ /* Definition to show that it has MSP430X CPU */`
		112
		113	`/************************************************************`
		114	`* PERIPHERAL FILE MAP`
		115	`************************************************************/`
		116
		117	`/************************************************************`
		118	`* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS`
		119	`************************************************************/`
		120
		121	`SFR_8BIT(IE1); /* Interrupt Enable 1 */`
		122	`#define WDTIE (0x01) /* Watchdog Interrupt Enable */`
		123	`#define OFIE (0x02) /* Osc. Fault Interrupt Enable */`
		124	`#define NMIIE (0x10) /* NMI Interrupt Enable */`
		125	`#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */`
		126
		127	`SFR_8BIT(IFG1); /* Interrupt Flag 1 */`
		128	`#define WDTIFG (0x01) /* Watchdog Interrupt Flag */`
		129	`#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */`
		130	`#define PORIFG (0x04) /* Power On Interrupt Flag */`
		131	`#define RSTIFG (0x08) /* Reset Interrupt Flag */`
		132	`#define NMIIFG (0x10) /* NMI Interrupt Flag */`
		133
		134	`SFR_8BIT(IE2); /* Interrupt Enable 2 */`
		135	`#define UC0IE IE2`
		136	`#define UCA0RXIE (0x01)`
		137	`#define UCA0TXIE (0x02)`
		138	`#define UCB0RXIE (0x04)`
		139	`#define UCB0TXIE (0x08)`
		140
		141	`SFR_8BIT(IFG2); /* Interrupt Flag 2 */`
		142	`#define UC0IFG IFG2`
		143	`#define UCA0RXIFG (0x01)`
		144	`#define UCA0TXIFG (0x02)`
		145	`#define UCB0RXIFG (0x04)`
		146	`#define UCB0TXIFG (0x08)`
		147
		148	`SFR_8BIT(UC1IE); /* USCI 1 Interrupt Enable */`
		149	`#define UCA1RXIE (0x01)`
		150	`#define UCA1TXIE (0x02)`
		151	`#define UCB1RXIE (0x04)`
		152	`#define UCB1TXIE (0x08)`
		153
		154	`SFR_8BIT(UC1IFG); /* ISCI 1 Interrupt Flags */`
		155	`#define UCA1RXIFG (0x01)`
		156	`#define UCA1TXIFG (0x02)`
		157	`#define UCB1RXIFG (0x04)`
		158	`#define UCB1TXIFG (0x08)`
		159
		160	`/************************************************************`
		161	`* ADC12`
		162	`************************************************************/`
		163	`#define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */`
		164
		165	`SFR_16BIT(ADC12CTL0); /* ADC12 Control 0 */`
		166	`SFR_16BIT(ADC12CTL1); /* ADC12 Control 1 */`
		167	`SFR_16BIT(ADC12IFG); /* ADC12 Interrupt Flag */`
		168	`SFR_16BIT(ADC12IE); /* ADC12 Interrupt Enable */`
		169	`SFR_16BIT(ADC12IV); /* ADC12 Interrupt Vector Word */`
		170
		171	`#define ADC12MEM_ (0x0140) /* ADC12 Conversion Memory */`
		172	`#ifdef __ASM_HEADER__`
		173	`#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */`
		174	`#else`
		175	`#define ADC12MEM ((int) ADC12MEM_) / ADC12 Conversion Memory (for C) */`
		176	`#endif`
		177	`SFR_16BIT(ADC12MEM0); /* ADC12 Conversion Memory 0 */`
		178	`SFR_16BIT(ADC12MEM1); /* ADC12 Conversion Memory 1 */`
		179	`SFR_16BIT(ADC12MEM2); /* ADC12 Conversion Memory 2 */`
		180	`SFR_16BIT(ADC12MEM3); /* ADC12 Conversion Memory 3 */`
		181	`SFR_16BIT(ADC12MEM4); /* ADC12 Conversion Memory 4 */`
		182	`SFR_16BIT(ADC12MEM5); /* ADC12 Conversion Memory 5 */`
		183	`SFR_16BIT(ADC12MEM6); /* ADC12 Conversion Memory 6 */`
		184	`SFR_16BIT(ADC12MEM7); /* ADC12 Conversion Memory 7 */`
		185	`SFR_16BIT(ADC12MEM8); /* ADC12 Conversion Memory 8 */`
		186	`SFR_16BIT(ADC12MEM9); /* ADC12 Conversion Memory 9 */`
		187	`SFR_16BIT(ADC12MEM10); /* ADC12 Conversion Memory 10 */`
		188	`SFR_16BIT(ADC12MEM11); /* ADC12 Conversion Memory 11 */`
		189	`SFR_16BIT(ADC12MEM12); /* ADC12 Conversion Memory 12 */`
		190	`SFR_16BIT(ADC12MEM13); /* ADC12 Conversion Memory 13 */`
		191	`SFR_16BIT(ADC12MEM14); /* ADC12 Conversion Memory 14 */`
		192	`SFR_16BIT(ADC12MEM15); /* ADC12 Conversion Memory 15 */`
		193
		194	`#define ADC12MCTL_ (0x0080) /* ADC12 Memory Control */`
		195	`#ifdef __ASM_HEADER__`
		196	`#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */`
		197	`#else`
		198	`#define ADC12MCTL ((char) ADC12MCTL_) / ADC12 Memory Control (for C) */`
		199	`#endif`
		200	`SFR_8BIT(ADC12MCTL0); /* ADC12 Memory Control 0 */`
		201	`SFR_8BIT(ADC12MCTL1); /* ADC12 Memory Control 1 */`
		202	`SFR_8BIT(ADC12MCTL2); /* ADC12 Memory Control 2 */`
		203	`SFR_8BIT(ADC12MCTL3); /* ADC12 Memory Control 3 */`
		204	`SFR_8BIT(ADC12MCTL4); /* ADC12 Memory Control 4 */`
		205	`SFR_8BIT(ADC12MCTL5); /* ADC12 Memory Control 5 */`
		206	`SFR_8BIT(ADC12MCTL6); /* ADC12 Memory Control 6 */`
		207	`SFR_8BIT(ADC12MCTL7); /* ADC12 Memory Control 7 */`
		208	`SFR_8BIT(ADC12MCTL8); /* ADC12 Memory Control 8 */`
		209	`SFR_8BIT(ADC12MCTL9); /* ADC12 Memory Control 9 */`
		210	`SFR_8BIT(ADC12MCTL10); /* ADC12 Memory Control 10 */`
		211	`SFR_8BIT(ADC12MCTL11); /* ADC12 Memory Control 11 */`
		212	`SFR_8BIT(ADC12MCTL12); /* ADC12 Memory Control 12 */`
		213	`SFR_8BIT(ADC12MCTL13); /* ADC12 Memory Control 13 */`
		214	`SFR_8BIT(ADC12MCTL14); /* ADC12 Memory Control 14 */`
		215	`SFR_8BIT(ADC12MCTL15); /* ADC12 Memory Control 15 */`
		216
		217	`/* ADC12CTL0 */`
		218	`#define ADC12SC (0x001) /* ADC12 Start Conversion */`
		219	`#define ENC (0x002) /* ADC12 Enable Conversion */`
		220	`#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */`
		221	`#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */`
		222	`#define ADC12ON (0x010) /* ADC12 On/enable */`
		223	`#define REFON (0x020) /* ADC12 Reference on */`
		224	`#define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */`
		225	`#define MSC (0x080) /* ADC12 Multiple SampleConversion */`
		226	`#define SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */`
		227	`#define SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */`
		228	`#define SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */`
		229	`#define SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */`
		230	`#define SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */`
		231	`#define SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */`
		232	`#define SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */`
		233	`#define SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */`
		234	`#define MSH (0x080)`
		235
		236	`#define SHT0_0 (00x100u) / ADC12 Sample Hold 0 Select Bit: 0 */`
		237	`#define SHT0_1 (10x100u) / ADC12 Sample Hold 0 Select Bit: 1 */`
		238	`#define SHT0_2 (20x100u) / ADC12 Sample Hold 0 Select Bit: 2 */`
		239	`#define SHT0_3 (30x100u) / ADC12 Sample Hold 0 Select Bit: 3 */`
		240	`#define SHT0_4 (40x100u) / ADC12 Sample Hold 0 Select Bit: 4 */`
		241	`#define SHT0_5 (50x100u) / ADC12 Sample Hold 0 Select Bit: 5 */`
		242	`#define SHT0_6 (60x100u) / ADC12 Sample Hold 0 Select Bit: 6 */`
		243	`#define SHT0_7 (70x100u) / ADC12 Sample Hold 0 Select Bit: 7 */`
		244	`#define SHT0_8 (80x100u) / ADC12 Sample Hold 0 Select Bit: 8 */`
		245	`#define SHT0_9 (90x100u) / ADC12 Sample Hold 0 Select Bit: 9 */`
		246	`#define SHT0_10 (100x100u) / ADC12 Sample Hold 0 Select Bit: 10 */`
		247	`#define SHT0_11 (110x100u) / ADC12 Sample Hold 0 Select Bit: 11 */`
		248	`#define SHT0_12 (120x100u) / ADC12 Sample Hold 0 Select Bit: 12 */`
		249	`#define SHT0_13 (130x100u) / ADC12 Sample Hold 0 Select Bit: 13 */`
		250	`#define SHT0_14 (140x100u) / ADC12 Sample Hold 0 Select Bit: 14 */`
		251	`#define SHT0_15 (150x100u) / ADC12 Sample Hold 0 Select Bit: 15 */`
		252
		253	`#define SHT1_0 (00x1000u) / ADC12 Sample Hold 1 Select Bit: 0 */`
		254	`#define SHT1_1 (10x1000u) / ADC12 Sample Hold 1 Select Bit: 1 */`
		255	`#define SHT1_2 (20x1000u) / ADC12 Sample Hold 1 Select Bit: 2 */`
		256	`#define SHT1_3 (30x1000u) / ADC12 Sample Hold 1 Select Bit: 3 */`
		257	`#define SHT1_4 (40x1000u) / ADC12 Sample Hold 1 Select Bit: 4 */`
		258	`#define SHT1_5 (50x1000u) / ADC12 Sample Hold 1 Select Bit: 5 */`
		259	`#define SHT1_6 (60x1000u) / ADC12 Sample Hold 1 Select Bit: 6 */`
		260	`#define SHT1_7 (70x1000u) / ADC12 Sample Hold 1 Select Bit: 7 */`
		261	`#define SHT1_8 (80x1000u) / ADC12 Sample Hold 1 Select Bit: 8 */`
		262	`#define SHT1_9 (90x1000u) / ADC12 Sample Hold 1 Select Bit: 9 */`
		263	`#define SHT1_10 (100x1000u) / ADC12 Sample Hold 1 Select Bit: 10 */`
		264	`#define SHT1_11 (110x1000u) / ADC12 Sample Hold 1 Select Bit: 11 */`
		265	`#define SHT1_12 (120x1000u) / ADC12 Sample Hold 1 Select Bit: 12 */`
		266	`#define SHT1_13 (130x1000u) / ADC12 Sample Hold 1 Select Bit: 13 */`
		267	`#define SHT1_14 (140x1000u) / ADC12 Sample Hold 1 Select Bit: 14 */`
		268	`#define SHT1_15 (150x1000u) / ADC12 Sample Hold 1 Select Bit: 15 */`
		269
		270	`/* ADC12CTL1 */`
		271	`#define ADC12BUSY (0x0001) /* ADC12 Busy */`
		272	`#define CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */`
		273	`#define CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */`
		274	`#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */`
		275	`#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */`
		276	`#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */`
		277	`#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */`
		278	`#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */`
		279	`#define ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */`
		280	`#define SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */`
		281	`#define SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */`
		282	`#define SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */`
		283	`#define CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */`
		284	`#define CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */`
		285	`#define CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */`
		286	`#define CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */`
		287
		288	`#define CONSEQ_0 (02u) / ADC12 Conversion Sequence Select: 0 */`
		289	`#define CONSEQ_1 (12u) / ADC12 Conversion Sequence Select: 1 */`
		290	`#define CONSEQ_2 (22u) / ADC12 Conversion Sequence Select: 2 */`
		291	`#define CONSEQ_3 (32u) / ADC12 Conversion Sequence Select: 3 */`
		292	`#define ADC12SSEL_0 (08u) / ADC12 Clock Source Select: 0 */`
		293	`#define ADC12SSEL_1 (18u) / ADC12 Clock Source Select: 1 */`
		294	`#define ADC12SSEL_2 (28u) / ADC12 Clock Source Select: 2 */`
		295	`#define ADC12SSEL_3 (38u) / ADC12 Clock Source Select: 3 */`
		296	`#define ADC12DIV_0 (00x20u) / ADC12 Clock Divider Select: 0 */`
		297	`#define ADC12DIV_1 (10x20u) / ADC12 Clock Divider Select: 1 */`
		298	`#define ADC12DIV_2 (20x20u) / ADC12 Clock Divider Select: 2 */`
		299	`#define ADC12DIV_3 (30x20u) / ADC12 Clock Divider Select: 3 */`
		300	`#define ADC12DIV_4 (40x20u) / ADC12 Clock Divider Select: 4 */`
		301	`#define ADC12DIV_5 (50x20u) / ADC12 Clock Divider Select: 5 */`
		302	`#define ADC12DIV_6 (60x20u) / ADC12 Clock Divider Select: 6 */`
		303	`#define ADC12DIV_7 (70x20u) / ADC12 Clock Divider Select: 7 */`
		304	`#define SHS_0 (00x400u) / ADC12 Sample/Hold Source: 0 */`
		305	`#define SHS_1 (10x400u) / ADC12 Sample/Hold Source: 1 */`
		306	`#define SHS_2 (20x400u) / ADC12 Sample/Hold Source: 2 */`
		307	`#define SHS_3 (30x400u) / ADC12 Sample/Hold Source: 3 */`
		308	`#define CSTARTADD_0 (00x1000u) / ADC12 Conversion Start Address: 0 */`
		309	`#define CSTARTADD_1 (10x1000u) / ADC12 Conversion Start Address: 1 */`
		310	`#define CSTARTADD_2 (20x1000u) / ADC12 Conversion Start Address: 2 */`
		311	`#define CSTARTADD_3 (30x1000u) / ADC12 Conversion Start Address: 3 */`
		312	`#define CSTARTADD_4 (40x1000u) / ADC12 Conversion Start Address: 4 */`
		313	`#define CSTARTADD_5 (50x1000u) / ADC12 Conversion Start Address: 5 */`
		314	`#define CSTARTADD_6 (60x1000u) / ADC12 Conversion Start Address: 6 */`
		315	`#define CSTARTADD_7 (70x1000u) / ADC12 Conversion Start Address: 7 */`
		316	`#define CSTARTADD_8 (80x1000u) / ADC12 Conversion Start Address: 8 */`
		317	`#define CSTARTADD_9 (90x1000u) / ADC12 Conversion Start Address: 9 */`
		318	`#define CSTARTADD_10 (100x1000u) / ADC12 Conversion Start Address: 10 */`
		319	`#define CSTARTADD_11 (110x1000u) / ADC12 Conversion Start Address: 11 */`
		320	`#define CSTARTADD_12 (120x1000u) / ADC12 Conversion Start Address: 12 */`
		321	`#define CSTARTADD_13 (130x1000u) / ADC12 Conversion Start Address: 13 */`
		322	`#define CSTARTADD_14 (140x1000u) / ADC12 Conversion Start Address: 14 */`
		323	`#define CSTARTADD_15 (150x1000u) / ADC12 Conversion Start Address: 15 */`
		324
		325	`/* ADC12MCTLx */`
		326	`#define INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */`
		327	`#define INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */`
		328	`#define INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */`
		329	`#define INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */`
		330	`#define SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */`
		331	`#define SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */`
		332	`#define SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */`
		333	`#define EOS (0x0080) /* ADC12 End of Sequence */`
		334
		335	`#define INCH_0 (0) /* ADC12 Input Channel 0 */`
		336	`#define INCH_1 (1) /* ADC12 Input Channel 1 */`
		337	`#define INCH_2 (2) /* ADC12 Input Channel 2 */`
		338	`#define INCH_3 (3) /* ADC12 Input Channel 3 */`
		339	`#define INCH_4 (4) /* ADC12 Input Channel 4 */`
		340	`#define INCH_5 (5) /* ADC12 Input Channel 5 */`
		341	`#define INCH_6 (6) /* ADC12 Input Channel 6 */`
		342	`#define INCH_7 (7) /* ADC12 Input Channel 7 */`
		343	`#define INCH_8 (8) /* ADC12 Input Channel 8 */`
		344	`#define INCH_9 (9) /* ADC12 Input Channel 9 */`
		345	`#define INCH_10 (10) /* ADC12 Input Channel 10 */`
		346	`#define INCH_11 (11) /* ADC12 Input Channel 11 */`
		347	`#define INCH_12 (12) /* ADC12 Input Channel 12 */`
		348	`#define INCH_13 (13) /* ADC12 Input Channel 13 */`
		349	`#define INCH_14 (14) /* ADC12 Input Channel 14 */`
		350	`#define INCH_15 (15) /* ADC12 Input Channel 15 */`
		351
		352	`#define SREF_0 (00x10u) / ADC12 Select Reference 0 */`
		353	`#define SREF_1 (10x10u) / ADC12 Select Reference 1 */`
		354	`#define SREF_2 (20x10u) / ADC12 Select Reference 2 */`
		355	`#define SREF_3 (30x10u) / ADC12 Select Reference 3 */`
		356	`#define SREF_4 (40x10u) / ADC12 Select Reference 4 */`
		357	`#define SREF_5 (50x10u) / ADC12 Select Reference 5 */`
		358	`#define SREF_6 (60x10u) / ADC12 Select Reference 6 */`
		359	`#define SREF_7 (70x10u) / ADC12 Select Reference 7 */`
		360
		361	`/* ADC12IV Definitions */`
		362	`#define ADC12IV_NONE (0x0000) /* No Interrupt pending */`
		363	`#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */`
		364	`#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */`
		365	`#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */`
		366	`#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */`
		367	`#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */`
		368	`#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */`
		369	`#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */`
		370	`#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */`
		371	`#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */`
		372	`#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */`
		373	`#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */`
		374	`#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */`
		375	`#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */`
		376	`#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */`
		377	`#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */`
		378	`#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */`
		379	`#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */`
		380	`#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */`
		381
		382	`/************************************************************`
		383	`* Basic Clock Module`
		384	`************************************************************/`
		385	`#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */`
		386
		387	`SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */`
		388	`SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */`
		389	`SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */`
		390	`SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */`
		391
		392	`#define MOD0 (0x01) /* Modulation Bit 0 */`
		393	`#define MOD1 (0x02) /* Modulation Bit 1 */`
		394	`#define MOD2 (0x04) /* Modulation Bit 2 */`
		395	`#define MOD3 (0x08) /* Modulation Bit 3 */`
		396	`#define MOD4 (0x10) /* Modulation Bit 4 */`
		397	`#define DCO0 (0x20) /* DCO Select Bit 0 */`
		398	`#define DCO1 (0x40) /* DCO Select Bit 1 */`
		399	`#define DCO2 (0x80) /* DCO Select Bit 2 */`
		400
		401	`#define RSEL0 (0x01) /* Range Select Bit 0 */`
		402	`#define RSEL1 (0x02) /* Range Select Bit 1 */`
		403	`#define RSEL2 (0x04) /* Range Select Bit 2 */`
		404	`#define RSEL3 (0x08) /* Range Select Bit 3 */`
		405	`#define DIVA0 (0x10) /* ACLK Divider 0 */`
		406	`#define DIVA1 (0x20) /* ACLK Divider 1 */`
		407	`#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */`
		408	`#define XT2OFF (0x80) /* Enable XT2CLK */`
		409
		410	`#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */`
		411	`#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */`
		412	`#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */`
		413	`#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */`
		414
		415	`#define DCOR (0x01) /* Enable External Resistor : 1 */`
		416	`#define DIVS0 (0x02) /* SMCLK Divider 0 */`
		417	`#define DIVS1 (0x04) /* SMCLK Divider 1 */`
		418	`#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */`
		419	`#define DIVM0 (0x10) /* MCLK Divider 0 */`
		420	`#define DIVM1 (0x20) /* MCLK Divider 1 */`
		421	`#define SELM0 (0x40) /* MCLK Source Select 0 */`
		422	`#define SELM1 (0x80) /* MCLK Source Select 1 */`
		423
		424	`#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */`
		425	`#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */`
		426	`#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */`
		427	`#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */`
		428
		429	`#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */`
		430	`#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */`
		431	`#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */`
		432	`#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */`
		433
		434	`#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */`
		435	`#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */`
		436	`#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */`
		437	`#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */`
		438
		439	`#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */`
		440	`#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */`
		441	`#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */`
		442	`#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */`
		443	`#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */`
		444	`#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */`
		445	`#define XT2S0 (0x40) /* Mode 0 for XT2 */`
		446	`#define XT2S1 (0x80) /* Mode 1 for XT2 */`
		447
		448	`#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */`
		449	`#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */`
		450	`#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */`
		451	`#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */`
		452
		453	`#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */`
		454	`#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */`
		455	`#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */`
		456	`#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */`
		457
		458	`#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */`
		459	`#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */`
		460	`#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */`
		461	`#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */`
		462
		463	`/************************************************************`
		464	`* Comparator A`
		465	`************************************************************/`
		466	`#define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */`
		467
		468	`SFR_8BIT(CACTL1); /* Comparator A Control 1 */`
		469	`SFR_8BIT(CACTL2); /* Comparator A Control 2 */`
		470	`SFR_8BIT(CAPD); /* Comparator A Port Disable */`
		471
		472	`#define CAIFG (0x01) /* Comp. A Interrupt Flag */`
		473	`#define CAIE (0x02) /* Comp. A Interrupt Enable */`
		474	`#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */`
		475	`#define CAON (0x08) /* Comp. A enable */`
		476	`#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */`
		477	`#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */`
		478	`#define CARSEL (0x40) /* Comp. A Internal Reference Enable */`
		479	`#define CAEX (0x80) /* Comp. A Exchange Inputs */`
		480
		481	`#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */`
		482	`#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25Vcc /`
		483	`#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5Vcc /`
		484	`#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/`
		485
		486	`#define CAOUT (0x01) /* Comp. A Output */`
		487	`#define CAF (0x02) /* Comp. A Enable Output Filter */`
		488	`#define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */`
		489	`#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */`
		490	`#define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */`
		491	`#define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */`
		492	`#define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */`
		493	`#define CASHORT (0x80) /* Comp. A Short + and - Terminals */`
		494
		495	`#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */`
		496	`#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */`
		497	`#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */`
		498	`#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */`
		499	`#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */`
		500	`#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */`
		501	`#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */`
		502	`#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */`
		503
		504	`/************************************************************`
		505	`* DAC12`
		506	`************************************************************/`
		507	`#define __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */`
		508
		509	`SFR_16BIT(DAC12_0CTL); /* DAC12_0 Control */`
		510	`SFR_16BIT(DAC12_1CTL); /* DAC12_1 Control */`
		511
		512	`#define DAC12GRP (0x0001) /* DAC12 group */`
		513	`#define DAC12ENC (0x0002) /* DAC12 enable conversion */`
		514	`#define DAC12IFG (0x0004) /* DAC12 interrupt flag */`
		515	`#define DAC12IE (0x0008) /* DAC12 interrupt enable */`
		516	`#define DAC12DF (0x0010) /* DAC12 data format */`
		517	`#define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */`
		518	`#define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */`
		519	`#define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */`
		520	`#define DAC12IR (0x0100) /* DAC12 input reference and output range */`
		521	`#define DAC12CALON (0x0200) /* DAC12 calibration */`
		522	`#define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */`
		523	`#define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */`
		524	`#define DAC12RES (0x1000) /* DAC12 resolution */`
		525	`#define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */`
		526	`#define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */`
		527	`#define DAC12OPS (0x8000) /* DAC12 Operation Amp. */`
		528
		529	`#define DAC12AMP_0 (00x0020u) / DAC12 amplifier 0: off, 3-state */`
		530	`#define DAC12AMP_1 (10x0020u) / DAC12 amplifier 1: off, off */`
		531	`#define DAC12AMP_2 (20x0020u) / DAC12 amplifier 2: low, low */`
		532	`#define DAC12AMP_3 (30x0020u) / DAC12 amplifier 3: low, medium */`
		533	`#define DAC12AMP_4 (40x0020u) / DAC12 amplifier 4: low, high */`
		534	`#define DAC12AMP_5 (50x0020u) / DAC12 amplifier 5: medium, medium */`
		535	`#define DAC12AMP_6 (60x0020u) / DAC12 amplifier 6: medium, high */`
		536	`#define DAC12AMP_7 (70x0020u) / DAC12 amplifier 7: high, high */`
		537
		538	`#define DAC12LSEL_0 (00x0400u) / DAC12 load select 0: direct */`
		539	`#define DAC12LSEL_1 (10x0400u) / DAC12 load select 1: latched with DAT */`
		540	`#define DAC12LSEL_2 (20x0400u) / DAC12 load select 2: latched with pos. Timer_A3.OUT1 */`
		541	`#define DAC12LSEL_3 (30x0400u) / DAC12 load select 3: latched with pos. Timer_B7.OUT1 */`
		542
		543	`#define DAC12SREF_0 (00x2000u) / DAC12 reference 0: Vref+ */`
		544	`#define DAC12SREF_1 (10x2000u) / DAC12 reference 1: Vref+ */`
		545	`#define DAC12SREF_2 (20x2000u) / DAC12 reference 2: Veref+ */`
		546	`#define DAC12SREF_3 (30x2000u) / DAC12 reference 3: Veref+ */`
		547
		548	`SFR_16BIT(DAC12_0DAT); /* DAC12_0 Data */`
		549	`SFR_16BIT(DAC12_1DAT); /* DAC12_1 Data */`
		550	`/************************************************************`
		551	`* DMA_X`
		552	`************************************************************/`
		553	`#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */`
		554
		555	`SFR_16BIT(DMACTL0); /* DMA Module Control 0 */`
		556	`#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */`
		557	`#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */`
		558	`#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */`
		559	`#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */`
		560	`#define DMA1TSEL0 (0x0010) /* DMA channel 1 transfer select bit 0 */`
		561	`#define DMA1TSEL1 (0x0020) /* DMA channel 1 transfer select bit 1 */`
		562	`#define DMA1TSEL2 (0x0040) /* DMA channel 1 transfer select bit 2 */`
		563	`#define DMA1TSEL3 (0x0080) /* DMA channel 1 transfer select bit 3 */`
		564	`#define DMA2TSEL0 (0x0100) /* DMA channel 2 transfer select bit 0 */`
		565	`#define DMA2TSEL1 (0x0200) /* DMA channel 2 transfer select bit 1 */`
		566	`#define DMA2TSEL2 (0x0400) /* DMA channel 2 transfer select bit 2 */`
		567	`#define DMA2TSEL3 (0x0800) /* DMA channel 2 transfer select bit 3 */`
		568
		569	`#define DMA0TSEL_0 (00x0001u) / DMA channel 0 transfer select 0: DMA_REQ (sw)*/`
		570	`#define DMA0TSEL_1 (10x0001u) / DMA channel 0 transfer select 1: Timer_A (TACCR2.IFG) */`
		571	`#define DMA0TSEL_2 (20x0001u) / DMA channel 0 transfer select 2: Timer_B (TBCCR2.IFG) */`
		572	`#define DMA0TSEL_3 (30x0001u) / DMA channel 0 transfer select 3: USCIA0 receive */`
		573	`#define DMA0TSEL_4 (40x0001u) / DMA channel 0 transfer select 4: USCIA0 transmit */`
		574	`#define DMA0TSEL_5 (50x0001u) / DMA channel 0 transfer select 5: DAC12_0CTL.DAC12IFG */`
		575	`#define DMA0TSEL_6 (60x0001u) / DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */`
		576	`#define DMA0TSEL_7 (70x0001u) / DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */`
		577	`#define DMA0TSEL_8 (80x0001u) / DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */`
		578	`#define DMA0TSEL_9 (90x0001u) / DMA channel 0 transfer select 9: USCIA1 receive */`
		579	`#define DMA0TSEL_10 (100x0001u) / DMA channel 0 transfer select 10: USCIA1 transmit */`
		580	`#define DMA0TSEL_11 (110x0001u) / DMA channel 0 transfer select 11: Multiplier ready */`
		581	`#define DMA0TSEL_12 (120x0001u) / DMA channel 0 transfer select 12: USCIB0 receive */`
		582	`#define DMA0TSEL_13 (130x0001u) / DMA channel 0 transfer select 13: USCIB0 transmit */`
		583	`#define DMA0TSEL_14 (140x0001u) / DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */`
		584	`#define DMA0TSEL_15 (150x0001u) / DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */`
		585
		586	`#define DMA1TSEL_0 (00x0010u) / DMA channel 1 transfer select 0: DMA_REQ */`
		587	`#define DMA1TSEL_1 (10x0010u) / DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */`
		588	`#define DMA1TSEL_2 (20x0010u) / DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */`
		589	`#define DMA1TSEL_3 (30x0010u) / DMA channel 1 transfer select 3: USCIA0 receive */`
		590	`#define DMA1TSEL_4 (40x0010u) / DMA channel 1 transfer select 4: USCIA0 transmit */`
		591	`#define DMA1TSEL_5 (50x0010u) / DMA channel 1 transfer select 5: DAC12.0IFG */`
		592	`#define DMA1TSEL_6 (60x0010u) / DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */`
		593	`#define DMA1TSEL_7 (70x0010u) / DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */`
		594	`#define DMA1TSEL_8 (80x0010u) / DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */`
		595	`#define DMA1TSEL_9 (90x0010u) / DMA channel 1 transfer select 9: USCIA1 receive */`
		596	`#define DMA1TSEL_10 (100x0010u) / DMA channel 1 transfer select 10: USCIA1 transmit */`
		597	`#define DMA1TSEL_11 (110x0010u) / DMA channel 1 transfer select 11: Multiplier ready */`
		598	`#define DMA1TSEL_12 (120x0010u) / DMA channel 1 transfer select 12: USCIB0 receive */`
		599	`#define DMA1TSEL_13 (130x0010u) / DMA channel 1 transfer select 13: USCIB0 transmit */`
		600	`#define DMA1TSEL_14 (140x0010u) / DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */`
		601	`#define DMA1TSEL_15 (150x0010u) / DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */`
		602
		603	`#define DMA2TSEL_0 (00x0100u) / DMA channel 2 transfer select 0: DMA_REQ */`
		604	`#define DMA2TSEL_1 (10x0100u) / DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */`
		605	`#define DMA2TSEL_2 (20x0100u) / DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */`
		606	`#define DMA2TSEL_3 (30x0100u) / DMA channel 2 transfer select 3: USCIA0 receive */`
		607	`#define DMA2TSEL_4 (40x0100u) / DMA channel 2 transfer select 4: USCIA0 transmit */`
		608	`#define DMA2TSEL_5 (50x0100u) / DMA channel 2 transfer select 5: DAC12.0IFG */`
		609	`#define DMA2TSEL_6 (60x0100u) / DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */`
		610	`#define DMA2TSEL_7 (70x0100u) / DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */`
		611	`#define DMA2TSEL_8 (80x0100u) / DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */`
		612	`#define DMA2TSEL_9 (90x0100u) / DMA channel 2 transfer select 9: USCIA1 receive */`
		613	`#define DMA2TSEL_10 (100x0100u) / DMA channel 2 transfer select 10: USCIA1 transmit */`
		614	`#define DMA2TSEL_11 (110x0100u) / DMA channel 2 transfer select 11: Multiplier ready */`
		615	`#define DMA2TSEL_12 (120x0100u) / DMA channel 2 transfer select 12: USCIB0 receive */`
		616	`#define DMA2TSEL_13 (130x0100u) / DMA channel 2 transfer select 13: USCIB0 transmit */`
		617	`#define DMA2TSEL_14 (140x0100u) / DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */`
		618	`#define DMA2TSEL_15 (150x0100u) / DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */`
		619
		620	`SFR_16BIT(DMACTL1); /* DMA Module Control 1 */`
		621	`#define ENNMI (0x0001) /* Enable NMI interruption of DMA */`
		622	`#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */`
		623	`#define DMAONFETCH (0x0004) /* DMA transfer on instruction fetch */`
		624
		625	`SFR_16BIT(DMAIV); /* DMA Interrupt Vector Word */`
		626	`SFR_16BIT(DMA0CTL); /* DMA Channel 0 Control */`
		627	`SFR_16BIT(DMA1CTL); /* DMA Channel 1 Control */`
		628	`SFR_16BIT(DMA2CTL); /* DMA Channel 2 Control */`
		629
		630	`#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */`
		631	`#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */`
		632	`#define DMAIE (0x0004) /* DMA interrupt enable */`
		633	`#define DMAIFG (0x0008) /* DMA interrupt flag */`
		634	`#define DMAEN (0x0010) /* DMA enable */`
		635	`#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */`
		636	`#define DMASRCBYTE (0x0040) /* DMA source byte */`
		637	`#define DMADSTBYTE (0x0080) /* DMA destination byte */`
		638	`#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */`
		639	`#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */`
		640	`#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */`
		641	`#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */`
		642	`#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */`
		643	`#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */`
		644	`#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */`
		645
		646	`#define DMASWDW (00x0040u) / DMA transfer: source word to destination word */`
		647	`#define DMASBDW (10x0040u) / DMA transfer: source byte to destination word */`
		648	`#define DMASWDB (20x0040u) / DMA transfer: source word to destination byte */`
		649	`#define DMASBDB (30x0040u) / DMA transfer: source byte to destination byte */`
		650
		651	`#define DMASRCINCR_0 (00x0100u) / DMA source increment 0: source address unchanged */`
		652	`#define DMASRCINCR_1 (10x0100u) / DMA source increment 1: source address unchanged */`
		653	`#define DMASRCINCR_2 (20x0100u) / DMA source increment 2: source address decremented */`
		654	`#define DMASRCINCR_3 (30x0100u) / DMA source increment 3: source address incremented */`
		655
		656	`#define DMADSTINCR_0 (00x0400u) / DMA destination increment 0: destination address unchanged */`
		657	`#define DMADSTINCR_1 (10x0400u) / DMA destination increment 1: destination address unchanged */`
		658	`#define DMADSTINCR_2 (20x0400u) / DMA destination increment 2: destination address decremented */`
		659	`#define DMADSTINCR_3 (30x0400u) / DMA destination increment 3: destination address incremented */`
		660
		661	`#define DMADT_0 (00x1000u) / DMA transfer mode 0: single */`
		662	`#define DMADT_1 (10x1000u) / DMA transfer mode 1: block */`
		663	`#define DMADT_2 (20x1000u) / DMA transfer mode 2: interleaved */`
		664	`#define DMADT_3 (30x1000u) / DMA transfer mode 3: interleaved */`
		665	`#define DMADT_4 (40x1000u) / DMA transfer mode 4: single, repeat */`
		666	`#define DMADT_5 (50x1000u) / DMA transfer mode 5: block, repeat */`
		667	`#define DMADT_6 (60x1000u) / DMA transfer mode 6: interleaved, repeat */`
		668	`#define DMADT_7 (70x1000u) / DMA transfer mode 7: interleaved, repeat */`
		669
		670	`SFR_20BIT(DMA0SA); /* DMA Channel 0 Source Address */`
		671	`SFR_16BIT(DMA0SAL); /* DMA Channel 0 Source Address */`
		672	`SFR_20BIT(DMA0DA); /* DMA Channel 0 Destination Address */`
		673	`SFR_16BIT(DMA0DAL); /* DMA Channel 0 Destination Address */`
		674	`SFR_16BIT(DMA0SZ); /* DMA Channel 0 Transfer Size */`
		675	`SFR_20BIT(DMA1SA); /* DMA Channel 1 Source Address */`
		676	`SFR_16BIT(DMA1SAL); /* DMA Channel 1 Source Address */`
		677	`SFR_20BIT(DMA1DA); /* DMA Channel 1 Destination Address */`
		678	`SFR_16BIT(DMA1DAL); /* DMA Channel 1 Destination Address */`
		679	`SFR_16BIT(DMA1SZ); /* DMA Channel 1 Transfer Size */`
		680	`SFR_20BIT(DMA2SA); /* DMA Channel 2 Source Address */`
		681	`SFR_16BIT(DMA2SAL); /* DMA Channel 2 Source Address */`
		682	`SFR_20BIT(DMA2DA); /* DMA Channel 2 Destination Address */`
		683	`SFR_16BIT(DMA2DAL); /* DMA Channel 2 Destination Address */`
		684	`SFR_16BIT(DMA2SZ); /* DMA Channel 2 Transfer Size */`
		685
		686	`/* DMAIV Definitions */`
		687	`#define DMAIV_NONE (0x0000) /* No Interrupt pending */`
		688	`#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG */`
		689	`#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG */`
		690	`#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG */`
		691
		692	`/*************************************************************`
		693	`* Flash Memory`
		694	`*************************************************************/`
		695	`#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */`
		696
		697	`SFR_16BIT(FCTL1); /* FLASH Control 1 */`
		698	`SFR_16BIT(FCTL2); /* FLASH Control 2 */`
		699	`SFR_16BIT(FCTL3); /* FLASH Control 3 */`
		700	`SFR_16BIT(FCTL4); /* FLASH Control 4 */`
		701
		702	`#define FRKEY (0x9600) /* Flash key returned by read */`
		703	`#define FWKEY (0xA500) /* Flash key for write */`
		704	`#define FXKEY (0x3300) /* for use with XOR instruction */`
		705
		706	`#define ERASE (0x0002) /* Enable bit for Flash segment erase */`
		707	`#define MERAS (0x0004) /* Enable bit for Flash mass erase */`
		708	`#define EEI (0x0008) /* Enable Erase Interrupts */`
		709	`#define EEIEX (0x0010) /* Enable Emergency Interrupt Exit */`
		710	`#define WRT (0x0040) /* Enable bit for Flash write */`
		711	`#define BLKWRT (0x0080) /* Enable bit for Flash segment write */`
		712	`#define SEGWRT (0x0080) /* old definition / / Enable bit for Flash segment write */`
		713
		714	`#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */`
		715	`#define FN1 (0x0002) /* 32FN5 + 16FN4 + 8FN3 + 4FN2 + 2FN1 + FN0 + 1 /`
		716	`#ifndef FN2`
		717	`#define FN2 (0x0004)`
		718	`#endif`
		719	`#ifndef FN3`
		720	`#define FN3 (0x0008)`
		721	`#endif`
		722	`#ifndef FN4`
		723	`#define FN4 (0x0010)`
		724	`#endif`
		725	`#define FN5 (0x0020)`
		726	`#define FSSEL0 (0x0040) /* Flash clock select 0 / / to distinguish from USART SSELx */`
		727	`#define FSSEL1 (0x0080) /* Flash clock select 1 */`
		728
		729	`#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */`
		730	`#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */`
		731	`#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */`
		732	`#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */`
		733
		734	`#define BUSY (0x0001) /* Flash busy: 1 */`
		735	`#define KEYV (0x0002) /* Flash Key violation flag */`
		736	`#define ACCVIFG (0x0004) /* Flash Access violation flag */`
		737	`#define WAIT (0x0008) /* Wait flag for segment write */`
		738	`#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */`
		739	`#define EMEX (0x0020) /* Flash Emergency Exit */`
		740	`#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */`
		741	`#define FAIL (0x0080) /* Last Program or Erase failed */`
		742
		743	`#define MGR0 (0x0010) /* Marginal read 0 mode. */`
		744	`#define MGR1 (0x0020) /* Marginal read 1 mode. */`
		745
		746	`/************************************************************`
		747	`* HARDWARE MULTIPLIER`
		748	`************************************************************/`
		749	`#define __MSP430_HAS_MPY__ /* Definition to show that Module is available */`
		750
		751	`SFR_16BIT(MPY); /* Multiply Unsigned/Operand 1 */`
		752	`SFR_16BIT(MPYS); /* Multiply Signed/Operand 1 */`
		753	`SFR_16BIT(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */`
		754	`SFR_16BIT(MACS); /* Multiply Signed and Accumulate/Operand 1 */`
		755	`SFR_16BIT(OP2); /* Operand 2 */`
		756	`SFR_16BIT(RESLO); /* Result Low Word */`
		757	`SFR_16BIT(RESHI); /* Result High Word */`
		758	`SFR_16BIT(SUMEXT); /* Sum Extend */`
		759
		760	`/************************************************************`
		761	`* DIGITAL I/O Port1/2 Pull up / Pull down Resistors`
		762	`************************************************************/`
		763	`#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */`
		764	`#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */`
		765
		766	`SFR_8BIT(P1IN); /* Port 1 Input */`
		767	`SFR_8BIT(P1OUT); /* Port 1 Output */`
		768	`SFR_8BIT(P1DIR); /* Port 1 Direction */`
		769	`SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */`
		770	`SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */`
		771	`SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */`
		772	`SFR_8BIT(P1SEL); /* Port 1 Selection */`
		773	`SFR_8BIT(P1REN); /* Port 1 Resistor Enable */`
		774
		775	`SFR_8BIT(P2IN); /* Port 2 Input */`
		776	`SFR_8BIT(P2OUT); /* Port 2 Output */`
		777	`SFR_8BIT(P2DIR); /* Port 2 Direction */`
		778	`SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */`
		779	`SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */`
		780	`SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */`
		781	`SFR_8BIT(P2SEL); /* Port 2 Selection */`
		782	`SFR_8BIT(P2REN); /* Port 2 Resistor Enable */`
		783
		784	`/************************************************************`
		785	`* DIGITAL I/O Port3/4 Pull up / Pull down Resistors`
		786	`************************************************************/`
		787	`#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */`
		788	`#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */`
		789
		790	`SFR_8BIT(P3IN); /* Port 3 Input */`
		791	`SFR_8BIT(P3OUT); /* Port 3 Output */`
		792	`SFR_8BIT(P3DIR); /* Port 3 Direction */`
		793	`SFR_8BIT(P3SEL); /* Port 3 Selection */`
		794	`SFR_8BIT(P3REN); /* Port 3 Resistor Enable */`
		795
		796	`SFR_8BIT(P4IN); /* Port 4 Input */`
		797	`SFR_8BIT(P4OUT); /* Port 4 Output */`
		798	`SFR_8BIT(P4DIR); /* Port 4 Direction */`
		799	`SFR_8BIT(P4SEL); /* Port 4 Selection */`
		800	`SFR_8BIT(P4REN); /* Port 4 Resistor Enable */`
		801
		802	`/************************************************************`
		803	`* DIGITAL I/O Port5/6 Pull up / Pull down Resistors`
		804	`************************************************************/`
		805	`#define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */`
		806	`#define __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */`
		807
		808	`SFR_8BIT(P5IN); /* Port 5 Input */`
		809	`SFR_8BIT(P5OUT); /* Port 5 Output */`
		810	`SFR_8BIT(P5DIR); /* Port 5 Direction */`
		811	`SFR_8BIT(P5SEL); /* Port 5 Selection */`
		812	`SFR_8BIT(P5REN); /* Port 5 Resistor Enable */`
		813
		814	`SFR_8BIT(P6IN); /* Port 6 Input */`
		815	`SFR_8BIT(P6OUT); /* Port 6 Output */`
		816	`SFR_8BIT(P6DIR); /* Port 6 Direction */`
		817	`SFR_8BIT(P6SEL); /* Port 6 Selection */`
		818	`SFR_8BIT(P6REN); /* Port 6 Resistor Enable */`
		819
		820	`/************************************************************`
		821	`* DIGITAL I/O Port7/8 Pull up / Pull down Resistors`
		822	`************************************************************/`
		823	`#define __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */`
		824	`#define __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */`
		825	`#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */`
		826
		827	`SFR_8BIT(P7IN); /* Port 7 Input */`
		828	`SFR_8BIT(P7OUT); /* Port 7 Output */`
		829	`SFR_8BIT(P7DIR); /* Port 7 Direction */`
		830	`SFR_8BIT(P7SEL); /* Port 7 Selection */`
		831	`SFR_8BIT(P7REN); /* Port 7 Resistor Enable */`
		832
		833	`SFR_8BIT(P8IN); /* Port 8 Input */`
		834	`SFR_8BIT(P8OUT); /* Port 8 Output */`
		835	`SFR_8BIT(P8DIR); /* Port 8 Direction */`
		836	`SFR_8BIT(P8SEL); /* Port 8 Selection */`
		837	`SFR_8BIT(P8REN); /* Port 8 Resistor Enable */`
		838
		839	`SFR_16BIT(PAIN); /* Port A Input */`
		840	`SFR_16BIT(PAOUT); /* Port A Output */`
		841	`SFR_16BIT(PADIR); /* Port A Direction */`
		842	`SFR_16BIT(PASEL); /* Port A Selection */`
		843	`SFR_16BIT(PAREN); /* Port A Resistor Enable */`
		844
		845	`/************************************************************`
		846	`* Brown-Out, Supply Voltage Supervision (SVS)`
		847	`************************************************************/`
		848	`#define __MSP430_HAS_SVS__ /* Definition to show that Module is available */`
		849
		850	`SFR_8BIT(SVSCTL); /* SVS Control */`
		851	`#define SVSFG (0x01) /* SVS Flag */`
		852	`#define SVSOP (0x02) /* SVS output (read only) */`
		853	`#define SVSON (0x04) /* Switches the SVS on/off */`
		854	`#define PORON (0x08) /* Enable POR Generation if Low Voltage */`
		855	`#define VLD0 (0x10)`
		856	`#define VLD1 (0x20)`
		857	`#define VLD2 (0x40)`
		858	`#define VLD3 (0x80)`
		859
		860	`#define VLDON (0x10)`
		861	`#define VLDOFF (0x00)`
		862	`#define VLD_1_8V (0x10)`
		863
		864	`/************************************************************`
		865	`* Timer A3`
		866	`************************************************************/`
		867	`#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */`
		868
		869	`SFR_16BIT(TAIV); /* Timer A Interrupt Vector Word */`
		870	`SFR_16BIT(TACTL); /* Timer A Control */`
		871	`SFR_16BIT(TACCTL0); /* Timer A Capture/Compare Control 0 */`
		872	`SFR_16BIT(TACCTL1); /* Timer A Capture/Compare Control 1 */`
		873	`SFR_16BIT(TACCTL2); /* Timer A Capture/Compare Control 2 */`
		874	`SFR_16BIT(TAR); /* Timer A Counter Register */`
		875	`SFR_16BIT(TACCR0); /* Timer A Capture/Compare 0 */`
		876	`SFR_16BIT(TACCR1); /* Timer A Capture/Compare 1 */`
		877	`SFR_16BIT(TACCR2); /* Timer A Capture/Compare 2 */`
		878
		879	`/* Alternate register names */`
		880	`#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */`
		881	`#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */`
		882	`#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */`
		883	`#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */`
		884	`#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */`
		885	`#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */`
		886	`#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */`
		887	`#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */`
		888	`#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */`
		889	`#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */`
		890	`#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */`
		891	`#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */`
		892	`/* Alternate register names - 5xx style */`
		893	`#define TA0IV TAIV /* Timer A Interrupt Vector Word */`
		894	`#define TA0CTL TACTL /* Timer A Control */`
		895	`#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */`
		896	`#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */`
		897	`#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */`
		898	`#define TA0R TAR /* Timer A Counter Register */`
		899	`#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */`
		900	`#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */`
		901	`#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */`
		902	`#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */`
		903	`#define TA0CTL_ TACTL_ /* Timer A Control */`
		904	`#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */`
		905	`#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */`
		906	`#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */`
		907	`#define TA0R_ TAR_ /* Timer A Counter Register */`
		908	`#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */`
		909	`#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */`
		910	`#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */`
		911
		912	`#define TASSEL1 (0x0200) /* Timer A clock source select 0 */`
		913	`#define TASSEL0 (0x0100) /* Timer A clock source select 1 */`
		914	`#define ID1 (0x0080) /* Timer A clock input divider 1 */`
		915	`#define ID0 (0x0040) /* Timer A clock input divider 0 */`
		916	`#define MC1 (0x0020) /* Timer A mode control 1 */`
		917	`#define MC0 (0x0010) /* Timer A mode control 0 */`
		918	`#define TACLR (0x0004) /* Timer A counter clear */`
		919	`#define TAIE (0x0002) /* Timer A counter interrupt enable */`
		920	`#define TAIFG (0x0001) /* Timer A counter interrupt flag */`
		921
		922	`#define MC_0 (00x10u) / Timer A mode control: 0 - Stop */`
		923	`#define MC_1 (10x10u) / Timer A mode control: 1 - Up to CCR0 */`
		924	`#define MC_2 (20x10u) / Timer A mode control: 2 - Continous up */`
		925	`#define MC_3 (30x10u) / Timer A mode control: 3 - Up/Down */`
		926	`#define ID_0 (00x40u) / Timer A input divider: 0 - /1 */`
		927	`#define ID_1 (10x40u) / Timer A input divider: 1 - /2 */`
		928	`#define ID_2 (20x40u) / Timer A input divider: 2 - /4 */`
		929	`#define ID_3 (30x40u) / Timer A input divider: 3 - /8 */`
		930	`#define TASSEL_0 (00x100u) / Timer A clock source select: 0 - TACLK */`
		931	`#define TASSEL_1 (10x100u) / Timer A clock source select: 1 - ACLK */`
		932	`#define TASSEL_2 (20x100u) / Timer A clock source select: 2 - SMCLK */`
		933	`#define TASSEL_3 (30x100u) / Timer A clock source select: 3 - INCLK */`
		934
		935	`#define CM1 (0x8000) /* Capture mode 1 */`
		936	`#define CM0 (0x4000) /* Capture mode 0 */`
		937	`#define CCIS1 (0x2000) /* Capture input select 1 */`
		938	`#define CCIS0 (0x1000) /* Capture input select 0 */`
		939	`#define SCS (0x0800) /* Capture sychronize */`
		940	`#define SCCI (0x0400) /* Latched capture signal (read) */`
		941	`#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */`
		942	`#define OUTMOD2 (0x0080) /* Output mode 2 */`
		943	`#define OUTMOD1 (0x0040) /* Output mode 1 */`
		944	`#define OUTMOD0 (0x0020) /* Output mode 0 */`
		945	`#define CCIE (0x0010) /* Capture/compare interrupt enable */`
		946	`#define CCI (0x0008) /* Capture input signal (read) */`
		947	`#define OUT (0x0004) /* PWM Output signal if output mode 0 */`
		948	`#define COV (0x0002) /* Capture/compare overflow flag */`
		949	`#define CCIFG (0x0001) /* Capture/compare interrupt flag */`
		950
		951	`#define OUTMOD_0 (00x20u) / PWM output mode: 0 - output only */`
		952	`#define OUTMOD_1 (10x20u) / PWM output mode: 1 - set */`
		953	`#define OUTMOD_2 (20x20u) / PWM output mode: 2 - PWM toggle/reset */`
		954	`#define OUTMOD_3 (30x20u) / PWM output mode: 3 - PWM set/reset */`
		955	`#define OUTMOD_4 (40x20u) / PWM output mode: 4 - toggle */`
		956	`#define OUTMOD_5 (50x20u) / PWM output mode: 5 - Reset */`
		957	`#define OUTMOD_6 (60x20u) / PWM output mode: 6 - PWM toggle/set */`
		958	`#define OUTMOD_7 (70x20u) / PWM output mode: 7 - PWM reset/set */`
		959	`#define CCIS_0 (00x1000u) / Capture input select: 0 - CCIxA */`
		960	`#define CCIS_1 (10x1000u) / Capture input select: 1 - CCIxB */`
		961	`#define CCIS_2 (20x1000u) / Capture input select: 2 - GND */`
		962	`#define CCIS_3 (30x1000u) / Capture input select: 3 - Vcc */`
		963	`#define CM_0 (00x4000u) / Capture mode: 0 - disabled */`
		964	`#define CM_1 (10x4000u) / Capture mode: 1 - pos. edge */`
		965	`#define CM_2 (20x4000u) / Capture mode: 1 - neg. edge */`
		966	`#define CM_3 (30x4000u) / Capture mode: 1 - both edges */`
		967
		968	`/* TA3IV Definitions */`
		969	`#define TAIV_NONE (0x0000) /* No Interrupt pending */`
		970	`#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */`
		971	`#define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */`
		972	`#define TAIV_6 (0x0006) /* Reserved */`
		973	`#define TAIV_8 (0x0008) /* Reserved */`
		974	`#define TAIV_TAIFG (0x000A) /* TAIFG */`
		975
		976	`/************************************************************`
		977	`* Timer B7`
		978	`************************************************************/`
		979	`#define __MSP430_HAS_TB7__ /* Definition to show that Module is available */`
		980
		981	`SFR_16BIT(TBIV); /* Timer B Interrupt Vector Word */`
		982	`SFR_16BIT(TBCTL); /* Timer B Control */`
		983	`SFR_16BIT(TBCCTL0); /* Timer B Capture/Compare Control 0 */`
		984	`SFR_16BIT(TBCCTL1); /* Timer B Capture/Compare Control 1 */`
		985	`SFR_16BIT(TBCCTL2); /* Timer B Capture/Compare Control 2 */`
		986	`SFR_16BIT(TBCCTL3); /* Timer B Capture/Compare Control 3 */`
		987	`SFR_16BIT(TBCCTL4); /* Timer B Capture/Compare Control 4 */`
		988	`SFR_16BIT(TBCCTL5); /* Timer B Capture/Compare Control 5 */`
		989	`SFR_16BIT(TBCCTL6); /* Timer B Capture/Compare Control 6 */`
		990	`SFR_16BIT(TBR); /* Timer B Counter Register */`
		991	`SFR_16BIT(TBCCR0); /* Timer B Capture/Compare 0 */`
		992	`SFR_16BIT(TBCCR1); /* Timer B Capture/Compare 1 */`
		993	`SFR_16BIT(TBCCR2); /* Timer B Capture/Compare 2 */`
		994	`SFR_16BIT(TBCCR3); /* Timer B Capture/Compare 3 */`
		995	`SFR_16BIT(TBCCR4); /* Timer B Capture/Compare 4 */`
		996	`SFR_16BIT(TBCCR5); /* Timer B Capture/Compare 5 */`
		997	`SFR_16BIT(TBCCR6); /* Timer B Capture/Compare 6 */`
		998
		999	`/* Alternate register names - 5xx style */`
		1000	`#define TB0IV TBIV /* Timer B Interrupt Vector Word */`
		1001	`#define TB0CTL TBCTL /* Timer B Control */`
		1002	`#define TB0CCTL0 TBCCTL0 /* Timer B Capture/Compare Control 0 */`
		1003	`#define TB0CCTL1 TBCCTL1 /* Timer B Capture/Compare Control 1 */`
		1004	`#define TB0CCTL2 TBCCTL2 /* Timer B Capture/Compare Control 2 */`
		1005	`#define TB0CCTL3 TBCCTL3 /* Timer B Capture/Compare Control 3 */`
		1006	`#define TB0CCTL4 TBCCTL4 /* Timer B Capture/Compare Control 4 */`
		1007	`#define TB0CCTL5 TBCCTL5 /* Timer B Capture/Compare Control 5 */`
		1008	`#define TB0CCTL6 TBCCTL6 /* Timer B Capture/Compare Control 6 */`
		1009	`#define TB0R TBR /* Timer B Counter Register */`
		1010	`#define TB0CCR0 TBCCR0 /* Timer B Capture/Compare 0 */`
		1011	`#define TB0CCR1 TBCCR1 /* Timer B Capture/Compare 1 */`
		1012	`#define TB0CCR2 TBCCR2 /* Timer B Capture/Compare 2 */`
		1013	`#define TB0CCR3 TBCCR3 /* Timer B Capture/Compare 3 */`
		1014	`#define TB0CCR4 TBCCR4 /* Timer B Capture/Compare 4 */`
		1015	`#define TB0CCR5 TBCCR5 /* Timer B Capture/Compare 5 */`
		1016	`#define TB0CCR6 TBCCR6 /* Timer B Capture/Compare 6 */`
		1017	`#define TB0IV_ TBIV_ /* Timer B Interrupt Vector Word */`
		1018	`#define TB0CTL_ TBCTL_ /* Timer B Control */`
		1019	`#define TB0CCTL0_ TBCCTL0_ /* Timer B Capture/Compare Control 0 */`
		1020	`#define TB0CCTL1_ TBCCTL1_ /* Timer B Capture/Compare Control 1 */`
		1021	`#define TB0CCTL2_ TBCCTL2_ /* Timer B Capture/Compare Control 2 */`
		1022	`#define TB0CCTL3_ TBCCTL3_ /* Timer B Capture/Compare Control 3 */`
		1023	`#define TB0CCTL4_ TBCCTL4_ /* Timer B Capture/Compare Control 4 */`
		1024	`#define TB0CCTL5_ TBCCTL5_ /* Timer B Capture/Compare Control 5 */`
		1025	`#define TB0CCTL6_ TBCCTL6_ /* Timer B Capture/Compare Control 6 */`
		1026	`#define TB0R_ TBR_ /* Timer B Counter Register */`
		1027	`#define TB0CCR0_ TBCCR0_ /* Timer B Capture/Compare 0 */`
		1028	`#define TB0CCR1_ TBCCR1_ /* Timer B Capture/Compare 1 */`
		1029	`#define TB0CCR2_ TBCCR2_ /* Timer B Capture/Compare 2 */`
		1030	`#define TB0CCR3_ TBCCR3_ /* Timer B Capture/Compare 3 */`
		1031	`#define TB0CCR4_ TBCCR4_ /* Timer B Capture/Compare 4 */`
		1032	`#define TB0CCR5_ TBCCR5_ /* Timer B Capture/Compare 5 */`
		1033	`#define TB0CCR6_ TBCCR6_ /* Timer B Capture/Compare 6 */`
		1034
		1035	`#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */`
		1036	`#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */`
		1037	`#define CNTL1 (0x1000) /* Counter lenght 1 */`
		1038	`#define CNTL0 (0x0800) /* Counter lenght 0 */`
		1039	`#define TBSSEL1 (0x0200) /* Clock source 1 */`
		1040	`#define TBSSEL0 (0x0100) /* Clock source 0 */`
		1041	`#define TBCLR (0x0004) /* Timer B counter clear */`
		1042	`#define TBIE (0x0002) /* Timer B interrupt enable */`
		1043	`#define TBIFG (0x0001) /* Timer B interrupt flag */`
		1044
		1045	`#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */`
		1046	`#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */`
		1047
		1048	`#define TBSSEL_0 (00x0100u) / Clock Source: TBCLK */`
		1049	`#define TBSSEL_1 (10x0100u) / Clock Source: ACLK */`
		1050	`#define TBSSEL_2 (20x0100u) / Clock Source: SMCLK */`
		1051	`#define TBSSEL_3 (30x0100u) / Clock Source: INCLK */`
		1052	`#define CNTL_0 (00x0800u) / Counter lenght: 16 bit */`
		1053	`#define CNTL_1 (10x0800u) / Counter lenght: 12 bit */`
		1054	`#define CNTL_2 (20x0800u) / Counter lenght: 10 bit */`
		1055	`#define CNTL_3 (30x0800u) / Counter lenght: 8 bit */`
		1056	`#define SHR_0 (00x2000u) / Timer B Group: 0 - individually */`
		1057	`#define SHR_1 (10x2000u) / Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */`
		1058	`#define SHR_2 (20x2000u) / Timer B Group: 2 - 2 groups (1-3, 4-6)*/`
		1059	`#define SHR_3 (30x2000u) / Timer B Group: 3 - 1 group (all) */`
		1060	`#define TBCLGRP_0 (00x2000u) / Timer B Group: 0 - individually */`
		1061	`#define TBCLGRP_1 (10x2000u) / Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */`
		1062	`#define TBCLGRP_2 (20x2000u) / Timer B Group: 2 - 2 groups (1-3, 4-6)*/`
		1063	`#define TBCLGRP_3 (30x2000u) / Timer B Group: 3 - 1 group (all) */`
		1064
		1065	`/* Additional Timer B Control Register bits are defined in Timer A */`
		1066	`#define CLLD1 (0x0400) /* Compare latch load source 1 */`
		1067	`#define CLLD0 (0x0200) /* Compare latch load source 0 */`
		1068
		1069	`#define SLSHR1 (0x0400) /* Compare latch load source 1 */`
		1070	`#define SLSHR0 (0x0200) /* Compare latch load source 0 */`
		1071
		1072	`#define SLSHR_0 (00x0200u) / Compare latch load sourec : 0 - immediate */`
		1073	`#define SLSHR_1 (10x0200u) / Compare latch load sourec : 1 - TBR counts to 0 */`
		1074	`#define SLSHR_2 (20x0200u) / Compare latch load sourec : 2 - up/down */`
		1075	`#define SLSHR_3 (30x0200u) / Compare latch load sourec : 3 - TBR counts to TBCTL0 */`
		1076
		1077	`#define CLLD_0 (00x0200u) / Compare latch load sourec : 0 - immediate */`
		1078	`#define CLLD_1 (10x0200u) / Compare latch load sourec : 1 - TBR counts to 0 */`
		1079	`#define CLLD_2 (20x0200u) / Compare latch load sourec : 2 - up/down */`
		1080	`#define CLLD_3 (30x0200u) / Compare latch load sourec : 3 - TBR counts to TBCTL0 */`
		1081
		1082	`/* TB7IV Definitions */`
		1083	`#define TBIV_NONE (0x0000) /* No Interrupt pending */`
		1084	`#define TBIV_TBCCR1 (0x0002) /* TBCCR1_CCIFG */`
		1085	`#define TBIV_TBCCR2 (0x0004) /* TBCCR2_CCIFG */`
		1086	`#define TBIV_TBCCR3 (0x0006) /* TBCCR3_CCIFG */`
		1087	`#define TBIV_TBCCR4 (0x0008) /* TBCCR4_CCIFG */`
		1088	`#define TBIV_TBCCR5 (0x000A) /* TBCCR3_CCIFG */`
		1089	`#define TBIV_TBCCR6 (0x000C) /* TBCCR4_CCIFG */`
		1090	`#define TBIV_TBIFG (0x000E) /* TBIFG */`
		1091
		1092	`/************************************************************`
		1093	`* USCI`
		1094	`************************************************************/`
		1095	`#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */`
		1096	`#define __MSP430_HAS_USCI_AB0__ /* Definition to show that Module is available */`
		1097	`#define __MSP430_HAS_USCI_AB1__ /* Definition to show that Module is available */`
		1098
		1099	`SFR_8BIT(UCA0CTL0); /* USCI A0 Control Register 0 */`
		1100	`SFR_8BIT(UCA0CTL1); /* USCI A0 Control Register 1 */`
		1101	`SFR_8BIT(UCA0BR0); /* USCI A0 Baud Rate 0 */`
		1102	`SFR_8BIT(UCA0BR1); /* USCI A0 Baud Rate 1 */`
		1103	`SFR_8BIT(UCA0MCTL); /* USCI A0 Modulation Control */`
		1104	`SFR_8BIT(UCA0STAT); /* USCI A0 Status Register */`
		1105	`SFR_8BIT(UCA0RXBUF); /* USCI A0 Receive Buffer */`
		1106	`SFR_8BIT(UCA0TXBUF); /* USCI A0 Transmit Buffer */`
		1107	`SFR_8BIT(UCA0ABCTL); /* USCI A0 LIN Control */`
		1108	`SFR_8BIT(UCA0IRTCTL); /* USCI A0 IrDA Transmit Control */`
		1109	`SFR_8BIT(UCA0IRRCTL); /* USCI A0 IrDA Receive Control */`
		1110
		1111
		1112
		1113	`SFR_8BIT(UCB0CTL0); /* USCI B0 Control Register 0 */`
		1114	`SFR_8BIT(UCB0CTL1); /* USCI B0 Control Register 1 */`
		1115	`SFR_8BIT(UCB0BR0); /* USCI B0 Baud Rate 0 */`
		1116	`SFR_8BIT(UCB0BR1); /* USCI B0 Baud Rate 1 */`
		1117	`SFR_8BIT(UCB0I2CIE); /* USCI B0 I2C Interrupt Enable Register */`
		1118	`SFR_8BIT(UCB0STAT); /* USCI B0 Status Register */`
		1119	`SFR_8BIT(UCB0RXBUF); /* USCI B0 Receive Buffer */`
		1120	`SFR_8BIT(UCB0TXBUF); /* USCI B0 Transmit Buffer */`
		1121	`SFR_16BIT(UCB0I2COA); /* USCI B0 I2C Own Address */`
		1122	`SFR_16BIT(UCB0I2CSA); /* USCI B0 I2C Slave Address */`
		1123
		1124	`SFR_8BIT(UCA1CTL0); /* USCI A1 Control Register 0 */`
		1125	`SFR_8BIT(UCA1CTL1); /* USCI A1 Control Register 1 */`
		1126	`SFR_8BIT(UCA1BR0); /* USCI A1 Baud Rate 0 */`
		1127	`SFR_8BIT(UCA1BR1); /* USCI A1 Baud Rate 1 */`
		1128	`SFR_8BIT(UCA1MCTL); /* USCI A1 Modulation Control */`
		1129	`SFR_8BIT(UCA1STAT); /* USCI A1 Status Register */`
		1130	`SFR_8BIT(UCA1RXBUF); /* USCI A1 Receive Buffer */`
		1131	`SFR_8BIT(UCA1TXBUF); /* USCI A1 Transmit Buffer */`
		1132	`SFR_8BIT(UCA1ABCTL); /* USCI A1 LIN Control */`
		1133	`SFR_8BIT(UCA1IRTCTL); /* USCI A1 IrDA Transmit Control */`
		1134	`SFR_8BIT(UCA1IRRCTL); /* USCI A1 IrDA Receive Control */`
		1135
		1136
		1137
		1138	`SFR_8BIT(UCB1CTL0); /* USCI B1 Control Register 0 */`
		1139	`SFR_8BIT(UCB1CTL1); /* USCI B1 Control Register 1 */`
		1140	`SFR_8BIT(UCB1BR0); /* USCI B1 Baud Rate 0 */`
		1141	`SFR_8BIT(UCB1BR1); /* USCI B1 Baud Rate 1 */`
		1142	`SFR_8BIT(UCB1I2CIE); /* USCI B1 I2C Interrupt Enable Register */`
		1143	`SFR_8BIT(UCB1STAT); /* USCI B1 Status Register */`
		1144	`SFR_8BIT(UCB1RXBUF); /* USCI B1 Receive Buffer */`
		1145	`SFR_8BIT(UCB1TXBUF); /* USCI B1 Transmit Buffer */`
		1146	`SFR_16BIT(UCB1I2COA); /* USCI B1 I2C Own Address */`
		1147	`SFR_16BIT(UCB1I2CSA); /* USCI B1 I2C Slave Address */`
		1148
		1149	`// UART-Mode Bits`
		1150	`#define UCPEN (0x80) /* Async. Mode: Parity enable */`
		1151	`#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */`
		1152	`#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */`
		1153	`#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */`
		1154	`#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */`
		1155	`#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */`
		1156	`#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */`
		1157	`#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */`
		1158
		1159	`// SPI-Mode Bits`
		1160	`#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */`
		1161	`#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */`
		1162	`#define UCMST (0x08) /* Sync. Mode: Master Select */`
		1163
		1164	`// I2C-Mode Bits`
		1165	`#define UCA10 (0x80) /* 10-bit Address Mode */`
		1166	`#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */`
		1167	`#define UCMM (0x20) /* Multi-Master Environment */`
		1168	`//#define res (0x10) /* reserved */`
		1169	`#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */`
		1170	`#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */`
		1171	`#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */`
		1172	`#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */`
		1173
		1174	`// UART-Mode Bits`
		1175	`#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */`
		1176	`#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */`
		1177	`#define UCRXEIE (0x20) /* RX Error interrupt enable */`
		1178	`#define UCBRKIE (0x10) /* Break interrupt enable */`
		1179	`#define UCDORM (0x08) /* Dormant (Sleep) Mode */`
		1180	`#define UCTXADDR (0x04) /* Send next Data as Address */`
		1181	`#define UCTXBRK (0x02) /* Send next Data as Break */`
		1182	`#define UCSWRST (0x01) /* USCI Software Reset */`
		1183
		1184	`// SPI-Mode Bits`
		1185	`//#define res (0x20) /* reserved */`
		1186	`//#define res (0x10) /* reserved */`
		1187	`//#define res (0x08) /* reserved */`
		1188	`//#define res (0x04) /* reserved */`
		1189	`//#define res (0x02) /* reserved */`
		1190
		1191	`// I2C-Mode Bits`
		1192	`//#define res (0x20) /* reserved */`
		1193	`#define UCTR (0x10) /* Transmit/Receive Select/Flag */`
		1194	`#define UCTXNACK (0x08) /* Transmit NACK */`
		1195	`#define UCTXSTP (0x04) /* Transmit STOP */`
		1196	`#define UCTXSTT (0x02) /* Transmit START */`
		1197	`#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */`
		1198	`#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */`
		1199	`#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */`
		1200	`#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */`
		1201
		1202	`#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */`
		1203	`#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */`
		1204	`#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */`
		1205	`#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */`
		1206	`#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */`
		1207	`#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */`
		1208	`#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */`
		1209	`#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */`
		1210
		1211	`#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */`
		1212	`#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */`
		1213	`#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */`
		1214	`#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */`
		1215	`#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */`
		1216	`#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */`
		1217	`#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */`
		1218	`#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */`
		1219	`#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */`
		1220	`#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */`
		1221	`#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */`
		1222	`#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */`
		1223	`#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */`
		1224	`#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */`
		1225	`#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */`
		1226	`#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */`
		1227
		1228	`#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */`
		1229	`#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */`
		1230	`#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */`
		1231	`#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */`
		1232	`#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */`
		1233	`#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */`
		1234	`#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */`
		1235	`#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */`
		1236
		1237	`#define UCLISTEN (0x80) /* USCI Listen mode */`
		1238	`#define UCFE (0x40) /* USCI Frame Error Flag */`
		1239	`#define UCOE (0x20) /* USCI Overrun Error Flag */`
		1240	`#define UCPE (0x10) /* USCI Parity Error Flag */`
		1241	`#define UCBRK (0x08) /* USCI Break received */`
		1242	`#define UCRXERR (0x04) /* USCI RX Error Flag */`
		1243	`#define UCADDR (0x02) /* USCI Address received Flag */`
		1244	`#define UCBUSY (0x01) /* USCI Busy Flag */`
		1245	`#define UCIDLE (0x02) /* USCI Idle line detected Flag */`
		1246
		1247	`//#define res (0x80) /* reserved */`
		1248	`//#define res (0x40) /* reserved */`
		1249	`//#define res (0x20) /* reserved */`
		1250	`//#define res (0x10) /* reserved */`
		1251	`#define UCNACKIE (0x08) /* NACK Condition interrupt enable */`
		1252	`#define UCSTPIE (0x04) /* STOP Condition interrupt enable */`
		1253	`#define UCSTTIE (0x02) /* START Condition interrupt enable */`
		1254	`#define UCALIE (0x01) /* Arbitration Lost interrupt enable */`
		1255
		1256	`#define UCSCLLOW (0x40) /* SCL low */`
		1257	`#define UCGC (0x20) /* General Call address received Flag */`
		1258	`#define UCBBUSY (0x10) /* Bus Busy Flag */`
		1259	`#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */`
		1260	`#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */`
		1261	`#define UCSTTIFG (0x02) /* START Condition interrupt Flag */`
		1262	`#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */`
		1263
		1264	`#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */`
		1265	`#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */`
		1266	`#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */`
		1267	`#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */`
		1268	`#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */`
		1269	`#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */`
		1270	`#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */`
		1271	`#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */`
		1272
		1273	`#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */`
		1274	`#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */`
		1275	`#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */`
		1276	`#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */`
		1277	`#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */`
		1278	`#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */`
		1279	`#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */`
		1280	`#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */`
		1281
		1282	`//#define res (0x80) /* reserved */`
		1283	`//#define res (0x40) /* reserved */`
		1284	`#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */`
		1285	`#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */`
		1286	`#define UCSTOE (0x08) /* Sync-Field Timeout error */`
		1287	`#define UCBTOE (0x04) /* Break Timeout error */`
		1288	`//#define res (0x02) /* reserved */`
		1289	`#define UCABDEN (0x01) /* Auto Baud Rate detect enable */`
		1290
		1291	`#define UCGCEN (0x8000) /* I2C General Call enable */`
		1292	`#define UCOA9 (0x0200) /* I2C Own Address 9 */`
		1293	`#define UCOA8 (0x0100) /* I2C Own Address 8 */`
		1294	`#define UCOA7 (0x0080) /* I2C Own Address 7 */`
		1295	`#define UCOA6 (0x0040) /* I2C Own Address 6 */`
		1296	`#define UCOA5 (0x0020) /* I2C Own Address 5 */`
		1297	`#define UCOA4 (0x0010) /* I2C Own Address 4 */`
		1298	`#define UCOA3 (0x0008) /* I2C Own Address 3 */`
		1299	`#define UCOA2 (0x0004) /* I2C Own Address 2 */`
		1300	`#define UCOA1 (0x0002) /* I2C Own Address 1 */`
		1301	`#define UCOA0 (0x0001) /* I2C Own Address 0 */`
		1302
		1303	`#define UCSA9 (0x0200) /* I2C Slave Address 9 */`
		1304	`#define UCSA8 (0x0100) /* I2C Slave Address 8 */`
		1305	`#define UCSA7 (0x0080) /* I2C Slave Address 7 */`
		1306	`#define UCSA6 (0x0040) /* I2C Slave Address 6 */`
		1307	`#define UCSA5 (0x0020) /* I2C Slave Address 5 */`
		1308	`#define UCSA4 (0x0010) /* I2C Slave Address 4 */`
		1309	`#define UCSA3 (0x0008) /* I2C Slave Address 3 */`
		1310	`#define UCSA2 (0x0004) /* I2C Slave Address 2 */`
		1311	`#define UCSA1 (0x0002) /* I2C Slave Address 1 */`
		1312	`#define UCSA0 (0x0001) /* I2C Slave Address 0 */`
		1313
		1314	`/************************************************************`
		1315	`* WATCHDOG TIMER`
		1316	`************************************************************/`
		1317	`#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */`
		1318
		1319	`SFR_16BIT(WDTCTL); /* Watchdog Timer Control */`
		1320	`/* The bit names have been prefixed with "WDT" */`
		1321	`#define WDTIS0 (0x0001)`
		1322	`#define WDTIS1 (0x0002)`
		1323	`#define WDTSSEL (0x0004)`
		1324	`#define WDTCNTCL (0x0008)`
		1325	`#define WDTTMSEL (0x0010)`
		1326	`#define WDTNMI (0x0020)`
		1327	`#define WDTNMIES (0x0040)`
		1328	`#define WDTHOLD (0x0080)`
		1329
		1330	`#define WDTPW (0x5A00)`
		1331
		1332	`/* WDT-interval times [1ms] coded with Bits 0-2 */`
		1333	`/* WDT is clocked by fSMCLK (assumed 1MHz) */`
		1334	`#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */`
		1335	`#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */`
		1336	`#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */`
		1337	`#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */`
		1338	`/* WDT is clocked by fACLK (assumed 32KHz) */`
		1339	`#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */`
		1340	`#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */`
		1341	`#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */`
		1342	`#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */`
		1343	`/* Watchdog mode -> reset after expired time */`
		1344	`/* WDT is clocked by fSMCLK (assumed 1MHz) */`
		1345	`#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */`
		1346	`#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */`
		1347	`#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */`
		1348	`#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */`
		1349	`/* WDT is clocked by fACLK (assumed 32KHz) */`
		1350	`#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */`
		1351	`#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */`
		1352	`#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */`
		1353	`#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */`
		1354
		1355	`/* INTERRUPT CONTROL */`
		1356	`/* These two bits are defined in the Special Function Registers */`
		1357	`/* #define WDTIE 0x01 */`
		1358	`/* #define WDTIFG 0x01 */`
		1359
		1360	`/************************************************************`
		1361	`* Calibration Data in Info Mem`
		1362	`************************************************************/`
		1363
		1364	`/* TLV Calibration Data Structure */`
		1365	`#define TAG_DCO_30 (0x01) /* Tag for DCO30 Calibration Data */`
		1366	`#define TAG_ADC12_1 (0x08) /* Tag for ADC12_1 Calibration Data */`
		1367	`#define TAG_EMPTY (0xFE) /* Tag for Empty Data Field in Calibration Data */`
		1368
		1369	`#ifndef __DisableCalData`
		1370	`SFR_16BIT(TLV_CHECKSUM); /* TLV CHECK SUM */`
		1371	`SFR_8BIT(TLV_DCO_30_TAG); /* TLV TAG_DCO30 TAG */`
		1372	`SFR_8BIT(TLV_DCO_30_LEN); /* TLV TAG_DCO30 LEN */`
		1373	`SFR_8BIT(TLV_ADC12_1_TAG); /* TLV ADC12_1 TAG */`
		1374	`SFR_8BIT(TLV_ADC12_1_LEN); /* TLV ADC12_1 LEN */`
		1375	`#endif`
		1376
		1377	`#define CAL_ADC_25T85 (0x0007) /* Index for 2.5V/85Deg Cal. Value */`
		1378	`#define CAL_ADC_25T30 (0x0006) /* Index for 2.5V/30Deg Cal. Value */`
		1379	`#define CAL_ADC_25VREF_FACTOR (0x0005) /* Index for 2.5V Ref. Factor */`
		1380	`#define CAL_ADC_15T85 (0x0004) /* Index for 1.5V/85Deg Cal. Value */`
		1381	`#define CAL_ADC_15T30 (0x0003) /* Index for 1.5V/30Deg Cal. Value */`
		1382	`#define CAL_ADC_15VREF_FACTOR (0x0002) /* Index for ADC 1.5V Ref. Factor */`
		1383	`#define CAL_ADC_OFFSET (0x0001) /* Index for ADC Offset */`
		1384	`#define CAL_ADC_GAIN_FACTOR (0x0000) /* Index for ADC Gain Factor */`
		1385
		1386	`#define CAL_DCO_16MHZ (0x0000) /* Index for DCOCTL Calibration Data for 16MHz */`
		1387	`#define CAL_BC1_16MHZ (0x0001) /* Index for BCSCTL1 Calibration Data for 16MHz */`
		1388	`#define CAL_DCO_12MHZ (0x0002) /* Index for DCOCTL Calibration Data for 12MHz */`
		1389	`#define CAL_BC1_12MHZ (0x0003) /* Index for BCSCTL1 Calibration Data for 12MHz */`
		1390	`#define CAL_DCO_8MHZ (0x0004) /* Index for DCOCTL Calibration Data for 8MHz */`
		1391	`#define CAL_BC1_8MHZ (0x0005) /* Index for BCSCTL1 Calibration Data for 8MHz */`
		1392	`#define CAL_DCO_1MHZ (0x0006) /* Index for DCOCTL Calibration Data for 1MHz */`
		1393	`#define CAL_BC1_1MHZ (0x0007) /* Index for BCSCTL1 Calibration Data for 1MHz */`
		1394
		1395
		1396	`/************************************************************`
		1397	`* Calibration Data in Info Mem`
		1398	`************************************************************/`
		1399
		1400	`#ifndef __DisableCalData`
		1401
		1402	`SFR_8BIT(CALDCO_16MHZ); /* DCOCTL Calibration Data for 16MHz */`
		1403	`SFR_8BIT(CALBC1_16MHZ); /* BCSCTL1 Calibration Data for 16MHz */`
		1404	`SFR_8BIT(CALDCO_12MHZ); /* DCOCTL Calibration Data for 12MHz */`
		1405	`SFR_8BIT(CALBC1_12MHZ); /* BCSCTL1 Calibration Data for 12MHz */`
		1406	`SFR_8BIT(CALDCO_8MHZ); /* DCOCTL Calibration Data for 8MHz */`
		1407	`SFR_8BIT(CALBC1_8MHZ); /* BCSCTL1 Calibration Data for 8MHz */`
		1408	`SFR_8BIT(CALDCO_1MHZ); /* DCOCTL Calibration Data for 1MHz */`
		1409	`SFR_8BIT(CALBC1_1MHZ); /* BCSCTL1 Calibration Data for 1MHz */`
		1410
		1411	`#endif /* #ifndef __DisableCalData */`
		1412
		1413	`/************************************************************`
		1414	`* Interrupt Vectors (offset from 0xFFC0)`
		1415	`************************************************************/`
		1416
		1417	`#pragma diag_suppress 1107`
		1418	`#define VECTOR_NAME(name) name##_ptr`
		1419	`#define EMIT_PRAGMA(x) _Pragma(#x)`
		1420	`#define CREATE_VECTOR(name) void * const VECTOR_NAME(name) = (void *)(long)&name`
		1421	`#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))`
		1422	`#define PLACE_INTERRUPT(func) EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))`
		1423	`#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \`
		1424	`PLACE_VECTOR(VECTOR_NAME(func), offset) \`
		1425	`PLACE_INTERRUPT(func)`
		1426
		1427	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1428	`#define RESERVED0_VECTOR ".int00" /* 0xFFC0 Reserved Int. Vector 0 */`
		1429	`#else`
		1430	`#define RESERVED0_VECTOR (0 * 1u) /* 0xFFC0 Reserved Int. Vector 0 */`
		1431	`/#define RESERVED0_ISR(func) ISR_VECTOR(func, ".int00") / /* 0xFFC0 Reserved Int. Vector 0 / / CCE V2 Style */`
		1432	`#endif`
		1433	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1434	`#define RESERVED1_VECTOR ".int01" /* 0xFFC2 Reserved Int. Vector 1 */`
		1435	`#else`
		1436	`#define RESERVED1_VECTOR (1 * 1u) /* 0xFFC2 Reserved Int. Vector 1 */`
		1437	`/#define RESERVED1_ISR(func) ISR_VECTOR(func, ".int01") / /* 0xFFC2 Reserved Int. Vector 1 / / CCE V2 Style */`
		1438	`#endif`
		1439	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1440	`#define RESERVED2_VECTOR ".int02" /* 0xFFC4 Reserved Int. Vector 2 */`
		1441	`#else`
		1442	`#define RESERVED2_VECTOR (2 * 1u) /* 0xFFC4 Reserved Int. Vector 2 */`
		1443	`/#define RESERVED2_ISR(func) ISR_VECTOR(func, ".int02") / /* 0xFFC4 Reserved Int. Vector 2 / / CCE V2 Style */`
		1444	`#endif`
		1445	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1446	`#define RESERVED3_VECTOR ".int03" /* 0xFFC6 Reserved Int. Vector 3 */`
		1447	`#else`
		1448	`#define RESERVED3_VECTOR (3 * 1u) /* 0xFFC6 Reserved Int. Vector 3 */`
		1449	`/#define RESERVED3_ISR(func) ISR_VECTOR(func, ".int03") / /* 0xFFC6 Reserved Int. Vector 3 / / CCE V2 Style */`
		1450	`#endif`
		1451	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1452	`#define RESERVED4_VECTOR ".int04" /* 0xFFC8 Reserved Int. Vector 4 */`
		1453	`#else`
		1454	`#define RESERVED4_VECTOR (4 * 1u) /* 0xFFC8 Reserved Int. Vector 4 */`
		1455	`/#define RESERVED4_ISR(func) ISR_VECTOR(func, ".int04") / /* 0xFFC8 Reserved Int. Vector 4 / / CCE V2 Style */`
		1456	`#endif`
		1457	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1458	`#define RESERVED5_VECTOR ".int05" /* 0xFFCA Reserved Int. Vector 5 */`
		1459	`#else`
		1460	`#define RESERVED5_VECTOR (5 * 1u) /* 0xFFCA Reserved Int. Vector 5 */`
		1461	`/#define RESERVED5_ISR(func) ISR_VECTOR(func, ".int05") / /* 0xFFCA Reserved Int. Vector 5 / / CCE V2 Style */`
		1462	`#endif`
		1463	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1464	`#define RESERVED6_VECTOR ".int06" /* 0xFFCC Reserved Int. Vector 6 */`
		1465	`#else`
		1466	`#define RESERVED6_VECTOR (6 * 1u) /* 0xFFCC Reserved Int. Vector 6 */`
		1467	`/#define RESERVED6_ISR(func) ISR_VECTOR(func, ".int06") / /* 0xFFCC Reserved Int. Vector 6 / / CCE V2 Style */`
		1468	`#endif`
		1469	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1470	`#define RESERVED7_VECTOR ".int07" /* 0xFFCE Reserved Int. Vector 7 */`
		1471	`#else`
		1472	`#define RESERVED7_VECTOR (7 * 1u) /* 0xFFCE Reserved Int. Vector 7 */`
		1473	`/#define RESERVED7_ISR(func) ISR_VECTOR(func, ".int07") / /* 0xFFCE Reserved Int. Vector 7 / / CCE V2 Style */`
		1474	`#endif`
		1475	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1476	`#define RESERVED8_VECTOR ".int08" /* 0xFFD0 Reserved Int. Vector 8 */`
		1477	`#else`
		1478	`#define RESERVED8_VECTOR (8 * 1u) /* 0xFFD0 Reserved Int. Vector 8 */`
		1479	`/#define RESERVED8_ISR(func) ISR_VECTOR(func, ".int08") / /* 0xFFD0 Reserved Int. Vector 8 / / CCE V2 Style */`
		1480	`#endif`
		1481	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1482	`#define RESERVED9_VECTOR ".int09" /* 0xFFD2 Reserved Int. Vector 9 */`
		1483	`#else`
		1484	`#define RESERVED9_VECTOR (9 * 1u) /* 0xFFD2 Reserved Int. Vector 9 */`
		1485	`/#define RESERVED9_ISR(func) ISR_VECTOR(func, ".int09") / /* 0xFFD2 Reserved Int. Vector 9 / / CCE V2 Style */`
		1486	`#endif`
		1487	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1488	`#define RESERVED10_VECTOR ".int10" /* 0xFFD4 Reserved Int. Vector 10 */`
		1489	`#else`
		1490	`#define RESERVED10_VECTOR (10 * 1u) /* 0xFFD4 Reserved Int. Vector 10 */`
		1491	`/#define RESERVED10_ISR(func) ISR_VECTOR(func, ".int10") / /* 0xFFD4 Reserved Int. Vector 10 / / CCE V2 Style */`
		1492	`#endif`
		1493	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1494	`#define RESERVED11_VECTOR ".int11" /* 0xFFD6 Reserved Int. Vector 11 */`
		1495	`#else`
		1496	`#define RESERVED11_VECTOR (11 * 1u) /* 0xFFD6 Reserved Int. Vector 11 */`
		1497	`/#define RESERVED11_ISR(func) ISR_VECTOR(func, ".int11") / /* 0xFFD6 Reserved Int. Vector 11 / / CCE V2 Style */`
		1498	`#endif`
		1499	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1500	`#define RESERVED12_VECTOR ".int12" /* 0xFFD8 Reserved Int. Vector 12 */`
		1501	`#else`
		1502	`#define RESERVED12_VECTOR (12 * 1u) /* 0xFFD8 Reserved Int. Vector 12 */`
		1503	`/#define RESERVED12_ISR(func) ISR_VECTOR(func, ".int12") / /* 0xFFD8 Reserved Int. Vector 12 / / CCE V2 Style */`
		1504	`#endif`
		1505	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1506	`#define RESERVED13_VECTOR ".int13" /* 0xFFDA Reserved Int. Vector 13 */`
		1507	`#else`
		1508	`#define RESERVED13_VECTOR (13 * 1u) /* 0xFFDA Reserved Int. Vector 13 */`
		1509	`/#define RESERVED13_ISR(func) ISR_VECTOR(func, ".int13") / /* 0xFFDA Reserved Int. Vector 13 / / CCE V2 Style */`
		1510	`#endif`
		1511	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1512	`#define DAC12_VECTOR ".int14" /* 0xFFDC DAC12 */`
		1513	`#else`
		1514	`#define DAC12_VECTOR (14 * 1u) /* 0xFFDC DAC12 */`
		1515	`/#define DAC12_ISR(func) ISR_VECTOR(func, ".int14") / /* 0xFFDC DAC12 / / CCE V2 Style */`
		1516	`#endif`
		1517	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1518	`#define DMA_VECTOR ".int15" /* 0xFFDE DMA */`
		1519	`#else`
		1520	`#define DMA_VECTOR (15 * 1u) /* 0xFFDE DMA */`
		1521	`/#define DMA_ISR(func) ISR_VECTOR(func, ".int15") / /* 0xFFDE DMA / / CCE V2 Style */`
		1522	`#endif`
		1523	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1524	`#define USCIAB1TX_VECTOR ".int16" /* 0xFFE0 USCI A1/B1 Transmit */`
		1525	`#else`
		1526	`#define USCIAB1TX_VECTOR (16 * 1u) /* 0xFFE0 USCI A1/B1 Transmit */`
		1527	`/#define USCIAB1TX_ISR(func) ISR_VECTOR(func, ".int16") / /* 0xFFE0 USCI A1/B1 Transmit / / CCE V2 Style */`
		1528	`#endif`
		1529	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1530	`#define USCIAB1RX_VECTOR ".int17" /* 0xFFE2 USCI A1/B1 Receive */`
		1531	`#else`
		1532	`#define USCIAB1RX_VECTOR (17 * 1u) /* 0xFFE2 USCI A1/B1 Receive */`
		1533	`/#define USCIAB1RX_ISR(func) ISR_VECTOR(func, ".int17") / /* 0xFFE2 USCI A1/B1 Receive / / CCE V2 Style */`
		1534	`#endif`
		1535	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1536	`#define PORT1_VECTOR ".int18" /* 0xFFE4 Port 1 */`
		1537	`#else`
		1538	`#define PORT1_VECTOR (18 * 1u) /* 0xFFE4 Port 1 */`
		1539	`/#define PORT1_ISR(func) ISR_VECTOR(func, ".int18") / /* 0xFFE4 Port 1 / / CCE V2 Style */`
		1540	`#endif`
		1541	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1542	`#define PORT2_VECTOR ".int19" /* 0xFFE6 Port 2 */`
		1543	`#else`
		1544	`#define PORT2_VECTOR (19 * 1u) /* 0xFFE6 Port 2 */`
		1545	`/#define PORT2_ISR(func) ISR_VECTOR(func, ".int19") / /* 0xFFE6 Port 2 / / CCE V2 Style */`
		1546	`#endif`
		1547	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1548	`#define RESERVED20_VECTOR ".int20" /* 0xFFE8 Reserved Int. Vector 20 */`
		1549	`#else`
		1550	`#define RESERVED20_VECTOR (20 * 1u) /* 0xFFE8 Reserved Int. Vector 20 */`
		1551	`/#define RESERVED20_ISR(func) ISR_VECTOR(func, ".int20") / /* 0xFFE8 Reserved Int. Vector 20 / / CCE V2 Style */`
		1552	`#endif`
		1553	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1554	`#define ADC12_VECTOR ".int21" /* 0xFFEA ADC */`
		1555	`#else`
		1556	`#define ADC12_VECTOR (21 * 1u) /* 0xFFEA ADC */`
		1557	`/#define ADC12_ISR(func) ISR_VECTOR(func, ".int21") / /* 0xFFEA ADC / / CCE V2 Style */`
		1558	`#endif`
		1559	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1560	`#define USCIAB0TX_VECTOR ".int22" /* 0xFFEC USCI A0/B0 Transmit */`
		1561	`#else`
		1562	`#define USCIAB0TX_VECTOR (22 * 1u) /* 0xFFEC USCI A0/B0 Transmit */`
		1563	`/#define USCIAB0TX_ISR(func) ISR_VECTOR(func, ".int22") / /* 0xFFEC USCI A0/B0 Transmit / / CCE V2 Style */`
		1564	`#endif`
		1565	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1566	`#define USCIAB0RX_VECTOR ".int23" /* 0xFFEE USCI A0/B0 Receive */`
		1567	`#else`
		1568	`#define USCIAB0RX_VECTOR (23 * 1u) /* 0xFFEE USCI A0/B0 Receive */`
		1569	`/#define USCIAB0RX_ISR(func) ISR_VECTOR(func, ".int23") / /* 0xFFEE USCI A0/B0 Receive / / CCE V2 Style */`
		1570	`#endif`
		1571	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1572	`#define TIMERA1_VECTOR ".int24" /* 0xFFF0 Timer A CC1-2, TA */`
		1573	`#else`
		1574	`#define TIMERA1_VECTOR (24 * 1u) /* 0xFFF0 Timer A CC1-2, TA */`
		1575	`/#define TIMERA1_ISR(func) ISR_VECTOR(func, ".int24") / /* 0xFFF0 Timer A CC1-2, TA / / CCE V2 Style */`
		1576	`#endif`
		1577	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1578	`#define TIMERA0_VECTOR ".int25" /* 0xFFF2 Timer A CC0 */`
		1579	`#else`
		1580	`#define TIMERA0_VECTOR (25 * 1u) /* 0xFFF2 Timer A CC0 */`
		1581	`/#define TIMERA0_ISR(func) ISR_VECTOR(func, ".int25") / /* 0xFFF2 Timer A CC0 / / CCE V2 Style */`
		1582	`#endif`
		1583	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1584	`#define WDT_VECTOR ".int26" /* 0xFFF4 Watchdog Timer */`
		1585	`#else`
		1586	`#define WDT_VECTOR (26 * 1u) /* 0xFFF4 Watchdog Timer */`
		1587	`/#define WDT_ISR(func) ISR_VECTOR(func, ".int26") / /* 0xFFF4 Watchdog Timer / / CCE V2 Style */`
		1588	`#endif`
		1589	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1590	`#define COMPARATORA_VECTOR ".int27" /* 0xFFF6 Comparator A */`
		1591	`#else`
		1592	`#define COMPARATORA_VECTOR (27 * 1u) /* 0xFFF6 Comparator A */`
		1593	`/#define COMPARATORA_ISR(func) ISR_VECTOR(func, ".int27") / /* 0xFFF6 Comparator A / / CCE V2 Style */`
		1594	`#endif`
		1595	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1596	`#define TIMERB1_VECTOR ".int28" /* 0xFFF8 Timer B CC1-6, TB */`
		1597	`#else`
		1598	`#define TIMERB1_VECTOR (28 * 1u) /* 0xFFF8 Timer B CC1-6, TB */`
		1599	`/#define TIMERB1_ISR(func) ISR_VECTOR(func, ".int28") / /* 0xFFF8 Timer B CC1-6, TB / / CCE V2 Style */`
		1600	`#endif`
		1601	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1602	`#define TIMERB0_VECTOR ".int29" /* 0xFFFA Timer B CC0 */`
		1603	`#else`
		1604	`#define TIMERB0_VECTOR (29 * 1u) /* 0xFFFA Timer B CC0 */`
		1605	`/#define TIMERB0_ISR(func) ISR_VECTOR(func, ".int29") / /* 0xFFFA Timer B CC0 / / CCE V2 Style */`
		1606	`#endif`
		1607	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1608	`#define NMI_VECTOR ".int30" /* 0xFFFC Non-maskable */`
		1609	`#else`
		1610	`#define NMI_VECTOR (30 * 1u) /* 0xFFFC Non-maskable */`
		1611	`/#define NMI_ISR(func) ISR_VECTOR(func, ".int30") / /* 0xFFFC Non-maskable / / CCE V2 Style */`
		1612	`#endif`
		1613	`#ifdef __ASM_HEADER__ /* Begin #defines for assembler */`
		1614	`#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */`
		1615	`#else`
		1616	`#define RESET_VECTOR (31 * 1u) /* 0xFFFE Reset [Highest Priority] */`
		1617	`/#define RESET_ISR(func) ISR_VECTOR(func, ".int31") / /* 0xFFFE Reset [Highest Priority] / / CCE V2 Style */`
		1618	`#endif`
		1619
		1620	`/************************************************************`
		1621	`* End of Modules`
		1622	`************************************************************/`
		1623
		1624	`#ifdef __cplusplus`
		1625	`}`
		1626	`#endif /* extern "C" */`
		1627
		1628	`#endif /* #ifndef __msp430x26x */`
		1629

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(root)/TexasInstrumentsMsp430/trunk/src/ccsv4/msp430/include/msp430f2617.h – Rev 2850