| 2850 |
dpurdie |
1 |
/********************************************************************
|
|
|
2 |
*
|
|
|
3 |
* Standard register and bit definitions for the Texas Instruments
|
|
|
4 |
* MSP430 microcontroller.
|
|
|
5 |
*
|
|
|
6 |
* This file supports assembler and C development for
|
|
|
7 |
* MSP430x20x1 devices.
|
|
|
8 |
*
|
|
|
9 |
* Texas Instruments, Version 1.2
|
|
|
10 |
*
|
|
|
11 |
* Rev. 1.0, Setup
|
|
|
12 |
* Rev. 1.1, Removed some TACCx2 definition on TA2 module
|
|
|
13 |
* Rev. 1.2, added definitions for Interrupt Vectors xxIV
|
|
|
14 |
*
|
|
|
15 |
********************************************************************/
|
|
|
16 |
|
|
|
17 |
#ifndef __msp430x20x1
|
|
|
18 |
#define __msp430x20x1
|
|
|
19 |
|
|
|
20 |
#ifdef __cplusplus
|
|
|
21 |
extern "C" {
|
|
|
22 |
#endif
|
|
|
23 |
|
|
|
24 |
|
|
|
25 |
/*----------------------------------------------------------------------------*/
|
|
|
26 |
/* PERIPHERAL FILE MAP */
|
|
|
27 |
/*----------------------------------------------------------------------------*/
|
|
|
28 |
|
|
|
29 |
/* External references resolved by a device-specific linker command file */
|
|
|
30 |
#define SFR_8BIT(address) extern volatile unsigned char address
|
|
|
31 |
#define SFR_16BIT(address) extern volatile unsigned int address
|
|
|
32 |
|
|
|
33 |
|
|
|
34 |
/************************************************************
|
|
|
35 |
* STANDARD BITS
|
|
|
36 |
************************************************************/
|
|
|
37 |
|
|
|
38 |
#define BIT0 (0x0001)
|
|
|
39 |
#define BIT1 (0x0002)
|
|
|
40 |
#define BIT2 (0x0004)
|
|
|
41 |
#define BIT3 (0x0008)
|
|
|
42 |
#define BIT4 (0x0010)
|
|
|
43 |
#define BIT5 (0x0020)
|
|
|
44 |
#define BIT6 (0x0040)
|
|
|
45 |
#define BIT7 (0x0080)
|
|
|
46 |
#define BIT8 (0x0100)
|
|
|
47 |
#define BIT9 (0x0200)
|
|
|
48 |
#define BITA (0x0400)
|
|
|
49 |
#define BITB (0x0800)
|
|
|
50 |
#define BITC (0x1000)
|
|
|
51 |
#define BITD (0x2000)
|
|
|
52 |
#define BITE (0x4000)
|
|
|
53 |
#define BITF (0x8000)
|
|
|
54 |
|
|
|
55 |
/************************************************************
|
|
|
56 |
* STATUS REGISTER BITS
|
|
|
57 |
************************************************************/
|
|
|
58 |
|
|
|
59 |
#define C (0x0001)
|
|
|
60 |
#define Z (0x0002)
|
|
|
61 |
#define N (0x0004)
|
|
|
62 |
#define V (0x0100)
|
|
|
63 |
#define GIE (0x0008)
|
|
|
64 |
#define CPUOFF (0x0010)
|
|
|
65 |
#define OSCOFF (0x0020)
|
|
|
66 |
#define SCG0 (0x0040)
|
|
|
67 |
#define SCG1 (0x0080)
|
|
|
68 |
|
|
|
69 |
/* Low Power Modes coded with Bits 4-7 in SR */
|
|
|
70 |
|
|
|
71 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
72 |
#define LPM0 (CPUOFF)
|
|
|
73 |
#define LPM1 (SCG0+CPUOFF)
|
|
|
74 |
#define LPM2 (SCG1+CPUOFF)
|
|
|
75 |
#define LPM3 (SCG1+SCG0+CPUOFF)
|
|
|
76 |
#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
|
|
|
77 |
/* End #defines for assembler */
|
|
|
78 |
|
|
|
79 |
#else /* Begin #defines for C */
|
|
|
80 |
#define LPM0_bits (CPUOFF)
|
|
|
81 |
#define LPM1_bits (SCG0+CPUOFF)
|
|
|
82 |
#define LPM2_bits (SCG1+CPUOFF)
|
|
|
83 |
#define LPM3_bits (SCG1+SCG0+CPUOFF)
|
|
|
84 |
#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
|
|
|
85 |
|
|
|
86 |
#include "in430.h"
|
|
|
87 |
|
|
|
88 |
#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
|
|
|
89 |
#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
|
|
|
90 |
#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
|
|
|
91 |
#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
|
|
|
92 |
#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
|
|
|
93 |
#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
|
|
|
94 |
#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
|
|
|
95 |
#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
|
|
|
96 |
#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
|
|
|
97 |
#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
|
|
|
98 |
#endif /* End #defines for C */
|
|
|
99 |
|
|
|
100 |
/************************************************************
|
|
|
101 |
* PERIPHERAL FILE MAP
|
|
|
102 |
************************************************************/
|
|
|
103 |
|
|
|
104 |
/************************************************************
|
|
|
105 |
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
|
|
|
106 |
************************************************************/
|
|
|
107 |
|
|
|
108 |
SFR_8BIT(IE1); /* Interrupt Enable 1 */
|
|
|
109 |
#define WDTIE (0x01) /* Watchdog Interrupt Enable */
|
|
|
110 |
#define OFIE (0x02) /* Osc. Fault Interrupt Enable */
|
|
|
111 |
#define NMIIE (0x10) /* NMI Interrupt Enable */
|
|
|
112 |
#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */
|
|
|
113 |
|
|
|
114 |
SFR_8BIT(IFG1); /* Interrupt Flag 1 */
|
|
|
115 |
#define WDTIFG (0x01) /* Watchdog Interrupt Flag */
|
|
|
116 |
#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */
|
|
|
117 |
#define PORIFG (0x04) /* Power On Interrupt Flag */
|
|
|
118 |
#define RSTIFG (0x08) /* Reset Interrupt Flag */
|
|
|
119 |
#define NMIIFG (0x10) /* NMI Interrupt Flag */
|
|
|
120 |
|
|
|
121 |
/************************************************************
|
|
|
122 |
* Basic Clock Module
|
|
|
123 |
************************************************************/
|
|
|
124 |
#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */
|
|
|
125 |
|
|
|
126 |
SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */
|
|
|
127 |
SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */
|
|
|
128 |
SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */
|
|
|
129 |
SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */
|
|
|
130 |
|
|
|
131 |
#define MOD0 (0x01) /* Modulation Bit 0 */
|
|
|
132 |
#define MOD1 (0x02) /* Modulation Bit 1 */
|
|
|
133 |
#define MOD2 (0x04) /* Modulation Bit 2 */
|
|
|
134 |
#define MOD3 (0x08) /* Modulation Bit 3 */
|
|
|
135 |
#define MOD4 (0x10) /* Modulation Bit 4 */
|
|
|
136 |
#define DCO0 (0x20) /* DCO Select Bit 0 */
|
|
|
137 |
#define DCO1 (0x40) /* DCO Select Bit 1 */
|
|
|
138 |
#define DCO2 (0x80) /* DCO Select Bit 2 */
|
|
|
139 |
|
|
|
140 |
#define RSEL0 (0x01) /* Range Select Bit 0 */
|
|
|
141 |
#define RSEL1 (0x02) /* Range Select Bit 1 */
|
|
|
142 |
#define RSEL2 (0x04) /* Range Select Bit 2 */
|
|
|
143 |
#define RSEL3 (0x08) /* Range Select Bit 3 */
|
|
|
144 |
#define DIVA0 (0x10) /* ACLK Divider 0 */
|
|
|
145 |
#define DIVA1 (0x20) /* ACLK Divider 1 */
|
|
|
146 |
#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */
|
|
|
147 |
#define XT2OFF (0x80) /* Enable XT2CLK */
|
|
|
148 |
|
|
|
149 |
#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */
|
|
|
150 |
#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */
|
|
|
151 |
#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */
|
|
|
152 |
#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */
|
|
|
153 |
|
|
|
154 |
#define DIVS0 (0x02) /* SMCLK Divider 0 */
|
|
|
155 |
#define DIVS1 (0x04) /* SMCLK Divider 1 */
|
|
|
156 |
#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
|
|
|
157 |
#define DIVM0 (0x10) /* MCLK Divider 0 */
|
|
|
158 |
#define DIVM1 (0x20) /* MCLK Divider 1 */
|
|
|
159 |
#define SELM0 (0x40) /* MCLK Source Select 0 */
|
|
|
160 |
#define SELM1 (0x80) /* MCLK Source Select 1 */
|
|
|
161 |
|
|
|
162 |
#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */
|
|
|
163 |
#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */
|
|
|
164 |
#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */
|
|
|
165 |
#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */
|
|
|
166 |
|
|
|
167 |
#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */
|
|
|
168 |
#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */
|
|
|
169 |
#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */
|
|
|
170 |
#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */
|
|
|
171 |
|
|
|
172 |
#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */
|
|
|
173 |
#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */
|
|
|
174 |
#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
|
|
|
175 |
#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */
|
|
|
176 |
|
|
|
177 |
#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */
|
|
|
178 |
#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */
|
|
|
179 |
#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */
|
|
|
180 |
#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */
|
|
|
181 |
#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */
|
|
|
182 |
#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */
|
|
|
183 |
#define XT2S0 (0x40) /* Mode 0 for XT2 */
|
|
|
184 |
#define XT2S1 (0x80) /* Mode 1 for XT2 */
|
|
|
185 |
|
|
|
186 |
#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */
|
|
|
187 |
#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */
|
|
|
188 |
#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */
|
|
|
189 |
#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */
|
|
|
190 |
|
|
|
191 |
#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */
|
|
|
192 |
#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */
|
|
|
193 |
#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */
|
|
|
194 |
#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */
|
|
|
195 |
|
|
|
196 |
#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */
|
|
|
197 |
#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */
|
|
|
198 |
#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */
|
|
|
199 |
#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */
|
|
|
200 |
|
|
|
201 |
/************************************************************
|
|
|
202 |
* Comparator A
|
|
|
203 |
************************************************************/
|
|
|
204 |
#define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */
|
|
|
205 |
|
|
|
206 |
SFR_8BIT(CACTL1); /* Comparator A Control 1 */
|
|
|
207 |
SFR_8BIT(CACTL2); /* Comparator A Control 2 */
|
|
|
208 |
SFR_8BIT(CAPD); /* Comparator A Port Disable */
|
|
|
209 |
|
|
|
210 |
#define CAIFG (0x01) /* Comp. A Interrupt Flag */
|
|
|
211 |
#define CAIE (0x02) /* Comp. A Interrupt Enable */
|
|
|
212 |
#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
|
|
|
213 |
#define CAON (0x08) /* Comp. A enable */
|
|
|
214 |
#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
|
|
|
215 |
#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
|
|
|
216 |
#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
|
|
|
217 |
#define CAEX (0x80) /* Comp. A Exchange Inputs */
|
|
|
218 |
|
|
|
219 |
#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
|
|
|
220 |
#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
|
|
|
221 |
#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
|
|
|
222 |
#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
|
|
|
223 |
|
|
|
224 |
#define CAOUT (0x01) /* Comp. A Output */
|
|
|
225 |
#define CAF (0x02) /* Comp. A Enable Output Filter */
|
|
|
226 |
#define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */
|
|
|
227 |
#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */
|
|
|
228 |
#define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */
|
|
|
229 |
#define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */
|
|
|
230 |
#define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */
|
|
|
231 |
#define CASHORT (0x80) /* Comp. A Short + and - Terminals */
|
|
|
232 |
|
|
|
233 |
#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
|
|
|
234 |
#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
|
|
|
235 |
#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
|
|
|
236 |
#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
|
|
|
237 |
#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
|
|
|
238 |
#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
|
|
|
239 |
#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
|
|
|
240 |
#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
|
|
|
241 |
|
|
|
242 |
/*************************************************************
|
|
|
243 |
* Flash Memory
|
|
|
244 |
*************************************************************/
|
|
|
245 |
#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */
|
|
|
246 |
|
|
|
247 |
SFR_16BIT(FCTL1); /* FLASH Control 1 */
|
|
|
248 |
SFR_16BIT(FCTL2); /* FLASH Control 2 */
|
|
|
249 |
SFR_16BIT(FCTL3); /* FLASH Control 3 */
|
|
|
250 |
|
|
|
251 |
#define FRKEY (0x9600) /* Flash key returned by read */
|
|
|
252 |
#define FWKEY (0xA500) /* Flash key for write */
|
|
|
253 |
#define FXKEY (0x3300) /* for use with XOR instruction */
|
|
|
254 |
|
|
|
255 |
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
|
|
|
256 |
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
|
|
|
257 |
#define WRT (0x0040) /* Enable bit for Flash write */
|
|
|
258 |
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
|
|
|
259 |
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
|
|
|
260 |
|
|
|
261 |
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
|
|
|
262 |
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
|
|
|
263 |
#ifndef FN2
|
|
|
264 |
#define FN2 (0x0004)
|
|
|
265 |
#endif
|
|
|
266 |
#ifndef FN3
|
|
|
267 |
#define FN3 (0x0008)
|
|
|
268 |
#endif
|
|
|
269 |
#ifndef FN4
|
|
|
270 |
#define FN4 (0x0010)
|
|
|
271 |
#endif
|
|
|
272 |
#define FN5 (0x0020)
|
|
|
273 |
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
|
|
|
274 |
#define FSSEL1 (0x0080) /* Flash clock select 1 */
|
|
|
275 |
|
|
|
276 |
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
|
|
|
277 |
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
|
|
|
278 |
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
|
|
|
279 |
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
|
|
|
280 |
|
|
|
281 |
#define BUSY (0x0001) /* Flash busy: 1 */
|
|
|
282 |
#define KEYV (0x0002) /* Flash Key violation flag */
|
|
|
283 |
#define ACCVIFG (0x0004) /* Flash Access violation flag */
|
|
|
284 |
#define WAIT (0x0008) /* Wait flag for segment write */
|
|
|
285 |
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
|
|
|
286 |
#define EMEX (0x0020) /* Flash Emergency Exit */
|
|
|
287 |
#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
|
|
|
288 |
#define FAIL (0x0080) /* Last Program or Erase failed */
|
|
|
289 |
|
|
|
290 |
/************************************************************
|
|
|
291 |
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
|
|
|
292 |
************************************************************/
|
|
|
293 |
#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
|
|
|
294 |
#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
|
|
|
295 |
|
|
|
296 |
SFR_8BIT(P1IN); /* Port 1 Input */
|
|
|
297 |
SFR_8BIT(P1OUT); /* Port 1 Output */
|
|
|
298 |
SFR_8BIT(P1DIR); /* Port 1 Direction */
|
|
|
299 |
SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */
|
|
|
300 |
SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */
|
|
|
301 |
SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */
|
|
|
302 |
SFR_8BIT(P1SEL); /* Port 1 Selection */
|
|
|
303 |
SFR_8BIT(P1REN); /* Port 1 Resistor Enable */
|
|
|
304 |
|
|
|
305 |
SFR_8BIT(P2IN); /* Port 2 Input */
|
|
|
306 |
SFR_8BIT(P2OUT); /* Port 2 Output */
|
|
|
307 |
SFR_8BIT(P2DIR); /* Port 2 Direction */
|
|
|
308 |
SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */
|
|
|
309 |
SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */
|
|
|
310 |
SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */
|
|
|
311 |
SFR_8BIT(P2SEL); /* Port 2 Selection */
|
|
|
312 |
SFR_8BIT(P2REN); /* Port 2 Resistor Enable */
|
|
|
313 |
|
|
|
314 |
/************************************************************
|
|
|
315 |
* Timer A2
|
|
|
316 |
************************************************************/
|
|
|
317 |
#define __MSP430_HAS_TA2__ /* Definition to show that Module is available */
|
|
|
318 |
|
|
|
319 |
SFR_16BIT(TAIV); /* Timer A Interrupt Vector Word */
|
|
|
320 |
SFR_16BIT(TACTL); /* Timer A Control */
|
|
|
321 |
SFR_16BIT(TACCTL0); /* Timer A Capture/Compare Control 0 */
|
|
|
322 |
SFR_16BIT(TACCTL1); /* Timer A Capture/Compare Control 1 */
|
|
|
323 |
SFR_16BIT(TAR); /* Timer A Counter Register */
|
|
|
324 |
SFR_16BIT(TACCR0); /* Timer A Capture/Compare 0 */
|
|
|
325 |
SFR_16BIT(TACCR1); /* Timer A Capture/Compare 1 */
|
|
|
326 |
|
|
|
327 |
/* Alternate register names */
|
|
|
328 |
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
329 |
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
330 |
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
331 |
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
332 |
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
333 |
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
334 |
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
335 |
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
336 |
/* Alternate register names - 5xx style */
|
|
|
337 |
#define TA0IV TAIV /* Timer A Interrupt Vector Word */
|
|
|
338 |
#define TA0CTL TACTL /* Timer A Control */
|
|
|
339 |
#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
|
|
|
340 |
#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
|
|
|
341 |
#define TA0R TAR /* Timer A Counter Register */
|
|
|
342 |
#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */
|
|
|
343 |
#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */
|
|
|
344 |
#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */
|
|
|
345 |
#define TA0CTL_ TACTL_ /* Timer A Control */
|
|
|
346 |
#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
|
|
|
347 |
#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
|
|
|
348 |
#define TA0R_ TAR_ /* Timer A Counter Register */
|
|
|
349 |
#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
|
|
|
350 |
#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
|
|
|
351 |
|
|
|
352 |
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
|
|
|
353 |
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
|
|
|
354 |
#define ID1 (0x0080) /* Timer A clock input divider 1 */
|
|
|
355 |
#define ID0 (0x0040) /* Timer A clock input divider 0 */
|
|
|
356 |
#define MC1 (0x0020) /* Timer A mode control 1 */
|
|
|
357 |
#define MC0 (0x0010) /* Timer A mode control 0 */
|
|
|
358 |
#define TACLR (0x0004) /* Timer A counter clear */
|
|
|
359 |
#define TAIE (0x0002) /* Timer A counter interrupt enable */
|
|
|
360 |
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
|
|
|
361 |
|
|
|
362 |
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
|
|
|
363 |
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
|
|
|
364 |
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
|
|
|
365 |
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
|
|
|
366 |
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
|
|
|
367 |
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
|
|
|
368 |
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
|
|
|
369 |
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
|
|
|
370 |
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
|
|
|
371 |
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
|
|
|
372 |
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
|
|
|
373 |
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
|
|
|
374 |
|
|
|
375 |
#define CM1 (0x8000) /* Capture mode 1 */
|
|
|
376 |
#define CM0 (0x4000) /* Capture mode 0 */
|
|
|
377 |
#define CCIS1 (0x2000) /* Capture input select 1 */
|
|
|
378 |
#define CCIS0 (0x1000) /* Capture input select 0 */
|
|
|
379 |
#define SCS (0x0800) /* Capture sychronize */
|
|
|
380 |
#define SCCI (0x0400) /* Latched capture signal (read) */
|
|
|
381 |
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
|
|
|
382 |
#define OUTMOD2 (0x0080) /* Output mode 2 */
|
|
|
383 |
#define OUTMOD1 (0x0040) /* Output mode 1 */
|
|
|
384 |
#define OUTMOD0 (0x0020) /* Output mode 0 */
|
|
|
385 |
#define CCIE (0x0010) /* Capture/compare interrupt enable */
|
|
|
386 |
#define CCI (0x0008) /* Capture input signal (read) */
|
|
|
387 |
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
|
|
|
388 |
#define COV (0x0002) /* Capture/compare overflow flag */
|
|
|
389 |
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
|
|
|
390 |
|
|
|
391 |
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
|
|
|
392 |
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
|
|
|
393 |
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
|
|
|
394 |
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
|
|
|
395 |
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
|
|
|
396 |
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
|
|
|
397 |
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
|
|
|
398 |
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
|
|
|
399 |
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
|
|
|
400 |
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
|
|
|
401 |
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
|
|
|
402 |
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
|
|
|
403 |
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
|
|
|
404 |
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
|
|
|
405 |
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
|
|
|
406 |
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
|
|
|
407 |
|
|
|
408 |
/* TA2IV Definitions */
|
|
|
409 |
#define TAIV_NONE (0x0000) /* No Interrupt pending */
|
|
|
410 |
#define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */
|
|
|
411 |
#define TAIV_2 (0x0004) /* Reserved */
|
|
|
412 |
#define TAIV_6 (0x0006) /* Reserved */
|
|
|
413 |
#define TAIV_8 (0x0008) /* Reserved */
|
|
|
414 |
#define TAIV_TAIFG (0x000A) /* TAIFG */
|
|
|
415 |
|
|
|
416 |
/************************************************************
|
|
|
417 |
* WATCHDOG TIMER
|
|
|
418 |
************************************************************/
|
|
|
419 |
#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
|
|
|
420 |
|
|
|
421 |
SFR_16BIT(WDTCTL); /* Watchdog Timer Control */
|
|
|
422 |
/* The bit names have been prefixed with "WDT" */
|
|
|
423 |
#define WDTIS0 (0x0001)
|
|
|
424 |
#define WDTIS1 (0x0002)
|
|
|
425 |
#define WDTSSEL (0x0004)
|
|
|
426 |
#define WDTCNTCL (0x0008)
|
|
|
427 |
#define WDTTMSEL (0x0010)
|
|
|
428 |
#define WDTNMI (0x0020)
|
|
|
429 |
#define WDTNMIES (0x0040)
|
|
|
430 |
#define WDTHOLD (0x0080)
|
|
|
431 |
|
|
|
432 |
#define WDTPW (0x5A00)
|
|
|
433 |
|
|
|
434 |
/* WDT-interval times [1ms] coded with Bits 0-2 */
|
|
|
435 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
436 |
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
|
|
|
437 |
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
|
|
|
438 |
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
|
|
|
439 |
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
440 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
441 |
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
|
|
|
442 |
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
|
|
|
443 |
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
|
|
|
444 |
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
445 |
/* Watchdog mode -> reset after expired time */
|
|
|
446 |
/* WDT is clocked by fSMCLK (assumed 1MHz) */
|
|
|
447 |
#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
|
|
|
448 |
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
|
|
|
449 |
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
|
|
|
450 |
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
|
|
|
451 |
/* WDT is clocked by fACLK (assumed 32KHz) */
|
|
|
452 |
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
|
|
|
453 |
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
|
|
|
454 |
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
|
|
|
455 |
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
|
|
|
456 |
|
|
|
457 |
/* INTERRUPT CONTROL */
|
|
|
458 |
/* These two bits are defined in the Special Function Registers */
|
|
|
459 |
/* #define WDTIE 0x01 */
|
|
|
460 |
/* #define WDTIFG 0x01 */
|
|
|
461 |
|
|
|
462 |
/************************************************************
|
|
|
463 |
* Calibration Data in Info Mem
|
|
|
464 |
************************************************************/
|
|
|
465 |
|
|
|
466 |
#ifndef __DisableCalData
|
|
|
467 |
|
|
|
468 |
SFR_8BIT(CALDCO_16MHZ); /* DCOCTL Calibration Data for 16MHz */
|
|
|
469 |
SFR_8BIT(CALBC1_16MHZ); /* BCSCTL1 Calibration Data for 16MHz */
|
|
|
470 |
SFR_8BIT(CALDCO_12MHZ); /* DCOCTL Calibration Data for 12MHz */
|
|
|
471 |
SFR_8BIT(CALBC1_12MHZ); /* BCSCTL1 Calibration Data for 12MHz */
|
|
|
472 |
SFR_8BIT(CALDCO_8MHZ); /* DCOCTL Calibration Data for 8MHz */
|
|
|
473 |
SFR_8BIT(CALBC1_8MHZ); /* BCSCTL1 Calibration Data for 8MHz */
|
|
|
474 |
SFR_8BIT(CALDCO_1MHZ); /* DCOCTL Calibration Data for 1MHz */
|
|
|
475 |
SFR_8BIT(CALBC1_1MHZ); /* BCSCTL1 Calibration Data for 1MHz */
|
|
|
476 |
|
|
|
477 |
#endif /* #ifndef __DisableCalData */
|
|
|
478 |
|
|
|
479 |
/************************************************************
|
|
|
480 |
* Interrupt Vectors (offset from 0xFFE0)
|
|
|
481 |
************************************************************/
|
|
|
482 |
|
|
|
483 |
#define VECTOR_NAME(name) name##_ptr
|
|
|
484 |
#define EMIT_PRAGMA(x) _Pragma(#x)
|
|
|
485 |
#define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name
|
|
|
486 |
#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section))
|
|
|
487 |
#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \
|
|
|
488 |
PLACE_VECTOR(VECTOR_NAME(func), offset)
|
|
|
489 |
|
|
|
490 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
491 |
#define PORT1_VECTOR ".int02" /* 0xFFE4 Port 1 */
|
|
|
492 |
#else
|
|
|
493 |
#define PORT1_VECTOR (2 * 1u) /* 0xFFE4 Port 1 */
|
|
|
494 |
/*#define PORT1_ISR(func) ISR_VECTOR(func, ".int02") */ /* 0xFFE4 Port 1 */ /* CCE V2 Style */
|
|
|
495 |
#endif
|
|
|
496 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
497 |
#define PORT2_VECTOR ".int03" /* 0xFFE6 Port 2 */
|
|
|
498 |
#else
|
|
|
499 |
#define PORT2_VECTOR (3 * 1u) /* 0xFFE6 Port 2 */
|
|
|
500 |
/*#define PORT2_ISR(func) ISR_VECTOR(func, ".int03") */ /* 0xFFE6 Port 2 */ /* CCE V2 Style */
|
|
|
501 |
#endif
|
|
|
502 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
503 |
#define TIMERA1_VECTOR ".int08" /* 0xFFF0 Timer A CC1-2, TA */
|
|
|
504 |
#else
|
|
|
505 |
#define TIMERA1_VECTOR (8 * 1u) /* 0xFFF0 Timer A CC1-2, TA */
|
|
|
506 |
/*#define TIMERA1_ISR(func) ISR_VECTOR(func, ".int08") */ /* 0xFFF0 Timer A CC1-2, TA */ /* CCE V2 Style */
|
|
|
507 |
#endif
|
|
|
508 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
509 |
#define TIMERA0_VECTOR ".int09" /* 0xFFF2 Timer A CC0 */
|
|
|
510 |
#else
|
|
|
511 |
#define TIMERA0_VECTOR (9 * 1u) /* 0xFFF2 Timer A CC0 */
|
|
|
512 |
/*#define TIMERA0_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 Timer A CC0 */ /* CCE V2 Style */
|
|
|
513 |
#endif
|
|
|
514 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
515 |
#define WDT_VECTOR ".int10" /* 0xFFF4 Watchdog Timer */
|
|
|
516 |
#else
|
|
|
517 |
#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */
|
|
|
518 |
/*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
|
|
|
519 |
#endif
|
|
|
520 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
521 |
#define COMPARATORA_VECTOR ".int11" /* 0xFFF6 Comparator A */
|
|
|
522 |
#else
|
|
|
523 |
#define COMPARATORA_VECTOR (11 * 1u) /* 0xFFF6 Comparator A */
|
|
|
524 |
/*#define COMPARATORA_ISR(func) ISR_VECTOR(func, ".int11") */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */
|
|
|
525 |
#endif
|
|
|
526 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
527 |
#define NMI_VECTOR ".int14" /* 0xFFFC Non-maskable */
|
|
|
528 |
#else
|
|
|
529 |
#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */
|
|
|
530 |
/*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */
|
|
|
531 |
#endif
|
|
|
532 |
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
|
|
|
533 |
#define RESET_VECTOR ".reset" /* 0xFFFE Reset [Highest Priority] */
|
|
|
534 |
#else
|
|
|
535 |
#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */
|
|
|
536 |
/*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
|
|
|
537 |
#endif
|
|
|
538 |
|
|
|
539 |
/************************************************************
|
|
|
540 |
* End of Modules
|
|
|
541 |
************************************************************/
|
|
|
542 |
|
|
|
543 |
#ifdef __cplusplus
|
|
|
544 |
}
|
|
|
545 |
#endif /* extern "C" */
|
|
|
546 |
|
|
|
547 |
#endif /* #ifndef __msp430x20x1 */
|
|
|
548 |
|