| 2850 |
dpurdie |
1 |
/******************************************************************************/
|
|
|
2 |
/* msp430f122.cmd */
|
|
|
3 |
/* - Linker Command File for defintions in the header file */
|
|
|
4 |
/* Please do not change ! */
|
|
|
5 |
/* */
|
|
|
6 |
/******************************************************************************/
|
|
|
7 |
|
|
|
8 |
|
|
|
9 |
/************************************************************
|
|
|
10 |
* STANDARD BITS
|
|
|
11 |
************************************************************/
|
|
|
12 |
/************************************************************
|
|
|
13 |
* STATUS REGISTER BITS
|
|
|
14 |
************************************************************/
|
|
|
15 |
/************************************************************
|
|
|
16 |
* PERIPHERAL FILE MAP
|
|
|
17 |
************************************************************/
|
|
|
18 |
/************************************************************
|
|
|
19 |
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
|
|
|
20 |
************************************************************/
|
|
|
21 |
IE1 = 0x0000;
|
|
|
22 |
IFG1 = 0x0002;
|
|
|
23 |
IE2 = 0x0001;
|
|
|
24 |
IFG2 = 0x0003;
|
|
|
25 |
ME2 = 0x0005;
|
|
|
26 |
/************************************************************
|
|
|
27 |
* WATCHDOG TIMER
|
|
|
28 |
************************************************************/
|
|
|
29 |
WDTCTL = 0x0120;
|
|
|
30 |
/************************************************************
|
|
|
31 |
* DIGITAL I/O Port1/2
|
|
|
32 |
************************************************************/
|
|
|
33 |
P1IN = 0x0020;
|
|
|
34 |
P1OUT = 0x0021;
|
|
|
35 |
P1DIR = 0x0022;
|
|
|
36 |
P1IFG = 0x0023;
|
|
|
37 |
P1IES = 0x0024;
|
|
|
38 |
P1IE = 0x0025;
|
|
|
39 |
P1SEL = 0x0026;
|
|
|
40 |
P2IN = 0x0028;
|
|
|
41 |
P2OUT = 0x0029;
|
|
|
42 |
P2DIR = 0x002A;
|
|
|
43 |
P2IFG = 0x002B;
|
|
|
44 |
P2IES = 0x002C;
|
|
|
45 |
P2IE = 0x002D;
|
|
|
46 |
P2SEL = 0x002E;
|
|
|
47 |
/************************************************************
|
|
|
48 |
* DIGITAL I/O Port3
|
|
|
49 |
************************************************************/
|
|
|
50 |
P3IN = 0x0018;
|
|
|
51 |
P3OUT = 0x0019;
|
|
|
52 |
P3DIR = 0x001A;
|
|
|
53 |
P3SEL = 0x001B;
|
|
|
54 |
/************************************************************
|
|
|
55 |
* USART
|
|
|
56 |
************************************************************/
|
|
|
57 |
/************************************************************
|
|
|
58 |
* USART 0
|
|
|
59 |
************************************************************/
|
|
|
60 |
U0CTL = 0x0070;
|
|
|
61 |
U0TCTL = 0x0071;
|
|
|
62 |
U0RCTL = 0x0072;
|
|
|
63 |
U0MCTL = 0x0073;
|
|
|
64 |
U0BR0 = 0x0074;
|
|
|
65 |
U0BR1 = 0x0075;
|
|
|
66 |
U0RXBUF = 0x0076;
|
|
|
67 |
U0TXBUF = 0x0077;
|
|
|
68 |
/************************************************************
|
|
|
69 |
* Timer A3
|
|
|
70 |
************************************************************/
|
|
|
71 |
TAIV = 0x012E;
|
|
|
72 |
TACTL = 0x0160;
|
|
|
73 |
TACCTL0 = 0x0162;
|
|
|
74 |
TACCTL1 = 0x0164;
|
|
|
75 |
TACCTL2 = 0x0166;
|
|
|
76 |
TAR = 0x0170;
|
|
|
77 |
TACCR0 = 0x0172;
|
|
|
78 |
TACCR1 = 0x0174;
|
|
|
79 |
TACCR2 = 0x0176;
|
|
|
80 |
/************************************************************
|
|
|
81 |
* Basic Clock Module
|
|
|
82 |
************************************************************/
|
|
|
83 |
DCOCTL = 0x0056;
|
|
|
84 |
BCSCTL1 = 0x0057;
|
|
|
85 |
BCSCTL2 = 0x0058;
|
|
|
86 |
/*************************************************************
|
|
|
87 |
* Flash Memory
|
|
|
88 |
*************************************************************/
|
|
|
89 |
FCTL1 = 0x0128;
|
|
|
90 |
FCTL2 = 0x012A;
|
|
|
91 |
FCTL3 = 0x012C;
|
|
|
92 |
/************************************************************
|
|
|
93 |
* Comparator A
|
|
|
94 |
************************************************************/
|
|
|
95 |
CACTL1 = 0x0059;
|
|
|
96 |
CACTL2 = 0x005A;
|
|
|
97 |
CAPD = 0x005B;
|
|
|
98 |
/************************************************************
|
|
|
99 |
* Interrupt Vectors (offset from 0xFFE0)
|
|
|
100 |
************************************************************/
|
|
|
101 |
/************************************************************
|
|
|
102 |
* End of Modules
|
|
|
103 |
************************************************************/
|