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2850 dpurdie 1 
/********************************************************************
2 
*
3 
* Standard register and bit definitions for the Texas Instruments
4 
* MSP430 microcontroller.
5 
*
6 
* This file supports assembler and C development for
7 
* MSP430x09x devices.
8 
*
9 
* Texas Instruments, Version 1.1
10 
*
11 
* Rev. 1.0, Initial Release
12 
* Rev. 1.0, Added LCMP : A-POOL Latch comparator
13 
*
14 
*
15 
********************************************************************/
16 
 
17 
#ifndef __msp430x09x
18 
#define __msp430x09x
19 
 
20 
#ifdef __cplusplus
21 
extern "C" {
22 
#endif
23 
 
24 
 
25 
/*----------------------------------------------------------------------------*/
26 
/* PERIPHERAL FILE MAP                                                        */
27 
/*----------------------------------------------------------------------------*/
28 
 
29 
/* External references resolved by a device-specific linker command file */
30 
#define SFR_8BIT(address)   extern volatile unsigned char address
31 
#define SFR_16BIT(address)  extern volatile unsigned int address
32 
//#define SFR_20BIT(address)  extern volatile unsigned int address
33 
typedef void (* __SFR_FARPTR)();
34 
#define SFR_20BIT(address) extern __SFR_FARPTR address
35 
#define SFR_32BIT(address)  extern volatile unsigned long address
36 
 
37 
 
38 
 
39 
/************************************************************
40 
* STANDARD BITS
41 
************************************************************/
42 
 
43 
#define BIT0                   (0x0001)
44 
#define BIT1                   (0x0002)
45 
#define BIT2                   (0x0004)
46 
#define BIT3                   (0x0008)
47 
#define BIT4                   (0x0010)
48 
#define BIT5                   (0x0020)
49 
#define BIT6                   (0x0040)
50 
#define BIT7                   (0x0080)
51 
#define BIT8                   (0x0100)
52 
#define BIT9                   (0x0200)
53 
#define BITA                   (0x0400)
54 
#define BITB                   (0x0800)
55 
#define BITC                   (0x1000)
56 
#define BITD                   (0x2000)
57 
#define BITE                   (0x4000)
58 
#define BITF                   (0x8000)
59 
 
60 
/************************************************************
61 
* STATUS REGISTER BITS
62 
************************************************************/
63 
 
64 
#define C                      (0x0001)
65 
#define Z                      (0x0002)
66 
#define N                      (0x0004)
67 
#define V                      (0x0100)
68 
#define GIE                    (0x0008)
69 
#define CPUOFF                 (0x0010)
70 
#define OSCOFF                 (0x0020)
71 
#define SCG0                   (0x0040)
72 
#define SCG1                   (0x0080)
73 
 
74 
/* Low Power Modes coded with Bits 4-7 in SR */
75 
 
76 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
77 
#define LPM0                   (CPUOFF)
78 
#define LPM1                   (SCG0+CPUOFF)
79 
#define LPM2                   (SCG1+CPUOFF)
80 
#define LPM3                   (SCG1+SCG0+CPUOFF)
81 
#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
82 
/* End #defines for assembler */
83 
 
84 
#else /* Begin #defines for C */
85 
#define LPM0_bits              (CPUOFF)
86 
#define LPM1_bits              (SCG0+CPUOFF)
87 
#define LPM2_bits              (SCG1+CPUOFF)
88 
#define LPM3_bits              (SCG1+SCG0+CPUOFF)
89 
#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
90 
 
91 
#include "in430.h"
92 
 
93 
#define LPM0         _bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
94 
#define LPM0_EXIT    _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
95 
#define LPM1         _bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
96 
#define LPM1_EXIT    _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
97 
#define LPM2         _bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
98 
#define LPM2_EXIT    _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
99 
#define LPM3         _bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
100 
#define LPM3_EXIT    _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
101 
#define LPM4         _bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
102 
#define LPM4_EXIT    _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
103 
#endif /* End #defines for C */
104 
 
105 
/************************************************************
106 
* CPU
107 
************************************************************/
108 
#define __MSP430_HAS_MSP430XV2_CPU__                /* Definition to show that it has MSP430XV2 CPU */
109 
 
110 
/************************************************************
111 
* PERIPHERAL FILE MAP
112 
************************************************************/
113 
 
114 
/************************************************************
115 
* A-POOL
116 
************************************************************/
117 
#define __MSP430_HAS_APOOL__                  /* Definition to show that Module is available */
118 
#define __MSP430_BASEADDRESS_APOOL__ 0x01A0
119 
 
120 
SFR_16BIT(APCNF);                             /* A-POOL Configuration Register */
121 
SFR_8BIT(APCNF_L);                            /* A-POOL Configuration Register */
122 
SFR_8BIT(APCNF_H);                            /* A-POOL Configuration Register */
123 
SFR_16BIT(APCTL);                             /* A-POOL Control Register 1 */
124 
SFR_8BIT(APCTL_L);                            /* A-POOL Control Register 1 */
125 
SFR_8BIT(APCTL_H);                            /* A-POOL Control Register 1 */
126 
SFR_16BIT(APOMR);                             /* A-POOL Operation Mode Register 2 */
127 
SFR_8BIT(APOMR_L);                            /* A-POOL Operation Mode Register 2 */
128 
SFR_8BIT(APOMR_H);                            /* A-POOL Operation Mode Register 2 */
129 
SFR_16BIT(APVDIV);                            /* A-POOL Voltage Divider Register 3 */
130 
SFR_8BIT(APVDIV_L);                           /* A-POOL Voltage Divider Register 3 */
131 
SFR_8BIT(APVDIV_H);                           /* A-POOL Voltage Divider Register 3 */
132 
SFR_16BIT(APTRIM);                            /* A-POOL trimming register */
133 
SFR_8BIT(APTRIM_L);                           /* A-POOL trimming register */
134 
SFR_8BIT(APTRIM_H);                           /* A-POOL trimming register */
135 
SFR_16BIT(APINT);                             /* A-POOL Integer Conversion Register */
136 
SFR_8BIT(APINT_L);                            /* A-POOL Integer Conversion Register */
137 
SFR_8BIT(APINT_H);                            /* A-POOL Integer Conversion Register */
138 
SFR_16BIT(APINTB);                            /* A-POOL Integer Conversion Buffer Register */
139 
SFR_8BIT(APINTB_L);                           /* A-POOL Integer Conversion Buffer Register */
140 
SFR_8BIT(APINTB_H);                           /* A-POOL Integer Conversion Buffer Register */
141 
SFR_16BIT(APFRACT);                           /* A-POOL Fractional Conversion Register */
142 
SFR_8BIT(APFRACT_L);                          /* A-POOL Fractional Conversion Register */
143 
SFR_8BIT(APFRACT_H);                          /* A-POOL Fractional Conversion Register */
144 
SFR_16BIT(APFRACTB);                          /* A-POOL Fractional Conversion Buffer Register */
145 
SFR_8BIT(APFRACTB_L);                         /* A-POOL Fractional Conversion Buffer Register */
146 
SFR_8BIT(APFRACTB_H);                         /* A-POOL Fractional Conversion Buffer Register */
147 
SFR_16BIT(APIFG);                             /* A-POOL Interrupt Flag Register */
148 
SFR_8BIT(APIFG_L);                            /* A-POOL Interrupt Flag Register */
149 
SFR_8BIT(APIFG_H);                            /* A-POOL Interrupt Flag Register */
150 
SFR_16BIT(APIE);                              /* A-POOL Interrupt Enable Register */
151 
SFR_8BIT(APIE_L);                             /* A-POOL Interrupt Enable Register */
152 
SFR_8BIT(APIE_H);                             /* A-POOL Interrupt Enable Register */
153 
SFR_16BIT(APIV);                              /* A-POOL Interrupt Vector Word */
154 
SFR_8BIT(APIV_L);                             /* A-POOL Interrupt Vector Word */
155 
SFR_8BIT(APIV_H);                             /* A-POOL Interrupt Vector Word */
156 
 
157 
/* APCNF Control Bits */
158 
#define TA0EN                  (0x0001)       /* A-POOL TimerA0 trigger enable */
159 
#define TA1EN                  (0x0002)       /* A-POOL TimerA1 trigger enable */
160 
#define DFSET0                 (0x0004)       /* A-POOL Deglitch Filter Bit: 0 */
161 
#define DFSET1                 (0x0008)       /* A-POOL Deglitch Filter Bit: 1 */
162 
#define LCMP                   (0x0010)       /* A-POOL Latch comparator */
163 
#define CMPON                  (0x0020)       /* A-POOL Comparator enable */
164 
#define DBON                   (0x0040)       /* A-POOL DAC buffer enable signal */
165 
#define CONVON                 (0x0080)       /* A-POOL Enable for converter’s resistor ladder */
166 
#define CLKSEL0                (0x0100)       /* A-POOL Conversion clock select Bit: 0 */
167 
#define CLKSEL1                (0x0200)       /* A-POOL Conversion clock select Bit: 1 */
168 
#define EOCBU                  (0x0400)       /* A-POOL Enable bit for loading conversion buffer */
169 
#define ATBU                   (0x0800)       /* A-POOL Automatic update of conversion register */
170 
#define A3PSEL                 (0x1000)       /* A-POOL Analog input A3 access Bit */
171 
#define APREFON                (0x2000)       /* A-POOL Internal voltage reference enable */
172 
#define VREFEN                 (0x4000)       /* A-POOL Reference voltage pin enable */
173 
//#define RESERVED             (0x8000)  /* A-POOL */
174 
 
175 
/* APCNF Control Bits */
176 
#define TA0EN_L                (0x0001)       /* A-POOL TimerA0 trigger enable */
177 
#define TA1EN_L                (0x0002)       /* A-POOL TimerA1 trigger enable */
178 
#define DFSET0_L               (0x0004)       /* A-POOL Deglitch Filter Bit: 0 */
179 
#define DFSET1_L               (0x0008)       /* A-POOL Deglitch Filter Bit: 1 */
180 
#define LCMP_L                 (0x0010)       /* A-POOL Latch comparator */
181 
#define CMPON_L                (0x0020)       /* A-POOL Comparator enable */
182 
#define DBON_L                 (0x0040)       /* A-POOL DAC buffer enable signal */
183 
#define CONVON_L               (0x0080)       /* A-POOL Enable for converter’s resistor ladder */
184 
//#define RESERVED             (0x8000)  /* A-POOL */
185 
 
186 
/* APCNF Control Bits */
187 
#define CLKSEL0_H              (0x0001)       /* A-POOL Conversion clock select Bit: 0 */
188 
#define CLKSEL1_H              (0x0002)       /* A-POOL Conversion clock select Bit: 1 */
189 
#define EOCBU_H                (0x0004)       /* A-POOL Enable bit for loading conversion buffer */
190 
#define ATBU_H                 (0x0008)       /* A-POOL Automatic update of conversion register */
191 
#define A3PSEL_H               (0x0010)       /* A-POOL Analog input A3 access Bit */
192 
#define APREFON_H              (0x0020)       /* A-POOL Internal voltage reference enable */
193 
#define VREFEN_H               (0x0040)       /* A-POOL Reference voltage pin enable */
194 
//#define RESERVED             (0x8000)  /* A-POOL */
195 
 
196 
#define DFSET_0                (0x0000)       /* A-POOL Deglitch Filter select: 0 */
197 
#define DFSET_1                (0x0004)       /* A-POOL Deglitch Filter select: 1 */
198 
#define DFSET_2                (0x0008)       /* A-POOL Deglitch Filter select: 2 */
199 
#define DFSET_3                (0x000C)       /* A-POOL Deglitch Filter select: 3 */
200 
 
201 
#define CLKSEL_0               (0x0000)       /* A-POOL Conversion clock select: 0 */
202 
#define CLKSEL_1               (0x0100)       /* A-POOL Conversion clock select: 1 */
203 
#define CLKSEL_2               (0x0200)       /* A-POOL Conversion clock select: 2 */
204 
#define CLKSEL_VLOCLK          (0x0000)       /* A-POOL Conversion clock select: VLOCLK */
205 
#define CLKSEL_MCLK            (0x0100)       /* A-POOL Conversion clock select: MCLK */
206 
#define CLKSEL_SMCLK           (0x0200)       /* A-POOL Conversion clock select: SMCLK */
207 
 
208 
/* APCTL Control Bits */
209 
#define ODEN                   (0x0001)       /* A-POOL Output driver enable */
210 
#define OSWP                   (0x0002)       /* A-POOL Output swap */
211 
#define OSEL                   (0x0004)       /* A-POOL Output buffer select */
212 
#define SLOPE                  (0x0008)       /* A-POOL Slope select of converter */
213 
#define APNSEL0                (0x0010)       /* A-POOL Neg. Channel Input Select 0 */
214 
#define APNSEL1                (0x0020)       /* A-POOL Neg. Channel Input Select 1 */
215 
#define APNSEL2                (0x0040)       /* A-POOL Neg. Channel Input Select 2 */
216 
#define APNSEL3                (0x0080)       /* A-POOL Neg. Channel Input Select 3 */
217 
#define RUNSTOP                (0x0100)       /* A-POOL Converter’s Run/Stop bit */
218 
#define SBSTP                  (0x0200)       /* A-POOL Saturation based conversion stop enable */
219 
#define CBSTP                  (0x0400)       /* A-POOL Comparator based conversion stop enable */
220 
#define TBSTP                  (0x0800)       /* A-POOL Timer based conversion stop enable for TimerA0 */
221 
#define APPSEL0                (0x1000)       /* A-POOL Pos. Channel Input Select 0 */
222 
#define APPSEL1                (0x2000)       /* A-POOL Pos. Channel Input Select 1 */
223 
#define APPSEL2                (0x4000)       /* A-POOL Pos. Channel Input Select 2 */
224 
#define APPSEL3                (0x8000)       /* A-POOL Pos. Channel Input Select 3 */
225 
 
226 
/* APCTL Control Bits */
227 
#define ODEN_L                 (0x0001)       /* A-POOL Output driver enable */
228 
#define OSWP_L                 (0x0002)       /* A-POOL Output swap */
229 
#define OSEL_L                 (0x0004)       /* A-POOL Output buffer select */
230 
#define SLOPE_L                (0x0008)       /* A-POOL Slope select of converter */
231 
#define APNSEL0_L              (0x0010)       /* A-POOL Neg. Channel Input Select 0 */
232 
#define APNSEL1_L              (0x0020)       /* A-POOL Neg. Channel Input Select 1 */
233 
#define APNSEL2_L              (0x0040)       /* A-POOL Neg. Channel Input Select 2 */
234 
#define APNSEL3_L              (0x0080)       /* A-POOL Neg. Channel Input Select 3 */
235 
 
236 
/* APCTL Control Bits */
237 
#define RUNSTOP_H              (0x0001)       /* A-POOL Converter’s Run/Stop bit */
238 
#define SBSTP_H                (0x0002)       /* A-POOL Saturation based conversion stop enable */
239 
#define CBSTP_H                (0x0004)       /* A-POOL Comparator based conversion stop enable */
240 
#define TBSTP_H                (0x0008)       /* A-POOL Timer based conversion stop enable for TimerA0 */
241 
#define APPSEL0_H              (0x0010)       /* A-POOL Pos. Channel Input Select 0 */
242 
#define APPSEL1_H              (0x0020)       /* A-POOL Pos. Channel Input Select 1 */
243 
#define APPSEL2_H              (0x0040)       /* A-POOL Pos. Channel Input Select 2 */
244 
#define APPSEL3_H              (0x0080)       /* A-POOL Pos. Channel Input Select 3 */
245 
 
246 
#define APNSEL_0               (0x0000)       /* A-POOL V- terminal Input Select: Channel 0 */
247 
#define APNSEL_1               (0x0010)       /* A-POOL V- terminal Input Select: Channel 1 */
248 
#define APNSEL_2               (0x0020)       /* A-POOL V- terminal Input Select: Channel 2 */
249 
#define APNSEL_3               (0x0030)       /* A-POOL V- terminal Input Select: Channel 3 */
250 
#define APNSEL_4               (0x0040)       /* A-POOL V- terminal Input Select: Channel 4 */
251 
#define APNSEL_5               (0x0050)       /* A-POOL V- terminal Input Select: Channel 5 */
252 
#define APNSEL_6               (0x0060)       /* A-POOL V- terminal Input Select: Channel 6 */
253 
#define APNSEL_7               (0x0070)       /* A-POOL V- terminal Input Select: Channel 7 */
254 
 
255 
#define APPSEL_0               (0x0000)       /* A-POOL V+ Terminal Input Select: Channel 0 */
256 
#define APPSEL_1               (0x1000)       /* A-POOL V+ Terminal Input Select: Channel 1 */
257 
#define APPSEL_2               (0x2000)       /* A-POOL V+ Terminal Input Select: Channel 2 */
258 
#define APPSEL_3               (0x3000)       /* A-POOL V+ Terminal Input Select: Channel 3 */
259 
#define APPSEL_4               (0x4000)       /* A-POOL V+ Terminal Input Select: Channel 4 */
260 
#define APPSEL_5               (0x5000)       /* A-POOL V+ Terminal Input Select: Channel 5 */
261 
#define APPSEL_6               (0x6000)       /* A-POOL V+ Terminal Input Select: Channel 6 */
262 
#define APPSEL_7               (0x7000)       /* A-POOL V+ Terminal Input Select: Channel 7 */
263 
#define APPSEL_8               (0x8000)       /* A-POOL V+ Terminal Input Select: Channel 8 */
264 
 
265 
/* APVDIV Control Bits */
266 
#define A0DIV                  (0x0001)       /* A-POOL Analog channel #0 voltage divider control */
267 
#define A1DIV                  (0x0002)       /* A-POOL Analog channel #1 voltage divider control */
268 
#define A2DIV0                 (0x0004)       /* A-POOL Analog channel #2 voltage divider control Bit : 0 */
269 
#define A2DIV1                 (0x0008)       /* A-POOL Analog channel #2 voltage divider control Bit : 1 */
270 
#define A3DIV0                 (0x0010)       /* A-POOL Analog channel #3 voltage divider control Bit : 0 */
271 
#define A3DIV1                 (0x0020)       /* A-POOL Analog channel #3 voltage divider control Bit : 0 */
272 
#define TMPSEN                 (0x0040)       /* A-POOL Temperature sensor enable */
273 
#define VCCDIVEN               (0x0080)       /* A-POOL VCC voltage divider enable */
274 
//#define RESERVED             (0x0100)  /* A-POOL */
275 
//#define RESERVED             (0x0200)  /* A-POOL */
276 
#define CLKTRIM0               (0x0400)       /* A-POOL Clock trimming Bit : 0 */
277 
#define CLKTRIM1               (0x0800)       /* A-POOL Clock trimming Bit : 1 */
278 
//#define RESERVED             (0x1000)  /* A-POOL */
279 
//#define RESERVED             (0x2000)  /* A-POOL */
280 
//#define RESERVED             (0x4000)  /* A-POOL */
281 
//#define RESERVED             (0x8000)  /* A-POOL */
282 
 
283 
/* APVDIV Control Bits */
284 
#define A0DIV_L                (0x0001)       /* A-POOL Analog channel #0 voltage divider control */
285 
#define A1DIV_L                (0x0002)       /* A-POOL Analog channel #1 voltage divider control */
286 
#define A2DIV0_L               (0x0004)       /* A-POOL Analog channel #2 voltage divider control Bit : 0 */
287 
#define A2DIV1_L               (0x0008)       /* A-POOL Analog channel #2 voltage divider control Bit : 1 */
288 
#define A3DIV0_L               (0x0010)       /* A-POOL Analog channel #3 voltage divider control Bit : 0 */
289 
#define A3DIV1_L               (0x0020)       /* A-POOL Analog channel #3 voltage divider control Bit : 0 */
290 
#define TMPSEN_L               (0x0040)       /* A-POOL Temperature sensor enable */
291 
#define VCCDIVEN_L             (0x0080)       /* A-POOL VCC voltage divider enable */
292 
//#define RESERVED             (0x0100)  /* A-POOL */
293 
//#define RESERVED             (0x0200)  /* A-POOL */
294 
//#define RESERVED             (0x1000)  /* A-POOL */
295 
//#define RESERVED             (0x2000)  /* A-POOL */
296 
//#define RESERVED             (0x4000)  /* A-POOL */
297 
//#define RESERVED             (0x8000)  /* A-POOL */
298 
 
299 
/* APVDIV Control Bits */
300 
//#define RESERVED             (0x0100)  /* A-POOL */
301 
//#define RESERVED             (0x0200)  /* A-POOL */
302 
#define CLKTRIM0_H             (0x0004)       /* A-POOL Clock trimming Bit : 0 */
303 
#define CLKTRIM1_H             (0x0008)       /* A-POOL Clock trimming Bit : 1 */
304 
//#define RESERVED             (0x1000)  /* A-POOL */
305 
//#define RESERVED             (0x2000)  /* A-POOL */
306 
//#define RESERVED             (0x4000)  /* A-POOL */
307 
//#define RESERVED             (0x8000)  /* A-POOL */
308 
 
309 
#define A2DIV_0                (0x0000)       /* A-POOL Analog channel #2 voltage divider control: 0 */
310 
#define A2DIV_1                (0x0004)       /* A-POOL Analog channel #2 voltage divider control: 1 */
311 
#define A2DIV_2                (0x0008)       /* A-POOL Analog channel #2 voltage divider control: 2 */
312 
#define A2DIV_3                (0x000C)       /* A-POOL Analog channel #2 voltage divider control: 3 */
313 
 
314 
#define A3DIV_0                (0x0000)       /* A-POOL Analog channel #3 voltage divider control: 0 */
315 
#define A3DIV_1                (0x0010)       /* A-POOL Analog channel #3 voltage divider control: 1 */
316 
#define A3DIV_2                (0x0020)       /* A-POOL Analog channel #3 voltage divider control: 2 */
317 
#define A3DIV_3                (0x0030)       /* A-POOL Analog channel #3 voltage divider control: 3 */
318 
 
319 
#define CLKTRIM_0              (0x0000)       /* A-POOL Clock trimming: 0 */
320 
#define CLKTRIM_1              (0x0400)       /* A-POOL Clock trimming: 1 */
321 
#define CLKTRIM_2              (0x0800)       /* A-POOL Clock trimming: 2 */
322 
#define CLKTRIM_3              (0x0C00)       /* A-POOL Clock trimming: 3 */
323 
 
324 
#define REFTRIM_0              (0x0000)       /* A-POOL Reference trimming: 0 */
325 
#define REFTRIM_1              (0x1000)       /* A-POOL Reference trimming: 1 */
326 
#define REFTRIM_2              (0x2000)       /* A-POOL Reference trimming: 2 */
327 
#define REFTRIM_3              (0x3000)       /* A-POOL Reference trimming: 3 */
328 
#define REFTRIM_4              (0x4000)       /* A-POOL Reference trimming: 4 */
329 
#define REFTRIM_5              (0x5000)       /* A-POOL Reference trimming: 5 */
330 
#define REFTRIM_6              (0x6000)       /* A-POOL Reference trimming: 6 */
331 
#define REFTRIM_7              (0x7000)       /* A-POOL Reference trimming: 7 */
332 
 
333 
/* APTRIM Control Bits */
334 
#define REFTSEL                (0x0001)       /* A-POOL Register bank used for the reference trimming */
335 
#define REFTRIM0               (0x1000)       /* A-POOL Reference trimming bit: 0 */
336 
#define REFTRIM1               (0x2000)       /* A-POOL Reference trimming bit: 1 */
337 
#define REFTRIM2               (0x4000)       /* A-POOL Reference trimming bit: 2 */
338 
#define REFTRIM3               (0x8000)       /* A-POOL Reference trimming bit: 3 */
339 
 
340 
/* APTRIM Control Bits */
341 
#define REFTSEL_L              (0x0001)       /* A-POOL Register bank used for the reference trimming */
342 
 
343 
/* APTRIM Control Bits */
344 
#define REFTRIM0_H             (0x0010)       /* A-POOL Reference trimming bit: 0 */
345 
#define REFTRIM1_H             (0x0020)       /* A-POOL Reference trimming bit: 1 */
346 
#define REFTRIM2_H             (0x0040)       /* A-POOL Reference trimming bit: 2 */
347 
#define REFTRIM3_H             (0x0080)       /* A-POOL Reference trimming bit: 3 */
348 
 
349 
/* APOMR Control Bits */
350 
#define CLKDIV0                (0x0001)       /* A-POOL Prescaler Control Bit: 0 */
351 
#define CLKDIV1                (0x0002)       /* A-POOL Prescaler Control Bit: 1 */
352 
#define CLKDIV2                (0x0004)       /* A-POOL Prescaler Control Bit: 2 */
353 
#define SAREN                  (0x0008)       /* A-POOL SAR conversion enable */
354 
#define CTEN                   (0x0100)       /* A-POOL Continuous time mode of comparator */
355 
#define AZCMP                  (0x0200)       /* A-POOL Clocked zero compensated long term comparison */
356 
#define AZSWREQ                (0x0400)       /* A-POOL SW request for Auto Zero Phase */
357 
#define SVMINH                 (0x0800)       /* A-POOL Suppress the generation of an SVM interrupt event. */
358 
 
359 
/* APOMR Control Bits */
360 
#define CLKDIV0_L              (0x0001)       /* A-POOL Prescaler Control Bit: 0 */
361 
#define CLKDIV1_L              (0x0002)       /* A-POOL Prescaler Control Bit: 1 */
362 
#define CLKDIV2_L              (0x0004)       /* A-POOL Prescaler Control Bit: 2 */
363 
#define SAREN_L                (0x0008)       /* A-POOL SAR conversion enable */
364 
 
365 
/* APOMR Control Bits */
366 
#define CTEN_H                 (0x0001)       /* A-POOL Continuous time mode of comparator */
367 
#define AZCMP_H                (0x0002)       /* A-POOL Clocked zero compensated long term comparison */
368 
#define AZSWREQ_H              (0x0004)       /* A-POOL SW request for Auto Zero Phase */
369 
#define SVMINH_H               (0x0008)       /* A-POOL Suppress the generation of an SVM interrupt event. */
370 
 
371 
#define CLKDIV_0               (0x0000)       /* A-POOL Prescaler Control 0 : /1 */
372 
#define CLKDIV_1               (0x0001)       /* A-POOL Prescaler Control 1 : /2 */
373 
#define CLKDIV_2               (0x0002)       /* A-POOL Prescaler Control 2 : /4 */
374 
#define CLKDIV_3               (0x0003)       /* A-POOL Prescaler Control 3 : /8 */
375 
#define CLKDIV_4               (0x0004)       /* A-POOL Prescaler Control 4 : /16 */
376 
#define CLKDIV_5               (0x0005)       /* A-POOL Prescaler Control 5 : /32 */
377 
#define CLKDIV__1              (0x0000)       /* A-POOL Prescaler Control 0 : /1 */
378 
#define CLKDIV__2              (0x0001)       /* A-POOL Prescaler Control 1 : /2 */
379 
#define CLKDIV__4              (0x0002)       /* A-POOL Prescaler Control 2 : /4 */
380 
#define CLKDIV__8              (0x0003)       /* A-POOL Prescaler Control 3 : /8 */
381 
#define CLKDIV__16             (0x0004)       /* A-POOL Prescaler Control 4 : /16 */
382 
#define CLKDIV__32             (0x0005)       /* A-POOL Prescaler Control 5 : /32 */
383 
 
384 
/* APIFG Control Bits */
385 
#define EOCIFG                 (0x0001)       /* A-POOL End of conversion interrupt flag */
386 
#define CFIFG                  (0x0002)       /* A-POOL Comparator falling edge interrupt flag */
387 
#define CRIFG                  (0x0004)       /* A-POOL Comparator rising edge interrupt flag */
388 
#define REFOKIFG               (0x0008)       /* A-POOL Reference voltage ready interrupt flag */
389 
 
390 
/* APIFG Control Bits */
391 
#define EOCIFG_L               (0x0001)       /* A-POOL End of conversion interrupt flag */
392 
#define CFIFG_L                (0x0002)       /* A-POOL Comparator falling edge interrupt flag */
393 
#define CRIFG_L                (0x0004)       /* A-POOL Comparator rising edge interrupt flag */
394 
#define REFOKIFG_L             (0x0008)       /* A-POOL Reference voltage ready interrupt flag */
395 
 
396 
/* APIFG Control Bits */
397 
 
398 
/* APIFG Control Bits */
399 
#define EOCIE                  (0x0001)       /* A-POOL End of conversion interrupt enable */
400 
#define CFIE                   (0x0002)       /* A-POOL Comparator falling edge interrupt enable */
401 
#define CRIE                   (0x0004)       /* A-POOL Comparator rising edge interrupt enable */
402 
#define REFIKIE                (0x0008)       /* A-POOL Reference voltage ready interrupt enable */
403 
 
404 
/* APIFG Control Bits */
405 
#define EOCIE_L                (0x0001)       /* A-POOL End of conversion interrupt enable */
406 
#define CFIE_L                 (0x0002)       /* A-POOL Comparator falling edge interrupt enable */
407 
#define CRIE_L                 (0x0004)       /* A-POOL Comparator rising edge interrupt enable */
408 
#define REFIKIE_L              (0x0008)       /* A-POOL Reference voltage ready interrupt enable */
409 
 
410 
/* APIFG Control Bits */
411 
 
412 
/* APIV Definitions */
413 
#define APIV_NONE              (0x0000)       /* No Interrupt pending */
414 
#define APIV_EOCIF             (0x0002)       /* EOCIFG */
415 
#define APIV_CFIFG             (0x0004)       /* CFIFG */
416 
#define APIV_CRIFG             (0x0006)       /* CRIFG */
417 
 
418 
/************************************************************
419 
* COMPACT CLOCK SYSTEM
420 
************************************************************/
421 
#define __MSP430_HAS_CCS__                    /* Definition to show that Module is available */
422 
#define __MSP430_BASEADDRESS_CCS__ 0x0160
423 
 
424 
SFR_16BIT(CCSCTL0);                           /* CCS Control Register 0 */
425 
SFR_8BIT(CCSCTL0_L);                          /* CCS Control Register 0 */
426 
SFR_8BIT(CCSCTL0_H);                          /* CCS Control Register 0 */
427 
SFR_16BIT(CCSCTL1);                           /* CCS Control Register 1 */
428 
SFR_8BIT(CCSCTL1_L);                          /* CCS Control Register 1 */
429 
SFR_8BIT(CCSCTL1_H);                          /* CCS Control Register 1 */
430 
SFR_16BIT(CCSCTL2);                           /* CCS Control Register 2 */
431 
SFR_8BIT(CCSCTL2_L);                          /* CCS Control Register 2 */
432 
SFR_8BIT(CCSCTL2_H);                          /* CCS Control Register 2 */
433 
SFR_16BIT(CCSCTL4);                           /* CCS Control Register 4 */
434 
SFR_8BIT(CCSCTL4_L);                          /* CCS Control Register 4 */
435 
SFR_8BIT(CCSCTL4_H);                          /* CCS Control Register 4 */
436 
SFR_16BIT(CCSCTL5);                           /* CCS Control Register 5 */
437 
SFR_8BIT(CCSCTL5_L);                          /* CCS Control Register 5 */
438 
SFR_8BIT(CCSCTL5_H);                          /* CCS Control Register 5 */
439 
SFR_16BIT(CCSCTL6);                           /* CCS Control Register 6 */
440 
SFR_8BIT(CCSCTL6_L);                          /* CCS Control Register 6 */
441 
SFR_8BIT(CCSCTL6_H);                          /* CCS Control Register 6 */
442 
SFR_16BIT(CCSCTL7);                           /* CCS Control Register 7 */
443 
SFR_8BIT(CCSCTL7_L);                          /* CCS Control Register 7 */
444 
SFR_8BIT(CCSCTL7_H);                          /* CCS Control Register 7 */
445 
SFR_16BIT(CCSCTL8);                           /* CCS Control Register 8 */
446 
SFR_8BIT(CCSCTL8_L);                          /* CCS Control Register 8 */
447 
SFR_8BIT(CCSCTL8_H);                          /* CCS Control Register 8 */
448 
 
449 
/* CCSCTL0 Control Bits */
450 
 
451 
/* CCSCTL0 Control Bits */
452 
 
453 
/* CCSCTL0 Control Bits */
454 
#define CCSKEY                 (0xA500)       /* CCS Password */
455 
 
456 
/* CCSCTL1 Control Bits */
457 
#define DIVCLK                 (0x0001)       /* Clock division for CLKIN / X-OSC */
458 
 
459 
/* CCSCTL1 Control Bits */
460 
#define DIVCLK_L               (0x0001)       /* Clock division for CLKIN / X-OSC */
461 
 
462 
/* CCSCTL1 Control Bits */
463 
 
464 
/* CCSCTL2 Control Bits */
465 
#define FSEL0                  (0x0001)       /* Frequency trimming of the HF-OSC Bit: 0 */
466 
#define FSEL1                  (0x0002)       /* Frequency trimming of the HF-OSC Bit: 1 */
467 
#define FSEL2                  (0x0004)       /* Frequency trimming of the HF-OSC Bit: 2 */
468 
#define FSEL3                  (0x0008)       /* Frequency trimming of the HF-OSC Bit: 3 */
469 
#define FSEL4                  (0x0010)       /* Frequency trimming of the HF-OSC Bit: 4 */
470 
#define FSEL5                  (0x0020)       /* Frequency trimming of the HF-OSC Bit: 5 */
471 
#define FSEL6                  (0x0040)       /* Frequency trimming of the HF-OSC Bit: 6 */
472 
 
473 
/* CCSCTL2 Control Bits */
474 
#define FSEL0_L                (0x0001)       /* Frequency trimming of the HF-OSC Bit: 0 */
475 
#define FSEL1_L                (0x0002)       /* Frequency trimming of the HF-OSC Bit: 1 */
476 
#define FSEL2_L                (0x0004)       /* Frequency trimming of the HF-OSC Bit: 2 */
477 
#define FSEL3_L                (0x0008)       /* Frequency trimming of the HF-OSC Bit: 3 */
478 
#define FSEL4_L                (0x0010)       /* Frequency trimming of the HF-OSC Bit: 4 */
479 
#define FSEL5_L                (0x0020)       /* Frequency trimming of the HF-OSC Bit: 5 */
480 
#define FSEL6_L                (0x0040)       /* Frequency trimming of the HF-OSC Bit: 6 */
481 
 
482 
/* CCSCTL2 Control Bits */
483 
 
484 
/* CCSCTL4 Control Bits */
485 
#define SELM0                  (0x0001)       /* MCLK Source Select Bit: 0 */
486 
#define SELM1                  (0x0002)       /* MCLK Source Select Bit: 1 */
487 
//#define RESERVED            (0x0004)    /* RESERVED */
488 
//#define RESERVED            (0x0008)    /* RESERVED */
489 
#define SELS0                  (0x0010)       /* SMCLK Source Select Bit: 0 */
490 
#define SELS1                  (0x0020)       /* SMCLK Source Select Bit: 1 */
491 
//#define RESERVED            (0x0040)    /* RESERVED */
492 
//#define RESERVED            (0x0080)    /* RESERVED */
493 
#define SELA0                  (0x0100)       /* ACLK Source Select Bit: 0 */
494 
#define SELA1                  (0x0200)       /* ACLK Source Select Bit: 1 */
495 
//#define RESERVED            (0x0400)    /* RESERVED */
496 
//#define RESERVED            (0x0800)    /* RESERVED */
497 
//#define RESERVED            (0x1000)    /* RESERVED */
498 
//#define RESERVED            (0x2000)    /* RESERVED */
499 
//#define RESERVED            (0x4000)    /* RESERVED */
500 
//#define RESERVED            (0x8000)    /* RESERVED */
501 
 
502 
/* CCSCTL4 Control Bits */
503 
#define SELM0_L                (0x0001)       /* MCLK Source Select Bit: 0 */
504 
#define SELM1_L                (0x0002)       /* MCLK Source Select Bit: 1 */
505 
//#define RESERVED            (0x0004)    /* RESERVED */
506 
//#define RESERVED            (0x0008)    /* RESERVED */
507 
#define SELS0_L                (0x0010)       /* SMCLK Source Select Bit: 0 */
508 
#define SELS1_L                (0x0020)       /* SMCLK Source Select Bit: 1 */
509 
//#define RESERVED            (0x0040)    /* RESERVED */
510 
//#define RESERVED            (0x0080)    /* RESERVED */
511 
//#define RESERVED            (0x0400)    /* RESERVED */
512 
//#define RESERVED            (0x0800)    /* RESERVED */
513 
//#define RESERVED            (0x1000)    /* RESERVED */
514 
//#define RESERVED            (0x2000)    /* RESERVED */
515 
//#define RESERVED            (0x4000)    /* RESERVED */
516 
//#define RESERVED            (0x8000)    /* RESERVED */
517 
 
518 
/* CCSCTL4 Control Bits */
519 
//#define RESERVED            (0x0004)    /* RESERVED */
520 
//#define RESERVED            (0x0008)    /* RESERVED */
521 
//#define RESERVED            (0x0040)    /* RESERVED */
522 
//#define RESERVED            (0x0080)    /* RESERVED */
523 
#define SELA0_H                (0x0001)       /* ACLK Source Select Bit: 0 */
524 
#define SELA1_H                (0x0002)       /* ACLK Source Select Bit: 1 */
525 
//#define RESERVED            (0x0400)    /* RESERVED */
526 
//#define RESERVED            (0x0800)    /* RESERVED */
527 
//#define RESERVED            (0x1000)    /* RESERVED */
528 
//#define RESERVED            (0x2000)    /* RESERVED */
529 
//#define RESERVED            (0x4000)    /* RESERVED */
530 
//#define RESERVED            (0x8000)    /* RESERVED */
531 
 
532 
#define SELM_0                 (0x0000)       /* MCLK Source Select 0 */
533 
#define SELM_1                 (0x0001)       /* MCLK Source Select 1 */
534 
#define SELM_2                 (0x0002)       /* MCLK Source Select 2 */
535 
#define SELM_3                 (0x0003)       /* MCLK Source Select 3 */
536 
#define SELM__HFCLK            (0x0000)       /* MCLK Source Select HFCLK */
537 
#define SELM__LFCLK            (0x0001)       /* MCLK Source Select LFCLK */
538 
#define SELM__CLKIN            (0x0002)       /* MCLK Source Select CLKIN */
539 
 
540 
#define SELS_0                 (0x0000)       /* SMCLK Source Select 0 */
541 
#define SELS_1                 (0x0010)       /* SMCLK Source Select 1 */
542 
#define SELS_2                 (0x0020)       /* SMCLK Source Select 2 */
543 
#define SELS_3                 (0x0030)       /* SMCLK Source Select 3 */
544 
#define SELS__HFCLK            (0x0000)       /* SMCLK Source Select HFCLK */
545 
#define SELS__LFCLK            (0x0010)       /* SMCLK Source Select LFCLK */
546 
#define SELS__CLKIN            (0x0020)       /* SMCLK Source Select CLKIN */
547 
 
548 
#define SELA_0                 (0x0000)       /* ACLK Source Select 0 */
549 
#define SELA_1                 (0x0100)       /* ACLK Source Select 1 */
550 
#define SELA_2                 (0x0200)       /* ACLK Source Select 2 */
551 
#define SELA_3                 (0x0300)       /* ACLK Source Select 3 */
552 
#define SELA__HFCLK            (0x0000)       /* ACLK Source Select HFCLK */
553 
#define SELA__LFCLK            (0x0100)       /* ACLK Source Select LFCLK */
554 
#define SELA__CLKIN            (0x0200)       /* ACLK Source Select CLKIN */
555 
 
556 
/* CCSCTL5 Control Bits */
557 
#define DIVM0                  (0x0001)       /* MCLK Divider Bit: 0 */
558 
#define DIVM1                  (0x0002)       /* MCLK Divider Bit: 1 */
559 
#define DIVM2                  (0x0004)       /* MCLK Divider Bit: 2 */
560 
//#define RESERVED            (0x0004)    /* RESERVED */
561 
//#define RESERVED            (0x0008)    /* RESERVED */
562 
#define DIVS0                  (0x0010)       /* SMCLK Divider Bit: 0 */
563 
#define DIVS1                  (0x0020)       /* SMCLK Divider Bit: 1 */
564 
#define DIVS2                  (0x0040)       /* SMCLK Divider Bit: 2 */
565 
//#define RESERVED            (0x0040)    /* RESERVED */
566 
//#define RESERVED            (0x0080)    /* RESERVED */
567 
#define DIVA0                  (0x0100)       /* ACLK Divider Bit: 0 */
568 
#define DIVA1                  (0x0200)       /* ACLK Divider Bit: 1 */
569 
#define DIVA2                  (0x0400)       /* ACLK Divider Bit: 2 */
570 
//#define RESERVED            (0x0400)    /* RESERVED */
571 
//#define RESERVED            (0x0800)    /* RESERVED */
572 
//#define RESERVED            (0x1000)    /* RESERVED */
573 
//#define RESERVED            (0x2000)    /* RESERVED */
574 
//#define RESERVED            (0x4000)    /* RESERVED */
575 
//#define RESERVED            (0x8000)    /* RESERVED */
576 
 
577 
/* CCSCTL5 Control Bits */
578 
#define DIVM0_L                (0x0001)       /* MCLK Divider Bit: 0 */
579 
#define DIVM1_L                (0x0002)       /* MCLK Divider Bit: 1 */
580 
#define DIVM2_L                (0x0004)       /* MCLK Divider Bit: 2 */
581 
//#define RESERVED            (0x0004)    /* RESERVED */
582 
//#define RESERVED            (0x0008)    /* RESERVED */
583 
#define DIVS0_L                (0x0010)       /* SMCLK Divider Bit: 0 */
584 
#define DIVS1_L                (0x0020)       /* SMCLK Divider Bit: 1 */
585 
#define DIVS2_L                (0x0040)       /* SMCLK Divider Bit: 2 */
586 
//#define RESERVED            (0x0040)    /* RESERVED */
587 
//#define RESERVED            (0x0080)    /* RESERVED */
588 
//#define RESERVED            (0x0400)    /* RESERVED */
589 
//#define RESERVED            (0x0800)    /* RESERVED */
590 
//#define RESERVED            (0x1000)    /* RESERVED */
591 
//#define RESERVED            (0x2000)    /* RESERVED */
592 
//#define RESERVED            (0x4000)    /* RESERVED */
593 
//#define RESERVED            (0x8000)    /* RESERVED */
594 
 
595 
/* CCSCTL5 Control Bits */
596 
//#define RESERVED            (0x0004)    /* RESERVED */
597 
//#define RESERVED            (0x0008)    /* RESERVED */
598 
//#define RESERVED            (0x0040)    /* RESERVED */
599 
//#define RESERVED            (0x0080)    /* RESERVED */
600 
#define DIVA0_H                (0x0001)       /* ACLK Divider Bit: 0 */
601 
#define DIVA1_H                (0x0002)       /* ACLK Divider Bit: 1 */
602 
#define DIVA2_H                (0x0004)       /* ACLK Divider Bit: 2 */
603 
//#define RESERVED            (0x0400)    /* RESERVED */
604 
//#define RESERVED            (0x0800)    /* RESERVED */
605 
//#define RESERVED            (0x1000)    /* RESERVED */
606 
//#define RESERVED            (0x2000)    /* RESERVED */
607 
//#define RESERVED            (0x4000)    /* RESERVED */
608 
//#define RESERVED            (0x8000)    /* RESERVED */
609 
 
610 
#define DIVM_0                 (0x0000)       /* MCLK Source Divider 0 */
611 
#define DIVM_1                 (0x0001)       /* MCLK Source Divider 1 */
612 
#define DIVM_2                 (0x0002)       /* MCLK Source Divider 2 */
613 
#define DIVM_3                 (0x0003)       /* MCLK Source Divider 3 */
614 
#define DIVM_4                 (0x0004)       /* MCLK Source Divider 4 */
615 
#define DIVM_5                 (0x0005)       /* MCLK Source Divider 5 */
616 
#define DIVM__1                (0x0000)       /* MCLK Source Divider f(MCLK)/1 */
617 
#define DIVM__2                (0x0001)       /* MCLK Source Divider f(MCLK)/2 */
618 
#define DIVM__4                (0x0002)       /* MCLK Source Divider f(MCLK)/4 */
619 
#define DIVM__8                (0x0003)       /* MCLK Source Divider f(MCLK)/8 */
620 
#define DIVM__16               (0x0004)       /* MCLK Source Divider f(MCLK)/16 */
621 
#define DIVM__32               (0x0005)       /* MCLK Source Divider f(MCLK)/32 */
622 
 
623 
#define DIVS_0                 (0x0000)       /* SMCLK Source Divider 0 */
624 
#define DIVS_1                 (0x0010)       /* SMCLK Source Divider 1 */
625 
#define DIVS_2                 (0x0020)       /* SMCLK Source Divider 2 */
626 
#define DIVS_3                 (0x0030)       /* SMCLK Source Divider 3 */
627 
#define DIVS_4                 (0x0040)       /* SMCLK Source Divider 4 */
628 
#define DIVS_5                 (0x0050)       /* SMCLK Source Divider 5 */
629 
#define DIVS__1                (0x0000)       /* SMCLK Source Divider f(SMCLK)/1 */
630 
#define DIVS__2                (0x0010)       /* SMCLK Source Divider f(SMCLK)/2 */
631 
#define DIVS__4                (0x0020)       /* SMCLK Source Divider f(SMCLK)/4 */
632 
#define DIVS__8                (0x0030)       /* SMCLK Source Divider f(SMCLK)/8 */
633 
#define DIVS__16               (0x0040)       /* SMCLK Source Divider f(SMCLK)/16 */
634 
#define DIVS__32               (0x0050)       /* SMCLK Source Divider f(SMCLK)/32 */
635 
 
636 
#define DIVA_0                 (0x0000)       /* ACLK Source Divider 0 */
637 
#define DIVA_1                 (0x0100)       /* ACLK Source Divider 1 */
638 
#define DIVA_2                 (0x0200)       /* ACLK Source Divider 2 */
639 
#define DIVA_3                 (0x0300)       /* ACLK Source Divider 3 */
640 
#define DIVA_4                 (0x0400)       /* ACLK Source Divider 4 */
641 
#define DIVA_5                 (0x0500)       /* ACLK Source Divider 5 */
642 
#define DIVA__1                (0x0000)       /* ACLK Source Divider f(ACLK)/1 */
643 
#define DIVA__2                (0x0100)       /* ACLK Source Divider f(ACLK)/2 */
644 
#define DIVA__4                (0x0200)       /* ACLK Source Divider f(ACLK)/4 */
645 
#define DIVA__8                (0x0300)       /* ACLK Source Divider f(ACLK)/8 */
646 
#define DIVA__16               (0x0400)       /* ACLK Source Divider f(ACLK)/16 */
647 
#define DIVA__32               (0x0500)       /* ACLK Source Divider f(ACLK)/32 */
648 
 
649 
/* CCSCTL6 Control Bits */
650 
#define XTOFF                  (0x0001)       /* Disable XT oscillator */
651 
 
652 
/* CCSCTL6 Control Bits */
653 
#define XTOFF_L                (0x0001)       /* Disable XT oscillator */
654 
 
655 
/* CCSCTL6 Control Bits */
656 
 
657 
/* CCSCTL7 Control Bits */
658 
#define XOFFG                  (0x0001)       /* X-tal Oscillator Fault Flag */
659 
#define HFOFFG                 (0x0002)       /* High Frequency Oscillator Fault Flag */
660 
 
661 
/* CCSCTL7 Control Bits */
662 
#define XOFFG_L                (0x0001)       /* X-tal Oscillator Fault Flag */
663 
#define HFOFFG_L               (0x0002)       /* High Frequency Oscillator Fault Flag */
664 
 
665 
/* CCSCTL7 Control Bits */
666 
 
667 
/* CCSCTL8 Control Bits */
668 
#define ACLKREQEN              (0x0001)       /* ACLK Clock Request Enable */
669 
#define MCLKREQEN              (0x0002)       /* MCLK Clock Request Enable */
670 
#define SMCLKREQEN             (0x0004)       /* SMCLK Clock Request Enable */
671 
 
672 
/* CCSCTL8 Control Bits */
673 
#define ACLKREQEN_L            (0x0001)       /* ACLK Clock Request Enable */
674 
#define MCLKREQEN_L            (0x0002)       /* MCLK Clock Request Enable */
675 
#define SMCLKREQEN_L           (0x0004)       /* SMCLK Clock Request Enable */
676 
 
677 
/* CCSCTL8 Control Bits */
678 
 
679 
/************************************************************
680 
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
681 
************************************************************/
682 
#define __MSP430_HAS_PORT1_R__                /* Definition to show that Module is available */
683 
#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
684 
#define __MSP430_HAS_PORT2_R__                /* Definition to show that Module is available */
685 
#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
686 
#define __MSP430_HAS_PORTA_R__                /* Definition to show that Module is available */
687 
#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
688 
 
689 
SFR_16BIT(PAIN);                              /* Port A Input */
690 
SFR_8BIT(PAIN_L);                             /* Port A Input */
691 
SFR_8BIT(PAIN_H);                             /* Port A Input */
692 
SFR_16BIT(PAOUT);                             /* Port A Output */
693 
SFR_8BIT(PAOUT_L);                            /* Port A Output */
694 
SFR_8BIT(PAOUT_H);                            /* Port A Output */
695 
SFR_16BIT(PADIR);                             /* Port A Direction */
696 
SFR_8BIT(PADIR_L);                            /* Port A Direction */
697 
SFR_8BIT(PADIR_H);                            /* Port A Direction */
698 
SFR_16BIT(PAREN);                             /* Port A Resistor Enable */
699 
SFR_8BIT(PAREN_L);                            /* Port A Resistor Enable */
700 
SFR_8BIT(PAREN_H);                            /* Port A Resistor Enable */
701 
SFR_16BIT(PADS);                              /* Port A Resistor Drive Strenght */
702 
SFR_8BIT(PADS_L);                             /* Port A Resistor Drive Strenght */
703 
SFR_8BIT(PADS_H);                             /* Port A Resistor Drive Strenght */
704 
SFR_16BIT(PASEL0);                            /* Port A Selection 0 */
705 
SFR_8BIT(PASEL0_L);                           /* Port A Selection 0 */
706 
SFR_8BIT(PASEL0_H);                           /* Port A Selection 0 */
707 
SFR_16BIT(PASEL1);                            /* Port A Selection 1 */
708 
SFR_8BIT(PASEL1_L);                           /* Port A Selection 1 */
709 
SFR_8BIT(PASEL1_H);                           /* Port A Selection 1 */
710 
SFR_16BIT(PAIES);                             /* Port A Interrupt Edge Select */
711 
SFR_8BIT(PAIES_L);                            /* Port A Interrupt Edge Select */
712 
SFR_8BIT(PAIES_H);                            /* Port A Interrupt Edge Select */
713 
SFR_16BIT(PAIE);                              /* Port A Interrupt Enable */
714 
SFR_8BIT(PAIE_L);                             /* Port A Interrupt Enable */
715 
SFR_8BIT(PAIE_H);                             /* Port A Interrupt Enable */
716 
SFR_16BIT(PAIFG);                             /* Port A Interrupt Flag */
717 
SFR_8BIT(PAIFG_L);                            /* Port A Interrupt Flag */
718 
SFR_8BIT(PAIFG_H);                            /* Port A Interrupt Flag */
719 
 
720 
 
721 
SFR_16BIT(P1IV);                              /* Port 1 Interrupt Vector Word */
722 
SFR_16BIT(P2IV);                              /* Port 2 Interrupt Vector Word */
723 
#define P1IN                   (PAIN_L)       /* Port 1 Input */
724 
#define P1OUT                  (PAOUT_L)      /* Port 1 Output */
725 
#define P1DIR                  (PADIR_L)      /* Port 1 Direction */
726 
#define P1REN                  (PAREN_L)      /* Port 1 Resistor Enable */
727 
#define P1DS                   (PADS_L)       /* Port 1 Resistor Drive Strenght */
728 
#define P1SEL0                 (PASEL0_L)     /* Port 1 Selection 0 */
729 
#define P1SEL1                 (PASEL1_L)     /* Port 1 Selection 1 */
730 
#define P1IES                  (PAIES_L)      /* Port 1 Interrupt Edge Select */
731 
#define P1IE                   (PAIE_L)       /* Port 1 Interrupt Enable */
732 
#define P1IFG                  (PAIFG_L)      /* Port 1 Interrupt Flag */
733 
 
734 
//Definitions for P1IV
735 
#define P1IV_NONE              (0x0000)       /* No Interrupt pending */
736 
#define P1IV_P1IFG0            (0x0002)       /* P1IV P1IFG.0 */
737 
#define P1IV_P1IFG1            (0x0004)       /* P1IV P1IFG.1 */
738 
#define P1IV_P1IFG2            (0x0006)       /* P1IV P1IFG.2 */
739 
#define P1IV_P1IFG3            (0x0008)       /* P1IV P1IFG.3 */
740 
#define P1IV_P1IFG4            (0x000A)       /* P1IV P1IFG.4 */
741 
#define P1IV_P1IFG5            (0x000C)       /* P1IV P1IFG.5 */
742 
#define P1IV_P1IFG6            (0x000E)       /* P1IV P1IFG.6 */
743 
#define P1IV_P1IFG7            (0x0010)       /* P1IV P1IFG.7 */
744 
 
745 
#define P2IN                   (PAIN_H)       /* Port 2 Input */
746 
#define P2OUT                  (PAOUT_H)      /* Port 2 Output */
747 
#define P2DIR                  (PADIR_H)      /* Port 2 Direction */
748 
#define P2REN                  (PAREN_H)      /* Port 2 Resistor Enable */
749 
#define P2DS                   (PADS_H)       /* Port 2 Resistor Drive Strenght */
750 
#define P2SEL0                 (PASEL0_H)     /* Port 2 Selection 0 */
751 
#define P2SEL1                 (PASEL1_H)     /* Port 2 Selection 1 */
752 
#define P2IES                  (PAIES_H)      /* Port 2 Interrupt Edge Select */
753 
#define P2IE                   (PAIE_H)       /* Port 2 Interrupt Enable */
754 
#define P2IFG                  (PAIFG_H)      /* Port 2 Interrupt Flag */
755 
 
756 
//Definitions for P2IV
757 
#define P2IV_NONE              (0x0000)       /* No Interrupt pending */
758 
#define P2IV_P2IFG0            (0x0002)       /* P2IV P2IFG.0 */
759 
#define P2IV_P2IFG1            (0x0004)       /* P2IV P2IFG.1 */
760 
#define P2IV_P2IFG2            (0x0006)       /* P2IV P2IFG.2 */
761 
#define P2IV_P2IFG3            (0x0008)       /* P2IV P2IFG.3 */
762 
#define P2IV_P2IFG4            (0x000A)       /* P2IV P2IFG.4 */
763 
#define P2IV_P2IFG5            (0x000C)       /* P2IV P2IFG.5 */
764 
#define P2IV_P2IFG6            (0x000E)       /* P2IV P2IFG.6 */
765 
#define P2IV_P2IFG7            (0x0010)       /* P2IV P2IFG.7 */
766 
 
767 
 
768 
/************************************************************
769 
* SFR - Special Function Register Module
770 
************************************************************/
771 
#define __MSP430_HAS_SFR__                    /* Definition to show that Module is available */
772 
#define __MSP430_BASEADDRESS_SFR__ 0x0100
773 
 
774 
SFR_16BIT(SFRIE1);                            /* Interrupt Enable 1 */
775 
SFR_8BIT(SFRIE1_L);                           /* Interrupt Enable 1 */
776 
SFR_8BIT(SFRIE1_H);                           /* Interrupt Enable 1 */
777 
 
778 
/* SFRIE1 Control Bits */
779 
#define WDTIE                  (0x0001)       /* WDT Interrupt Enable */
780 
#define OFIE                   (0x0002)       /* Osc Fault Enable */
781 
//#define Reserved          (0x0004)
782 
#define VMAIE                  (0x0008)       /* Vacant Memory Interrupt Enable */
783 
#define NMIIE                  (0x0010)       /* NMI Interrupt Enable */
784 
#define JMBINIE                (0x0040)       /* JTAG Mail Box input Interrupt Enable */
785 
#define JMBOUTIE               (0x0080)       /* JTAG Mail Box output Interrupt Enable */
786 
#define SVMIE                  (0x0100)       /* SVM Interrupt Enable */
787 
 
788 
#define WDTIE_L                (0x0001)       /* WDT Interrupt Enable */
789 
#define OFIE_L                 (0x0002)       /* Osc Fault Enable */
790 
//#define Reserved          (0x0004)
791 
#define VMAIE_L                (0x0008)       /* Vacant Memory Interrupt Enable */
792 
#define NMIIE_L                (0x0010)       /* NMI Interrupt Enable */
793 
#define JMBINIE_L              (0x0040)       /* JTAG Mail Box input Interrupt Enable */
794 
#define JMBOUTIE_L             (0x0080)       /* JTAG Mail Box output Interrupt Enable */
795 
 
796 
//#define Reserved          (0x0004)
797 
#define SVMIE_H                (0x0001)       /* SVM Interrupt Enable */
798 
 
799 
SFR_16BIT(SFRIFG1);                           /* Interrupt Flag 1 */
800 
SFR_8BIT(SFRIFG1_L);                          /* Interrupt Flag 1 */
801 
SFR_8BIT(SFRIFG1_H);                          /* Interrupt Flag 1 */
802 
/* SFRIFG1 Control Bits */
803 
#define WDTIFG                 (0x0001)       /* WDT Interrupt Flag */
804 
#define OFIFG                  (0x0002)       /* Osc Fault Flag */
805 
//#define Reserved          (0x0004)
806 
#define VMAIFG                 (0x0008)       /* Vacant Memory Interrupt Flag */
807 
#define NMIIFG                 (0x0010)       /* NMI Interrupt Flag */
808 
//#define Reserved          (0x0020)
809 
#define JMBINIFG               (0x0040)       /* JTAG Mail Box input Interrupt Flag */
810 
#define JMBOUTIFG              (0x0080)       /* JTAG Mail Box output Interrupt Flag */
811 
#define SVMIFG                 (0x0100)       /* SVM Interrupt Flag */
812 
 
813 
#define WDTIFG_L               (0x0001)       /* WDT Interrupt Flag */
814 
#define OFIFG_L                (0x0002)       /* Osc Fault Flag */
815 
//#define Reserved          (0x0004)
816 
#define VMAIFG_L               (0x0008)       /* Vacant Memory Interrupt Flag */
817 
#define NMIIFG_L               (0x0010)       /* NMI Interrupt Flag */
818 
//#define Reserved          (0x0020)
819 
#define JMBINIFG_L             (0x0040)       /* JTAG Mail Box input Interrupt Flag */
820 
#define JMBOUTIFG_L            (0x0080)       /* JTAG Mail Box output Interrupt Flag */
821 
 
822 
//#define Reserved          (0x0004)
823 
//#define Reserved          (0x0020)
824 
#define SVMIFG_H               (0x0001)       /* SVM Interrupt Flag */
825 
 
826 
SFR_16BIT(SFRRPCR);                           /* RESET Pin Control Register */
827 
SFR_8BIT(SFRRPCR_L);                          /* RESET Pin Control Register */
828 
SFR_8BIT(SFRRPCR_H);                          /* RESET Pin Control Register */
829 
/* SFRRPCR Control Bits */
830 
#define SYSNMI                 (0x0001)       /* NMI select */
831 
#define SYSNMIIES              (0x0002)       /* NMI edge select */
832 
#define SYSRSTUP               (0x0004)       /* RESET Pin pull down/up select */
833 
#define SYSRSTRE               (0x0008)       /* RESET Pin Resistor enable */
834 
 
835 
#define SYSNMI_L               (0x0001)       /* NMI select */
836 
#define SYSNMIIES_L            (0x0002)       /* NMI edge select */
837 
#define SYSRSTUP_L             (0x0004)       /* RESET Pin pull down/up select */
838 
#define SYSRSTRE_L             (0x0008)       /* RESET Pin Resistor enable */
839 
 
840 
/************************************************************
841 
* COMPACT SYS - System Module
842 
************************************************************/
843 
#define __MSP430_HAS_SYS__                    /* Definition to show that Module is available */
844 
#define __MSP430_BASEADDRESS_SYS__ 0x0180
845 
 
846 
SFR_16BIT(SYSCTL);                            /* System control */
847 
SFR_8BIT(SYSCTL_L);                           /* System control */
848 
SFR_8BIT(SYSCTL_H);                           /* System control */
849 
SFR_16BIT(SYSBSLC);                           /* Boot strap configuration area */
850 
SFR_8BIT(SYSBSLC_L);                          /* Boot strap configuration area */
851 
SFR_8BIT(SYSBSLC_H);                          /* Boot strap configuration area */
852 
SFR_16BIT(SYSJMBC);                           /* JTAG mailbox control */
853 
SFR_8BIT(SYSJMBC_L);                          /* JTAG mailbox control */
854 
SFR_8BIT(SYSJMBC_H);                          /* JTAG mailbox control */
855 
SFR_16BIT(SYSJMBI0);                          /* JTAG mailbox input 0 */
856 
SFR_8BIT(SYSJMBI0_L);                         /* JTAG mailbox input 0 */
857 
SFR_8BIT(SYSJMBI0_H);                         /* JTAG mailbox input 0 */
858 
SFR_16BIT(SYSJMBI1);                          /* JTAG mailbox input 1 */
859 
SFR_8BIT(SYSJMBI1_L);                         /* JTAG mailbox input 1 */
860 
SFR_8BIT(SYSJMBI1_H);                         /* JTAG mailbox input 1 */
861 
SFR_16BIT(SYSJMBO0);                          /* JTAG mailbox output 0 */
862 
SFR_8BIT(SYSJMBO0_L);                         /* JTAG mailbox output 0 */
863 
SFR_8BIT(SYSJMBO0_H);                         /* JTAG mailbox output 0 */
864 
SFR_16BIT(SYSJMBO1);                          /* JTAG mailbox output 1 */
865 
SFR_8BIT(SYSJMBO1_L);                         /* JTAG mailbox output 1 */
866 
SFR_8BIT(SYSJMBO1_H);                         /* JTAG mailbox output 1 */
867 
SFR_16BIT(SYSCNF);                            /* System Configuration Register */
868 
SFR_8BIT(SYSCNF_L);                           /* System Configuration Register */
869 
SFR_8BIT(SYSCNF_H);                           /* System Configuration Register */
870 
 
871 
SFR_16BIT(SYSBERRIV);                         /* Bus Error vector generator */
872 
SFR_8BIT(SYSBERRIV_L);                        /* Bus Error vector generator */
873 
SFR_8BIT(SYSBERRIV_H);                        /* Bus Error vector generator */
874 
SFR_16BIT(SYSUNIV);                           /* User NMI vector generator */
875 
SFR_8BIT(SYSUNIV_L);                          /* User NMI vector generator */
876 
SFR_8BIT(SYSUNIV_H);                          /* User NMI vector generator */
877 
SFR_16BIT(SYSSNIV);                           /* System NMI vector generator */
878 
SFR_8BIT(SYSSNIV_L);                          /* System NMI vector generator */
879 
SFR_8BIT(SYSSNIV_H);                          /* System NMI vector generator */
880 
SFR_16BIT(SYSRSTIV);                          /* Reset vector generator */
881 
SFR_8BIT(SYSRSTIV_L);                         /* Reset vector generator */
882 
SFR_8BIT(SYSRSTIV_H);                         /* Reset vector generator */
883 
 
884 
/* SYSCTL Control Bits */
885 
#define SYSRIVECT              (0x0001)       /* SYS - RAM based interrupt vectors */
886 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
887 
#define SYSPMMPE               (0x0004)       /* SYS - PMM access protect */
888 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
889 
#define SYSBSLIND              (0x0010)       /* SYS - TCK/RST indication detected */
890 
#define SYSJTAGPIN             (0x0020)       /* SYS - Dedicated JTAG pins enabled */
891 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
892 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
893 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
894 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
895 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
896 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
897 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
898 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
899 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
900 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
901 
 
902 
/* SYSCTL Control Bits */
903 
#define SYSRIVECT_L            (0x0001)       /* SYS - RAM based interrupt vectors */
904 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
905 
#define SYSPMMPE_L             (0x0004)       /* SYS - PMM access protect */
906 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
907 
#define SYSBSLIND_L            (0x0010)       /* SYS - TCK/RST indication detected */
908 
#define SYSJTAGPIN_L           (0x0020)       /* SYS - Dedicated JTAG pins enabled */
909 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
910 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
911 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
912 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
913 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
914 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
915 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
916 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
917 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
918 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
919 
 
920 
/* SYSCTL Control Bits */
921 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
922 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
923 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
924 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
925 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
926 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
927 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
928 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
929 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
930 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
931 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
932 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
933 
 
934 
/* SYSBSLC Control Bits */
935 
#define SYSBSLSIZE0            (0x0001)       /* SYS - BSL Protection Size 0 */
936 
#define SYSBSLSIZE1            (0x0002)       /* SYS - BSL Protection Size 1 */
937 
#define SYSBSLR                (0x0004)       /* SYS - RAM assigned to BSL */
938 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
939 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
940 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
941 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
942 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
943 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
944 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
945 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
946 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
947 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
948 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
949 
#define SYSBSLOFF              (0x4000)       /* SYS - BSL Memeory disabled */
950 
#define SYSBSLPE               (0x8000)       /* SYS - BSL Memory protection enabled */
951 
 
952 
/* SYSBSLC Control Bits */
953 
#define SYSBSLSIZE0_L          (0x0001)       /* SYS - BSL Protection Size 0 */
954 
#define SYSBSLSIZE1_L          (0x0002)       /* SYS - BSL Protection Size 1 */
955 
#define SYSBSLR_L              (0x0004)       /* SYS - RAM assigned to BSL */
956 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
957 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
958 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
959 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
960 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
961 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
962 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
963 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
964 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
965 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
966 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
967 
 
968 
/* SYSBSLC Control Bits */
969 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
970 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
971 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
972 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
973 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
974 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
975 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
976 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
977 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
978 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
979 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
980 
#define SYSBSLOFF_H            (0x0040)       /* SYS - BSL Memeory disabled */
981 
#define SYSBSLPE_H             (0x0080)       /* SYS - BSL Memory protection enabled */
982 
 
983 
/* SYSJMBC Control Bits */
984 
#define JMBIN0FG               (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
985 
#define JMBIN1FG               (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
986 
#define JMBOUT0FG              (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
987 
#define JMBOUT1FG              (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
988 
#define JMBMODE                (0x0010)       /* SYS - JMB 16/32 Bit Mode */
989 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
990 
#define JMBCLR0OFF             (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
991 
#define JMBCLR1OFF             (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
992 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
993 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
994 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
995 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
996 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
997 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
998 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
999 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
1000 
 
1001 
/* SYSJMBC Control Bits */
1002 
#define JMBIN0FG_L             (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
1003 
#define JMBIN1FG_L             (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
1004 
#define JMBOUT0FG_L            (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
1005 
#define JMBOUT1FG_L            (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
1006 
#define JMBMODE_L              (0x0010)       /* SYS - JMB 16/32 Bit Mode */
1007 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
1008 
#define JMBCLR0OFF_L           (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
1009 
#define JMBCLR1OFF_L           (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
1010 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
1011 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
1012 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
1013 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
1014 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
1015 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
1016 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
1017 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
1018 
 
1019 
/* SYSJMBC Control Bits */
1020 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
1021 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
1022 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
1023 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
1024 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
1025 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
1026 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
1027 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
1028 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
1029 
 
1030 
/* SYSCNF Control Bits */
1031 
//#define RESERVED            (0x0001)  /* SYS - Reserved */
1032 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
1033 
#define SVMOE                  (0x0004)       /* SYS - SVM output enable */
1034 
#define SVMPO                  (0x0008)       /* SYS - SVM based Ports off flag */
1035 
#define SVMPD                  (0x0010)       /* SYS - Incoming JTAG Mailbox 0 Flag */
1036 
#define SVMEN                  (0x0020)       /* SYS - SVM based port disable */
1037 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
1038 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
1039 
#define RAMLCK0                (0x0100)       /* SYS - Write lock enable for configuration RAM */
1040 
#define RAMLCK1                (0x0200)       /* SYS - Write lock enable for application’s code RAM */
1041 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
1042 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
1043 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
1044 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
1045 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
1046 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
1047 
 
1048 
/* SYSCNF Control Bits */
1049 
//#define RESERVED            (0x0001)  /* SYS - Reserved */
1050 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
1051 
#define SVMOE_L                (0x0004)       /* SYS - SVM output enable */
1052 
#define SVMPO_L                (0x0008)       /* SYS - SVM based Ports off flag */
1053 
#define SVMPD_L                (0x0010)       /* SYS - Incoming JTAG Mailbox 0 Flag */
1054 
#define SVMEN_L                (0x0020)       /* SYS - SVM based port disable */
1055 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
1056 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
1057 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
1058 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
1059 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
1060 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
1061 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
1062 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
1063 
 
1064 
/* SYSCNF Control Bits */
1065 
//#define RESERVED            (0x0001)  /* SYS - Reserved */
1066 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
1067 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
1068 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
1069 
#define RAMLCK0_H              (0x0001)       /* SYS - Write lock enable for configuration RAM */
1070 
#define RAMLCK1_H              (0x0002)       /* SYS - Write lock enable for application’s code RAM */
1071 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
1072 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
1073 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
1074 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
1075 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
1076 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
1077 
 
1078 
/* SYSUNIV Definitions */
1079 
#define SYSUNIV_NONE           (0x0000)       /* No Interrupt pending */
1080 
#define SYSUNIV_NMIIFG         (0x0002)       /* SYSUNIV : NMIIFG */
1081 
#define SYSUNIV_OFIFG          (0x0004)       /* SYSUNIV : Osc. Fail - OFIFG */
1082 
#define SYSUNIV_SYSBERRIV      (0x0006)       /* SYSUNIV : Bus Error - SYSBERRIV */
1083 
 
1084 
/* SYSSNIV Definitions */
1085 
#define SYSSNIV_NONE           (0x0000)       /* No Interrupt pending */
1086 
#define SYSSNIV_SVMIFG         (0x0002)       /* SYSSNIV : SVMLIFG */
1087 
#define SYSSNIV_VMAIFG         (0x0004)       /* SYSSNIV : VMAIFG */
1088 
#define SYSSNIV_JMBINIFG       (0x0006)       /* SYSSNIV : JMBINIFG */
1089 
#define SYSSNIV_JMBOUTIFG      (0x0008)       /* SYSSNIV : JMBOUTIFG */
1090 
 
1091 
/* SYSRSTIV Definitions */
1092 
#define SYSRSTIV_NONE          (0x0000)       /* No Interrupt pending */
1093 
#define SYSRSTIV_BOR           (0x0002)       /* SYSRSTIV : BOR */
1094 
#define SYSRSTIV_SVMBOR        (0x0004)       /* SYSRSTIV : SVMBOR */
1095 
#define SYSRSTIV_RSTNMI        (0x0006)       /* SYSRSTIV : RST/NMI */
1096 
#define SYSRSTIV_DOBOR         (0x0008)       /* SYSRSTIV : Do BOR */
1097 
#define SYSRSTIV_SECYV         (0x000A)       /* SYSRSTIV : Security violation */
1098 
#define SYSRSTIV_DOPOR         (0x000C)       /* SYSRSTIV : Do POR */
1099 
#define SYSRSTIV_WDTTO         (0x000E)       /* SYSRSTIV : WDT Time out */
1100 
#define SYSRSTIV_WDTKEY        (0x0010)       /* SYSRSTIV : WDTKEY violation */
1101 
#define SYSRSTIV_CCSKEY        (0x0012)       /* SYSRSTIV : CCS Key violation */
1102 
#define SYSRSTIV_PMMKEY        (0x0014)       /* SYSRSTIV : PMMKEY violation */
1103 
#define SYSRSTIV_PERF          (0x0016)       /* SYSRSTIV : peripheral/config area fetch */
1104 
/************************************************************
1105 
* Timer0_A3
1106 
************************************************************/
1107 
#define __MSP430_HAS_T0A3__                   /* Definition to show that Module is available */
1108 
#define __MSP430_BASEADDRESS_T0A3__ 0x0340
1109 
 
1110 
SFR_16BIT(TA0CTL);                            /* Timer0_A3 Control */
1111 
SFR_16BIT(TA0CCTL0);                          /* Timer0_A3 Capture/Compare Control 0 */
1112 
SFR_16BIT(TA0CCTL1);                          /* Timer0_A3 Capture/Compare Control 1 */
1113 
SFR_16BIT(TA0CCTL2);                          /* Timer0_A3 Capture/Compare Control 2 */
1114 
SFR_16BIT(TA0R);                              /* Timer0_A3 */
1115 
SFR_16BIT(TA0CCR0);                           /* Timer0_A3 Capture/Compare 0 */
1116 
SFR_16BIT(TA0CCR1);                           /* Timer0_A3 Capture/Compare 1 */
1117 
SFR_16BIT(TA0CCR2);                           /* Timer0_A3 Capture/Compare 2 */
1118 
SFR_16BIT(TA0IV);                             /* Timer0_A3 Interrupt Vector Word */
1119 
SFR_16BIT(TA0EX0);                            /* Timer0_A3 Expansion Register 0 */
1120 
 
1121 
/* TAxCTL Control Bits */
1122 
#define TASSEL1                (0x0200)       /* Timer A clock source select 0 */
1123 
#define TASSEL0                (0x0100)       /* Timer A clock source select 1 */
1124 
#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
1125 
#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
1126 
#define MC1                    (0x0020)       /* Timer A mode control 1 */
1127 
#define MC0                    (0x0010)       /* Timer A mode control 0 */
1128 
#define TACLR                  (0x0004)       /* Timer A counter clear */
1129 
#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
1130 
#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
1131 
 
1132 
#define MC_0                   (0*0x10u)      /* Timer A mode control: 0 - Stop */
1133 
#define MC_1                   (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
1134 
#define MC_2                   (2*0x10u)      /* Timer A mode control: 2 - Continous up */
1135 
#define MC_3                   (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
1136 
#define ID_0                   (0*0x40u)      /* Timer A input divider: 0 - /1 */
1137 
#define ID_1                   (1*0x40u)      /* Timer A input divider: 1 - /2 */
1138 
#define ID_2                   (2*0x40u)      /* Timer A input divider: 2 - /4 */
1139 
#define ID_3                   (3*0x40u)      /* Timer A input divider: 3 - /8 */
1140 
#define TASSEL_0               (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
1141 
#define TASSEL_1               (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
1142 
#define TASSEL_2               (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
1143 
#define TASSEL_3               (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
1144 
#define MC__STOP               (0*0x10u)      /* Timer A mode control: 0 - Stop */
1145 
#define MC__UP                 (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
1146 
#define MC__CONTINOUS          (2*0x10u)      /* Timer A mode control: 2 - Continous up */
1147 
#define MC__UPDOWN             (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
1148 
#define ID__1                  (0*0x40u)      /* Timer A input divider: 0 - /1 */
1149 
#define ID__2                  (1*0x40u)      /* Timer A input divider: 1 - /2 */
1150 
#define ID__4                  (2*0x40u)      /* Timer A input divider: 2 - /4 */
1151 
#define ID__8                  (3*0x40u)      /* Timer A input divider: 3 - /8 */
1152 
#define TASSEL__TACLK          (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
1153 
#define TASSEL__ACLK           (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
1154 
#define TASSEL__SMCLK          (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
1155 
#define TASSEL__INCLK          (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
1156 
 
1157 
/* TAxCCTLx Control Bits */
1158 
#define CM1                    (0x8000)       /* Capture mode 1 */
1159 
#define CM0                    (0x4000)       /* Capture mode 0 */
1160 
#define CCIS1                  (0x2000)       /* Capture input select 1 */
1161 
#define CCIS0                  (0x1000)       /* Capture input select 0 */
1162 
#define SCS                    (0x0800)       /* Capture sychronize */
1163 
#define SCCI                   (0x0400)       /* Latched capture signal (read) */
1164 
#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
1165 
#define OUTMOD2                (0x0080)       /* Output mode 2 */
1166 
#define OUTMOD1                (0x0040)       /* Output mode 1 */
1167 
#define OUTMOD0                (0x0020)       /* Output mode 0 */
1168 
#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
1169 
#define CCI                    (0x0008)       /* Capture input signal (read) */
1170 
#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
1171 
#define COV                    (0x0002)       /* Capture/compare overflow flag */
1172 
#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
1173 
 
1174 
#define OUTMOD_0               (0*0x20u)      /* PWM output mode: 0 - output only */
1175 
#define OUTMOD_1               (1*0x20u)      /* PWM output mode: 1 - set */
1176 
#define OUTMOD_2               (2*0x20u)      /* PWM output mode: 2 - PWM toggle/reset */
1177 
#define OUTMOD_3               (3*0x20u)      /* PWM output mode: 3 - PWM set/reset */
1178 
#define OUTMOD_4               (4*0x20u)      /* PWM output mode: 4 - toggle */
1179 
#define OUTMOD_5               (5*0x20u)      /* PWM output mode: 5 - Reset */
1180 
#define OUTMOD_6               (6*0x20u)      /* PWM output mode: 6 - PWM toggle/set */
1181 
#define OUTMOD_7               (7*0x20u)      /* PWM output mode: 7 - PWM reset/set */
1182 
#define CCIS_0                 (0*0x1000u)    /* Capture input select: 0 - CCIxA */
1183 
#define CCIS_1                 (1*0x1000u)    /* Capture input select: 1 - CCIxB */
1184 
#define CCIS_2                 (2*0x1000u)    /* Capture input select: 2 - GND */
1185 
#define CCIS_3                 (3*0x1000u)    /* Capture input select: 3 - Vcc */
1186 
#define CM_0                   (0*0x4000u)    /* Capture mode: 0 - disabled */
1187 
#define CM_1                   (1*0x4000u)    /* Capture mode: 1 - pos. edge */
1188 
#define CM_2                   (2*0x4000u)    /* Capture mode: 1 - neg. edge */
1189 
#define CM_3                   (3*0x4000u)    /* Capture mode: 1 - both edges */
1190 
 
1191 
/* TAxEX0 Control Bits */
1192 
#define TAIDEX0                (0x0001)       /* Timer A Input divider expansion Bit: 0 */
1193 
#define TAIDEX1                (0x0002)       /* Timer A Input divider expansion Bit: 1 */
1194 
#define TAIDEX2                (0x0004)       /* Timer A Input divider expansion Bit: 2 */
1195 
 
1196 
#define TAIDEX_0               (0*0x0001u)    /* Timer A Input divider expansion : /1 */
1197 
#define TAIDEX_1               (1*0x0001u)    /* Timer A Input divider expansion : /2 */
1198 
#define TAIDEX_2               (2*0x0001u)    /* Timer A Input divider expansion : /3 */
1199 
#define TAIDEX_3               (3*0x0001u)    /* Timer A Input divider expansion : /4 */
1200 
#define TAIDEX_4               (4*0x0001u)    /* Timer A Input divider expansion : /5 */
1201 
#define TAIDEX_5               (5*0x0001u)    /* Timer A Input divider expansion : /6 */
1202 
#define TAIDEX_6               (6*0x0001u)    /* Timer A Input divider expansion : /7 */
1203 
#define TAIDEX_7               (7*0x0001u)    /* Timer A Input divider expansion : /8 */
1204 
 
1205 
/* T0A3IV Definitions */
1206 
#define TA0IV_NONE             (0x0000)       /* No Interrupt pending */
1207 
#define TA0IV_TA0CCR1          (0x0002)       /* TA0CCR1_CCIFG */
1208 
#define TA0IV_TA0CCR2          (0x0004)       /* TA0CCR2_CCIFG */
1209 
#define TA0IV_3                (0x0006)       /* Reserved */
1210 
#define TA0IV_4                (0x0008)       /* Reserved */
1211 
#define TA0IV_5                (0x000A)       /* Reserved */
1212 
#define TA0IV_6                (0x000C)       /* Reserved */
1213 
#define TA0IV_TA0IFG           (0x000E)       /* TA0IFG */
1214 
 
1215 
/************************************************************
1216 
* Timer1_A3
1217 
************************************************************/
1218 
#define __MSP430_HAS_T1A3__                   /* Definition to show that Module is available */
1219 
#define __MSP430_BASEADDRESS_T1A3__ 0x0380
1220 
 
1221 
SFR_16BIT(TA1CTL);                            /* Timer1_A3 Control */
1222 
SFR_16BIT(TA1CCTL0);                          /* Timer1_A3 Capture/Compare Control 0 */
1223 
SFR_16BIT(TA1CCTL1);                          /* Timer1_A3 Capture/Compare Control 1 */
1224 
SFR_16BIT(TA1CCTL2);                          /* Timer1_A3 Capture/Compare Control 2 */
1225 
SFR_16BIT(TA1R);                              /* Timer1_A3 */
1226 
SFR_16BIT(TA1CCR0);                           /* Timer1_A3 Capture/Compare 0 */
1227 
SFR_16BIT(TA1CCR1);                           /* Timer1_A3 Capture/Compare 1 */
1228 
SFR_16BIT(TA1CCR2);                           /* Timer1_A3 Capture/Compare 2 */
1229 
SFR_16BIT(TA1IV);                             /* Timer1_A3 Interrupt Vector Word */
1230 
SFR_16BIT(TA1EX0);                            /* Timer1_A3 Expansion Register 0 */
1231 
 
1232 
/* Bits are already defined within the Timer0_Ax */
1233 
 
1234 
/* TA1IV Definitions */
1235 
#define TA1IV_NONE             (0x0000)       /* No Interrupt pending */
1236 
#define TA1IV_TA1CCR1          (0x0002)       /* TA1CCR1_CCIFG */
1237 
#define TA1IV_TA1CCR2          (0x0004)       /* TA1CCR2_CCIFG */
1238 
#define TA1IV_3                (0x0006)       /* Reserved */
1239 
#define TA1IV_4                (0x0008)       /* Reserved */
1240 
#define TA1IV_5                (0x000A)       /* Reserved */
1241 
#define TA1IV_6                (0x000C)       /* Reserved */
1242 
#define TA1IV_TA1IFG           (0x000E)       /* TA1IFG */
1243 
 
1244 
/************************************************************
1245 
* WATCHDOG TIMER A
1246 
************************************************************/
1247 
#define __MSP430_HAS_WDT_A__                  /* Definition to show that Module is available */
1248 
#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
1249 
 
1250 
SFR_16BIT(WDTCTL);                            /* Watchdog Timer Control */
1251 
SFR_8BIT(WDTCTL_L);                           /* Watchdog Timer Control */
1252 
SFR_8BIT(WDTCTL_H);                           /* Watchdog Timer Control */
1253 
/* The bit names have been prefixed with "WDT" */
1254 
/* WDTCTL Control Bits */
1255 
#define WDTIS0                 (0x0001)       /* WDT - Timer Interval Select 0 */
1256 
#define WDTIS1                 (0x0002)       /* WDT - Timer Interval Select 1 */
1257 
#define WDTIS2                 (0x0004)       /* WDT - Timer Interval Select 2 */
1258 
#define WDTCNTCL               (0x0008)       /* WDT - Timer Clear */
1259 
#define WDTTMSEL               (0x0010)       /* WDT - Timer Mode Select */
1260 
#define WDTSSEL0               (0x0020)       /* WDT - Timer Clock Source Select 0 */
1261 
#define WDTSSEL1               (0x0040)       /* WDT - Timer Clock Source Select 1 */
1262 
#define WDTHOLD                (0x0080)       /* WDT - Timer hold */
1263 
 
1264 
/* WDTCTL Control Bits */
1265 
#define WDTIS0_L               (0x0001)       /* WDT - Timer Interval Select 0 */
1266 
#define WDTIS1_L               (0x0002)       /* WDT - Timer Interval Select 1 */
1267 
#define WDTIS2_L               (0x0004)       /* WDT - Timer Interval Select 2 */
1268 
#define WDTCNTCL_L             (0x0008)       /* WDT - Timer Clear */
1269 
#define WDTTMSEL_L             (0x0010)       /* WDT - Timer Mode Select */
1270 
#define WDTSSEL0_L             (0x0020)       /* WDT - Timer Clock Source Select 0 */
1271 
#define WDTSSEL1_L             (0x0040)       /* WDT - Timer Clock Source Select 1 */
1272 
#define WDTHOLD_L              (0x0080)       /* WDT - Timer hold */
1273 
 
1274 
/* WDTCTL Control Bits */
1275 
 
1276 
#define WDTPW                  (0x5A00)
1277 
 
1278 
#define WDTIS_0                (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
1279 
#define WDTIS_1                (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
1280 
#define WDTIS_2                (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
1281 
#define WDTIS_3                (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
1282 
#define WDTIS_4                (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
1283 
#define WDTIS_5                (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
1284 
#define WDTIS_6                (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
1285 
#define WDTIS_7                (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
1286 
#define WDTIS__2G              (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
1287 
#define WDTIS__128M            (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
1288 
#define WDTIS__8192K           (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
1289 
#define WDTIS__512K            (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
1290 
#define WDTIS__32K             (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
1291 
#define WDTIS__8192            (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
1292 
#define WDTIS__512             (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
1293 
#define WDTIS__64              (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
1294 
 
1295 
#define WDTSSEL_0              (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
1296 
#define WDTSSEL_1              (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
1297 
#define WDTSSEL_2              (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
1298 
#define WDTSSEL_3              (3*0x0020u)    /* WDT - Timer Clock Source Select: reserved */
1299 
#define WDTSSEL__SMCLK         (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
1300 
#define WDTSSEL__ACLK          (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
1301 
#define WDTSSEL__VLO           (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
1302 
 
1303 
/* WDT-interval times [1ms] coded with Bits 0-2 */
1304 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
1305 
#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2)                         /* 32ms interval (default) */
1306 
#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0)                  /* 8ms     " */
1307 
#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1)                  /* 0.5ms   " */
1308 
#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)           /* 0.064ms " */
1309 
/* WDT is clocked by fACLK (assumed 32KHz) */
1310 
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)                /* 1000ms  " */
1311 
#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0)         /* 250ms   " */
1312 
#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1)         /* 16ms    " */
1313 
#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0)  /* 1.9ms   " */
1314 
/* Watchdog mode -> reset after expired time */
1315 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
1316 
#define WDT_MRST_32         (WDTPW+WDTCNTCL+WDTIS2)                                  /* 32ms interval (default) */
1317 
#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS2+WDTIS0)                           /* 8ms     " */
1318 
#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS2+WDTIS1)                           /* 0.5ms   " */
1319 
#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)                    /* 0.064ms " */
1320 
/* WDT is clocked by fACLK (assumed 32KHz) */
1321 
#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2)                         /* 1000ms  " */
1322 
#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0)                  /* 250ms   " */
1323 
#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1)                  /* 16ms    " */
1324 
#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0)           /* 1.9ms   " */
1325 
 
1326 
 
1327 
/************************************************************
1328 
* Interrupt Vectors (offset from 0xFFFF - 0x20)
1329 
************************************************************/
1330 
 
1331 
#pragma diag_suppress 1107
1332 
#define VECTOR_NAME(name)             name##_ptr
1333 
#define EMIT_PRAGMA(x)                _Pragma(#x)
1334 
#define CREATE_VECTOR(name)           void * const VECTOR_NAME(name) = (void *)(long)&name
1335 
#define PLACE_VECTOR(vector,section)  EMIT_PRAGMA(DATA_SECTION(vector,section))
1336 
#define PLACE_INTERRUPT(func)         EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
1337 
#define ISR_VECTOR(func,offset)       CREATE_VECTOR(func); \
1338 
                                      PLACE_VECTOR(VECTOR_NAME(func), offset) \
1339 
                                      PLACE_INTERRUPT(func)
1340 
 
1341 
 
1342 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1343 
#define PORT2_VECTOR            ".int05"                    /* 0xFFEA Port 2 */
1344 
#else
1345 
#define PORT2_VECTOR            (5 * 1u)                     /* 0xFFEA Port 2 */
1346 
/*#define PORT2_ISR(func)         ISR_VECTOR(func, ".int05")  */ /* 0xFFEA Port 2 */ /* CCE V2 Style */
1347 
#endif
1348 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1349 
#define TIMER0_A1_VECTOR        ".int06"                    /* 0xFFEC Timer0_A3 CC1-2, TA1 */
1350 
#else
1351 
#define TIMER0_A1_VECTOR        (6 * 1u)                     /* 0xFFEC Timer0_A3 CC1-2, TA1 */
1352 
/*#define TIMER0_A1_ISR(func)     ISR_VECTOR(func, ".int06")  */ /* 0xFFEC Timer0_A3 CC1-2, TA1 */ /* CCE V2 Style */
1353 
#endif
1354 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1355 
#define TIMER0_A0_VECTOR        ".int07"                    /* 0xFFEE Timer0_A3 CC0 */
1356 
#else
1357 
#define TIMER0_A0_VECTOR        (7 * 1u)                     /* 0xFFEE Timer0_A3 CC0 */
1358 
/*#define TIMER0_A0_ISR(func)     ISR_VECTOR(func, ".int07")  */ /* 0xFFEE Timer0_A3 CC0 */ /* CCE V2 Style */
1359 
#endif
1360 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1361 
#define PORT1_VECTOR            ".int08"                    /* 0xFFF0 Port 1 */
1362 
#else
1363 
#define PORT1_VECTOR            (8 * 1u)                     /* 0xFFF0 Port 1 */
1364 
/*#define PORT1_ISR(func)         ISR_VECTOR(func, ".int08")  */ /* 0xFFF0 Port 1 */ /* CCE V2 Style */
1365 
#endif
1366 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1367 
#define APOOL_VECTOR            ".int09"                    /* 0xFFF2 Analog Pool */
1368 
#else
1369 
#define APOOL_VECTOR            (9 * 1u)                     /* 0xFFF2 Analog Pool */
1370 
/*#define APOOL_ISR(func)         ISR_VECTOR(func, ".int09")  */ /* 0xFFF2 Analog Pool */ /* CCE V2 Style */
1371 
#endif
1372 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1373 
#define WDT_VECTOR              ".int10"                    /* 0xFFF4 Watchdog Timer */
1374 
#else
1375 
#define WDT_VECTOR              (10 * 1u)                    /* 0xFFF4 Watchdog Timer */
1376 
/*#define WDT_ISR(func)           ISR_VECTOR(func, ".int10")  */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
1377 
#endif
1378 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1379 
#define TIMER1_A1_VECTOR        ".int11"                    /* 0xFFF6 Timer1_A5 CC1-4, TA */
1380 
#else
1381 
#define TIMER1_A1_VECTOR        (11 * 1u)                    /* 0xFFF6 Timer1_A5 CC1-4, TA */
1382 
/*#define TIMER1_A1_ISR(func)     ISR_VECTOR(func, ".int11")  */ /* 0xFFF6 Timer1_A5 CC1-4, TA */ /* CCE V2 Style */
1383 
#endif
1384 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1385 
#define TIMER1_A0_VECTOR        ".int12"                    /* 0xFFF8 Timer1_A5 CC0 */
1386 
#else
1387 
#define TIMER1_A0_VECTOR        (12 * 1u)                    /* 0xFFF8 Timer1_A5 CC0 */
1388 
/*#define TIMER1_A0_ISR(func)     ISR_VECTOR(func, ".int12")  */ /* 0xFFF8 Timer1_A5 CC0 */ /* CCE V2 Style */
1389 
#endif
1390 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1391 
#define UNMI_VECTOR             ".int13"                    /* 0xFFFA User Non-maskable */
1392 
#else
1393 
#define UNMI_VECTOR             (13 * 1u)                    /* 0xFFFA User Non-maskable */
1394 
/*#define UNMI_ISR(func)          ISR_VECTOR(func, ".int13")  */ /* 0xFFFA User Non-maskable */ /* CCE V2 Style */
1395 
#endif
1396 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1397 
#define SYSNMI_VECTOR           ".int14"                    /* 0xFFFC System Non-maskable */
1398 
#else
1399 
#define SYSNMI_VECTOR           (14 * 1u)                    /* 0xFFFC System Non-maskable */
1400 
/*#define SYSNMI_ISR(func)        ISR_VECTOR(func, ".int14")  */ /* 0xFFFC System Non-maskable */ /* CCE V2 Style */
1401 
#endif
1402 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
1403 
#define RESET_VECTOR            ".reset"                    /* 0xFFFE Reset [Highest Priority] */
1404 
#else
1405 
#define RESET_VECTOR            (15 * 1u)                    /* 0xFFFE Reset [Highest Priority] */
1406 
/*#define RESET_ISR(func)         ISR_VECTOR(func, ".int15")  */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
1407 
#endif
1408 
 
1409 
/************************************************************
1410 
* End of Modules
1411 
************************************************************/
1412 
 
1413 
#ifdef __cplusplus
1414 
}
1415 
#endif /* extern "C" */
1416 
 
1417 
#endif /* #ifndef __msp430x09x */
1418