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2850 dpurdie 1 
/********************************************************************
2 
*
3 
* Standard register and bit definitions for the Texas Instruments
4 
* MSP430 microcontroller.
5 
*
6 
* This file supports assembler and C development for
7 
* MSP430x54xA devices.
8 
*
9 
* Texas Instruments, Version 1.4
10 
*
11 
* Rev. 1.0, Setup
12 
* Rev. 1.1, added PM5CTL0
13 
* Rev. 1.2, fixed wrong bit definition in PM5CTL0 (LOCKLPM5)
14 
* Rev. 1.3, Changed access type of DMAxSZ registers to word only
15 
* Rev. 1.4  Changed access type of TimerA/B registers to word only
16 
*
17 
********************************************************************/
18 
 
19 
#ifndef __msp430x54xA
20 
#define __msp430x54xA
21 
 
22 
#ifdef __cplusplus
23 
extern "C" {
24 
#endif
25 
 
26 
 
27 
/*----------------------------------------------------------------------------*/
28 
/* PERIPHERAL FILE MAP                                                        */
29 
/*----------------------------------------------------------------------------*/
30 
 
31 
/* External references resolved by a device-specific linker command file */
32 
#define SFR_8BIT(address)   extern volatile unsigned char address
33 
#define SFR_16BIT(address)  extern volatile unsigned int address
34 
//#define SFR_20BIT(address)  extern volatile unsigned int address
35 
typedef void (* __SFR_FARPTR)();
36 
#define SFR_20BIT(address) extern __SFR_FARPTR address
37 
#define SFR_32BIT(address)  extern volatile unsigned long address
38 
 
39 
 
40 
 
41 
/************************************************************
42 
* STANDARD BITS
43 
************************************************************/
44 
 
45 
#define BIT0                   (0x0001)
46 
#define BIT1                   (0x0002)
47 
#define BIT2                   (0x0004)
48 
#define BIT3                   (0x0008)
49 
#define BIT4                   (0x0010)
50 
#define BIT5                   (0x0020)
51 
#define BIT6                   (0x0040)
52 
#define BIT7                   (0x0080)
53 
#define BIT8                   (0x0100)
54 
#define BIT9                   (0x0200)
55 
#define BITA                   (0x0400)
56 
#define BITB                   (0x0800)
57 
#define BITC                   (0x1000)
58 
#define BITD                   (0x2000)
59 
#define BITE                   (0x4000)
60 
#define BITF                   (0x8000)
61 
 
62 
/************************************************************
63 
* STATUS REGISTER BITS
64 
************************************************************/
65 
 
66 
#define C                      (0x0001)
67 
#define Z                      (0x0002)
68 
#define N                      (0x0004)
69 
#define V                      (0x0100)
70 
#define GIE                    (0x0008)
71 
#define CPUOFF                 (0x0010)
72 
#define OSCOFF                 (0x0020)
73 
#define SCG0                   (0x0040)
74 
#define SCG1                   (0x0080)
75 
 
76 
/* Low Power Modes coded with Bits 4-7 in SR */
77 
 
78 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
79 
#define LPM0                   (CPUOFF)
80 
#define LPM1                   (SCG0+CPUOFF)
81 
#define LPM2                   (SCG1+CPUOFF)
82 
#define LPM3                   (SCG1+SCG0+CPUOFF)
83 
#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)
84 
/* End #defines for assembler */
85 
 
86 
#else /* Begin #defines for C */
87 
#define LPM0_bits              (CPUOFF)
88 
#define LPM1_bits              (SCG0+CPUOFF)
89 
#define LPM2_bits              (SCG1+CPUOFF)
90 
#define LPM3_bits              (SCG1+SCG0+CPUOFF)
91 
#define LPM4_bits              (SCG1+SCG0+OSCOFF+CPUOFF)
92 
 
93 
#include "in430.h"
94 
 
95 
#define LPM0         _bis_SR_register(LPM0_bits)         /* Enter Low Power Mode 0 */
96 
#define LPM0_EXIT    _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
97 
#define LPM1         _bis_SR_register(LPM1_bits)         /* Enter Low Power Mode 1 */
98 
#define LPM1_EXIT    _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
99 
#define LPM2         _bis_SR_register(LPM2_bits)         /* Enter Low Power Mode 2 */
100 
#define LPM2_EXIT    _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
101 
#define LPM3         _bis_SR_register(LPM3_bits)         /* Enter Low Power Mode 3 */
102 
#define LPM3_EXIT    _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
103 
#define LPM4         _bis_SR_register(LPM4_bits)         /* Enter Low Power Mode 4 */
104 
#define LPM4_EXIT    _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
105 
#endif /* End #defines for C */
106 
 
107 
/************************************************************
108 
* CPU
109 
************************************************************/
110 
#define __MSP430_HAS_MSP430XV2_CPU__                /* Definition to show that it has MSP430XV2 CPU */
111 
 
112 
/************************************************************
113 
* PERIPHERAL FILE MAP
114 
************************************************************/
115 
 
116 
/************************************************************
117 
* ADC12 PLUS
118 
************************************************************/
119 
#define __MSP430_HAS_ADC12_PLUS__                /* Definition to show that Module is available */
120 
#define __MSP430_BASEADDRESS_ADC12_PLUS__ 0x0700
121 
 
122 
SFR_16BIT(ADC12CTL0);                         /* ADC12+ Control 0 */
123 
SFR_8BIT(ADC12CTL0_L);                        /* ADC12+ Control 0 */
124 
SFR_8BIT(ADC12CTL0_H);                        /* ADC12+ Control 0 */
125 
SFR_16BIT(ADC12CTL1);                         /* ADC12+ Control 1 */
126 
SFR_8BIT(ADC12CTL1_L);                        /* ADC12+ Control 1 */
127 
SFR_8BIT(ADC12CTL1_H);                        /* ADC12+ Control 1 */
128 
SFR_16BIT(ADC12CTL2);                         /* ADC12+ Control 2 */
129 
SFR_8BIT(ADC12CTL2_L);                        /* ADC12+ Control 2 */
130 
SFR_8BIT(ADC12CTL2_H);                        /* ADC12+ Control 2 */
131 
SFR_16BIT(ADC12IFG);                          /* ADC12+ Interrupt Flag */
132 
SFR_8BIT(ADC12IFG_L);                         /* ADC12+ Interrupt Flag */
133 
SFR_8BIT(ADC12IFG_H);                         /* ADC12+ Interrupt Flag */
134 
SFR_16BIT(ADC12IE);                           /* ADC12+ Interrupt Enable */
135 
SFR_8BIT(ADC12IE_L);                          /* ADC12+ Interrupt Enable */
136 
SFR_8BIT(ADC12IE_H);                          /* ADC12+ Interrupt Enable */
137 
SFR_16BIT(ADC12IV);                           /* ADC12+ Interrupt Vector Word */
138 
SFR_8BIT(ADC12IV_L);                          /* ADC12+ Interrupt Vector Word */
139 
SFR_8BIT(ADC12IV_H);                          /* ADC12+ Interrupt Vector Word */
140 
 
141 
SFR_16BIT(ADC12MEM0);                         /* ADC12 Conversion Memory 0 */
142 
SFR_8BIT(ADC12MEM0_L);                        /* ADC12 Conversion Memory 0 */
143 
SFR_8BIT(ADC12MEM0_H);                        /* ADC12 Conversion Memory 0 */
144 
SFR_16BIT(ADC12MEM1);                         /* ADC12 Conversion Memory 1 */
145 
SFR_8BIT(ADC12MEM1_L);                        /* ADC12 Conversion Memory 1 */
146 
SFR_8BIT(ADC12MEM1_H);                        /* ADC12 Conversion Memory 1 */
147 
SFR_16BIT(ADC12MEM2);                         /* ADC12 Conversion Memory 2 */
148 
SFR_8BIT(ADC12MEM2_L);                        /* ADC12 Conversion Memory 2 */
149 
SFR_8BIT(ADC12MEM2_H);                        /* ADC12 Conversion Memory 2 */
150 
SFR_16BIT(ADC12MEM3);                         /* ADC12 Conversion Memory 3 */
151 
SFR_8BIT(ADC12MEM3_L);                        /* ADC12 Conversion Memory 3 */
152 
SFR_8BIT(ADC12MEM3_H);                        /* ADC12 Conversion Memory 3 */
153 
SFR_16BIT(ADC12MEM4);                         /* ADC12 Conversion Memory 4 */
154 
SFR_8BIT(ADC12MEM4_L);                        /* ADC12 Conversion Memory 4 */
155 
SFR_8BIT(ADC12MEM4_H);                        /* ADC12 Conversion Memory 4 */
156 
SFR_16BIT(ADC12MEM5);                         /* ADC12 Conversion Memory 5 */
157 
SFR_8BIT(ADC12MEM5_L);                        /* ADC12 Conversion Memory 5 */
158 
SFR_8BIT(ADC12MEM5_H);                        /* ADC12 Conversion Memory 5 */
159 
SFR_16BIT(ADC12MEM6);                         /* ADC12 Conversion Memory 6 */
160 
SFR_8BIT(ADC12MEM6_L);                        /* ADC12 Conversion Memory 6 */
161 
SFR_8BIT(ADC12MEM6_H);                        /* ADC12 Conversion Memory 6 */
162 
SFR_16BIT(ADC12MEM7);                         /* ADC12 Conversion Memory 7 */
163 
SFR_8BIT(ADC12MEM7_L);                        /* ADC12 Conversion Memory 7 */
164 
SFR_8BIT(ADC12MEM7_H);                        /* ADC12 Conversion Memory 7 */
165 
SFR_16BIT(ADC12MEM8);                         /* ADC12 Conversion Memory 8 */
166 
SFR_8BIT(ADC12MEM8_L);                        /* ADC12 Conversion Memory 8 */
167 
SFR_8BIT(ADC12MEM8_H);                        /* ADC12 Conversion Memory 8 */
168 
SFR_16BIT(ADC12MEM9);                         /* ADC12 Conversion Memory 9 */
169 
SFR_8BIT(ADC12MEM9_L);                        /* ADC12 Conversion Memory 9 */
170 
SFR_8BIT(ADC12MEM9_H);                        /* ADC12 Conversion Memory 9 */
171 
SFR_16BIT(ADC12MEM10);                        /* ADC12 Conversion Memory 10 */
172 
SFR_8BIT(ADC12MEM10_L);                       /* ADC12 Conversion Memory 10 */
173 
SFR_8BIT(ADC12MEM10_H);                       /* ADC12 Conversion Memory 10 */
174 
SFR_16BIT(ADC12MEM11);                        /* ADC12 Conversion Memory 11 */
175 
SFR_8BIT(ADC12MEM11_L);                       /* ADC12 Conversion Memory 11 */
176 
SFR_8BIT(ADC12MEM11_H);                       /* ADC12 Conversion Memory 11 */
177 
SFR_16BIT(ADC12MEM12);                        /* ADC12 Conversion Memory 12 */
178 
SFR_8BIT(ADC12MEM12_L);                       /* ADC12 Conversion Memory 12 */
179 
SFR_8BIT(ADC12MEM12_H);                       /* ADC12 Conversion Memory 12 */
180 
SFR_16BIT(ADC12MEM13);                        /* ADC12 Conversion Memory 13 */
181 
SFR_8BIT(ADC12MEM13_L);                       /* ADC12 Conversion Memory 13 */
182 
SFR_8BIT(ADC12MEM13_H);                       /* ADC12 Conversion Memory 13 */
183 
SFR_16BIT(ADC12MEM14);                        /* ADC12 Conversion Memory 14 */
184 
SFR_8BIT(ADC12MEM14_L);                       /* ADC12 Conversion Memory 14 */
185 
SFR_8BIT(ADC12MEM14_H);                       /* ADC12 Conversion Memory 14 */
186 
SFR_16BIT(ADC12MEM15);                        /* ADC12 Conversion Memory 15 */
187 
SFR_8BIT(ADC12MEM15_L);                       /* ADC12 Conversion Memory 15 */
188 
SFR_8BIT(ADC12MEM15_H);                       /* ADC12 Conversion Memory 15 */
189 
#define ADC12MEM_              ADC12MEM       /* ADC12 Conversion Memory */
190 
#ifdef __ASM_HEADER__
191 
#define ADC12MEM               ADC12MEM0      /* ADC12 Conversion Memory (for assembler) */
192 
#else
193 
#define ADC12MEM               ((int*)        &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
194 
#endif
195 
 
196 
SFR_8BIT(ADC12MCTL0);                         /* ADC12 Memory Control 0 */
197 
SFR_8BIT(ADC12MCTL1);                         /* ADC12 Memory Control 1 */
198 
SFR_8BIT(ADC12MCTL2);                         /* ADC12 Memory Control 2 */
199 
SFR_8BIT(ADC12MCTL3);                         /* ADC12 Memory Control 3 */
200 
SFR_8BIT(ADC12MCTL4);                         /* ADC12 Memory Control 4 */
201 
SFR_8BIT(ADC12MCTL5);                         /* ADC12 Memory Control 5 */
202 
SFR_8BIT(ADC12MCTL6);                         /* ADC12 Memory Control 6 */
203 
SFR_8BIT(ADC12MCTL7);                         /* ADC12 Memory Control 7 */
204 
SFR_8BIT(ADC12MCTL8);                         /* ADC12 Memory Control 8 */
205 
SFR_8BIT(ADC12MCTL9);                         /* ADC12 Memory Control 9 */
206 
SFR_8BIT(ADC12MCTL10);                        /* ADC12 Memory Control 10 */
207 
SFR_8BIT(ADC12MCTL11);                        /* ADC12 Memory Control 11 */
208 
SFR_8BIT(ADC12MCTL12);                        /* ADC12 Memory Control 12 */
209 
SFR_8BIT(ADC12MCTL13);                        /* ADC12 Memory Control 13 */
210 
SFR_8BIT(ADC12MCTL14);                        /* ADC12 Memory Control 14 */
211 
SFR_8BIT(ADC12MCTL15);                        /* ADC12 Memory Control 15 */
212 
#define ADC12MCTL_             ADC12MCTL      /* ADC12 Memory Control */
213 
#ifdef __ASM_HEADER__
214 
#define ADC12MCTL              ADC12MCTL0     /* ADC12 Memory Control (for assembler) */
215 
#else
216 
#define ADC12MCTL              ((char*)       &ADC12MCTL0) /* ADC12 Memory Control (for C) */
217 
#endif
218 
 
219 
/* ADC12CTL0 Control Bits */
220 
#define ADC12SC                (0x0001)       /* ADC12 Start Conversion */
221 
#define ADC12ENC               (0x0002)       /* ADC12 Enable Conversion */
222 
#define ADC12TOVIE             (0x0004)       /* ADC12 Timer Overflow interrupt enable */
223 
#define ADC12OVIE              (0x0008)       /* ADC12 Overflow interrupt enable */
224 
#define ADC12ON                (0x0010)       /* ADC12 On/enable */
225 
#define ADC12REFON             (0x0020)       /* ADC12 Reference on */
226 
#define ADC12REF2_5V           (0x0040)       /* ADC12 Ref 0:1.5V / 1:2.5V */
227 
#define ADC12MSC               (0x0080)       /* ADC12 Multiple SampleConversion */
228 
#define ADC12SHT00             (0x0100)       /* ADC12 Sample Hold 0 Select Bit: 0 */
229 
#define ADC12SHT01             (0x0200)       /* ADC12 Sample Hold 0 Select Bit: 1 */
230 
#define ADC12SHT02             (0x0400)       /* ADC12 Sample Hold 0 Select Bit: 2 */
231 
#define ADC12SHT03             (0x0800)       /* ADC12 Sample Hold 0 Select Bit: 3 */
232 
#define ADC12SHT10             (0x1000)       /* ADC12 Sample Hold 1 Select Bit: 0 */
233 
#define ADC12SHT11             (0x2000)       /* ADC12 Sample Hold 1 Select Bit: 1 */
234 
#define ADC12SHT12             (0x4000)       /* ADC12 Sample Hold 1 Select Bit: 2 */
235 
#define ADC12SHT13             (0x8000)       /* ADC12 Sample Hold 1 Select Bit: 3 */
236 
 
237 
/* ADC12CTL0 Control Bits */
238 
#define ADC12SC_L              (0x0001)       /* ADC12 Start Conversion */
239 
#define ADC12ENC_L             (0x0002)       /* ADC12 Enable Conversion */
240 
#define ADC12TOVIE_L           (0x0004)       /* ADC12 Timer Overflow interrupt enable */
241 
#define ADC12OVIE_L            (0x0008)       /* ADC12 Overflow interrupt enable */
242 
#define ADC12ON_L              (0x0010)       /* ADC12 On/enable */
243 
#define ADC12REFON_L           (0x0020)       /* ADC12 Reference on */
244 
#define ADC12REF2_5V_L         (0x0040)       /* ADC12 Ref 0:1.5V / 1:2.5V */
245 
#define ADC12MSC_L             (0x0080)       /* ADC12 Multiple SampleConversion */
246 
 
247 
/* ADC12CTL0 Control Bits */
248 
#define ADC12SHT00_H           (0x0001)       /* ADC12 Sample Hold 0 Select Bit: 0 */
249 
#define ADC12SHT01_H           (0x0002)       /* ADC12 Sample Hold 0 Select Bit: 1 */
250 
#define ADC12SHT02_H           (0x0004)       /* ADC12 Sample Hold 0 Select Bit: 2 */
251 
#define ADC12SHT03_H           (0x0008)       /* ADC12 Sample Hold 0 Select Bit: 3 */
252 
#define ADC12SHT10_H           (0x0010)       /* ADC12 Sample Hold 1 Select Bit: 0 */
253 
#define ADC12SHT11_H           (0x0020)       /* ADC12 Sample Hold 1 Select Bit: 1 */
254 
#define ADC12SHT12_H           (0x0040)       /* ADC12 Sample Hold 1 Select Bit: 2 */
255 
#define ADC12SHT13_H           (0x0080)       /* ADC12 Sample Hold 1 Select Bit: 3 */
256 
 
257 
#define ADC12SHT0_0            (0*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 0 */
258 
#define ADC12SHT0_1            (1*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 1 */
259 
#define ADC12SHT0_2            (2*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 2 */
260 
#define ADC12SHT0_3            (3*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 3 */
261 
#define ADC12SHT0_4            (4*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 4 */
262 
#define ADC12SHT0_5            (5*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 5 */
263 
#define ADC12SHT0_6            (6*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 6 */
264 
#define ADC12SHT0_7            (7*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 7 */
265 
#define ADC12SHT0_8            (8*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 8 */
266 
#define ADC12SHT0_9            (9*0x100u)     /* ADC12 Sample Hold 0 Select Bit: 9 */
267 
#define ADC12SHT0_10           (10*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 10 */
268 
#define ADC12SHT0_11           (11*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 11 */
269 
#define ADC12SHT0_12           (12*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 12 */
270 
#define ADC12SHT0_13           (13*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 13 */
271 
#define ADC12SHT0_14           (14*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 14 */
272 
#define ADC12SHT0_15           (15*0x100u)    /* ADC12 Sample Hold 0 Select Bit: 15 */
273 
 
274 
#define ADC12SHT1_0            (0*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 0 */
275 
#define ADC12SHT1_1            (1*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 1 */
276 
#define ADC12SHT1_2            (2*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 2 */
277 
#define ADC12SHT1_3            (3*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 3 */
278 
#define ADC12SHT1_4            (4*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 4 */
279 
#define ADC12SHT1_5            (5*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 5 */
280 
#define ADC12SHT1_6            (6*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 6 */
281 
#define ADC12SHT1_7            (7*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 7 */
282 
#define ADC12SHT1_8            (8*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 8 */
283 
#define ADC12SHT1_9            (9*0x1000u)    /* ADC12 Sample Hold 1 Select Bit: 9 */
284 
#define ADC12SHT1_10           (10*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 10 */
285 
#define ADC12SHT1_11           (11*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 11 */
286 
#define ADC12SHT1_12           (12*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 12 */
287 
#define ADC12SHT1_13           (13*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 13 */
288 
#define ADC12SHT1_14           (14*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 14 */
289 
#define ADC12SHT1_15           (15*0x1000u)   /* ADC12 Sample Hold 1 Select Bit: 15 */
290 
 
291 
/* ADC12CTL1 Control Bits */
292 
#define ADC12BUSY              (0x0001)       /* ADC12 Busy */
293 
#define ADC12CONSEQ0           (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
294 
#define ADC12CONSEQ1           (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
295 
#define ADC12SSEL0             (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
296 
#define ADC12SSEL1             (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
297 
#define ADC12DIV0              (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
298 
#define ADC12DIV1              (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
299 
#define ADC12DIV2              (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
300 
#define ADC12ISSH              (0x0100)       /* ADC12 Invert Sample Hold Signal */
301 
#define ADC12SHP               (0x0200)       /* ADC12 Sample/Hold Pulse Mode */
302 
#define ADC12SHS0              (0x0400)       /* ADC12 Sample/Hold Source Bit: 0 */
303 
#define ADC12SHS1              (0x0800)       /* ADC12 Sample/Hold Source Bit: 1 */
304 
#define ADC12CSTARTADD0        (0x1000)       /* ADC12 Conversion Start Address Bit: 0 */
305 
#define ADC12CSTARTADD1        (0x2000)       /* ADC12 Conversion Start Address Bit: 1 */
306 
#define ADC12CSTARTADD2        (0x4000)       /* ADC12 Conversion Start Address Bit: 2 */
307 
#define ADC12CSTARTADD3        (0x8000)       /* ADC12 Conversion Start Address Bit: 3 */
308 
 
309 
/* ADC12CTL1 Control Bits */
310 
#define ADC12BUSY_L            (0x0001)       /* ADC12 Busy */
311 
#define ADC12CONSEQ0_L         (0x0002)       /* ADC12 Conversion Sequence Select Bit: 0 */
312 
#define ADC12CONSEQ1_L         (0x0004)       /* ADC12 Conversion Sequence Select Bit: 1 */
313 
#define ADC12SSEL0_L           (0x0008)       /* ADC12 Clock Source Select Bit: 0 */
314 
#define ADC12SSEL1_L           (0x0010)       /* ADC12 Clock Source Select Bit: 1 */
315 
#define ADC12DIV0_L            (0x0020)       /* ADC12 Clock Divider Select Bit: 0 */
316 
#define ADC12DIV1_L            (0x0040)       /* ADC12 Clock Divider Select Bit: 1 */
317 
#define ADC12DIV2_L            (0x0080)       /* ADC12 Clock Divider Select Bit: 2 */
318 
 
319 
/* ADC12CTL1 Control Bits */
320 
#define ADC12ISSH_H            (0x0001)       /* ADC12 Invert Sample Hold Signal */
321 
#define ADC12SHP_H             (0x0002)       /* ADC12 Sample/Hold Pulse Mode */
322 
#define ADC12SHS0_H            (0x0004)       /* ADC12 Sample/Hold Source Bit: 0 */
323 
#define ADC12SHS1_H            (0x0008)       /* ADC12 Sample/Hold Source Bit: 1 */
324 
#define ADC12CSTARTADD0_H      (0x0010)       /* ADC12 Conversion Start Address Bit: 0 */
325 
#define ADC12CSTARTADD1_H      (0x0020)       /* ADC12 Conversion Start Address Bit: 1 */
326 
#define ADC12CSTARTADD2_H      (0x0040)       /* ADC12 Conversion Start Address Bit: 2 */
327 
#define ADC12CSTARTADD3_H      (0x0080)       /* ADC12 Conversion Start Address Bit: 3 */
328 
 
329 
#define ADC12CONSEQ_0          (0*2u)         /* ADC12 Conversion Sequence Select: 0 */
330 
#define ADC12CONSEQ_1          (1*2u)         /* ADC12 Conversion Sequence Select: 1 */
331 
#define ADC12CONSEQ_2          (2*2u)         /* ADC12 Conversion Sequence Select: 2 */
332 
#define ADC12CONSEQ_3          (3*2u)         /* ADC12 Conversion Sequence Select: 3 */
333 
 
334 
#define ADC12SSEL_0            (0*8u)         /* ADC12 Clock Source Select: 0 */
335 
#define ADC12SSEL_1            (1*8u)         /* ADC12 Clock Source Select: 1 */
336 
#define ADC12SSEL_2            (2*8u)         /* ADC12 Clock Source Select: 2 */
337 
#define ADC12SSEL_3            (3*8u)         /* ADC12 Clock Source Select: 3 */
338 
 
339 
#define ADC12DIV_0             (0*0x20u)      /* ADC12 Clock Divider Select: 0 */
340 
#define ADC12DIV_1             (1*0x20u)      /* ADC12 Clock Divider Select: 1 */
341 
#define ADC12DIV_2             (2*0x20u)      /* ADC12 Clock Divider Select: 2 */
342 
#define ADC12DIV_3             (3*0x20u)      /* ADC12 Clock Divider Select: 3 */
343 
#define ADC12DIV_4             (4*0x20u)      /* ADC12 Clock Divider Select: 4 */
344 
#define ADC12DIV_5             (5*0x20u)      /* ADC12 Clock Divider Select: 5 */
345 
#define ADC12DIV_6             (6*0x20u)      /* ADC12 Clock Divider Select: 6 */
346 
#define ADC12DIV_7             (7*0x20u)      /* ADC12 Clock Divider Select: 7 */
347 
 
348 
#define ADC12SHS_0             (0*0x400u)     /* ADC12 Sample/Hold Source: 0 */
349 
#define ADC12SHS_1             (1*0x400u)     /* ADC12 Sample/Hold Source: 1 */
350 
#define ADC12SHS_2             (2*0x400u)     /* ADC12 Sample/Hold Source: 2 */
351 
#define ADC12SHS_3             (3*0x400u)     /* ADC12 Sample/Hold Source: 3 */
352 
 
353 
#define ADC12CSTARTADD_0       (0*0x1000u)    /* ADC12 Conversion Start Address: 0 */
354 
#define ADC12CSTARTADD_1       (1*0x1000u)    /* ADC12 Conversion Start Address: 1 */
355 
#define ADC12CSTARTADD_2       (2*0x1000u)    /* ADC12 Conversion Start Address: 2 */
356 
#define ADC12CSTARTADD_3       (3*0x1000u)    /* ADC12 Conversion Start Address: 3 */
357 
#define ADC12CSTARTADD_4       (4*0x1000u)    /* ADC12 Conversion Start Address: 4 */
358 
#define ADC12CSTARTADD_5       (5*0x1000u)    /* ADC12 Conversion Start Address: 5 */
359 
#define ADC12CSTARTADD_6       (6*0x1000u)    /* ADC12 Conversion Start Address: 6 */
360 
#define ADC12CSTARTADD_7       (7*0x1000u)    /* ADC12 Conversion Start Address: 7 */
361 
#define ADC12CSTARTADD_8       (8*0x1000u)    /* ADC12 Conversion Start Address: 8 */
362 
#define ADC12CSTARTADD_9       (9*0x1000u)    /* ADC12 Conversion Start Address: 9 */
363 
#define ADC12CSTARTADD_10      (10*0x1000u)   /* ADC12 Conversion Start Address: 10 */
364 
#define ADC12CSTARTADD_11      (11*0x1000u)   /* ADC12 Conversion Start Address: 11 */
365 
#define ADC12CSTARTADD_12      (12*0x1000u)   /* ADC12 Conversion Start Address: 12 */
366 
#define ADC12CSTARTADD_13      (13*0x1000u)   /* ADC12 Conversion Start Address: 13 */
367 
#define ADC12CSTARTADD_14      (14*0x1000u)   /* ADC12 Conversion Start Address: 14 */
368 
#define ADC12CSTARTADD_15      (15*0x1000u)   /* ADC12 Conversion Start Address: 15 */
369 
 
370 
/* ADC12CTL2 Control Bits */
371 
#define ADC12REFBURST          (0x0001)       /* ADC12+ Reference Burst */
372 
#define ADC12REFOUT            (0x0002)       /* ADC12+ Reference Out */
373 
#define ADC12SR                (0x0004)       /* ADC12+ Sampling Rate */
374 
#define ADC12DF                (0x0008)       /* ADC12+ Data Format */
375 
#define ADC12RES0              (0x0010)       /* ADC12+ Resolution Bit: 0 */
376 
#define ADC12RES1              (0x0020)       /* ADC12+ Resolution Bit: 1 */
377 
#define ADC12TCOFF             (0x0080)       /* ADC12+ Temperature Sensor Off */
378 
#define ADC12PDIV              (0x0100)       /* ADC12+ predivider 0:/1   1:/4 */
379 
 
380 
/* ADC12CTL2 Control Bits */
381 
#define ADC12REFBURST_L        (0x0001)       /* ADC12+ Reference Burst */
382 
#define ADC12REFOUT_L          (0x0002)       /* ADC12+ Reference Out */
383 
#define ADC12SR_L              (0x0004)       /* ADC12+ Sampling Rate */
384 
#define ADC12DF_L              (0x0008)       /* ADC12+ Data Format */
385 
#define ADC12RES0_L            (0x0010)       /* ADC12+ Resolution Bit: 0 */
386 
#define ADC12RES1_L            (0x0020)       /* ADC12+ Resolution Bit: 1 */
387 
#define ADC12TCOFF_L           (0x0080)       /* ADC12+ Temperature Sensor Off */
388 
 
389 
/* ADC12CTL2 Control Bits */
390 
#define ADC12PDIV_H            (0x0001)       /* ADC12+ predivider 0:/1   1:/4 */
391 
 
392 
#define ADC12RES_0             (0x0000)       /* ADC12+ Resolution : 8 Bit */
393 
#define ADC12RES_1             (0x0010)       /* ADC12+ Resolution : 10 Bit */
394 
#define ADC12RES_2             (0x0020)       /* ADC12+ Resolution : 12 Bit */
395 
#define ADC12RES_3             (0x0030)       /* ADC12+ Resolution : reserved */
396 
 
397 
/* ADC12MCTLx Control Bits */
398 
#define ADC12INCH0             (0x0001)       /* ADC12 Input Channel Select Bit 0 */
399 
#define ADC12INCH1             (0x0002)       /* ADC12 Input Channel Select Bit 1 */
400 
#define ADC12INCH2             (0x0004)       /* ADC12 Input Channel Select Bit 2 */
401 
#define ADC12INCH3             (0x0008)       /* ADC12 Input Channel Select Bit 3 */
402 
#define ADC12SREF0             (0x0010)       /* ADC12 Select Reference Bit 0 */
403 
#define ADC12SREF1             (0x0020)       /* ADC12 Select Reference Bit 1 */
404 
#define ADC12SREF2             (0x0040)       /* ADC12 Select Reference Bit 2 */
405 
#define ADC12EOS               (0x0080)       /* ADC12 End of Sequence */
406 
 
407 
#define ADC12INCH_0            (0x0000)       /* ADC12 Input Channel 0 */
408 
#define ADC12INCH_1            (0x0001)       /* ADC12 Input Channel 1 */
409 
#define ADC12INCH_2            (0x0002)       /* ADC12 Input Channel 2 */
410 
#define ADC12INCH_3            (0x0003)       /* ADC12 Input Channel 3 */
411 
#define ADC12INCH_4            (0x0004)       /* ADC12 Input Channel 4 */
412 
#define ADC12INCH_5            (0x0005)       /* ADC12 Input Channel 5 */
413 
#define ADC12INCH_6            (0x0006)       /* ADC12 Input Channel 6 */
414 
#define ADC12INCH_7            (0x0007)       /* ADC12 Input Channel 7 */
415 
#define ADC12INCH_8            (0x0008)       /* ADC12 Input Channel 8 */
416 
#define ADC12INCH_9            (0x0009)       /* ADC12 Input Channel 9 */
417 
#define ADC12INCH_10           (0x000A)       /* ADC12 Input Channel 10 */
418 
#define ADC12INCH_11           (0x000B)       /* ADC12 Input Channel 11 */
419 
#define ADC12INCH_12           (0x000C)       /* ADC12 Input Channel 12 */
420 
#define ADC12INCH_13           (0x000D)       /* ADC12 Input Channel 13 */
421 
#define ADC12INCH_14           (0x000E)       /* ADC12 Input Channel 14 */
422 
#define ADC12INCH_15           (0x000F)       /* ADC12 Input Channel 15 */
423 
 
424 
#define ADC12SREF_0            (0*0x10u)      /* ADC12 Select Reference 0 */
425 
#define ADC12SREF_1            (1*0x10u)      /* ADC12 Select Reference 1 */
426 
#define ADC12SREF_2            (2*0x10u)      /* ADC12 Select Reference 2 */
427 
#define ADC12SREF_3            (3*0x10u)      /* ADC12 Select Reference 3 */
428 
#define ADC12SREF_4            (4*0x10u)      /* ADC12 Select Reference 4 */
429 
#define ADC12SREF_5            (5*0x10u)      /* ADC12 Select Reference 5 */
430 
#define ADC12SREF_6            (6*0x10u)      /* ADC12 Select Reference 6 */
431 
#define ADC12SREF_7            (7*0x10u)      /* ADC12 Select Reference 7 */
432 
 
433 
#define ADC12IE0               (0x0001)       /* ADC12 Memory 0      Interrupt Enable */
434 
#define ADC12IE1               (0x0002)       /* ADC12 Memory 1      Interrupt Enable */
435 
#define ADC12IE2               (0x0004)       /* ADC12 Memory 2      Interrupt Enable */
436 
#define ADC12IE3               (0x0008)       /* ADC12 Memory 3      Interrupt Enable */
437 
#define ADC12IE4               (0x0010)       /* ADC12 Memory 4      Interrupt Enable */
438 
#define ADC12IE5               (0x0020)       /* ADC12 Memory 5      Interrupt Enable */
439 
#define ADC12IE6               (0x0040)       /* ADC12 Memory 6      Interrupt Enable */
440 
#define ADC12IE7               (0x0080)       /* ADC12 Memory 7      Interrupt Enable */
441 
#define ADC12IE8               (0x0100)       /* ADC12 Memory 8      Interrupt Enable */
442 
#define ADC12IE9               (0x0200)       /* ADC12 Memory 9      Interrupt Enable */
443 
#define ADC12IE10              (0x0400)       /* ADC12 Memory 10      Interrupt Enable */
444 
#define ADC12IE11              (0x0800)       /* ADC12 Memory 11      Interrupt Enable */
445 
#define ADC12IE12              (0x1000)       /* ADC12 Memory 12      Interrupt Enable */
446 
#define ADC12IE13              (0x2000)       /* ADC12 Memory 13      Interrupt Enable */
447 
#define ADC12IE14              (0x4000)       /* ADC12 Memory 14      Interrupt Enable */
448 
#define ADC12IE15              (0x8000)       /* ADC12 Memory 15      Interrupt Enable */
449 
 
450 
#define ADC12IE0_L             (0x0001)       /* ADC12 Memory 0      Interrupt Enable */
451 
#define ADC12IE1_L             (0x0002)       /* ADC12 Memory 1      Interrupt Enable */
452 
#define ADC12IE2_L             (0x0004)       /* ADC12 Memory 2      Interrupt Enable */
453 
#define ADC12IE3_L             (0x0008)       /* ADC12 Memory 3      Interrupt Enable */
454 
#define ADC12IE4_L             (0x0010)       /* ADC12 Memory 4      Interrupt Enable */
455 
#define ADC12IE5_L             (0x0020)       /* ADC12 Memory 5      Interrupt Enable */
456 
#define ADC12IE6_L             (0x0040)       /* ADC12 Memory 6      Interrupt Enable */
457 
#define ADC12IE7_L             (0x0080)       /* ADC12 Memory 7      Interrupt Enable */
458 
 
459 
#define ADC12IE8_H             (0x0001)       /* ADC12 Memory 8      Interrupt Enable */
460 
#define ADC12IE9_H             (0x0002)       /* ADC12 Memory 9      Interrupt Enable */
461 
#define ADC12IE10_H            (0x0004)       /* ADC12 Memory 10      Interrupt Enable */
462 
#define ADC12IE11_H            (0x0008)       /* ADC12 Memory 11      Interrupt Enable */
463 
#define ADC12IE12_H            (0x0010)       /* ADC12 Memory 12      Interrupt Enable */
464 
#define ADC12IE13_H            (0x0020)       /* ADC12 Memory 13      Interrupt Enable */
465 
#define ADC12IE14_H            (0x0040)       /* ADC12 Memory 14      Interrupt Enable */
466 
#define ADC12IE15_H            (0x0080)       /* ADC12 Memory 15      Interrupt Enable */
467 
 
468 
#define ADC12IFG0              (0x0001)       /* ADC12 Memory 0      Interrupt Flag */
469 
#define ADC12IFG1              (0x0002)       /* ADC12 Memory 1      Interrupt Flag */
470 
#define ADC12IFG2              (0x0004)       /* ADC12 Memory 2      Interrupt Flag */
471 
#define ADC12IFG3              (0x0008)       /* ADC12 Memory 3      Interrupt Flag */
472 
#define ADC12IFG4              (0x0010)       /* ADC12 Memory 4      Interrupt Flag */
473 
#define ADC12IFG5              (0x0020)       /* ADC12 Memory 5      Interrupt Flag */
474 
#define ADC12IFG6              (0x0040)       /* ADC12 Memory 6      Interrupt Flag */
475 
#define ADC12IFG7              (0x0080)       /* ADC12 Memory 7      Interrupt Flag */
476 
#define ADC12IFG8              (0x0100)       /* ADC12 Memory 8      Interrupt Flag */
477 
#define ADC12IFG9              (0x0200)       /* ADC12 Memory 9      Interrupt Flag */
478 
#define ADC12IFG10             (0x0400)       /* ADC12 Memory 10      Interrupt Flag */
479 
#define ADC12IFG11             (0x0800)       /* ADC12 Memory 11      Interrupt Flag */
480 
#define ADC12IFG12             (0x1000)       /* ADC12 Memory 12      Interrupt Flag */
481 
#define ADC12IFG13             (0x2000)       /* ADC12 Memory 13      Interrupt Flag */
482 
#define ADC12IFG14             (0x4000)       /* ADC12 Memory 14      Interrupt Flag */
483 
#define ADC12IFG15             (0x8000)       /* ADC12 Memory 15      Interrupt Flag */
484 
 
485 
#define ADC12IFG0_L            (0x0001)       /* ADC12 Memory 0      Interrupt Flag */
486 
#define ADC12IFG1_L            (0x0002)       /* ADC12 Memory 1      Interrupt Flag */
487 
#define ADC12IFG2_L            (0x0004)       /* ADC12 Memory 2      Interrupt Flag */
488 
#define ADC12IFG3_L            (0x0008)       /* ADC12 Memory 3      Interrupt Flag */
489 
#define ADC12IFG4_L            (0x0010)       /* ADC12 Memory 4      Interrupt Flag */
490 
#define ADC12IFG5_L            (0x0020)       /* ADC12 Memory 5      Interrupt Flag */
491 
#define ADC12IFG6_L            (0x0040)       /* ADC12 Memory 6      Interrupt Flag */
492 
#define ADC12IFG7_L            (0x0080)       /* ADC12 Memory 7      Interrupt Flag */
493 
 
494 
#define ADC12IFG8_H            (0x0001)       /* ADC12 Memory 8      Interrupt Flag */
495 
#define ADC12IFG9_H            (0x0002)       /* ADC12 Memory 9      Interrupt Flag */
496 
#define ADC12IFG10_H           (0x0004)       /* ADC12 Memory 10      Interrupt Flag */
497 
#define ADC12IFG11_H           (0x0008)       /* ADC12 Memory 11      Interrupt Flag */
498 
#define ADC12IFG12_H           (0x0010)       /* ADC12 Memory 12      Interrupt Flag */
499 
#define ADC12IFG13_H           (0x0020)       /* ADC12 Memory 13      Interrupt Flag */
500 
#define ADC12IFG14_H           (0x0040)       /* ADC12 Memory 14      Interrupt Flag */
501 
#define ADC12IFG15_H           (0x0080)       /* ADC12 Memory 15      Interrupt Flag */
502 
 
503 
/* ADC12IV Definitions */
504 
#define ADC12IV_NONE           (0x0000)       /* No Interrupt pending */
505 
#define ADC12IV_ADC12OVIFG     (0x0002)       /* ADC12OVIFG */
506 
#define ADC12IV_ADC12TOVIFG    (0x0004)       /* ADC12TOVIFG */
507 
#define ADC12IV_ADC12IFG0      (0x0006)       /* ADC12IFG0 */
508 
#define ADC12IV_ADC12IFG1      (0x0008)       /* ADC12IFG1 */
509 
#define ADC12IV_ADC12IFG2      (0x000A)       /* ADC12IFG2 */
510 
#define ADC12IV_ADC12IFG3      (0x000C)       /* ADC12IFG3 */
511 
#define ADC12IV_ADC12IFG4      (0x000E)       /* ADC12IFG4 */
512 
#define ADC12IV_ADC12IFG5      (0x0010)       /* ADC12IFG5 */
513 
#define ADC12IV_ADC12IFG6      (0x0012)       /* ADC12IFG6 */
514 
#define ADC12IV_ADC12IFG7      (0x0014)       /* ADC12IFG7 */
515 
#define ADC12IV_ADC12IFG8      (0x0016)       /* ADC12IFG8 */
516 
#define ADC12IV_ADC12IFG9      (0x0018)       /* ADC12IFG9 */
517 
#define ADC12IV_ADC12IFG10     (0x001A)       /* ADC12IFG10 */
518 
#define ADC12IV_ADC12IFG11     (0x001C)       /* ADC12IFG11 */
519 
#define ADC12IV_ADC12IFG12     (0x001E)       /* ADC12IFG12 */
520 
#define ADC12IV_ADC12IFG13     (0x0020)       /* ADC12IFG13 */
521 
#define ADC12IV_ADC12IFG14     (0x0022)       /* ADC12IFG14 */
522 
#define ADC12IV_ADC12IFG15     (0x0024)       /* ADC12IFG15 */
523 
 
524 
/*************************************************************
525 
* CRC Module
526 
*************************************************************/
527 
#define __MSP430_HAS_CRC__                    /* Definition to show that Module is available */
528 
#define __MSP430_BASEADDRESS_CRC__ 0x0150
529 
 
530 
SFR_16BIT(CRCDI);                             /* CRC Data In Register */
531 
SFR_8BIT(CRCDI_L);                            /* CRC Data In Register */
532 
SFR_8BIT(CRCDI_H);                            /* CRC Data In Register */
533 
SFR_16BIT(CRCDIRB);                           /* CRC data in reverse byte Register */
534 
SFR_8BIT(CRCDIRB_L);                          /* CRC data in reverse byte Register */
535 
SFR_8BIT(CRCDIRB_H);                          /* CRC data in reverse byte Register */
536 
SFR_16BIT(CRCINIRES);                         /* CRC Initialisation Register and Result Register */
537 
SFR_8BIT(CRCINIRES_L);                        /* CRC Initialisation Register and Result Register */
538 
SFR_8BIT(CRCINIRES_H);                        /* CRC Initialisation Register and Result Register */
539 
SFR_16BIT(CRCRESR);                           /* CRC reverse result Register */
540 
SFR_8BIT(CRCRESR_L);                          /* CRC reverse result Register */
541 
SFR_8BIT(CRCRESR_H);                          /* CRC reverse result Register */
542 
 
543 
/************************************************************
544 
* DMA_X
545 
************************************************************/
546 
#define __MSP430_HAS_DMAX_3__                 /* Definition to show that Module is available */
547 
#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500
548 
 
549 
SFR_16BIT(DMACTL0);                           /* DMA Module Control 0 */
550 
SFR_8BIT(DMACTL0_L);                          /* DMA Module Control 0 */
551 
SFR_8BIT(DMACTL0_H);                          /* DMA Module Control 0 */
552 
SFR_16BIT(DMACTL1);                           /* DMA Module Control 1 */
553 
SFR_8BIT(DMACTL1_L);                          /* DMA Module Control 1 */
554 
SFR_8BIT(DMACTL1_H);                          /* DMA Module Control 1 */
555 
SFR_16BIT(DMACTL2);                           /* DMA Module Control 2 */
556 
SFR_8BIT(DMACTL2_L);                          /* DMA Module Control 2 */
557 
SFR_8BIT(DMACTL2_H);                          /* DMA Module Control 2 */
558 
SFR_16BIT(DMACTL3);                           /* DMA Module Control 3 */
559 
SFR_8BIT(DMACTL3_L);                          /* DMA Module Control 3 */
560 
SFR_8BIT(DMACTL3_H);                          /* DMA Module Control 3 */
561 
SFR_16BIT(DMACTL4);                           /* DMA Module Control 4 */
562 
SFR_8BIT(DMACTL4_L);                          /* DMA Module Control 4 */
563 
SFR_8BIT(DMACTL4_H);                          /* DMA Module Control 4 */
564 
SFR_16BIT(DMAIV);                             /* DMA Interrupt Vector Word */
565 
SFR_8BIT(DMAIV_L);                            /* DMA Interrupt Vector Word */
566 
SFR_8BIT(DMAIV_H);                            /* DMA Interrupt Vector Word */
567 
 
568 
SFR_16BIT(DMA0CTL);                           /* DMA Channel 0 Control */
569 
SFR_8BIT(DMA0CTL_L);                          /* DMA Channel 0 Control */
570 
SFR_8BIT(DMA0CTL_H);                          /* DMA Channel 0 Control */
571 
SFR_20BIT(DMA0SA);                            /* DMA Channel 0 Source Address */
572 
SFR_16BIT(DMA0SAL);                           /* DMA Channel 0 Source Address */
573 
SFR_20BIT(DMA0DA);                            /* DMA Channel 0 Destination Address */
574 
SFR_16BIT(DMA0DAL);                           /* DMA Channel 0 Destination Address */
575 
SFR_16BIT(DMA0SZ);                            /* DMA Channel 0 Transfer Size */
576 
 
577 
SFR_16BIT(DMA1CTL);                           /* DMA Channel 1 Control */
578 
SFR_8BIT(DMA1CTL_L);                          /* DMA Channel 1 Control */
579 
SFR_8BIT(DMA1CTL_H);                          /* DMA Channel 1 Control */
580 
SFR_20BIT(DMA1SA);                            /* DMA Channel 1 Source Address */
581 
SFR_16BIT(DMA1SAL);                           /* DMA Channel 1 Source Address */
582 
SFR_20BIT(DMA1DA);                            /* DMA Channel 1 Destination Address */
583 
SFR_16BIT(DMA1DAL);                           /* DMA Channel 1 Destination Address */
584 
SFR_16BIT(DMA1SZ);                            /* DMA Channel 1 Transfer Size */
585 
 
586 
SFR_16BIT(DMA2CTL);                           /* DMA Channel 2 Control */
587 
SFR_8BIT(DMA2CTL_L);                          /* DMA Channel 2 Control */
588 
SFR_8BIT(DMA2CTL_H);                          /* DMA Channel 2 Control */
589 
SFR_20BIT(DMA2SA);                            /* DMA Channel 2 Source Address */
590 
SFR_16BIT(DMA2SAL);                           /* DMA Channel 2 Source Address */
591 
SFR_20BIT(DMA2DA);                            /* DMA Channel 2 Destination Address */
592 
SFR_16BIT(DMA2DAL);                           /* DMA Channel 2 Destination Address */
593 
SFR_16BIT(DMA2SZ);                            /* DMA Channel 2 Transfer Size */
594 
 
595 
/* DMACTL0 Control Bits */
596 
#define DMA0TSEL0              (0x0001)       /* DMA channel 0 transfer select bit 0 */
597 
#define DMA0TSEL1              (0x0002)       /* DMA channel 0 transfer select bit 1 */
598 
#define DMA0TSEL2              (0x0004)       /* DMA channel 0 transfer select bit 2 */
599 
#define DMA0TSEL3              (0x0008)       /* DMA channel 0 transfer select bit 3 */
600 
#define DMA0TSEL4              (0x0010)       /* DMA channel 0 transfer select bit 4 */
601 
#define DMA1TSEL0              (0x0100)       /* DMA channel 1 transfer select bit 0 */
602 
#define DMA1TSEL1              (0x0200)       /* DMA channel 1 transfer select bit 1 */
603 
#define DMA1TSEL2              (0x0400)       /* DMA channel 1 transfer select bit 2 */
604 
#define DMA1TSEL3              (0x0800)       /* DMA channel 1 transfer select bit 3 */
605 
#define DMA1TSEL4              (0x1000)       /* DMA channel 1 transfer select bit 4 */
606 
 
607 
/* DMACTL0 Control Bits */
608 
#define DMA0TSEL0_L            (0x0001)       /* DMA channel 0 transfer select bit 0 */
609 
#define DMA0TSEL1_L            (0x0002)       /* DMA channel 0 transfer select bit 1 */
610 
#define DMA0TSEL2_L            (0x0004)       /* DMA channel 0 transfer select bit 2 */
611 
#define DMA0TSEL3_L            (0x0008)       /* DMA channel 0 transfer select bit 3 */
612 
#define DMA0TSEL4_L            (0x0010)       /* DMA channel 0 transfer select bit 4 */
613 
 
614 
/* DMACTL0 Control Bits */
615 
#define DMA1TSEL0_H            (0x0001)       /* DMA channel 1 transfer select bit 0 */
616 
#define DMA1TSEL1_H            (0x0002)       /* DMA channel 1 transfer select bit 1 */
617 
#define DMA1TSEL2_H            (0x0004)       /* DMA channel 1 transfer select bit 2 */
618 
#define DMA1TSEL3_H            (0x0008)       /* DMA channel 1 transfer select bit 3 */
619 
#define DMA1TSEL4_H            (0x0010)       /* DMA channel 1 transfer select bit 4 */
620 
 
621 
/* DMACTL01 Control Bits */
622 
#define DMA2TSEL0              (0x0001)       /* DMA channel 2 transfer select bit 0 */
623 
#define DMA2TSEL1              (0x0002)       /* DMA channel 2 transfer select bit 1 */
624 
#define DMA2TSEL2              (0x0004)       /* DMA channel 2 transfer select bit 2 */
625 
#define DMA2TSEL3              (0x0008)       /* DMA channel 2 transfer select bit 3 */
626 
#define DMA2TSEL4              (0x0010)       /* DMA channel 2 transfer select bit 4 */
627 
 
628 
/* DMACTL01 Control Bits */
629 
#define DMA2TSEL0_L            (0x0001)       /* DMA channel 2 transfer select bit 0 */
630 
#define DMA2TSEL1_L            (0x0002)       /* DMA channel 2 transfer select bit 1 */
631 
#define DMA2TSEL2_L            (0x0004)       /* DMA channel 2 transfer select bit 2 */
632 
#define DMA2TSEL3_L            (0x0008)       /* DMA channel 2 transfer select bit 3 */
633 
#define DMA2TSEL4_L            (0x0010)       /* DMA channel 2 transfer select bit 4 */
634 
 
635 
/* DMACTL01 Control Bits */
636 
 
637 
/* DMACTL4 Control Bits */
638 
#define ENNMI                  (0x0001)       /* Enable NMI interruption of DMA */
639 
#define ROUNDROBIN             (0x0002)       /* Round-Robin DMA channel priorities */
640 
#define DMARMWDIS              (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
641 
 
642 
/* DMACTL4 Control Bits */
643 
#define ENNMI_L                (0x0001)       /* Enable NMI interruption of DMA */
644 
#define ROUNDROBIN_L           (0x0002)       /* Round-Robin DMA channel priorities */
645 
#define DMARMWDIS_L            (0x0004)       /* Inhibited DMA transfers during read-modify-write CPU operations */
646 
 
647 
/* DMACTL4 Control Bits */
648 
 
649 
/* DMAxCTL Control Bits */
650 
#define DMAREQ                 (0x0001)       /* Initiate DMA transfer with DMATSEL */
651 
#define DMAABORT               (0x0002)       /* DMA transfer aborted by NMI */
652 
#define DMAIE                  (0x0004)       /* DMA interrupt enable */
653 
#define DMAIFG                 (0x0008)       /* DMA interrupt flag */
654 
#define DMAEN                  (0x0010)       /* DMA enable */
655 
#define DMALEVEL               (0x0020)       /* DMA level sensitive trigger select */
656 
#define DMASRCBYTE             (0x0040)       /* DMA source byte */
657 
#define DMADSTBYTE             (0x0080)       /* DMA destination byte */
658 
#define DMASRCINCR0            (0x0100)       /* DMA source increment bit 0 */
659 
#define DMASRCINCR1            (0x0200)       /* DMA source increment bit 1 */
660 
#define DMADSTINCR0            (0x0400)       /* DMA destination increment bit 0 */
661 
#define DMADSTINCR1            (0x0800)       /* DMA destination increment bit 1 */
662 
#define DMADT0                 (0x1000)       /* DMA transfer mode bit 0 */
663 
#define DMADT1                 (0x2000)       /* DMA transfer mode bit 1 */
664 
#define DMADT2                 (0x4000)       /* DMA transfer mode bit 2 */
665 
 
666 
/* DMAxCTL Control Bits */
667 
#define DMAREQ_L               (0x0001)       /* Initiate DMA transfer with DMATSEL */
668 
#define DMAABORT_L             (0x0002)       /* DMA transfer aborted by NMI */
669 
#define DMAIE_L                (0x0004)       /* DMA interrupt enable */
670 
#define DMAIFG_L               (0x0008)       /* DMA interrupt flag */
671 
#define DMAEN_L                (0x0010)       /* DMA enable */
672 
#define DMALEVEL_L             (0x0020)       /* DMA level sensitive trigger select */
673 
#define DMASRCBYTE_L           (0x0040)       /* DMA source byte */
674 
#define DMADSTBYTE_L           (0x0080)       /* DMA destination byte */
675 
 
676 
/* DMAxCTL Control Bits */
677 
#define DMASRCINCR0_H          (0x0001)       /* DMA source increment bit 0 */
678 
#define DMASRCINCR1_H          (0x0002)       /* DMA source increment bit 1 */
679 
#define DMADSTINCR0_H          (0x0004)       /* DMA destination increment bit 0 */
680 
#define DMADSTINCR1_H          (0x0008)       /* DMA destination increment bit 1 */
681 
#define DMADT0_H               (0x0010)       /* DMA transfer mode bit 0 */
682 
#define DMADT1_H               (0x0020)       /* DMA transfer mode bit 1 */
683 
#define DMADT2_H               (0x0040)       /* DMA transfer mode bit 2 */
684 
 
685 
#define DMASWDW                (0*0x0040u)    /* DMA transfer: source word to destination word */
686 
#define DMASBDW                (1*0x0040u)    /* DMA transfer: source byte to destination word */
687 
#define DMASWDB                (2*0x0040u)    /* DMA transfer: source word to destination byte */
688 
#define DMASBDB                (3*0x0040u)    /* DMA transfer: source byte to destination byte */
689 
 
690 
#define DMASRCINCR_0           (0*0x0100u)    /* DMA source increment 0: source address unchanged */
691 
#define DMASRCINCR_1           (1*0x0100u)    /* DMA source increment 1: source address unchanged */
692 
#define DMASRCINCR_2           (2*0x0100u)    /* DMA source increment 2: source address decremented */
693 
#define DMASRCINCR_3           (3*0x0100u)    /* DMA source increment 3: source address incremented */
694 
 
695 
#define DMADSTINCR_0           (0*0x0400u)    /* DMA destination increment 0: destination address unchanged */
696 
#define DMADSTINCR_1           (1*0x0400u)    /* DMA destination increment 1: destination address unchanged */
697 
#define DMADSTINCR_2           (2*0x0400u)    /* DMA destination increment 2: destination address decremented */
698 
#define DMADSTINCR_3           (3*0x0400u)    /* DMA destination increment 3: destination address incremented */
699 
 
700 
#define DMADT_0                (0*0x1000u)    /* DMA transfer mode 0: Single transfer */
701 
#define DMADT_1                (1*0x1000u)    /* DMA transfer mode 1: Block transfer */
702 
#define DMADT_2                (2*0x1000u)    /* DMA transfer mode 2: Burst-Block transfer */
703 
#define DMADT_3                (3*0x1000u)    /* DMA transfer mode 3: Burst-Block transfer */
704 
#define DMADT_4                (4*0x1000u)    /* DMA transfer mode 4: Repeated Single transfer */
705 
#define DMADT_5                (5*0x1000u)    /* DMA transfer mode 5: Repeated Block transfer */
706 
#define DMADT_6                (6*0x1000u)    /* DMA transfer mode 6: Repeated Burst-Block transfer */
707 
#define DMADT_7                (7*0x1000u)    /* DMA transfer mode 7: Repeated Burst-Block transfer */
708 
 
709 
/* DMAIV Definitions */
710 
#define DMAIV_NONE             (0x0000)       /* No Interrupt pending */
711 
#define DMAIV_DMA0IFG          (0x0002)       /* DMA0IFG*/
712 
#define DMAIV_DMA1IFG          (0x0004)       /* DMA1IFG*/
713 
#define DMAIV_DMA2IFG          (0x0006)       /* DMA2IFG*/
714 
 
715 
#define DMA0TSEL_0             (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
716 
#define DMA0TSEL_1             (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
717 
#define DMA0TSEL_2             (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
718 
#define DMA0TSEL_3             (3*0x0001u)    /* DMA channel 0 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
719 
#define DMA0TSEL_4             (4*0x0001u)    /* DMA channel 0 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
720 
#define DMA0TSEL_5             (5*0x0001u)    /* DMA channel 0 transfer select 5:  TimerB (TB0CCR0.IFG) */
721 
#define DMA0TSEL_6             (6*0x0001u)    /* DMA channel 0 transfer select 6:  TimerB (TB0CCR2.IFG) */
722 
#define DMA0TSEL_7             (7*0x0001u)    /* DMA channel 0 transfer select 7:  Reserved */
723 
#define DMA0TSEL_8             (8*0x0001u)    /* DMA channel 0 transfer select 8:  Reserved */
724 
#define DMA0TSEL_9             (9*0x0001u)    /* DMA channel 0 transfer select 9:  Reserved */
725 
#define DMA0TSEL_10            (10*0x0001u)   /* DMA channel 0 transfer select 10: Reserved */
726 
#define DMA0TSEL_11            (11*0x0001u)   /* DMA channel 0 transfer select 11: Reserved */
727 
#define DMA0TSEL_12            (12*0x0001u)   /* DMA channel 0 transfer select 12: Reserved */
728 
#define DMA0TSEL_13            (13*0x0001u)   /* DMA channel 0 transfer select 13: Reserved */
729 
#define DMA0TSEL_14            (14*0x0001u)   /* DMA channel 0 transfer select 14: Reserved */
730 
#define DMA0TSEL_15            (15*0x0001u)   /* DMA channel 0 transfer select 15: Reserved */
731 
#define DMA0TSEL_16            (16*0x0001u)   /* DMA channel 0 transfer select 16: USCIA0 receive */
732 
#define DMA0TSEL_17            (17*0x0001u)   /* DMA channel 0 transfer select 17: USCIA0 transmit */
733 
#define DMA0TSEL_18            (18*0x0001u)   /* DMA channel 0 transfer select 18: USCIB0 receive */
734 
#define DMA0TSEL_19            (19*0x0001u)   /* DMA channel 0 transfer select 19: USCIB0 transmit */
735 
#define DMA0TSEL_20            (20*0x0001u)   /* DMA channel 0 transfer select 20: USCIA1 receive */
736 
#define DMA0TSEL_21            (21*0x0001u)   /* DMA channel 0 transfer select 21: USCIA1 transmit */
737 
#define DMA0TSEL_22            (22*0x0001u)   /* DMA channel 0 transfer select 22: USCIB1 receive */
738 
#define DMA0TSEL_23            (23*0x0001u)   /* DMA channel 0 transfer select 23: USCIB1 transmit */
739 
#define DMA0TSEL_24            (24*0x0001u)   /* DMA channel 0 transfer select 24: ADC12IFGx */
740 
#define DMA0TSEL_25            (25*0x0001u)   /* DMA channel 0 transfer select 25: Reserved */
741 
#define DMA0TSEL_26            (26*0x0001u)   /* DMA channel 0 transfer select 26: Reserved */
742 
#define DMA0TSEL_27            (27*0x0001u)   /* DMA channel 0 transfer select 27: Reserved */
743 
#define DMA0TSEL_28            (28*0x0001u)   /* DMA channel 0 transfer select 28: Reserved */
744 
#define DMA0TSEL_29            (29*0x0001u)   /* DMA channel 0 transfer select 29: Multiplier ready */
745 
#define DMA0TSEL_30            (30*0x0001u)   /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
746 
#define DMA0TSEL_31            (31*0x0001u)   /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
747 
 
748 
#define DMA1TSEL_0             (0*0x0100u)    /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
749 
#define DMA1TSEL_1             (1*0x0100u)    /* DMA channel 1 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
750 
#define DMA1TSEL_2             (2*0x0100u)    /* DMA channel 1 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
751 
#define DMA1TSEL_3             (3*0x0100u)    /* DMA channel 1 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
752 
#define DMA1TSEL_4             (4*0x0100u)    /* DMA channel 1 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
753 
#define DMA1TSEL_5             (5*0x0100u)    /* DMA channel 1 transfer select 5:  TimerB (TB0CCR0.IFG) */
754 
#define DMA1TSEL_6             (6*0x0100u)    /* DMA channel 1 transfer select 6:  TimerB (TB0CCR2.IFG) */
755 
#define DMA1TSEL_7             (7*0x0100u)    /* DMA channel 1 transfer select 7:  Reserved */
756 
#define DMA1TSEL_8             (8*0x0100u)    /* DMA channel 1 transfer select 8:  Reserved */
757 
#define DMA1TSEL_9             (9*0x0100u)    /* DMA channel 1 transfer select 9:  Reserved */
758 
#define DMA1TSEL_10            (10*0x0100u)   /* DMA channel 1 transfer select 10: Reserved */
759 
#define DMA1TSEL_11            (11*0x0100u)   /* DMA channel 1 transfer select 11: Reserved */
760 
#define DMA1TSEL_12            (12*0x0100u)   /* DMA channel 1 transfer select 12: Reserved */
761 
#define DMA1TSEL_13            (13*0x0100u)   /* DMA channel 1 transfer select 13: Reserved */
762 
#define DMA1TSEL_14            (14*0x0100u)   /* DMA channel 1 transfer select 14: Reserved */
763 
#define DMA1TSEL_15            (15*0x0100u)   /* DMA channel 1 transfer select 15: Reserved */
764 
#define DMA1TSEL_16            (16*0x0100u)   /* DMA channel 1 transfer select 16: USCIA0 receive */
765 
#define DMA1TSEL_17            (17*0x0100u)   /* DMA channel 1 transfer select 17: USCIA0 transmit */
766 
#define DMA1TSEL_18            (18*0x0100u)   /* DMA channel 1 transfer select 18: USCIB0 receive */
767 
#define DMA1TSEL_19            (19*0x0100u)   /* DMA channel 1 transfer select 19: USCIB0 transmit */
768 
#define DMA1TSEL_20            (20*0x0100u)   /* DMA channel 1 transfer select 20: USCIA1 receive */
769 
#define DMA1TSEL_21            (21*0x0100u)   /* DMA channel 1 transfer select 21: USCIA1 transmit */
770 
#define DMA1TSEL_22            (22*0x0100u)   /* DMA channel 1 transfer select 22: USCIB1 receive */
771 
#define DMA1TSEL_23            (23*0x0100u)   /* DMA channel 1 transfer select 23: USCIB1 transmit */
772 
#define DMA1TSEL_24            (24*0x0100u)   /* DMA channel 1 transfer select 24: ADC12IFGx */
773 
#define DMA1TSEL_25            (25*0x0100u)   /* DMA channel 1 transfer select 25: Reserved */
774 
#define DMA1TSEL_26            (26*0x0100u)   /* DMA channel 1 transfer select 26: Reserved */
775 
#define DMA1TSEL_27            (27*0x0100u)   /* DMA channel 1 transfer select 27: Reserved */
776 
#define DMA1TSEL_28            (28*0x0100u)   /* DMA channel 1 transfer select 28: Reserved */
777 
#define DMA1TSEL_29            (29*0x0100u)   /* DMA channel 1 transfer select 29: Multiplier ready */
778 
#define DMA1TSEL_30            (30*0x0100u)   /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
779 
#define DMA1TSEL_31            (31*0x0100u)   /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
780 
 
781 
#define DMA2TSEL_0             (0*0x0001u)    /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
782 
#define DMA2TSEL_1             (1*0x0001u)    /* DMA channel 2 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
783 
#define DMA2TSEL_2             (2*0x0001u)    /* DMA channel 2 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
784 
#define DMA2TSEL_3             (3*0x0001u)    /* DMA channel 2 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
785 
#define DMA2TSEL_4             (4*0x0001u)    /* DMA channel 2 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
786 
#define DMA2TSEL_5             (5*0x0001u)    /* DMA channel 2 transfer select 5:  TimerB (TB0CCR0.IFG) */
787 
#define DMA2TSEL_6             (6*0x0001u)    /* DMA channel 2 transfer select 6:  TimerB (TB0CCR2.IFG) */
788 
#define DMA2TSEL_7             (7*0x0001u)    /* DMA channel 2 transfer select 7:  Reserved */
789 
#define DMA2TSEL_8             (8*0x0001u)    /* DMA channel 2 transfer select 8:  Reserved */
790 
#define DMA2TSEL_9             (9*0x0001u)    /* DMA channel 2 transfer select 9:  Reserved */
791 
#define DMA2TSEL_10            (10*0x0001u)   /* DMA channel 2 transfer select 10: Reserved */
792 
#define DMA2TSEL_11            (11*0x0001u)   /* DMA channel 2 transfer select 11: Reserved */
793 
#define DMA2TSEL_12            (12*0x0001u)   /* DMA channel 2 transfer select 12: Reserved */
794 
#define DMA2TSEL_13            (13*0x0001u)   /* DMA channel 2 transfer select 13: Reserved */
795 
#define DMA2TSEL_14            (14*0x0001u)   /* DMA channel 2 transfer select 14: Reserved */
796 
#define DMA2TSEL_15            (15*0x0001u)   /* DMA channel 2 transfer select 15: Reserved */
797 
#define DMA2TSEL_16            (16*0x0001u)   /* DMA channel 2 transfer select 16: USCIA0 receive */
798 
#define DMA2TSEL_17            (17*0x0001u)   /* DMA channel 2 transfer select 17: USCIA0 transmit */
799 
#define DMA2TSEL_18            (18*0x0001u)   /* DMA channel 2 transfer select 18: USCIB0 receive */
800 
#define DMA2TSEL_19            (19*0x0001u)   /* DMA channel 2 transfer select 19: USCIB0 transmit */
801 
#define DMA2TSEL_20            (20*0x0001u)   /* DMA channel 2 transfer select 20: USCIA1 receive */
802 
#define DMA2TSEL_21            (21*0x0001u)   /* DMA channel 2 transfer select 21: USCIA1 transmit */
803 
#define DMA2TSEL_22            (22*0x0001u)   /* DMA channel 2 transfer select 22: USCIB1 receive */
804 
#define DMA2TSEL_23            (23*0x0001u)   /* DMA channel 2 transfer select 23: USCIB1 transmit */
805 
#define DMA2TSEL_24            (24*0x0001u)   /* DMA channel 2 transfer select 24: ADC12IFGx */
806 
#define DMA2TSEL_25            (25*0x0001u)   /* DMA channel 2 transfer select 25: Reserved */
807 
#define DMA2TSEL_26            (26*0x0001u)   /* DMA channel 2 transfer select 26: Reserved */
808 
#define DMA2TSEL_27            (27*0x0001u)   /* DMA channel 2 transfer select 27: Reserved */
809 
#define DMA2TSEL_28            (28*0x0001u)   /* DMA channel 2 transfer select 28: Reserved */
810 
#define DMA2TSEL_29            (29*0x0001u)   /* DMA channel 2 transfer select 29: Multiplier ready */
811 
#define DMA2TSEL_30            (30*0x0001u)   /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
812 
#define DMA2TSEL_31            (31*0x0001u)   /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
813 
 
814 
#define DMA0TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 0 transfer select 0:  DMA_REQ (sw) */
815 
#define DMA0TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 0 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
816 
#define DMA0TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 0 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
817 
#define DMA0TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 0 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
818 
#define DMA0TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 0 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
819 
#define DMA0TSEL__TB0CCR0      (5*0x0001u)    /* DMA channel 0 transfer select 5:  TimerB (TB0CCR0.IFG) */
820 
#define DMA0TSEL__TB0CCR2      (6*0x0001u)    /* DMA channel 0 transfer select 6:  TimerB (TB0CCR2.IFG) */
821 
#define DMA0TSEL__RES7         (7*0x0001u)    /* DMA channel 0 transfer select 7:  Reserved */
822 
#define DMA0TSEL__RES8         (8*0x0001u)    /* DMA channel 0 transfer select 8:  Reserved */
823 
#define DMA0TSEL__RES9         (9*0x0001u)    /* DMA channel 0 transfer select 9:  Reserved */
824 
#define DMA0TSEL__RES10        (10*0x0001u)   /* DMA channel 0 transfer select 10: Reserved */
825 
#define DMA0TSEL__RES11        (11*0x0001u)   /* DMA channel 0 transfer select 11: Reserved */
826 
#define DMA0TSEL__RES12        (12*0x0001u)   /* DMA channel 0 transfer select 12: Reserved */
827 
#define DMA0TSEL__RES13        (13*0x0001u)   /* DMA channel 0 transfer select 13: Reserved */
828 
#define DMA0TSEL__RES14        (14*0x0001u)   /* DMA channel 0 transfer select 14: Reserved */
829 
#define DMA0TSEL__RES15        (15*0x0001u)   /* DMA channel 0 transfer select 15: Reserved */
830 
#define DMA0TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 0 transfer select 16: USCIA0 receive */
831 
#define DMA0TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 0 transfer select 17: USCIA0 transmit */
832 
#define DMA0TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 0 transfer select 18: USCIB0 receive */
833 
#define DMA0TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 0 transfer select 19: USCIB0 transmit */
834 
#define DMA0TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 0 transfer select 20: USCIA1 receive */
835 
#define DMA0TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 0 transfer select 21: USCIA1 transmit */
836 
#define DMA0TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 0 transfer select 22: USCIB1 receive */
837 
#define DMA0TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 0 transfer select 23: USCIB1 transmit */
838 
#define DMA0TSEL__ADC12IFG     (24*0x0001u)   /* DMA channel 0 transfer select 24: ADC12IFGx */
839 
#define DMA0TSEL__RES25        (25*0x0001u)   /* DMA channel 0 transfer select 25: Reserved */
840 
#define DMA0TSEL__RES26        (26*0x0001u)   /* DMA channel 0 transfer select 26: Reserved */
841 
#define DMA0TSEL__RES27        (27*0x0001u)   /* DMA channel 0 transfer select 27: Reserved */
842 
#define DMA0TSEL__RES28        (28*0x0001u)   /* DMA channel 0 transfer select 28: Reserved */
843 
#define DMA0TSEL__MPY          (29*0x0001u)   /* DMA channel 0 transfer select 29: Multiplier ready */
844 
#define DMA0TSEL__DMA2IFG      (30*0x0001u)   /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
845 
#define DMA0TSEL__DMAE0        (31*0x0001u)   /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
846 
 
847 
#define DMA1TSEL__DMA_REQ      (0*0x0100u)    /* DMA channel 1 transfer select 0:  DMA_REQ (sw) */
848 
#define DMA1TSEL__TA0CCR0      (1*0x0100u)    /* DMA channel 1 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
849 
#define DMA1TSEL__TA0CCR2      (2*0x0100u)    /* DMA channel 1 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
850 
#define DMA1TSEL__TA1CCR0      (3*0x0100u)    /* DMA channel 1 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
851 
#define DMA1TSEL__TA1CCR2      (4*0x0100u)    /* DMA channel 1 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
852 
#define DMA1TSEL__TB0CCR0      (5*0x0100u)    /* DMA channel 1 transfer select 5:  TimerB (TB0CCR0.IFG) */
853 
#define DMA1TSEL__TB0CCR2      (6*0x0100u)    /* DMA channel 1 transfer select 6:  TimerB (TB0CCR2.IFG) */
854 
#define DMA1TSEL__RES7         (7*0x0100u)    /* DMA channel 1 transfer select 7:  Reserved */
855 
#define DMA1TSEL__RES8         (8*0x0100u)    /* DMA channel 1 transfer select 8:  Reserved */
856 
#define DMA1TSEL__RES9         (9*0x0100u)    /* DMA channel 1 transfer select 9:  Reserved */
857 
#define DMA1TSEL__RES10        (10*0x0100u)   /* DMA channel 1 transfer select 10: Reserved */
858 
#define DMA1TSEL__RES11        (11*0x0100u)   /* DMA channel 1 transfer select 11: Reserved */
859 
#define DMA1TSEL__RES12        (12*0x0100u)   /* DMA channel 1 transfer select 12: Reserved */
860 
#define DMA1TSEL__RES13        (13*0x0100u)   /* DMA channel 1 transfer select 13: Reserved */
861 
#define DMA1TSEL__RES14        (14*0x0100u)   /* DMA channel 1 transfer select 14: Reserved */
862 
#define DMA1TSEL__RES15        (15*0x0100u)   /* DMA channel 1 transfer select 15: Reserved */
863 
#define DMA1TSEL__USCIA0RX     (16*0x0100u)   /* DMA channel 1 transfer select 16: USCIA0 receive */
864 
#define DMA1TSEL__USCIA0TX     (17*0x0100u)   /* DMA channel 1 transfer select 17: USCIA0 transmit */
865 
#define DMA1TSEL__USCIB0RX     (18*0x0100u)   /* DMA channel 1 transfer select 18: USCIB0 receive */
866 
#define DMA1TSEL__USCIB0TX     (19*0x0100u)   /* DMA channel 1 transfer select 19: USCIB0 transmit */
867 
#define DMA1TSEL__USCIA1RX     (20*0x0100u)   /* DMA channel 1 transfer select 20: USCIA1 receive */
868 
#define DMA1TSEL__USCIA1TX     (21*0x0100u)   /* DMA channel 1 transfer select 21: USCIA1 transmit */
869 
#define DMA1TSEL__USCIB1RX     (22*0x0100u)   /* DMA channel 1 transfer select 22: USCIB1 receive */
870 
#define DMA1TSEL__USCIB1TX     (23*0x0100u)   /* DMA channel 1 transfer select 23: USCIB1 transmit */
871 
#define DMA1TSEL__ADC12IFG     (24*0x0100u)   /* DMA channel 1 transfer select 24: ADC12IFGx */
872 
#define DMA1TSEL__RES25        (25*0x0100u)   /* DMA channel 1 transfer select 25: Reserved */
873 
#define DMA1TSEL__RES26        (26*0x0100u)   /* DMA channel 1 transfer select 26: Reserved */
874 
#define DMA1TSEL__RES27        (27*0x0100u)   /* DMA channel 1 transfer select 27: Reserved */
875 
#define DMA1TSEL__RES28        (28*0x0100u)   /* DMA channel 1 transfer select 28: Reserved */
876 
#define DMA1TSEL__MPY          (29*0x0100u)   /* DMA channel 1 transfer select 29: Multiplier ready */
877 
#define DMA1TSEL__DMA0IFG      (30*0x0100u)   /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
878 
#define DMA1TSEL__DMAE0        (31*0x0100u)   /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
879 
 
880 
#define DMA2TSEL__DMA_REQ      (0*0x0001u)    /* DMA channel 2 transfer select 0:  DMA_REQ (sw) */
881 
#define DMA2TSEL__TA0CCR0      (1*0x0001u)    /* DMA channel 2 transfer select 1:  Timer0_A (TA0CCR0.IFG) */
882 
#define DMA2TSEL__TA0CCR2      (2*0x0001u)    /* DMA channel 2 transfer select 2:  Timer0_A (TA0CCR2.IFG) */
883 
#define DMA2TSEL__TA1CCR0      (3*0x0001u)    /* DMA channel 2 transfer select 3:  Timer1_A (TA1CCR0.IFG) */
884 
#define DMA2TSEL__TA1CCR2      (4*0x0001u)    /* DMA channel 2 transfer select 4:  Timer1_A (TA1CCR2.IFG) */
885 
#define DMA2TSEL__TB0CCR0      (5*0x0001u)    /* DMA channel 2 transfer select 5:  TimerB (TB0CCR0.IFG) */
886 
#define DMA2TSEL__TB0CCR2      (6*0x0001u)    /* DMA channel 2 transfer select 6:  TimerB (TB0CCR2.IFG) */
887 
#define DMA2TSEL__RES7         (7*0x0001u)    /* DMA channel 2 transfer select 7:  Reserved */
888 
#define DMA2TSEL__RES8         (8*0x0001u)    /* DMA channel 2 transfer select 8:  Reserved */
889 
#define DMA2TSEL__RES9         (9*0x0001u)    /* DMA channel 2 transfer select 9:  Reserved */
890 
#define DMA2TSEL__RES10        (10*0x0001u)   /* DMA channel 2 transfer select 10: Reserved */
891 
#define DMA2TSEL__RES11        (11*0x0001u)   /* DMA channel 2 transfer select 11: Reserved */
892 
#define DMA2TSEL__RES12        (12*0x0001u)   /* DMA channel 2 transfer select 12: Reserved */
893 
#define DMA2TSEL__RES13        (13*0x0001u)   /* DMA channel 2 transfer select 13: Reserved */
894 
#define DMA2TSEL__RES14        (14*0x0001u)   /* DMA channel 2 transfer select 14: Reserved */
895 
#define DMA2TSEL__RES15        (15*0x0001u)   /* DMA channel 2 transfer select 15: Reserved */
896 
#define DMA2TSEL__USCIA0RX     (16*0x0001u)   /* DMA channel 2 transfer select 16: USCIA0 receive */
897 
#define DMA2TSEL__USCIA0TX     (17*0x0001u)   /* DMA channel 2 transfer select 17: USCIA0 transmit */
898 
#define DMA2TSEL__USCIB0RX     (18*0x0001u)   /* DMA channel 2 transfer select 18: USCIB0 receive */
899 
#define DMA2TSEL__USCIB0TX     (19*0x0001u)   /* DMA channel 2 transfer select 19: USCIB0 transmit */
900 
#define DMA2TSEL__USCIA1RX     (20*0x0001u)   /* DMA channel 2 transfer select 20: USCIA1 receive */
901 
#define DMA2TSEL__USCIA1TX     (21*0x0001u)   /* DMA channel 2 transfer select 21: USCIA1 transmit */
902 
#define DMA2TSEL__USCIB1RX     (22*0x0001u)   /* DMA channel 2 transfer select 22: USCIB1 receive */
903 
#define DMA2TSEL__USCIB1TX     (23*0x0001u)   /* DMA channel 2 transfer select 23: USCIB1 transmit */
904 
#define DMA2TSEL__ADC12IFG     (24*0x0001u)   /* DMA channel 2 transfer select 24: ADC12IFGx */
905 
#define DMA2TSEL__RES25        (25*0x0001u)   /* DMA channel 2 transfer select 25: Reserved */
906 
#define DMA2TSEL__RES26        (26*0x0001u)   /* DMA channel 2 transfer select 26: Reserved */
907 
#define DMA2TSEL__RES27        (27*0x0001u)   /* DMA channel 2 transfer select 27: Reserved */
908 
#define DMA2TSEL__RES28        (28*0x0001u)   /* DMA channel 2 transfer select 28: Reserved */
909 
#define DMA2TSEL__MPY          (29*0x0001u)   /* DMA channel 2 transfer select 29: Multiplier ready */
910 
#define DMA2TSEL__DMA1IFG      (30*0x0001u)   /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
911 
#define DMA2TSEL__DMAE0        (31*0x0001u)   /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
912 
 
913 
/*************************************************************
914 
* Flash Memory
915 
*************************************************************/
916 
#define __MSP430_HAS_FLASH__                  /* Definition to show that Module is available */
917 
#define __MSP430_BASEADDRESS_FLASH__ 0x0140
918 
 
919 
SFR_16BIT(FCTL1);                             /* FLASH Control 1 */
920 
SFR_8BIT(FCTL1_L);                            /* FLASH Control 1 */
921 
SFR_8BIT(FCTL1_H);                            /* FLASH Control 1 */
922 
//sfrbw    FCTL2               (0x0142)  /* FLASH Control 2 */
923 
SFR_16BIT(FCTL3);                             /* FLASH Control 3 */
924 
SFR_8BIT(FCTL3_L);                            /* FLASH Control 3 */
925 
SFR_8BIT(FCTL3_H);                            /* FLASH Control 3 */
926 
SFR_16BIT(FCTL4);                             /* FLASH Control 4 */
927 
SFR_8BIT(FCTL4_L);                            /* FLASH Control 4 */
928 
SFR_8BIT(FCTL4_H);                            /* FLASH Control 4 */
929 
 
930 
#define FRPW                   (0x9600)       /* Flash password returned by read */
931 
#define FWPW                   (0xA500)       /* Flash password for write */
932 
#define FXPW                   (0x3300)       /* for use with XOR instruction */
933 
#define FRKEY                  (0x9600)       /* (legacy definition) Flash key returned by read */
934 
#define FWKEY                  (0xA500)       /* (legacy definition) Flash key for write */
935 
#define FXKEY                  (0x3300)       /* (legacy definition) for use with XOR instruction */
936 
 
937 
/* FCTL1 Control Bits */
938 
//#define RESERVED            (0x0001)  /* Reserved */
939 
#define ERASE                  (0x0002)       /* Enable bit for Flash segment erase */
940 
#define MERAS                  (0x0004)       /* Enable bit for Flash mass erase */
941 
//#define RESERVED            (0x0008)  /* Reserved */
942 
//#define RESERVED            (0x0010)  /* Reserved */
943 
#define SWRT                   (0x0020)       /* Smart Write enable */
944 
#define WRT                    (0x0040)       /* Enable bit for Flash write */
945 
#define BLKWRT                 (0x0080)       /* Enable bit for Flash segment write */
946 
 
947 
/* FCTL1 Control Bits */
948 
//#define RESERVED            (0x0001)  /* Reserved */
949 
#define ERASE_L                (0x0002)       /* Enable bit for Flash segment erase */
950 
#define MERAS_L                (0x0004)       /* Enable bit for Flash mass erase */
951 
//#define RESERVED            (0x0008)  /* Reserved */
952 
//#define RESERVED            (0x0010)  /* Reserved */
953 
#define SWRT_L                 (0x0020)       /* Smart Write enable */
954 
#define WRT_L                  (0x0040)       /* Enable bit for Flash write */
955 
#define BLKWRT_L               (0x0080)       /* Enable bit for Flash segment write */
956 
 
957 
/* FCTL1 Control Bits */
958 
//#define RESERVED            (0x0001)  /* Reserved */
959 
//#define RESERVED            (0x0008)  /* Reserved */
960 
//#define RESERVED            (0x0010)  /* Reserved */
961 
 
962 
/* FCTL3 Control Bits */
963 
#define BUSY                   (0x0001)       /* Flash busy: 1 */
964 
#define KEYV                   (0x0002)       /* Flash Key violation flag */
965 
#define ACCVIFG                (0x0004)       /* Flash Access violation flag */
966 
#define WAIT                   (0x0008)       /* Wait flag for segment write */
967 
#define LOCK                   (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
968 
#define EMEX                   (0x0020)       /* Flash Emergency Exit */
969 
#define LOCKA                  (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
970 
//#define RESERVED            (0x0080)  /* Reserved */
971 
 
972 
/* FCTL3 Control Bits */
973 
#define BUSY_L                 (0x0001)       /* Flash busy: 1 */
974 
#define KEYV_L                 (0x0002)       /* Flash Key violation flag */
975 
#define ACCVIFG_L              (0x0004)       /* Flash Access violation flag */
976 
#define WAIT_L                 (0x0008)       /* Wait flag for segment write */
977 
#define LOCK_L                 (0x0010)       /* Lock bit: 1 - Flash is locked (read only) */
978 
#define EMEX_L                 (0x0020)       /* Flash Emergency Exit */
979 
#define LOCKA_L                (0x0040)       /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
980 
//#define RESERVED            (0x0080)  /* Reserved */
981 
 
982 
/* FCTL3 Control Bits */
983 
//#define RESERVED            (0x0080)  /* Reserved */
984 
 
985 
/* FCTL4 Control Bits */
986 
#define VPE                    (0x0001)       /* Voltage Changed during Program Error Flag */
987 
#define MGR0                   (0x0010)       /* Marginal read 0 mode. */
988 
#define MGR1                   (0x0020)       /* Marginal read 1 mode. */
989 
#define LOCKINFO               (0x0080)       /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
990 
 
991 
/* FCTL4 Control Bits */
992 
#define VPE_L                  (0x0001)       /* Voltage Changed during Program Error Flag */
993 
#define MGR0_L                 (0x0010)       /* Marginal read 0 mode. */
994 
#define MGR1_L                 (0x0020)       /* Marginal read 1 mode. */
995 
#define LOCKINFO_L             (0x0080)       /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
996 
 
997 
/* FCTL4 Control Bits */
998 
 
999 
/************************************************************
1000 
* HARDWARE MULTIPLIER 32Bit
1001 
************************************************************/
1002 
#define __MSP430_HAS_MPY32__                  /* Definition to show that Module is available */
1003 
#define __MSP430_BASEADDRESS_MPY32__ 0x04C0
1004 
 
1005 
SFR_16BIT(MPY);                               /* Multiply Unsigned/Operand 1 */
1006 
SFR_8BIT(MPY_L);                              /* Multiply Unsigned/Operand 1 */
1007 
SFR_8BIT(MPY_H);                              /* Multiply Unsigned/Operand 1 */
1008 
SFR_16BIT(MPYS);                              /* Multiply Signed/Operand 1 */
1009 
SFR_8BIT(MPYS_L);                             /* Multiply Signed/Operand 1 */
1010 
SFR_8BIT(MPYS_H);                             /* Multiply Signed/Operand 1 */
1011 
SFR_16BIT(MAC);                               /* Multiply Unsigned and Accumulate/Operand 1 */
1012 
SFR_8BIT(MAC_L);                              /* Multiply Unsigned and Accumulate/Operand 1 */
1013 
SFR_8BIT(MAC_H);                              /* Multiply Unsigned and Accumulate/Operand 1 */
1014 
SFR_16BIT(MACS);                              /* Multiply Signed and Accumulate/Operand 1 */
1015 
SFR_8BIT(MACS_L);                             /* Multiply Signed and Accumulate/Operand 1 */
1016 
SFR_8BIT(MACS_H);                             /* Multiply Signed and Accumulate/Operand 1 */
1017 
SFR_16BIT(OP2);                               /* Operand 2 */
1018 
SFR_8BIT(OP2_L);                              /* Operand 2 */
1019 
SFR_8BIT(OP2_H);                              /* Operand 2 */
1020 
SFR_16BIT(RESLO);                             /* Result Low Word */
1021 
SFR_8BIT(RESLO_L);                            /* Result Low Word */
1022 
SFR_8BIT(RESLO_H);                            /* Result Low Word */
1023 
SFR_16BIT(RESHI);                             /* Result High Word */
1024 
SFR_8BIT(RESHI_L);                            /* Result High Word */
1025 
SFR_8BIT(RESHI_H);                            /* Result High Word */
1026 
SFR_16BIT(SUMEXT);                            /* Sum Extend */
1027 
SFR_8BIT(SUMEXT_L);                           /* Sum Extend */
1028 
SFR_8BIT(SUMEXT_H);                           /* Sum Extend */
1029 
 
1030 
SFR_16BIT(MPY32L);                            /* 32-bit operand 1 - multiply - low word */
1031 
SFR_8BIT(MPY32L_L);                           /* 32-bit operand 1 - multiply - low word */
1032 
SFR_8BIT(MPY32L_H);                           /* 32-bit operand 1 - multiply - low word */
1033 
SFR_16BIT(MPY32H);                            /* 32-bit operand 1 - multiply - high word */
1034 
SFR_8BIT(MPY32H_L);                           /* 32-bit operand 1 - multiply - high word */
1035 
SFR_8BIT(MPY32H_H);                           /* 32-bit operand 1 - multiply - high word */
1036 
SFR_16BIT(MPYS32L);                           /* 32-bit operand 1 - signed multiply - low word */
1037 
SFR_8BIT(MPYS32L_L);                          /* 32-bit operand 1 - signed multiply - low word */
1038 
SFR_8BIT(MPYS32L_H);                          /* 32-bit operand 1 - signed multiply - low word */
1039 
SFR_16BIT(MPYS32H);                           /* 32-bit operand 1 - signed multiply - high word */
1040 
SFR_8BIT(MPYS32H_L);                          /* 32-bit operand 1 - signed multiply - high word */
1041 
SFR_8BIT(MPYS32H_H);                          /* 32-bit operand 1 - signed multiply - high word */
1042 
SFR_16BIT(MAC32L);                            /* 32-bit operand 1 - multiply accumulate - low word */
1043 
SFR_8BIT(MAC32L_L);                           /* 32-bit operand 1 - multiply accumulate - low word */
1044 
SFR_8BIT(MAC32L_H);                           /* 32-bit operand 1 - multiply accumulate - low word */
1045 
SFR_16BIT(MAC32H);                            /* 32-bit operand 1 - multiply accumulate - high word */
1046 
SFR_8BIT(MAC32H_L);                           /* 32-bit operand 1 - multiply accumulate - high word */
1047 
SFR_8BIT(MAC32H_H);                           /* 32-bit operand 1 - multiply accumulate - high word */
1048 
SFR_16BIT(MACS32L);                           /* 32-bit operand 1 - signed multiply accumulate - low word */
1049 
SFR_8BIT(MACS32L_L);                          /* 32-bit operand 1 - signed multiply accumulate - low word */
1050 
SFR_8BIT(MACS32L_H);                          /* 32-bit operand 1 - signed multiply accumulate - low word */
1051 
SFR_16BIT(MACS32H);                           /* 32-bit operand 1 - signed multiply accumulate - high word */
1052 
SFR_8BIT(MACS32H_L);                          /* 32-bit operand 1 - signed multiply accumulate - high word */
1053 
SFR_8BIT(MACS32H_H);                          /* 32-bit operand 1 - signed multiply accumulate - high word */
1054 
SFR_16BIT(OP2L);                              /* 32-bit operand 2 - low word */
1055 
SFR_8BIT(OP2L_L);                             /* 32-bit operand 2 - low word */
1056 
SFR_8BIT(OP2L_H);                             /* 32-bit operand 2 - low word */
1057 
SFR_16BIT(OP2H);                              /* 32-bit operand 2 - high word */
1058 
SFR_8BIT(OP2H_L);                             /* 32-bit operand 2 - high word */
1059 
SFR_8BIT(OP2H_H);                             /* 32-bit operand 2 - high word */
1060 
SFR_16BIT(RES0);                              /* 32x32-bit result 0 - least significant word */
1061 
SFR_8BIT(RES0_L);                             /* 32x32-bit result 0 - least significant word */
1062 
SFR_8BIT(RES0_H);                             /* 32x32-bit result 0 - least significant word */
1063 
SFR_16BIT(RES1);                              /* 32x32-bit result 1 */
1064 
SFR_8BIT(RES1_L);                             /* 32x32-bit result 1 */
1065 
SFR_8BIT(RES1_H);                             /* 32x32-bit result 1 */
1066 
SFR_16BIT(RES2);                              /* 32x32-bit result 2 */
1067 
SFR_8BIT(RES2_L);                             /* 32x32-bit result 2 */
1068 
SFR_8BIT(RES2_H);                             /* 32x32-bit result 2 */
1069 
SFR_16BIT(RES3);                              /* 32x32-bit result 3 - most significant word */
1070 
SFR_8BIT(RES3_L);                             /* 32x32-bit result 3 - most significant word */
1071 
SFR_8BIT(RES3_H);                             /* 32x32-bit result 3 - most significant word */
1072 
SFR_16BIT(MPY32CTL0);                         /* MPY32 Control Register 0 */
1073 
SFR_8BIT(MPY32CTL0_L);                        /* MPY32 Control Register 0 */
1074 
SFR_8BIT(MPY32CTL0_H);                        /* MPY32 Control Register 0 */
1075 
 
1076 
#define MPY_B                  MPY_L          /* Multiply Unsigned/Operand 1 (Byte Access) */
1077 
#define MPYS_B                 MPYS_L         /* Multiply Signed/Operand 1 (Byte Access) */
1078 
#define MAC_B                  MAC_L          /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
1079 
#define MACS_B                 MACS_L         /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
1080 
#define OP2_B                  OP2_L          /* Operand 2 (Byte Access) */
1081 
#define MPY32L_B               MPY32L_L       /* 32-bit operand 1 - multiply - low word (Byte Access) */
1082 
#define MPY32H_B               MPY32H_L       /* 32-bit operand 1 - multiply - high word (Byte Access) */
1083 
#define MPYS32L_B              MPYS32L_L      /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
1084 
#define MPYS32H_B              MPYS32H_L      /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
1085 
#define MAC32L_B               MAC32L_L       /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
1086 
#define MAC32H_B               MAC32H_L       /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
1087 
#define MACS32L_B              MACS32L_L      /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
1088 
#define MACS32H_B              MACS32H_L      /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
1089 
#define OP2L_B                 OP2L_L         /* 32-bit operand 2 - low word (Byte Access) */
1090 
#define OP2H_B                 OP2H_L         /* 32-bit operand 2 - high word (Byte Access) */
1091 
 
1092 
/* MPY32CTL0 Control Bits */
1093 
#define MPYC                   (0x0001)       /* Carry of the multiplier */
1094 
//#define RESERVED            (0x0002)  /* Reserved */
1095 
#define MPYFRAC                (0x0004)       /* Fractional mode */
1096 
#define MPYSAT                 (0x0008)       /* Saturation mode */
1097 
#define MPYM0                  (0x0010)       /* Multiplier mode Bit:0 */
1098 
#define MPYM1                  (0x0020)       /* Multiplier mode Bit:1 */
1099 
#define OP1_32                 (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
1100 
#define OP2_32                 (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
1101 
#define MPYDLYWRTEN            (0x0100)       /* Delayed write enable */
1102 
#define MPYDLY32               (0x0200)       /* Delayed write mode */
1103 
 
1104 
/* MPY32CTL0 Control Bits */
1105 
#define MPYC_L                 (0x0001)       /* Carry of the multiplier */
1106 
//#define RESERVED            (0x0002)  /* Reserved */
1107 
#define MPYFRAC_L              (0x0004)       /* Fractional mode */
1108 
#define MPYSAT_L               (0x0008)       /* Saturation mode */
1109 
#define MPYM0_L                (0x0010)       /* Multiplier mode Bit:0 */
1110 
#define MPYM1_L                (0x0020)       /* Multiplier mode Bit:1 */
1111 
#define OP1_32_L               (0x0040)       /* Bit-width of operand 1 0:16Bit / 1:32Bit */
1112 
#define OP2_32_L               (0x0080)       /* Bit-width of operand 2 0:16Bit / 1:32Bit */
1113 
 
1114 
/* MPY32CTL0 Control Bits */
1115 
//#define RESERVED            (0x0002)  /* Reserved */
1116 
#define MPYDLYWRTEN_H          (0x0001)       /* Delayed write enable */
1117 
#define MPYDLY32_H             (0x0002)       /* Delayed write mode */
1118 
 
1119 
#define MPYM_0                 (0x0000)       /* Multiplier mode: MPY */
1120 
#define MPYM_1                 (0x0010)       /* Multiplier mode: MPYS */
1121 
#define MPYM_2                 (0x0020)       /* Multiplier mode: MAC */
1122 
#define MPYM_3                 (0x0030)       /* Multiplier mode: MACS */
1123 
#define MPYM__MPY              (0x0000)       /* Multiplier mode: MPY */
1124 
#define MPYM__MPYS             (0x0010)       /* Multiplier mode: MPYS */
1125 
#define MPYM__MAC              (0x0020)       /* Multiplier mode: MAC */
1126 
#define MPYM__MACS             (0x0030)       /* Multiplier mode: MACS */
1127 
 
1128 
/************************************************************
1129 
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
1130 
************************************************************/
1131 
#define __MSP430_HAS_PORT1_R__                /* Definition to show that Module is available */
1132 
#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
1133 
#define __MSP430_HAS_PORT2_R__                /* Definition to show that Module is available */
1134 
#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
1135 
#define __MSP430_HAS_PORTA_R__                /* Definition to show that Module is available */
1136 
#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
1137 
 
1138 
SFR_16BIT(PAIN);                              /* Port A Input */
1139 
SFR_8BIT(PAIN_L);                             /* Port A Input */
1140 
SFR_8BIT(PAIN_H);                             /* Port A Input */
1141 
SFR_16BIT(PAOUT);                             /* Port A Output */
1142 
SFR_8BIT(PAOUT_L);                            /* Port A Output */
1143 
SFR_8BIT(PAOUT_H);                            /* Port A Output */
1144 
SFR_16BIT(PADIR);                             /* Port A Direction */
1145 
SFR_8BIT(PADIR_L);                            /* Port A Direction */
1146 
SFR_8BIT(PADIR_H);                            /* Port A Direction */
1147 
SFR_16BIT(PAREN);                             /* Port A Resistor Enable */
1148 
SFR_8BIT(PAREN_L);                            /* Port A Resistor Enable */
1149 
SFR_8BIT(PAREN_H);                            /* Port A Resistor Enable */
1150 
SFR_16BIT(PADS);                              /* Port A Resistor Drive Strenght */
1151 
SFR_8BIT(PADS_L);                             /* Port A Resistor Drive Strenght */
1152 
SFR_8BIT(PADS_H);                             /* Port A Resistor Drive Strenght */
1153 
SFR_16BIT(PASEL);                             /* Port A Selection */
1154 
SFR_8BIT(PASEL_L);                            /* Port A Selection */
1155 
SFR_8BIT(PASEL_H);                            /* Port A Selection */
1156 
SFR_16BIT(PAIES);                             /* Port A Interrupt Edge Select */
1157 
SFR_8BIT(PAIES_L);                            /* Port A Interrupt Edge Select */
1158 
SFR_8BIT(PAIES_H);                            /* Port A Interrupt Edge Select */
1159 
SFR_16BIT(PAIE);                              /* Port A Interrupt Enable */
1160 
SFR_8BIT(PAIE_L);                             /* Port A Interrupt Enable */
1161 
SFR_8BIT(PAIE_H);                             /* Port A Interrupt Enable */
1162 
SFR_16BIT(PAIFG);                             /* Port A Interrupt Flag */
1163 
SFR_8BIT(PAIFG_L);                            /* Port A Interrupt Flag */
1164 
SFR_8BIT(PAIFG_H);                            /* Port A Interrupt Flag */
1165 
 
1166 
 
1167 
SFR_16BIT(P1IV);                              /* Port 1 Interrupt Vector Word */
1168 
SFR_16BIT(P2IV);                              /* Port 2 Interrupt Vector Word */
1169 
#define P1IN                   (PAIN_L)       /* Port 1 Input */
1170 
#define P1OUT                  (PAOUT_L)      /* Port 1 Output */
1171 
#define P1DIR                  (PADIR_L)      /* Port 1 Direction */
1172 
#define P1REN                  (PAREN_L)      /* Port 1 Resistor Enable */
1173 
#define P1DS                   (PADS_L)       /* Port 1 Resistor Drive Strenght */
1174 
#define P1SEL                  (PASEL_L)      /* Port 1 Selection */
1175 
#define P1IES                  (PAIES_L)      /* Port 1 Interrupt Edge Select */
1176 
#define P1IE                   (PAIE_L)       /* Port 1 Interrupt Enable */
1177 
#define P1IFG                  (PAIFG_L)      /* Port 1 Interrupt Flag */
1178 
 
1179 
//Definitions for P1IV
1180 
#define P1IV_NONE              (0x0000)       /* No Interrupt pending */
1181 
#define P1IV_P1IFG0            (0x0002)       /* P1IV P1IFG.0 */
1182 
#define P1IV_P1IFG1            (0x0004)       /* P1IV P1IFG.1 */
1183 
#define P1IV_P1IFG2            (0x0006)       /* P1IV P1IFG.2 */
1184 
#define P1IV_P1IFG3            (0x0008)       /* P1IV P1IFG.3 */
1185 
#define P1IV_P1IFG4            (0x000A)       /* P1IV P1IFG.4 */
1186 
#define P1IV_P1IFG5            (0x000C)       /* P1IV P1IFG.5 */
1187 
#define P1IV_P1IFG6            (0x000E)       /* P1IV P1IFG.6 */
1188 
#define P1IV_P1IFG7            (0x0010)       /* P1IV P1IFG.7 */
1189 
 
1190 
#define P2IN                   (PAIN_H)       /* Port 2 Input */
1191 
#define P2OUT                  (PAOUT_H)      /* Port 2 Output */
1192 
#define P2DIR                  (PADIR_H)      /* Port 2 Direction */
1193 
#define P2REN                  (PAREN_H)      /* Port 2 Resistor Enable */
1194 
#define P2DS                   (PADS_H)       /* Port 2 Resistor Drive Strenght */
1195 
#define P2SEL                  (PASEL_H)      /* Port 2 Selection */
1196 
#define P2IES                  (PAIES_H)      /* Port 2 Interrupt Edge Select */
1197 
#define P2IE                   (PAIE_H)       /* Port 2 Interrupt Enable */
1198 
#define P2IFG                  (PAIFG_H)      /* Port 2 Interrupt Flag */
1199 
 
1200 
//Definitions for P2IV
1201 
#define P2IV_NONE              (0x0000)       /* No Interrupt pending */
1202 
#define P2IV_P2IFG0            (0x0002)       /* P2IV P2IFG.0 */
1203 
#define P2IV_P2IFG1            (0x0004)       /* P2IV P2IFG.1 */
1204 
#define P2IV_P2IFG2            (0x0006)       /* P2IV P2IFG.2 */
1205 
#define P2IV_P2IFG3            (0x0008)       /* P2IV P2IFG.3 */
1206 
#define P2IV_P2IFG4            (0x000A)       /* P2IV P2IFG.4 */
1207 
#define P2IV_P2IFG5            (0x000C)       /* P2IV P2IFG.5 */
1208 
#define P2IV_P2IFG6            (0x000E)       /* P2IV P2IFG.6 */
1209 
#define P2IV_P2IFG7            (0x0010)       /* P2IV P2IFG.7 */
1210 
 
1211 
 
1212 
/************************************************************
1213 
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
1214 
************************************************************/
1215 
#define __MSP430_HAS_PORT3_R__                /* Definition to show that Module is available */
1216 
#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220
1217 
#define __MSP430_HAS_PORT4_R__                /* Definition to show that Module is available */
1218 
#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220
1219 
#define __MSP430_HAS_PORTB_R__                /* Definition to show that Module is available */
1220 
#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220
1221 
 
1222 
SFR_16BIT(PBIN);                              /* Port B Input */
1223 
SFR_8BIT(PBIN_L);                             /* Port B Input */
1224 
SFR_8BIT(PBIN_H);                             /* Port B Input */
1225 
SFR_16BIT(PBOUT);                             /* Port B Output */
1226 
SFR_8BIT(PBOUT_L);                            /* Port B Output */
1227 
SFR_8BIT(PBOUT_H);                            /* Port B Output */
1228 
SFR_16BIT(PBDIR);                             /* Port B Direction */
1229 
SFR_8BIT(PBDIR_L);                            /* Port B Direction */
1230 
SFR_8BIT(PBDIR_H);                            /* Port B Direction */
1231 
SFR_16BIT(PBREN);                             /* Port B Resistor Enable */
1232 
SFR_8BIT(PBREN_L);                            /* Port B Resistor Enable */
1233 
SFR_8BIT(PBREN_H);                            /* Port B Resistor Enable */
1234 
SFR_16BIT(PBDS);                              /* Port B Resistor Drive Strenght */
1235 
SFR_8BIT(PBDS_L);                             /* Port B Resistor Drive Strenght */
1236 
SFR_8BIT(PBDS_H);                             /* Port B Resistor Drive Strenght */
1237 
SFR_16BIT(PBSEL);                             /* Port B Selection */
1238 
SFR_8BIT(PBSEL_L);                            /* Port B Selection */
1239 
SFR_8BIT(PBSEL_H);                            /* Port B Selection */
1240 
 
1241 
 
1242 
#define P3IN                   (PBIN_L)       /* Port 3 Input */
1243 
#define P3OUT                  (PBOUT_L)      /* Port 3 Output */
1244 
#define P3DIR                  (PBDIR_L)      /* Port 3 Direction */
1245 
#define P3REN                  (PBREN_L)      /* Port 3 Resistor Enable */
1246 
#define P3DS                   (PBDS_L)       /* Port 3 Resistor Drive Strenght */
1247 
#define P3SEL                  (PBSEL_L)      /* Port 3 Selection */
1248 
 
1249 
#define P4IN                   (PBIN_H)       /* Port 4 Input */
1250 
#define P4OUT                  (PBOUT_H)      /* Port 4 Output */
1251 
#define P4DIR                  (PBDIR_H)      /* Port 4 Direction */
1252 
#define P4REN                  (PBREN_H)      /* Port 4 Resistor Enable */
1253 
#define P4DS                   (PBDS_H)       /* Port 4 Resistor Drive Strenght */
1254 
#define P4SEL                  (PBSEL_H)      /* Port 4 Selection */
1255 
 
1256 
 
1257 
/************************************************************
1258 
* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
1259 
************************************************************/
1260 
#define __MSP430_HAS_PORT5_R__                /* Definition to show that Module is available */
1261 
#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240
1262 
#define __MSP430_HAS_PORT6_R__                /* Definition to show that Module is available */
1263 
#define __MSP430_BASEADDRESS_PORT6_R__ 0x0240
1264 
#define __MSP430_HAS_PORTC_R__                /* Definition to show that Module is available */
1265 
#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240
1266 
 
1267 
SFR_16BIT(PCIN);                              /* Port C Input */
1268 
SFR_8BIT(PCIN_L);                             /* Port C Input */
1269 
SFR_8BIT(PCIN_H);                             /* Port C Input */
1270 
SFR_16BIT(PCOUT);                             /* Port C Output */
1271 
SFR_8BIT(PCOUT_L);                            /* Port C Output */
1272 
SFR_8BIT(PCOUT_H);                            /* Port C Output */
1273 
SFR_16BIT(PCDIR);                             /* Port C Direction */
1274 
SFR_8BIT(PCDIR_L);                            /* Port C Direction */
1275 
SFR_8BIT(PCDIR_H);                            /* Port C Direction */
1276 
SFR_16BIT(PCREN);                             /* Port C Resistor Enable */
1277 
SFR_8BIT(PCREN_L);                            /* Port C Resistor Enable */
1278 
SFR_8BIT(PCREN_H);                            /* Port C Resistor Enable */
1279 
SFR_16BIT(PCDS);                              /* Port C Resistor Drive Strenght */
1280 
SFR_8BIT(PCDS_L);                             /* Port C Resistor Drive Strenght */
1281 
SFR_8BIT(PCDS_H);                             /* Port C Resistor Drive Strenght */
1282 
SFR_16BIT(PCSEL);                             /* Port C Selection */
1283 
SFR_8BIT(PCSEL_L);                            /* Port C Selection */
1284 
SFR_8BIT(PCSEL_H);                            /* Port C Selection */
1285 
 
1286 
 
1287 
#define P5IN                   (PCIN_L)       /* Port 5 Input */
1288 
#define P5OUT                  (PCOUT_L)      /* Port 5 Output */
1289 
#define P5DIR                  (PCDIR_L)      /* Port 5 Direction */
1290 
#define P5REN                  (PCREN_L)      /* Port 5 Resistor Enable */
1291 
#define P5DS                   (PCDS_L)       /* Port 5 Resistor Drive Strenght */
1292 
#define P5SEL                  (PCSEL_L)      /* Port 5 Selection */
1293 
 
1294 
#define P6IN                   (PCIN_H)       /* Port 6 Input */
1295 
#define P6OUT                  (PCOUT_H)      /* Port 6 Output */
1296 
#define P6DIR                  (PCDIR_H)      /* Port 6 Direction */
1297 
#define P6REN                  (PCREN_H)      /* Port 6 Resistor Enable */
1298 
#define P6DS                   (PCDS_H)       /* Port 6 Resistor Drive Strenght */
1299 
#define P6SEL                  (PCSEL_H)      /* Port 6 Selection */
1300 
 
1301 
 
1302 
/************************************************************
1303 
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
1304 
************************************************************/
1305 
#define __MSP430_HAS_PORT7_R__                /* Definition to show that Module is available */
1306 
#define __MSP430_BASEADDRESS_PORT7_R__ 0x0260
1307 
#define __MSP430_HAS_PORT8_R__                /* Definition to show that Module is available */
1308 
#define __MSP430_BASEADDRESS_PORT8_R__ 0x0260
1309 
#define __MSP430_HAS_PORTD_R__                /* Definition to show that Module is available */
1310 
#define __MSP430_BASEADDRESS_PORTD_R__ 0x0260
1311 
 
1312 
SFR_16BIT(PDIN);                              /* Port D Input */
1313 
SFR_8BIT(PDIN_L);                             /* Port D Input */
1314 
SFR_8BIT(PDIN_H);                             /* Port D Input */
1315 
SFR_16BIT(PDOUT);                             /* Port D Output */
1316 
SFR_8BIT(PDOUT_L);                            /* Port D Output */
1317 
SFR_8BIT(PDOUT_H);                            /* Port D Output */
1318 
SFR_16BIT(PDDIR);                             /* Port D Direction */
1319 
SFR_8BIT(PDDIR_L);                            /* Port D Direction */
1320 
SFR_8BIT(PDDIR_H);                            /* Port D Direction */
1321 
SFR_16BIT(PDREN);                             /* Port D Resistor Enable */
1322 
SFR_8BIT(PDREN_L);                            /* Port D Resistor Enable */
1323 
SFR_8BIT(PDREN_H);                            /* Port D Resistor Enable */
1324 
SFR_16BIT(PDDS);                              /* Port D Resistor Drive Strenght */
1325 
SFR_8BIT(PDDS_L);                             /* Port D Resistor Drive Strenght */
1326 
SFR_8BIT(PDDS_H);                             /* Port D Resistor Drive Strenght */
1327 
SFR_16BIT(PDSEL);                             /* Port D Selection */
1328 
SFR_8BIT(PDSEL_L);                            /* Port D Selection */
1329 
SFR_8BIT(PDSEL_H);                            /* Port D Selection */
1330 
 
1331 
 
1332 
#define P7IN                   (PDIN_L)       /* Port 7 Input */
1333 
#define P7OUT                  (PDOUT_L)      /* Port 7 Output */
1334 
#define P7DIR                  (PDDIR_L)      /* Port 7 Direction */
1335 
#define P7REN                  (PDREN_L)      /* Port 7 Resistor Enable */
1336 
#define P7DS                   (PDDS_L)       /* Port 7 Resistor Drive Strenght */
1337 
#define P7SEL                  (PDSEL_L)      /* Port 7 Selection */
1338 
 
1339 
#define P8IN                   (PDIN_H)       /* Port 8 Input */
1340 
#define P8OUT                  (PDOUT_H)      /* Port 8 Output */
1341 
#define P8DIR                  (PDDIR_H)      /* Port 8 Direction */
1342 
#define P8REN                  (PDREN_H)      /* Port 8 Resistor Enable */
1343 
#define P8DS                   (PDDS_H)       /* Port 8 Resistor Drive Strenght */
1344 
#define P8SEL                  (PDSEL_H)      /* Port 8 Selection */
1345 
 
1346 
 
1347 
/************************************************************
1348 
* DIGITAL I/O Port9/10 Pull up / Pull down Resistors
1349 
************************************************************/
1350 
#define __MSP430_HAS_PORT9_R__                /* Definition to show that Module is available */
1351 
#define __MSP430_BASEADDRESS_PORT9_R__ 0x0280
1352 
#define __MSP430_HAS_PORT10_R__                /* Definition to show that Module is available */
1353 
#define __MSP430_BASEADDRESS_PORT10_R__ 0x0280
1354 
#define __MSP430_HAS_PORTE_R__                /* Definition to show that Module is available */
1355 
#define __MSP430_BASEADDRESS_PORTE_R__ 0x0280
1356 
 
1357 
SFR_16BIT(PEIN);                              /* Port E Input */
1358 
SFR_8BIT(PEIN_L);                             /* Port E Input */
1359 
SFR_8BIT(PEIN_H);                             /* Port E Input */
1360 
SFR_16BIT(PEOUT);                             /* Port E Output */
1361 
SFR_8BIT(PEOUT_L);                            /* Port E Output */
1362 
SFR_8BIT(PEOUT_H);                            /* Port E Output */
1363 
SFR_16BIT(PEDIR);                             /* Port E Direction */
1364 
SFR_8BIT(PEDIR_L);                            /* Port E Direction */
1365 
SFR_8BIT(PEDIR_H);                            /* Port E Direction */
1366 
SFR_16BIT(PEREN);                             /* Port E Resistor Enable */
1367 
SFR_8BIT(PEREN_L);                            /* Port E Resistor Enable */
1368 
SFR_8BIT(PEREN_H);                            /* Port E Resistor Enable */
1369 
SFR_16BIT(PEDS);                              /* Port E Resistor Drive Strenght */
1370 
SFR_8BIT(PEDS_L);                             /* Port E Resistor Drive Strenght */
1371 
SFR_8BIT(PEDS_H);                             /* Port E Resistor Drive Strenght */
1372 
SFR_16BIT(PESEL);                             /* Port E Selection */
1373 
SFR_8BIT(PESEL_L);                            /* Port E Selection */
1374 
SFR_8BIT(PESEL_H);                            /* Port E Selection */
1375 
 
1376 
 
1377 
#define P9IN                   (PEIN_L)       /* Port 9 Input */
1378 
#define P9OUT                  (PEOUT_L)      /* Port 9 Output */
1379 
#define P9DIR                  (PEDIR_L)      /* Port 9 Direction */
1380 
#define P9REN                  (PEREN_L)      /* Port 9 Resistor Enable */
1381 
#define P9DS                   (PEDS_L)       /* Port 9 Resistor Drive Strenght */
1382 
#define P9SEL                  (PESEL_L)      /* Port 9 Selection */
1383 
 
1384 
#define P10IN                  (PEIN_H)       /* Port 10 Input */
1385 
#define P10OUT                 (PEOUT_H)      /* Port 10 Output */
1386 
#define P10DIR                 (PEDIR_H)      /* Port 10 Direction */
1387 
#define P10REN                 (PEREN_H)      /* Port 10 Resistor Enable */
1388 
#define P10DS                  (PEDS_H)       /* Port 10 Resistor Drive Strenght */
1389 
#define P10SEL                 (PESEL_H)      /* Port 10 Selection */
1390 
 
1391 
 
1392 
/************************************************************
1393 
* DIGITAL I/O Port11 Pull up / Pull down Resistors
1394 
************************************************************/
1395 
#define __MSP430_HAS_PORT11_R__                /* Definition to show that Module is available */
1396 
#define __MSP430_BASEADDRESS_PORT11_R__ 0x02A0
1397 
#define __MSP430_HAS_PORTF_R__                /* Definition to show that Module is available */
1398 
#define __MSP430_BASEADDRESS_PORTF_R__ 0x02A0
1399 
 
1400 
SFR_16BIT(PFIN);                              /* Port F Input */
1401 
SFR_8BIT(PFIN_L);                             /* Port F Input */
1402 
SFR_8BIT(PFIN_H);                             /* Port F Input */
1403 
SFR_16BIT(PFOUT);                             /* Port F Output */
1404 
SFR_8BIT(PFOUT_L);                            /* Port F Output */
1405 
SFR_8BIT(PFOUT_H);                            /* Port F Output */
1406 
SFR_16BIT(PFDIR);                             /* Port F Direction */
1407 
SFR_8BIT(PFDIR_L);                            /* Port F Direction */
1408 
SFR_8BIT(PFDIR_H);                            /* Port F Direction */
1409 
SFR_16BIT(PFREN);                             /* Port F Resistor Enable */
1410 
SFR_8BIT(PFREN_L);                            /* Port F Resistor Enable */
1411 
SFR_8BIT(PFREN_H);                            /* Port F Resistor Enable */
1412 
SFR_16BIT(PFDS);                              /* Port F Resistor Drive Strenght */
1413 
SFR_8BIT(PFDS_L);                             /* Port F Resistor Drive Strenght */
1414 
SFR_8BIT(PFDS_H);                             /* Port F Resistor Drive Strenght */
1415 
SFR_16BIT(PFSEL);                             /* Port F Selection */
1416 
SFR_8BIT(PFSEL_L);                            /* Port F Selection */
1417 
SFR_8BIT(PFSEL_H);                            /* Port F Selection */
1418 
 
1419 
 
1420 
#define P11IN                  (PFIN_L)       /* Port 11 Input */
1421 
#define P11OUT                 (PFOUT_L)      /* Port 11 Output */
1422 
#define P11DIR                 (PFDIR_L)      /* Port 11 Direction */
1423 
#define P11REN                 (PFREN_L)      /* Port 11 Resistor Enable */
1424 
#define P11DS                  (PFDS_L)       /* Port 11 Resistor Drive Strenght */
1425 
#define P11SEL                 (PFSEL_L)      /* Port 11 Selection */
1426 
 
1427 
 
1428 
/************************************************************
1429 
* DIGITAL I/O PortJ Pull up / Pull down Resistors
1430 
************************************************************/
1431 
#define __MSP430_HAS_PORTJ_R__                /* Definition to show that Module is available */
1432 
#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320
1433 
 
1434 
SFR_16BIT(PJIN);                              /* Port J Input */
1435 
SFR_8BIT(PJIN_L);                             /* Port J Input */
1436 
SFR_8BIT(PJIN_H);                             /* Port J Input */
1437 
SFR_16BIT(PJOUT);                             /* Port J Output */
1438 
SFR_8BIT(PJOUT_L);                            /* Port J Output */
1439 
SFR_8BIT(PJOUT_H);                            /* Port J Output */
1440 
SFR_16BIT(PJDIR);                             /* Port J Direction */
1441 
SFR_8BIT(PJDIR_L);                            /* Port J Direction */
1442 
SFR_8BIT(PJDIR_H);                            /* Port J Direction */
1443 
SFR_16BIT(PJREN);                             /* Port J Resistor Enable */
1444 
SFR_8BIT(PJREN_L);                            /* Port J Resistor Enable */
1445 
SFR_8BIT(PJREN_H);                            /* Port J Resistor Enable */
1446 
SFR_16BIT(PJDS);                              /* Port J Resistor Drive Strenght */
1447 
SFR_8BIT(PJDS_L);                             /* Port J Resistor Drive Strenght */
1448 
SFR_8BIT(PJDS_H);                             /* Port J Resistor Drive Strenght */
1449 
 
1450 
/************************************************************
1451 
* PMM - Power Management System
1452 
************************************************************/
1453 
#define __MSP430_HAS_PMM__                    /* Definition to show that Module is available */
1454 
#define __MSP430_BASEADDRESS_PMM__ 0x0120
1455 
 
1456 
SFR_16BIT(PMMCTL0);                           /* PMM Control 0 */
1457 
SFR_8BIT(PMMCTL0_L);                          /* PMM Control 0 */
1458 
SFR_8BIT(PMMCTL0_H);                          /* PMM Control 0 */
1459 
SFR_16BIT(PMMCTL1);                           /* PMM Control 1 */
1460 
SFR_8BIT(PMMCTL1_L);                          /* PMM Control 1 */
1461 
SFR_8BIT(PMMCTL1_H);                          /* PMM Control 1 */
1462 
SFR_16BIT(SVSMHCTL);                          /* SVS and SVM high side control register */
1463 
SFR_8BIT(SVSMHCTL_L);                         /* SVS and SVM high side control register */
1464 
SFR_8BIT(SVSMHCTL_H);                         /* SVS and SVM high side control register */
1465 
SFR_16BIT(SVSMLCTL);                          /* SVS and SVM low side control register */
1466 
SFR_8BIT(SVSMLCTL_L);                         /* SVS and SVM low side control register */
1467 
SFR_8BIT(SVSMLCTL_H);                         /* SVS and SVM low side control register */
1468 
SFR_16BIT(SVSMIO);                            /* SVSIN and SVSOUT control register */
1469 
SFR_8BIT(SVSMIO_L);                           /* SVSIN and SVSOUT control register */
1470 
SFR_8BIT(SVSMIO_H);                           /* SVSIN and SVSOUT control register */
1471 
SFR_16BIT(PMMIFG);                            /* PMM Interrupt Flag */
1472 
SFR_8BIT(PMMIFG_L);                           /* PMM Interrupt Flag */
1473 
SFR_8BIT(PMMIFG_H);                           /* PMM Interrupt Flag */
1474 
SFR_16BIT(PMMRIE);                            /* PMM and RESET Interrupt Enable */
1475 
SFR_8BIT(PMMRIE_L);                           /* PMM and RESET Interrupt Enable */
1476 
SFR_8BIT(PMMRIE_H);                           /* PMM and RESET Interrupt Enable */
1477 
SFR_16BIT(PM5CTL0);                           /* PMM Power Mode 5 Control Register 0 */
1478 
SFR_8BIT(PM5CTL0_L);                          /* PMM Power Mode 5 Control Register 0 */
1479 
SFR_8BIT(PM5CTL0_H);                          /* PMM Power Mode 5 Control Register 0 */
1480 
 
1481 
#define PMMPW                  (0xA500)       /* PMM Register Write Password */
1482 
#define PMMPW_H                (0xA5)         /* PMM Register Write Password for high word access */
1483 
 
1484 
/* PMMCTL0 Control Bits */
1485 
#define PMMCOREV0              (0x0001)       /* PMM Core Voltage Bit: 0 */
1486 
#define PMMCOREV1              (0x0002)       /* PMM Core Voltage Bit: 1 */
1487 
#define PMMSWBOR               (0x0004)       /* PMM Software BOR */
1488 
#define PMMSWPOR               (0x0008)       /* PMM Software POR */
1489 
#define PMMREGOFF              (0x0010)       /* PMM Turn Regulator off */
1490 
#define PMMHPMRE               (0x0080)       /* PMM Global High Power Module Request Enable */
1491 
 
1492 
/* PMMCTL0 Control Bits */
1493 
#define PMMCOREV0_L            (0x0001)       /* PMM Core Voltage Bit: 0 */
1494 
#define PMMCOREV1_L            (0x0002)       /* PMM Core Voltage Bit: 1 */
1495 
#define PMMSWBOR_L             (0x0004)       /* PMM Software BOR */
1496 
#define PMMSWPOR_L             (0x0008)       /* PMM Software POR */
1497 
#define PMMREGOFF_L            (0x0010)       /* PMM Turn Regulator off */
1498 
#define PMMHPMRE_L             (0x0080)       /* PMM Global High Power Module Request Enable */
1499 
 
1500 
/* PMMCTL0 Control Bits */
1501 
 
1502 
#define PMMCOREV_0             (0x0000)       /* PMM Core Voltage 0 (1.35V) */
1503 
#define PMMCOREV_1             (0x0001)       /* PMM Core Voltage 1 (1.55V) */
1504 
#define PMMCOREV_2             (0x0002)       /* PMM Core Voltage 2 (1.75V) */
1505 
#define PMMCOREV_3             (0x0003)       /* PMM Core Voltage 3 (1.85V) */
1506 
 
1507 
/* PMMCTL1 Control Bits */
1508 
#define PMMREFMD               (0x0001)       /* PMM Reference Mode */
1509 
#define PMMCMD0                (0x0010)       /* PMM Voltage Regulator Current Mode Bit: 0 */
1510 
#define PMMCMD1                (0x0020)       /* PMM Voltage Regulator Current Mode Bit: 1 */
1511 
 
1512 
/* PMMCTL1 Control Bits */
1513 
#define PMMREFMD_L             (0x0001)       /* PMM Reference Mode */
1514 
#define PMMCMD0_L              (0x0010)       /* PMM Voltage Regulator Current Mode Bit: 0 */
1515 
#define PMMCMD1_L              (0x0020)       /* PMM Voltage Regulator Current Mode Bit: 1 */
1516 
 
1517 
/* PMMCTL1 Control Bits */
1518 
 
1519 
/* SVSMHCTL Control Bits */
1520 
#define SVSMHRRL0              (0x0001)       /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
1521 
#define SVSMHRRL1              (0x0002)       /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
1522 
#define SVSMHRRL2              (0x0004)       /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
1523 
#define SVSMHDLYST             (0x0008)       /* SVS and SVM high side delay status */
1524 
#define SVSHMD                 (0x0010)       /* SVS high side mode */
1525 
#define SVSMHEVM               (0x0040)       /* SVS and SVM high side event mask */
1526 
#define SVSMHACE               (0x0080)       /* SVS and SVM high side auto control enable */
1527 
#define SVSHRVL0               (0x0100)       /* SVS high side reset voltage level Bit: 0 */
1528 
#define SVSHRVL1               (0x0200)       /* SVS high side reset voltage level Bit: 1 */
1529 
#define SVSHE                  (0x0400)       /* SVS high side enable */
1530 
#define SVSHFP                 (0x0800)       /* SVS high side full performace mode */
1531 
#define SVMHOVPE               (0x1000)       /* SVM high side over-voltage enable */
1532 
#define SVMHE                  (0x4000)       /* SVM high side enable */
1533 
#define SVMHFP                 (0x8000)       /* SVM high side full performace mode */
1534 
 
1535 
/* SVSMHCTL Control Bits */
1536 
#define SVSMHRRL0_L            (0x0001)       /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
1537 
#define SVSMHRRL1_L            (0x0002)       /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
1538 
#define SVSMHRRL2_L            (0x0004)       /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
1539 
#define SVSMHDLYST_L           (0x0008)       /* SVS and SVM high side delay status */
1540 
#define SVSHMD_L               (0x0010)       /* SVS high side mode */
1541 
#define SVSMHEVM_L             (0x0040)       /* SVS and SVM high side event mask */
1542 
#define SVSMHACE_L             (0x0080)       /* SVS and SVM high side auto control enable */
1543 
 
1544 
/* SVSMHCTL Control Bits */
1545 
#define SVSHRVL0_H             (0x0001)       /* SVS high side reset voltage level Bit: 0 */
1546 
#define SVSHRVL1_H             (0x0002)       /* SVS high side reset voltage level Bit: 1 */
1547 
#define SVSHE_H                (0x0004)       /* SVS high side enable */
1548 
#define SVSHFP_H               (0x0008)       /* SVS high side full performace mode */
1549 
#define SVMHOVPE_H             (0x0010)       /* SVM high side over-voltage enable */
1550 
#define SVMHE_H                (0x0040)       /* SVM high side enable */
1551 
#define SVMHFP_H               (0x0080)       /* SVM high side full performace mode */
1552 
 
1553 
#define SVSMHRRL_0             (0x0000)       /* SVS and SVM high side Reset Release Voltage Level 0 */
1554 
#define SVSMHRRL_1             (0x0001)       /* SVS and SVM high side Reset Release Voltage Level 1 */
1555 
#define SVSMHRRL_2             (0x0002)       /* SVS and SVM high side Reset Release Voltage Level 2 */
1556 
#define SVSMHRRL_3             (0x0003)       /* SVS and SVM high side Reset Release Voltage Level 3 */
1557 
#define SVSMHRRL_4             (0x0004)       /* SVS and SVM high side Reset Release Voltage Level 4 */
1558 
#define SVSMHRRL_5             (0x0005)       /* SVS and SVM high side Reset Release Voltage Level 5 */
1559 
#define SVSMHRRL_6             (0x0006)       /* SVS and SVM high side Reset Release Voltage Level 6 */
1560 
#define SVSMHRRL_7             (0x0007)       /* SVS and SVM high side Reset Release Voltage Level 7 */
1561 
 
1562 
#define SVSHRVL_0              (0x0000)       /* SVS high side Reset Release Voltage Level 0 */
1563 
#define SVSHRVL_1              (0x0100)       /* SVS high side Reset Release Voltage Level 1 */
1564 
#define SVSHRVL_2              (0x0200)       /* SVS high side Reset Release Voltage Level 2 */
1565 
#define SVSHRVL_3              (0x0300)       /* SVS high side Reset Release Voltage Level 3 */
1566 
 
1567 
/* SVSMLCTL Control Bits */
1568 
#define SVSMLRRL0              (0x0001)       /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
1569 
#define SVSMLRRL1              (0x0002)       /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
1570 
#define SVSMLRRL2              (0x0004)       /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
1571 
#define SVSMLDLYST             (0x0008)       /* SVS and SVM low side delay status */
1572 
#define SVSLMD                 (0x0010)       /* SVS low side mode */
1573 
#define SVSMLEVM               (0x0040)       /* SVS and SVM low side event mask */
1574 
#define SVSMLACE               (0x0080)       /* SVS and SVM low side auto control enable */
1575 
#define SVSLRVL0               (0x0100)       /* SVS low side reset voltage level Bit: 0 */
1576 
#define SVSLRVL1               (0x0200)       /* SVS low side reset voltage level Bit: 1 */
1577 
#define SVSLE                  (0x0400)       /* SVS low side enable */
1578 
#define SVSLFP                 (0x0800)       /* SVS low side full performace mode */
1579 
#define SVMLOVPE               (0x1000)       /* SVM low side over-voltage enable */
1580 
#define SVMLE                  (0x4000)       /* SVM low side enable */
1581 
#define SVMLFP                 (0x8000)       /* SVM low side full performace mode */
1582 
 
1583 
/* SVSMLCTL Control Bits */
1584 
#define SVSMLRRL0_L            (0x0001)       /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
1585 
#define SVSMLRRL1_L            (0x0002)       /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
1586 
#define SVSMLRRL2_L            (0x0004)       /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
1587 
#define SVSMLDLYST_L           (0x0008)       /* SVS and SVM low side delay status */
1588 
#define SVSLMD_L               (0x0010)       /* SVS low side mode */
1589 
#define SVSMLEVM_L             (0x0040)       /* SVS and SVM low side event mask */
1590 
#define SVSMLACE_L             (0x0080)       /* SVS and SVM low side auto control enable */
1591 
 
1592 
/* SVSMLCTL Control Bits */
1593 
#define SVSLRVL0_H             (0x0001)       /* SVS low side reset voltage level Bit: 0 */
1594 
#define SVSLRVL1_H             (0x0002)       /* SVS low side reset voltage level Bit: 1 */
1595 
#define SVSLE_H                (0x0004)       /* SVS low side enable */
1596 
#define SVSLFP_H               (0x0008)       /* SVS low side full performace mode */
1597 
#define SVMLOVPE_H             (0x0010)       /* SVM low side over-voltage enable */
1598 
#define SVMLE_H                (0x0040)       /* SVM low side enable */
1599 
#define SVMLFP_H               (0x0080)       /* SVM low side full performace mode */
1600 
 
1601 
#define SVSMLRRL_0             (0x0000)       /* SVS and SVM low side Reset Release Voltage Level 0 */
1602 
#define SVSMLRRL_1             (0x0001)       /* SVS and SVM low side Reset Release Voltage Level 1 */
1603 
#define SVSMLRRL_2             (0x0002)       /* SVS and SVM low side Reset Release Voltage Level 2 */
1604 
#define SVSMLRRL_3             (0x0003)       /* SVS and SVM low side Reset Release Voltage Level 3 */
1605 
#define SVSMLRRL_4             (0x0004)       /* SVS and SVM low side Reset Release Voltage Level 4 */
1606 
#define SVSMLRRL_5             (0x0005)       /* SVS and SVM low side Reset Release Voltage Level 5 */
1607 
#define SVSMLRRL_6             (0x0006)       /* SVS and SVM low side Reset Release Voltage Level 6 */
1608 
#define SVSMLRRL_7             (0x0007)       /* SVS and SVM low side Reset Release Voltage Level 7 */
1609 
 
1610 
#define SVSLRVL_0              (0x0000)       /* SVS low side Reset Release Voltage Level 0 */
1611 
#define SVSLRVL_1              (0x0100)       /* SVS low side Reset Release Voltage Level 1 */
1612 
#define SVSLRVL_2              (0x0200)       /* SVS low side Reset Release Voltage Level 2 */
1613 
#define SVSLRVL_3              (0x0300)       /* SVS low side Reset Release Voltage Level 3 */
1614 
 
1615 
/* SVSMIO Control Bits */
1616 
#define SVMLOE                 (0x0008)       /* SVM low side output enable */
1617 
#define SVMLVLROE              (0x0010)       /* SVM low side voltage level reached output enable */
1618 
#define SVMOUTPOL              (0x0020)       /* SVMOUT pin polarity */
1619 
#define SVMHOE                 (0x0800)       /* SVM high side output enable */
1620 
#define SVMHVLROE              (0x1000)       /* SVM high side voltage level reached output enable */
1621 
 
1622 
/* SVSMIO Control Bits */
1623 
#define SVMLOE_L               (0x0008)       /* SVM low side output enable */
1624 
#define SVMLVLROE_L            (0x0010)       /* SVM low side voltage level reached output enable */
1625 
#define SVMOUTPOL_L            (0x0020)       /* SVMOUT pin polarity */
1626 
 
1627 
/* SVSMIO Control Bits */
1628 
#define SVMHOE_H               (0x0008)       /* SVM high side output enable */
1629 
#define SVMHVLROE_H            (0x0010)       /* SVM high side voltage level reached output enable */
1630 
 
1631 
/* PMMIFG Control Bits */
1632 
#define SVSMLDLYIFG            (0x0001)       /* SVS and SVM low side Delay expired interrupt flag */
1633 
#define SVMLIFG                (0x0002)       /* SVM low side interrupt flag */
1634 
#define SVMLVLRIFG             (0x0004)       /* SVM low side Voltage Level Reached interrupt flag */
1635 
#define SVSMHDLYIFG            (0x0010)       /* SVS and SVM high side Delay expired interrupt flag */
1636 
#define SVMHIFG                (0x0020)       /* SVM high side interrupt flag */
1637 
#define SVMHVLRIFG             (0x0040)       /* SVM high side Voltage Level Reached interrupt flag */
1638 
#define PMMBORIFG              (0x0100)       /* PMM Software BOR interrupt flag */
1639 
#define PMMRSTIFG              (0x0200)       /* PMM RESET pin interrupt flag */
1640 
#define PMMPORIFG              (0x0400)       /* PMM Software POR interrupt flag */
1641 
#define SVSHIFG                (0x1000)       /* SVS low side interrupt flag */
1642 
#define SVSLIFG                (0x2000)       /* SVS high side interrupt flag */
1643 
#define PMMLPM5IFG             (0x8000)       /* LPM5 indication Flag */
1644 
 
1645 
/* PMMIFG Control Bits */
1646 
#define SVSMLDLYIFG_L          (0x0001)       /* SVS and SVM low side Delay expired interrupt flag */
1647 
#define SVMLIFG_L              (0x0002)       /* SVM low side interrupt flag */
1648 
#define SVMLVLRIFG_L           (0x0004)       /* SVM low side Voltage Level Reached interrupt flag */
1649 
#define SVSMHDLYIFG_L          (0x0010)       /* SVS and SVM high side Delay expired interrupt flag */
1650 
#define SVMHIFG_L              (0x0020)       /* SVM high side interrupt flag */
1651 
#define SVMHVLRIFG_L           (0x0040)       /* SVM high side Voltage Level Reached interrupt flag */
1652 
 
1653 
/* PMMIFG Control Bits */
1654 
#define PMMBORIFG_H            (0x0001)       /* PMM Software BOR interrupt flag */
1655 
#define PMMRSTIFG_H            (0x0002)       /* PMM RESET pin interrupt flag */
1656 
#define PMMPORIFG_H            (0x0004)       /* PMM Software POR interrupt flag */
1657 
#define SVSHIFG_H              (0x0010)       /* SVS low side interrupt flag */
1658 
#define SVSLIFG_H              (0x0020)       /* SVS high side interrupt flag */
1659 
#define PMMLPM5IFG_H           (0x0080)       /* LPM5 indication Flag */
1660 
 
1661 
#define PMMRSTLPM5IFG          PMMLPM5IFG     /* LPM5 indication Flag */
1662 
 
1663 
/* PMMIE and RESET Control Bits */
1664 
#define SVSMLDLYIE             (0x0001)       /* SVS and SVM low side Delay expired interrupt enable */
1665 
#define SVMLIE                 (0x0002)       /* SVM low side interrupt enable */
1666 
#define SVMLVLRIE              (0x0004)       /* SVM low side Voltage Level Reached interrupt enable */
1667 
#define SVSMHDLYIE             (0x0010)       /* SVS and SVM high side Delay expired interrupt enable */
1668 
#define SVMHIE                 (0x0020)       /* SVM high side interrupt enable */
1669 
#define SVMHVLRIE              (0x0040)       /* SVM high side Voltage Level Reached interrupt enable */
1670 
#define SVSLPE                 (0x0100)       /* SVS low side POR enable */
1671 
#define SVMLVLRPE              (0x0200)       /* SVM low side Voltage Level reached POR enable */
1672 
#define SVSHPE                 (0x1000)       /* SVS high side POR enable */
1673 
#define SVMHVLRPE              (0x2000)       /* SVM high side Voltage Level reached POR enable */
1674 
 
1675 
/* PMMIE and RESET Control Bits */
1676 
#define SVSMLDLYIE_L           (0x0001)       /* SVS and SVM low side Delay expired interrupt enable */
1677 
#define SVMLIE_L               (0x0002)       /* SVM low side interrupt enable */
1678 
#define SVMLVLRIE_L            (0x0004)       /* SVM low side Voltage Level Reached interrupt enable */
1679 
#define SVSMHDLYIE_L           (0x0010)       /* SVS and SVM high side Delay expired interrupt enable */
1680 
#define SVMHIE_L               (0x0020)       /* SVM high side interrupt enable */
1681 
#define SVMHVLRIE_L            (0x0040)       /* SVM high side Voltage Level Reached interrupt enable */
1682 
 
1683 
/* PMMIE and RESET Control Bits */
1684 
#define SVSLPE_H               (0x0001)       /* SVS low side POR enable */
1685 
#define SVMLVLRPE_H            (0x0002)       /* SVM low side Voltage Level reached POR enable */
1686 
#define SVSHPE_H               (0x0010)       /* SVS high side POR enable */
1687 
#define SVMHVLRPE_H            (0x0020)       /* SVM high side Voltage Level reached POR enable */
1688 
 
1689 
/* PM5CTL0 Power Mode 5 Control Bits */
1690 
#define LOCKLPM5               (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
1691 
 
1692 
/* PM5CTL0 Power Mode 5 Control Bits */
1693 
#define LOCKLPM5_L             (0x0001)       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
1694 
 
1695 
/* PM5CTL0 Power Mode 5 Control Bits */
1696 
#define LOCKIO                 LOCKLPM5       /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
1697 
 
1698 
/*************************************************************
1699 
* RAM Control Module
1700 
*************************************************************/
1701 
#define __MSP430_HAS_RC__                     /* Definition to show that Module is available */
1702 
#define __MSP430_BASEADDRESS_RC__ 0x0158
1703 
 
1704 
SFR_16BIT(RCCTL0);                            /* Ram Controller Control Register */
1705 
SFR_8BIT(RCCTL0_L);                           /* Ram Controller Control Register */
1706 
SFR_8BIT(RCCTL0_H);                           /* Ram Controller Control Register */
1707 
 
1708 
/* RCCTL0 Control Bits */
1709 
#define RCRS0OFF               (0x0001)       /* RAM Controller RAM Sector 0 Off */
1710 
#define RCRS1OFF               (0x0002)       /* RAM Controller RAM Sector 1 Off */
1711 
#define RCRS2OFF               (0x0004)       /* RAM Controller RAM Sector 2 Off */
1712 
#define RCRS3OFF               (0x0008)       /* RAM Controller RAM Sector 3 Off */
1713 
 
1714 
/* RCCTL0 Control Bits */
1715 
#define RCRS0OFF_L             (0x0001)       /* RAM Controller RAM Sector 0 Off */
1716 
#define RCRS1OFF_L             (0x0002)       /* RAM Controller RAM Sector 1 Off */
1717 
#define RCRS2OFF_L             (0x0004)       /* RAM Controller RAM Sector 2 Off */
1718 
#define RCRS3OFF_L             (0x0008)       /* RAM Controller RAM Sector 3 Off */
1719 
 
1720 
/* RCCTL0 Control Bits */
1721 
 
1722 
#define RCKEY                  (0x5A00)
1723 
 
1724 
/************************************************************
1725 
* Shared Reference
1726 
************************************************************/
1727 
#define __MSP430_HAS_REF__                    /* Definition to show that Module is available */
1728 
#define __MSP430_BASEADDRESS_REF__ 0x01B0
1729 
 
1730 
SFR_16BIT(REFCTL0);                           /* REF Shared Reference control register 0 */
1731 
SFR_8BIT(REFCTL0_L);                          /* REF Shared Reference control register 0 */
1732 
SFR_8BIT(REFCTL0_H);                          /* REF Shared Reference control register 0 */
1733 
 
1734 
/* REFCTL0 Control Bits */
1735 
#define REFON                  (0x0001)       /* REF Reference On */
1736 
#define REFOUT                 (0x0002)       /* REF Reference output Buffer On */
1737 
//#define RESERVED            (0x0004)  /* Reserved */
1738 
#define REFTCOFF               (0x0008)       /* REF Temp.Sensor off */
1739 
#define REFVSEL0               (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
1740 
#define REFVSEL1               (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
1741 
//#define RESERVED            (0x0040)  /* Reserved */
1742 
#define REFMSTR                (0x0080)       /* REF Master Control */
1743 
#define REFGENACT              (0x0100)       /* REF Reference generator active */
1744 
#define REFBGACT               (0x0200)       /* REF Reference bandgap active */
1745 
#define REFGENBUSY             (0x0400)       /* REF Reference generator busy */
1746 
#define BGMODE                 (0x0800)       /* REF Bandgap mode */
1747 
//#define RESERVED            (0x1000)  /* Reserved */
1748 
//#define RESERVED            (0x2000)  /* Reserved */
1749 
//#define RESERVED            (0x4000)  /* Reserved */
1750 
//#define RESERVED            (0x8000)  /* Reserved */
1751 
 
1752 
/* REFCTL0 Control Bits */
1753 
#define REFON_L                (0x0001)       /* REF Reference On */
1754 
#define REFOUT_L               (0x0002)       /* REF Reference output Buffer On */
1755 
//#define RESERVED            (0x0004)  /* Reserved */
1756 
#define REFTCOFF_L             (0x0008)       /* REF Temp.Sensor off */
1757 
#define REFVSEL0_L             (0x0010)       /* REF Reference Voltage Level Select Bit:0 */
1758 
#define REFVSEL1_L             (0x0020)       /* REF Reference Voltage Level Select Bit:1 */
1759 
//#define RESERVED            (0x0040)  /* Reserved */
1760 
#define REFMSTR_L              (0x0080)       /* REF Master Control */
1761 
//#define RESERVED            (0x1000)  /* Reserved */
1762 
//#define RESERVED            (0x2000)  /* Reserved */
1763 
//#define RESERVED            (0x4000)  /* Reserved */
1764 
//#define RESERVED            (0x8000)  /* Reserved */
1765 
 
1766 
/* REFCTL0 Control Bits */
1767 
//#define RESERVED            (0x0004)  /* Reserved */
1768 
//#define RESERVED            (0x0040)  /* Reserved */
1769 
#define REFGENACT_H            (0x0001)       /* REF Reference generator active */
1770 
#define REFBGACT_H             (0x0002)       /* REF Reference bandgap active */
1771 
#define REFGENBUSY_H           (0x0004)       /* REF Reference generator busy */
1772 
#define BGMODE_H               (0x0008)       /* REF Bandgap mode */
1773 
//#define RESERVED            (0x1000)  /* Reserved */
1774 
//#define RESERVED            (0x2000)  /* Reserved */
1775 
//#define RESERVED            (0x4000)  /* Reserved */
1776 
//#define RESERVED            (0x8000)  /* Reserved */
1777 
 
1778 
#define REFVSEL_0              (0x0000)       /* REF Reference Voltage Level Select 1.5V */
1779 
#define REFVSEL_1              (0x0010)       /* REF Reference Voltage Level Select 2.0V */
1780 
#define REFVSEL_2              (0x0020)       /* REF Reference Voltage Level Select 2.5V */
1781 
#define REFVSEL_3              (0x0030)       /* REF Reference Voltage Level Select 2.5V */
1782 
 
1783 
/************************************************************
1784 
* Real Time Clock
1785 
************************************************************/
1786 
#define __MSP430_HAS_RTC__                    /* Definition to show that Module is available */
1787 
#define __MSP430_BASEADDRESS_RTC__ 0x04A0
1788 
 
1789 
SFR_16BIT(RTCCTL01);                          /* Real Timer Control 0/1 */
1790 
SFR_8BIT(RTCCTL01_L);                         /* Real Timer Control 0/1 */
1791 
SFR_8BIT(RTCCTL01_H);                         /* Real Timer Control 0/1 */
1792 
SFR_16BIT(RTCCTL23);                          /* Real Timer Control 2/3 */
1793 
SFR_8BIT(RTCCTL23_L);                         /* Real Timer Control 2/3 */
1794 
SFR_8BIT(RTCCTL23_H);                         /* Real Timer Control 2/3 */
1795 
SFR_16BIT(RTCPS0CTL);                         /* Real Timer Prescale Timer 0 Control */
1796 
SFR_8BIT(RTCPS0CTL_L);                        /* Real Timer Prescale Timer 0 Control */
1797 
SFR_8BIT(RTCPS0CTL_H);                        /* Real Timer Prescale Timer 0 Control */
1798 
SFR_16BIT(RTCPS1CTL);                         /* Real Timer Prescale Timer 1 Control */
1799 
SFR_8BIT(RTCPS1CTL_L);                        /* Real Timer Prescale Timer 1 Control */
1800 
SFR_8BIT(RTCPS1CTL_H);                        /* Real Timer Prescale Timer 1 Control */
1801 
SFR_16BIT(RTCPS);                             /* Real Timer Prescale Timer Control */
1802 
SFR_8BIT(RTCPS_L);                            /* Real Timer Prescale Timer Control */
1803 
SFR_8BIT(RTCPS_H);                            /* Real Timer Prescale Timer Control */
1804 
SFR_16BIT(RTCIV);                             /* Real Time Clock Interrupt Vector */
1805 
SFR_16BIT(RTCTIM0);                           /* Real Time Clock Time 0 */
1806 
SFR_8BIT(RTCTIM0_L);                          /* Real Time Clock Time 0 */
1807 
SFR_8BIT(RTCTIM0_H);                          /* Real Time Clock Time 0 */
1808 
SFR_16BIT(RTCTIM1);                           /* Real Time Clock Time 1 */
1809 
SFR_8BIT(RTCTIM1_L);                          /* Real Time Clock Time 1 */
1810 
SFR_8BIT(RTCTIM1_H);                          /* Real Time Clock Time 1 */
1811 
SFR_16BIT(RTCDATE);                           /* Real Time Clock Date */
1812 
SFR_8BIT(RTCDATE_L);                          /* Real Time Clock Date */
1813 
SFR_8BIT(RTCDATE_H);                          /* Real Time Clock Date */
1814 
SFR_16BIT(RTCYEAR);                           /* Real Time Clock Year */
1815 
SFR_8BIT(RTCYEAR_L);                          /* Real Time Clock Year */
1816 
SFR_8BIT(RTCYEAR_H);                          /* Real Time Clock Year */
1817 
SFR_16BIT(RTCAMINHR);                         /* Real Time Clock Alarm Min/Hour */
1818 
SFR_8BIT(RTCAMINHR_L);                        /* Real Time Clock Alarm Min/Hour */
1819 
SFR_8BIT(RTCAMINHR_H);                        /* Real Time Clock Alarm Min/Hour */
1820 
SFR_16BIT(RTCADOWDAY);                        /* Real Time Clock Alarm day of week/day */
1821 
SFR_8BIT(RTCADOWDAY_L);                       /* Real Time Clock Alarm day of week/day */
1822 
SFR_8BIT(RTCADOWDAY_H);                       /* Real Time Clock Alarm day of week/day */
1823 
 
1824 
#define RTCCTL0                RTCCTL01_L     /* Real Time Clock Control 0 */
1825 
#define RTCCTL1                RTCCTL01_H     /* Real Time Clock Control 1 */
1826 
#define RTCCTL2                RTCCTL23_L     /* Real Time Clock Control 2 */
1827 
#define RTCCTL3                RTCCTL23_H     /* Real Time Clock Control 3 */
1828 
#define RTCNT12                RTCTIM0
1829 
#define RTCNT34                RTCTIM1
1830 
#define RTCNT1                 RTCTIM0_L
1831 
#define RTCNT2                 RTCTIM0_H
1832 
#define RTCNT3                 RTCTIM1_L
1833 
#define RTCNT4                 RTCTIM1_H
1834 
#define RTCSEC                 RTCTIM0_L
1835 
#define RTCMIN                 RTCTIM0_H
1836 
#define RTCHOUR                RTCTIM1_L
1837 
#define RTCDOW                 RTCTIM1_H
1838 
#define RTCDAY                 RTCDATE_L
1839 
#define RTCMON                 RTCDATE_H
1840 
#define RTCYEARL               RTCYEAR_L
1841 
#define RTCYEARH               RTCYEAR_H
1842 
#define RT0PS                  RTCPS_L
1843 
#define RT1PS                  RTCPS_H
1844 
#define RTCAMIN                RTCAMINHR_L    /* Real Time Clock Alarm Min */
1845 
#define RTCAHOUR               RTCAMINHR_H    /* Real Time Clock Alarm Hour */
1846 
#define RTCADOW                RTCADOWDAY_L   /* Real Time Clock Alarm day of week */
1847 
#define RTCADAY                RTCADOWDAY_H   /* Real Time Clock Alarm day */
1848 
 
1849 
/* RTCCTL01 Control Bits */
1850 
#define RTCBCD                 (0x8000)       /* RTC BCD  0:Binary / 1:BCD */
1851 
#define RTCHOLD                (0x4000)       /* RTC Hold */
1852 
#define RTCMODE                (0x2000)       /* RTC Mode 0:Counter / 1: Calendar */
1853 
#define RTCRDY                 (0x1000)       /* RTC Ready */
1854 
#define RTCSSEL1               (0x0800)       /* RTC Source Select 1 */
1855 
#define RTCSSEL0               (0x0400)       /* RTC Source Select 0 */
1856 
#define RTCTEV1                (0x0200)       /* RTC Time Event 1 */
1857 
#define RTCTEV0                (0x0100)       /* RTC Time Event 0 */
1858 
//#define Reserved          (0x0080)
1859 
#define RTCTEVIE               (0x0040)       /* RTC Time Event Interrupt Enable Flag */
1860 
#define RTCAIE                 (0x0020)       /* RTC Alarm Interrupt Enable Flag */
1861 
#define RTCRDYIE               (0x0010)       /* RTC Ready Interrupt Enable Flag */
1862 
//#define Reserved          (0x0008)
1863 
#define RTCTEVIFG              (0x0004)       /* RTC Time Event Interrupt Flag */
1864 
#define RTCAIFG                (0x0002)       /* RTC Alarm Interrupt Flag */
1865 
#define RTCRDYIFG              (0x0001)       /* RTC Ready Interrupt Flag */
1866 
 
1867 
/* RTCCTL01 Control Bits */
1868 
//#define Reserved          (0x0080)
1869 
#define RTCTEVIE_L             (0x0040)       /* RTC Time Event Interrupt Enable Flag */
1870 
#define RTCAIE_L               (0x0020)       /* RTC Alarm Interrupt Enable Flag */
1871 
#define RTCRDYIE_L             (0x0010)       /* RTC Ready Interrupt Enable Flag */
1872 
//#define Reserved          (0x0008)
1873 
#define RTCTEVIFG_L            (0x0004)       /* RTC Time Event Interrupt Flag */
1874 
#define RTCAIFG_L              (0x0002)       /* RTC Alarm Interrupt Flag */
1875 
#define RTCRDYIFG_L            (0x0001)       /* RTC Ready Interrupt Flag */
1876 
 
1877 
/* RTCCTL01 Control Bits */
1878 
#define RTCBCD_H               (0x0080)       /* RTC BCD  0:Binary / 1:BCD */
1879 
#define RTCHOLD_H              (0x0040)       /* RTC Hold */
1880 
#define RTCMODE_H              (0x0020)       /* RTC Mode 0:Counter / 1: Calendar */
1881 
#define RTCRDY_H               (0x0010)       /* RTC Ready */
1882 
#define RTCSSEL1_H             (0x0008)       /* RTC Source Select 1 */
1883 
#define RTCSSEL0_H             (0x0004)       /* RTC Source Select 0 */
1884 
#define RTCTEV1_H              (0x0002)       /* RTC Time Event 1 */
1885 
#define RTCTEV0_H              (0x0001)       /* RTC Time Event 0 */
1886 
//#define Reserved          (0x0080)
1887 
//#define Reserved          (0x0008)
1888 
 
1889 
#define RTCSSEL_0              (0x0000)       /* RTC Source Select ACLK */
1890 
#define RTCSSEL_1              (0x0400)       /* RTC Source Select SMCLK */
1891 
#define RTCSSEL_2              (0x0800)       /* RTC Source Select RT1PS */
1892 
#define RTCSSEL_3              (0x0C00)       /* RTC Source Select RT1PS */
1893 
#define RTCSSEL__ACLK          (0x0000)       /* RTC Source Select ACLK */
1894 
#define RTCSSEL__SMCLK         (0x0400)       /* RTC Source Select SMCLK */
1895 
#define RTCSSEL__RT1PS         (0x0800)       /* RTC Source Select RT1PS */
1896 
#define RTCTEV_0               (0x0000)       /* RTC Time Event: 0 (Min. changed) */
1897 
#define RTCTEV_1               (0x0100)       /* RTC Time Event: 1 (Hour changed) */
1898 
#define RTCTEV_2               (0x0200)       /* RTC Time Event: 2 (12:00 changed) */
1899 
#define RTCTEV_3               (0x0300)       /* RTC Time Event: 3 (00:00 changed) */
1900 
#define RTCTEV__MIN            (0x0000)       /* RTC Time Event: 0 (Min. changed) */
1901 
#define RTCTEV__HOUR           (0x0100)       /* RTC Time Event: 1 (Hour changed) */
1902 
#define RTCTEV__1200           (0x0200)       /* RTC Time Event: 2 (12:00 changed) */
1903 
#define RTCTEV__0000           (0x0300)       /* RTC Time Event: 3 (00:00 changed) */
1904 
 
1905 
/* RTCCTL23 Control Bits */
1906 
#define RTCCALF1               (0x0200)       /* RTC Calibration Frequency Bit 1 */
1907 
#define RTCCALF0               (0x0100)       /* RTC Calibration Frequency Bit 0 */
1908 
#define RTCCALS                (0x0080)       /* RTC Calibration Sign */
1909 
//#define Reserved          (0x0040)
1910 
#define RTCCAL5                (0x0020)       /* RTC Calibration Bit 5 */
1911 
#define RTCCAL4                (0x0010)       /* RTC Calibration Bit 4 */
1912 
#define RTCCAL3                (0x0008)       /* RTC Calibration Bit 3 */
1913 
#define RTCCAL2                (0x0004)       /* RTC Calibration Bit 2 */
1914 
#define RTCCAL1                (0x0002)       /* RTC Calibration Bit 1 */
1915 
#define RTCCAL0                (0x0001)       /* RTC Calibration Bit 0 */
1916 
 
1917 
/* RTCCTL23 Control Bits */
1918 
#define RTCCALS_L              (0x0080)       /* RTC Calibration Sign */
1919 
//#define Reserved          (0x0040)
1920 
#define RTCCAL5_L              (0x0020)       /* RTC Calibration Bit 5 */
1921 
#define RTCCAL4_L              (0x0010)       /* RTC Calibration Bit 4 */
1922 
#define RTCCAL3_L              (0x0008)       /* RTC Calibration Bit 3 */
1923 
#define RTCCAL2_L              (0x0004)       /* RTC Calibration Bit 2 */
1924 
#define RTCCAL1_L              (0x0002)       /* RTC Calibration Bit 1 */
1925 
#define RTCCAL0_L              (0x0001)       /* RTC Calibration Bit 0 */
1926 
 
1927 
/* RTCCTL23 Control Bits */
1928 
#define RTCCALF1_H             (0x0002)       /* RTC Calibration Frequency Bit 1 */
1929 
#define RTCCALF0_H             (0x0001)       /* RTC Calibration Frequency Bit 0 */
1930 
//#define Reserved          (0x0040)
1931 
 
1932 
#define RTCCALF_0              (0x0000)       /* RTC Calibration Frequency: No Output */
1933 
#define RTCCALF_1              (0x0100)       /* RTC Calibration Frequency: 512 Hz */
1934 
#define RTCCALF_2              (0x0200)       /* RTC Calibration Frequency: 256 Hz */
1935 
#define RTCCALF_3              (0x0300)       /* RTC Calibration Frequency: 1 Hz */
1936 
 
1937 
/* RTCPS0CTL Control Bits */
1938 
//#define Reserved          (0x8000)
1939 
#define RT0SSEL                (0x4000)       /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
1940 
#define RT0PSDIV2              (0x2000)       /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
1941 
#define RT0PSDIV1              (0x1000)       /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
1942 
#define RT0PSDIV0              (0x0800)       /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
1943 
//#define Reserved          (0x0400)
1944 
//#define Reserved          (0x0200)
1945 
#define RT0PSHOLD              (0x0100)       /* RTC Prescale Timer 0 Hold */
1946 
//#define Reserved          (0x0080)
1947 
//#define Reserved          (0x0040)
1948 
//#define Reserved          (0x0020)
1949 
#define RT0IP2                 (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
1950 
#define RT0IP1                 (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
1951 
#define RT0IP0                 (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
1952 
#define RT0PSIE                (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
1953 
#define RT0PSIFG               (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
1954 
 
1955 
/* RTCPS0CTL Control Bits */
1956 
//#define Reserved          (0x8000)
1957 
//#define Reserved          (0x0400)
1958 
//#define Reserved          (0x0200)
1959 
//#define Reserved          (0x0080)
1960 
//#define Reserved          (0x0040)
1961 
//#define Reserved          (0x0020)
1962 
#define RT0IP2_L               (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
1963 
#define RT0IP1_L               (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
1964 
#define RT0IP0_L               (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
1965 
#define RT0PSIE_L              (0x0002)       /* RTC Prescale Timer 0 Interrupt Enable Flag */
1966 
#define RT0PSIFG_L             (0x0001)       /* RTC Prescale Timer 0 Interrupt Flag */
1967 
 
1968 
/* RTCPS0CTL Control Bits */
1969 
//#define Reserved          (0x8000)
1970 
#define RT0SSEL_H              (0x0040)       /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
1971 
#define RT0PSDIV2_H            (0x0020)       /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
1972 
#define RT0PSDIV1_H            (0x0010)       /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
1973 
#define RT0PSDIV0_H            (0x0008)       /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
1974 
//#define Reserved          (0x0400)
1975 
//#define Reserved          (0x0200)
1976 
#define RT0PSHOLD_H            (0x0001)       /* RTC Prescale Timer 0 Hold */
1977 
//#define Reserved          (0x0080)
1978 
//#define Reserved          (0x0040)
1979 
//#define Reserved          (0x0020)
1980 
 
1981 
#define RT0IP_0                (0x0000)       /* RTC Prescale Timer 0 Interrupt Interval /2 */
1982 
#define RT0IP_1                (0x0004)       /* RTC Prescale Timer 0 Interrupt Interval /4 */
1983 
#define RT0IP_2                (0x0008)       /* RTC Prescale Timer 0 Interrupt Interval /8 */
1984 
#define RT0IP_3                (0x000C)       /* RTC Prescale Timer 0 Interrupt Interval /16 */
1985 
#define RT0IP_4                (0x0010)       /* RTC Prescale Timer 0 Interrupt Interval /32 */
1986 
#define RT0IP_5                (0x0014)       /* RTC Prescale Timer 0 Interrupt Interval /64 */
1987 
#define RT0IP_6                (0x0018)       /* RTC Prescale Timer 0 Interrupt Interval /128 */
1988 
#define RT0IP_7                (0x001C)       /* RTC Prescale Timer 0 Interrupt Interval /256 */
1989 
 
1990 
#define RT0PSDIV_0             (0x0000)       /* RTC Prescale Timer 0 Clock Divide /2 */
1991 
#define RT0PSDIV_1             (0x0800)       /* RTC Prescale Timer 0 Clock Divide /4 */
1992 
#define RT0PSDIV_2             (0x1000)       /* RTC Prescale Timer 0 Clock Divide /8 */
1993 
#define RT0PSDIV_3             (0x1800)       /* RTC Prescale Timer 0 Clock Divide /16 */
1994 
#define RT0PSDIV_4             (0x2000)       /* RTC Prescale Timer 0 Clock Divide /32 */
1995 
#define RT0PSDIV_5             (0x2800)       /* RTC Prescale Timer 0 Clock Divide /64 */
1996 
#define RT0PSDIV_6             (0x3000)       /* RTC Prescale Timer 0 Clock Divide /128 */
1997 
#define RT0PSDIV_7             (0x3800)       /* RTC Prescale Timer 0 Clock Divide /256 */
1998 
 
1999 
/* RTCPS1CTL Control Bits */
2000 
#define RT1SSEL1               (0x8000)       /* RTC Prescale Timer 1 Source Select Bit 1 */
2001 
#define RT1SSEL0               (0x4000)       /* RTC Prescale Timer 1 Source Select Bit 0 */
2002 
#define RT1PSDIV2              (0x2000)       /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
2003 
#define RT1PSDIV1              (0x1000)       /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
2004 
#define RT1PSDIV0              (0x0800)       /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
2005 
//#define Reserved          (0x0400)
2006 
//#define Reserved          (0x0200)
2007 
#define RT1PSHOLD              (0x0100)       /* RTC Prescale Timer 1 Hold */
2008 
//#define Reserved          (0x0080)
2009 
//#define Reserved          (0x0040)
2010 
//#define Reserved          (0x0020)
2011 
#define RT1IP2                 (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
2012 
#define RT1IP1                 (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
2013 
#define RT1IP0                 (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
2014 
#define RT1PSIE                (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
2015 
#define RT1PSIFG               (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
2016 
 
2017 
/* RTCPS1CTL Control Bits */
2018 
//#define Reserved          (0x0400)
2019 
//#define Reserved          (0x0200)
2020 
//#define Reserved          (0x0080)
2021 
//#define Reserved          (0x0040)
2022 
//#define Reserved          (0x0020)
2023 
#define RT1IP2_L               (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
2024 
#define RT1IP1_L               (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
2025 
#define RT1IP0_L               (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
2026 
#define RT1PSIE_L              (0x0002)       /* RTC Prescale Timer 1 Interrupt Enable Flag */
2027 
#define RT1PSIFG_L             (0x0001)       /* RTC Prescale Timer 1 Interrupt Flag */
2028 
 
2029 
/* RTCPS1CTL Control Bits */
2030 
#define RT1SSEL1_H             (0x0080)       /* RTC Prescale Timer 1 Source Select Bit 1 */
2031 
#define RT1SSEL0_H             (0x0040)       /* RTC Prescale Timer 1 Source Select Bit 0 */
2032 
#define RT1PSDIV2_H            (0x0020)       /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
2033 
#define RT1PSDIV1_H            (0x0010)       /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
2034 
#define RT1PSDIV0_H            (0x0008)       /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
2035 
//#define Reserved          (0x0400)
2036 
//#define Reserved          (0x0200)
2037 
#define RT1PSHOLD_H            (0x0001)       /* RTC Prescale Timer 1 Hold */
2038 
//#define Reserved          (0x0080)
2039 
//#define Reserved          (0x0040)
2040 
//#define Reserved          (0x0020)
2041 
 
2042 
#define RT1IP_0                (0x0000)       /* RTC Prescale Timer 1 Interrupt Interval /2 */
2043 
#define RT1IP_1                (0x0004)       /* RTC Prescale Timer 1 Interrupt Interval /4 */
2044 
#define RT1IP_2                (0x0008)       /* RTC Prescale Timer 1 Interrupt Interval /8 */
2045 
#define RT1IP_3                (0x000C)       /* RTC Prescale Timer 1 Interrupt Interval /16 */
2046 
#define RT1IP_4                (0x0010)       /* RTC Prescale Timer 1 Interrupt Interval /32 */
2047 
#define RT1IP_5                (0x0014)       /* RTC Prescale Timer 1 Interrupt Interval /64 */
2048 
#define RT1IP_6                (0x0018)       /* RTC Prescale Timer 1 Interrupt Interval /128 */
2049 
#define RT1IP_7                (0x001C)       /* RTC Prescale Timer 1 Interrupt Interval /256 */
2050 
 
2051 
#define RT1PSDIV_0             (0x0000)       /* RTC Prescale Timer 1 Clock Divide /2 */
2052 
#define RT1PSDIV_1             (0x0800)       /* RTC Prescale Timer 1 Clock Divide /4 */
2053 
#define RT1PSDIV_2             (0x1000)       /* RTC Prescale Timer 1 Clock Divide /8 */
2054 
#define RT1PSDIV_3             (0x1800)       /* RTC Prescale Timer 1 Clock Divide /16 */
2055 
#define RT1PSDIV_4             (0x2000)       /* RTC Prescale Timer 1 Clock Divide /32 */
2056 
#define RT1PSDIV_5             (0x2800)       /* RTC Prescale Timer 1 Clock Divide /64 */
2057 
#define RT1PSDIV_6             (0x3000)       /* RTC Prescale Timer 1 Clock Divide /128 */
2058 
#define RT1PSDIV_7             (0x3800)       /* RTC Prescale Timer 1 Clock Divide /256 */
2059 
 
2060 
#define RT1SSEL_0              (0x0000)       /* RTC Prescale Timer Source Select ACLK */
2061 
#define RT1SSEL_1              (0x4000)       /* RTC Prescale Timer Source Select SMCLK */
2062 
#define RT1SSEL_2              (0x8000)       /* RTC Prescale Timer Source Select RT0PS */
2063 
#define RT1SSEL_3              (0xC000)       /* RTC Prescale Timer Source Select RT0PS */
2064 
 
2065 
/* RTC Definitions */
2066 
#define RTCIV_NONE             (0x0000)       /* No Interrupt pending */
2067 
#define RTCIV_RTCRDYIFG        (0x0002)       /* RTC ready: RTCRDYIFG */
2068 
#define RTCIV_RTCTEVIFG        (0x0004)       /* RTC interval timer: RTCTEVIFG */
2069 
#define RTCIV_RTCAIFG          (0x0006)       /* RTC user alarm: RTCAIFG */
2070 
#define RTCIV_RT0PSIFG         (0x0008)       /* RTC prescaler 0: RT0PSIFG */
2071 
#define RTCIV_RT1PSIFG         (0x000A)       /* RTC prescaler 1: RT1PSIFG */
2072 
 
2073 
/* Legacy Definitions */
2074 
#define RTC_NONE               (0x0000)       /* No Interrupt pending */
2075 
#define RTC_RTCRDYIFG          (0x0002)       /* RTC ready: RTCRDYIFG */
2076 
#define RTC_RTCTEVIFG          (0x0004)       /* RTC interval timer: RTCTEVIFG */
2077 
#define RTC_RTCAIFG            (0x0006)       /* RTC user alarm: RTCAIFG */
2078 
#define RTC_RT0PSIFG           (0x0008)       /* RTC prescaler 0: RT0PSIFG */
2079 
#define RTC_RT1PSIFG           (0x000A)       /* RTC prescaler 1: RT1PSIFG */
2080 
 
2081 
/************************************************************
2082 
* SFR - Special Function Register Module
2083 
************************************************************/
2084 
#define __MSP430_HAS_SFR__                    /* Definition to show that Module is available */
2085 
#define __MSP430_BASEADDRESS_SFR__ 0x0100
2086 
 
2087 
SFR_16BIT(SFRIE1);                            /* Interrupt Enable 1 */
2088 
SFR_8BIT(SFRIE1_L);                           /* Interrupt Enable 1 */
2089 
SFR_8BIT(SFRIE1_H);                           /* Interrupt Enable 1 */
2090 
 
2091 
/* SFRIE1 Control Bits */
2092 
#define WDTIE                  (0x0001)       /* WDT Interrupt Enable */
2093 
#define OFIE                   (0x0002)       /* Osc Fault Enable */
2094 
//#define Reserved          (0x0004)
2095 
#define VMAIE                  (0x0008)       /* Vacant Memory Interrupt Enable */
2096 
#define NMIIE                  (0x0010)       /* NMI Interrupt Enable */
2097 
#define ACCVIE                 (0x0020)       /* Flash Access Violation Interrupt Enable */
2098 
#define JMBINIE                (0x0040)       /* JTAG Mail Box input Interrupt Enable */
2099 
#define JMBOUTIE               (0x0080)       /* JTAG Mail Box output Interrupt Enable */
2100 
 
2101 
#define WDTIE_L                (0x0001)       /* WDT Interrupt Enable */
2102 
#define OFIE_L                 (0x0002)       /* Osc Fault Enable */
2103 
//#define Reserved          (0x0004)
2104 
#define VMAIE_L                (0x0008)       /* Vacant Memory Interrupt Enable */
2105 
#define NMIIE_L                (0x0010)       /* NMI Interrupt Enable */
2106 
#define ACCVIE_L               (0x0020)       /* Flash Access Violation Interrupt Enable */
2107 
#define JMBINIE_L              (0x0040)       /* JTAG Mail Box input Interrupt Enable */
2108 
#define JMBOUTIE_L             (0x0080)       /* JTAG Mail Box output Interrupt Enable */
2109 
 
2110 
//#define Reserved          (0x0004)
2111 
 
2112 
SFR_16BIT(SFRIFG1);                           /* Interrupt Flag 1 */
2113 
SFR_8BIT(SFRIFG1_L);                          /* Interrupt Flag 1 */
2114 
SFR_8BIT(SFRIFG1_H);                          /* Interrupt Flag 1 */
2115 
/* SFRIFG1 Control Bits */
2116 
#define WDTIFG                 (0x0001)       /* WDT Interrupt Flag */
2117 
#define OFIFG                  (0x0002)       /* Osc Fault Flag */
2118 
//#define Reserved          (0x0004)
2119 
#define VMAIFG                 (0x0008)       /* Vacant Memory Interrupt Flag */
2120 
#define NMIIFG                 (0x0010)       /* NMI Interrupt Flag */
2121 
//#define Reserved          (0x0020)
2122 
#define JMBINIFG               (0x0040)       /* JTAG Mail Box input Interrupt Flag */
2123 
#define JMBOUTIFG              (0x0080)       /* JTAG Mail Box output Interrupt Flag */
2124 
 
2125 
#define WDTIFG_L               (0x0001)       /* WDT Interrupt Flag */
2126 
#define OFIFG_L                (0x0002)       /* Osc Fault Flag */
2127 
//#define Reserved          (0x0004)
2128 
#define VMAIFG_L               (0x0008)       /* Vacant Memory Interrupt Flag */
2129 
#define NMIIFG_L               (0x0010)       /* NMI Interrupt Flag */
2130 
//#define Reserved          (0x0020)
2131 
#define JMBINIFG_L             (0x0040)       /* JTAG Mail Box input Interrupt Flag */
2132 
#define JMBOUTIFG_L            (0x0080)       /* JTAG Mail Box output Interrupt Flag */
2133 
 
2134 
//#define Reserved          (0x0004)
2135 
//#define Reserved          (0x0020)
2136 
 
2137 
SFR_16BIT(SFRRPCR);                           /* RESET Pin Control Register */
2138 
SFR_8BIT(SFRRPCR_L);                          /* RESET Pin Control Register */
2139 
SFR_8BIT(SFRRPCR_H);                          /* RESET Pin Control Register */
2140 
/* SFRRPCR Control Bits */
2141 
#define SYSNMI                 (0x0001)       /* NMI select */
2142 
#define SYSNMIIES              (0x0002)       /* NMI edge select */
2143 
#define SYSRSTUP               (0x0004)       /* RESET Pin pull down/up select */
2144 
#define SYSRSTRE               (0x0008)       /* RESET Pin Resistor enable */
2145 
 
2146 
#define SYSNMI_L               (0x0001)       /* NMI select */
2147 
#define SYSNMIIES_L            (0x0002)       /* NMI edge select */
2148 
#define SYSRSTUP_L             (0x0004)       /* RESET Pin pull down/up select */
2149 
#define SYSRSTRE_L             (0x0008)       /* RESET Pin Resistor enable */
2150 
 
2151 
/************************************************************
2152 
* SYS - System Module
2153 
************************************************************/
2154 
#define __MSP430_HAS_SYS__                    /* Definition to show that Module is available */
2155 
#define __MSP430_BASEADDRESS_SYS__ 0x0180
2156 
 
2157 
SFR_16BIT(SYSCTL);                            /* System control */
2158 
SFR_8BIT(SYSCTL_L);                           /* System control */
2159 
SFR_8BIT(SYSCTL_H);                           /* System control */
2160 
SFR_16BIT(SYSBSLC);                           /* Boot strap configuration area */
2161 
SFR_8BIT(SYSBSLC_L);                          /* Boot strap configuration area */
2162 
SFR_8BIT(SYSBSLC_H);                          /* Boot strap configuration area */
2163 
SFR_16BIT(SYSJMBC);                           /* JTAG mailbox control */
2164 
SFR_8BIT(SYSJMBC_L);                          /* JTAG mailbox control */
2165 
SFR_8BIT(SYSJMBC_H);                          /* JTAG mailbox control */
2166 
SFR_16BIT(SYSJMBI0);                          /* JTAG mailbox input 0 */
2167 
SFR_8BIT(SYSJMBI0_L);                         /* JTAG mailbox input 0 */
2168 
SFR_8BIT(SYSJMBI0_H);                         /* JTAG mailbox input 0 */
2169 
SFR_16BIT(SYSJMBI1);                          /* JTAG mailbox input 1 */
2170 
SFR_8BIT(SYSJMBI1_L);                         /* JTAG mailbox input 1 */
2171 
SFR_8BIT(SYSJMBI1_H);                         /* JTAG mailbox input 1 */
2172 
SFR_16BIT(SYSJMBO0);                          /* JTAG mailbox output 0 */
2173 
SFR_8BIT(SYSJMBO0_L);                         /* JTAG mailbox output 0 */
2174 
SFR_8BIT(SYSJMBO0_H);                         /* JTAG mailbox output 0 */
2175 
SFR_16BIT(SYSJMBO1);                          /* JTAG mailbox output 1 */
2176 
SFR_8BIT(SYSJMBO1_L);                         /* JTAG mailbox output 1 */
2177 
SFR_8BIT(SYSJMBO1_H);                         /* JTAG mailbox output 1 */
2178 
 
2179 
SFR_16BIT(SYSBERRIV);                         /* Bus Error vector generator */
2180 
SFR_8BIT(SYSBERRIV_L);                        /* Bus Error vector generator */
2181 
SFR_8BIT(SYSBERRIV_H);                        /* Bus Error vector generator */
2182 
SFR_16BIT(SYSUNIV);                           /* User NMI vector generator */
2183 
SFR_8BIT(SYSUNIV_L);                          /* User NMI vector generator */
2184 
SFR_8BIT(SYSUNIV_H);                          /* User NMI vector generator */
2185 
SFR_16BIT(SYSSNIV);                           /* System NMI vector generator */
2186 
SFR_8BIT(SYSSNIV_L);                          /* System NMI vector generator */
2187 
SFR_8BIT(SYSSNIV_H);                          /* System NMI vector generator */
2188 
SFR_16BIT(SYSRSTIV);                          /* Reset vector generator */
2189 
SFR_8BIT(SYSRSTIV_L);                         /* Reset vector generator */
2190 
SFR_8BIT(SYSRSTIV_H);                         /* Reset vector generator */
2191 
 
2192 
/* SYSCTL Control Bits */
2193 
#define SYSRIVECT              (0x0001)       /* SYS - RAM based interrupt vectors */
2194 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2195 
#define SYSPMMPE               (0x0004)       /* SYS - PMM access protect */
2196 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2197 
#define SYSBSLIND              (0x0010)       /* SYS - TCK/RST indication detected */
2198 
#define SYSJTAGPIN             (0x0020)       /* SYS - Dedicated JTAG pins enabled */
2199 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2200 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2201 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2202 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2203 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2204 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2205 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2206 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2207 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2208 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2209 
 
2210 
/* SYSCTL Control Bits */
2211 
#define SYSRIVECT_L            (0x0001)       /* SYS - RAM based interrupt vectors */
2212 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2213 
#define SYSPMMPE_L             (0x0004)       /* SYS - PMM access protect */
2214 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2215 
#define SYSBSLIND_L            (0x0010)       /* SYS - TCK/RST indication detected */
2216 
#define SYSJTAGPIN_L           (0x0020)       /* SYS - Dedicated JTAG pins enabled */
2217 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2218 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2219 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2220 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2221 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2222 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2223 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2224 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2225 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2226 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2227 
 
2228 
/* SYSCTL Control Bits */
2229 
//#define RESERVED            (0x0002)  /* SYS - Reserved */
2230 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2231 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2232 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2233 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2234 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2235 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2236 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2237 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2238 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2239 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2240 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2241 
 
2242 
/* SYSBSLC Control Bits */
2243 
#define SYSBSLSIZE0            (0x0001)       /* SYS - BSL Protection Size 0 */
2244 
#define SYSBSLSIZE1            (0x0002)       /* SYS - BSL Protection Size 1 */
2245 
#define SYSBSLR                (0x0004)       /* SYS - RAM assigned to BSL */
2246 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2247 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
2248 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2249 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2250 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2251 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2252 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2253 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2254 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2255 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2256 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2257 
#define SYSBSLOFF              (0x4000)       /* SYS - BSL Memeory disabled */
2258 
#define SYSBSLPE               (0x8000)       /* SYS - BSL Memory protection enabled */
2259 
 
2260 
/* SYSBSLC Control Bits */
2261 
#define SYSBSLSIZE0_L          (0x0001)       /* SYS - BSL Protection Size 0 */
2262 
#define SYSBSLSIZE1_L          (0x0002)       /* SYS - BSL Protection Size 1 */
2263 
#define SYSBSLR_L              (0x0004)       /* SYS - RAM assigned to BSL */
2264 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2265 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
2266 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2267 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2268 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2269 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2270 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2271 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2272 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2273 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2274 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2275 
 
2276 
/* SYSBSLC Control Bits */
2277 
//#define RESERVED            (0x0008)  /* SYS - Reserved */
2278 
//#define RESERVED            (0x0010)  /* SYS - Reserved */
2279 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2280 
//#define RESERVED            (0x0040)  /* SYS - Reserved */
2281 
//#define RESERVED            (0x0080)  /* SYS - Reserved */
2282 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2283 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2284 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2285 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2286 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2287 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2288 
#define SYSBSLOFF_H            (0x0040)       /* SYS - BSL Memeory disabled */
2289 
#define SYSBSLPE_H             (0x0080)       /* SYS - BSL Memory protection enabled */
2290 
 
2291 
/* SYSJMBC Control Bits */
2292 
#define JMBIN0FG               (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
2293 
#define JMBIN1FG               (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
2294 
#define JMBOUT0FG              (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
2295 
#define JMBOUT1FG              (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
2296 
#define JMBMODE                (0x0010)       /* SYS - JMB 16/32 Bit Mode */
2297 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2298 
#define JMBCLR0OFF             (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
2299 
#define JMBCLR1OFF             (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
2300 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2301 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2302 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2303 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2304 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2305 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2306 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2307 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2308 
 
2309 
/* SYSJMBC Control Bits */
2310 
#define JMBIN0FG_L             (0x0001)       /* SYS - Incoming JTAG Mailbox 0 Flag */
2311 
#define JMBIN1FG_L             (0x0002)       /* SYS - Incoming JTAG Mailbox 1 Flag */
2312 
#define JMBOUT0FG_L            (0x0004)       /* SYS - Outgoing JTAG Mailbox 0 Flag */
2313 
#define JMBOUT1FG_L            (0x0008)       /* SYS - Outgoing JTAG Mailbox 1 Flag */
2314 
#define JMBMODE_L              (0x0010)       /* SYS - JMB 16/32 Bit Mode */
2315 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2316 
#define JMBCLR0OFF_L           (0x0040)       /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
2317 
#define JMBCLR1OFF_L           (0x0080)       /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
2318 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2319 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2320 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2321 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2322 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2323 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2324 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2325 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2326 
 
2327 
/* SYSJMBC Control Bits */
2328 
//#define RESERVED            (0x0020)  /* SYS - Reserved */
2329 
//#define RESERVED            (0x0100)  /* SYS - Reserved */
2330 
//#define RESERVED            (0x0200)  /* SYS - Reserved */
2331 
//#define RESERVED            (0x0400)  /* SYS - Reserved */
2332 
//#define RESERVED            (0x0800)  /* SYS - Reserved */
2333 
//#define RESERVED            (0x1000)  /* SYS - Reserved */
2334 
//#define RESERVED            (0x2000)  /* SYS - Reserved */
2335 
//#define RESERVED            (0x4000)  /* SYS - Reserved */
2336 
//#define RESERVED            (0x8000)  /* SYS - Reserved */
2337 
 
2338 
/* SYSUNIV Definitions */
2339 
#define SYSUNIV_NONE           (0x0000)       /* No Interrupt pending */
2340 
#define SYSUNIV_NMIIFG         (0x0002)       /* SYSUNIV : NMIIFG */
2341 
#define SYSUNIV_OFIFG          (0x0004)       /* SYSUNIV : Osc. Fail - OFIFG */
2342 
#define SYSUNIV_ACCVIFG        (0x0006)       /* SYSUNIV : Access Violation - ACCVIFG */
2343 
#define SYSUNIV_SYSBERRIV      (0x0008)       /* SYSUNIV : Bus Error - SYSBERRIV */
2344 
 
2345 
/* SYSSNIV Definitions */
2346 
#define SYSSNIV_NONE           (0x0000)       /* No Interrupt pending */
2347 
#define SYSSNIV_SVMLIFG        (0x0002)       /* SYSSNIV : SVMLIFG */
2348 
#define SYSSNIV_SVMHIFG        (0x0004)       /* SYSSNIV : SVMHIFG */
2349 
#define SYSSNIV_DLYLIFG        (0x0006)       /* SYSSNIV : DLYLIFG */
2350 
#define SYSSNIV_DLYHIFG        (0x0008)       /* SYSSNIV : DLYHIFG */
2351 
#define SYSSNIV_VMAIFG         (0x000A)       /* SYSSNIV : VMAIFG */
2352 
#define SYSSNIV_JMBINIFG       (0x000C)       /* SYSSNIV : JMBINIFG */
2353 
#define SYSSNIV_JMBOUTIFG      (0x000E)       /* SYSSNIV : JMBOUTIFG */
2354 
#define SYSSNIV_VLRLIFG        (0x0010)       /* SYSSNIV : VLRLIFG */
2355 
#define SYSSNIV_VLRHIFG        (0x0012)       /* SYSSNIV : VLRHIFG */
2356 
 
2357 
/* SYSRSTIV Definitions */
2358 
#define SYSRSTIV_NONE          (0x0000)       /* No Interrupt pending */
2359 
#define SYSRSTIV_BOR           (0x0002)       /* SYSRSTIV : BOR */
2360 
#define SYSRSTIV_RSTNMI        (0x0004)       /* SYSRSTIV : RST/NMI */
2361 
#define SYSRSTIV_DOBOR         (0x0006)       /* SYSRSTIV : Do BOR */
2362 
#define SYSRSTIV_LPM5WU        (0x0008)       /* SYSRSTIV : Port LPM5 Wake Up */
2363 
#define SYSRSTIV_SECYV         (0x000A)       /* SYSRSTIV : Security violation */
2364 
#define SYSRSTIV_SVSL          (0x000C)       /* SYSRSTIV : SVSL */
2365 
#define SYSRSTIV_SVSH          (0x000E)       /* SYSRSTIV : SVSH */
2366 
#define SYSRSTIV_SVML_OVP      (0x0010)       /* SYSRSTIV : SVML_OVP */
2367 
#define SYSRSTIV_SVMH_OVP      (0x0012)       /* SYSRSTIV : SVMH_OVP */
2368 
#define SYSRSTIV_DOPOR         (0x0014)       /* SYSRSTIV : Do POR */
2369 
#define SYSRSTIV_WDTTO         (0x0016)       /* SYSRSTIV : WDT Time out */
2370 
#define SYSRSTIV_WDTKEY        (0x0018)       /* SYSRSTIV : WDTKEY violation */
2371 
#define SYSRSTIV_KEYV          (0x001A)       /* SYSRSTIV : Flash Key violation */
2372 
#define SYSRSTIV_PLLUL         (0x001C)       /* SYSRSTIV : PLL unlock */
2373 
#define SYSRSTIV_PERF          (0x001E)       /* SYSRSTIV : peripheral/config area fetch */
2374 
#define SYSRSTIV_PMMKEY        (0x0020)       /* SYSRSTIV : PMMKEY violation */
2375 
 
2376 
#define SYSRSTIV_PSSKEY        (0x0020)       /* SYSRSTIV : Legacy: PMMKEY violation */
2377 
 
2378 
/************************************************************
2379 
* Timer0_A5
2380 
************************************************************/
2381 
#define __MSP430_HAS_T0A5__                   /* Definition to show that Module is available */
2382 
#define __MSP430_BASEADDRESS_T0A5__ 0x0340
2383 
 
2384 
SFR_16BIT(TA0CTL);                            /* Timer0_A5 Control */
2385 
SFR_16BIT(TA0CCTL0);                          /* Timer0_A5 Capture/Compare Control 0 */
2386 
SFR_16BIT(TA0CCTL1);                          /* Timer0_A5 Capture/Compare Control 1 */
2387 
SFR_16BIT(TA0CCTL2);                          /* Timer0_A5 Capture/Compare Control 2 */
2388 
SFR_16BIT(TA0CCTL3);                          /* Timer0_A5 Capture/Compare Control 3 */
2389 
SFR_16BIT(TA0CCTL4);                          /* Timer0_A5 Capture/Compare Control 4 */
2390 
SFR_16BIT(TA0R);                              /* Timer0_A5 */
2391 
SFR_16BIT(TA0CCR0);                           /* Timer0_A5 Capture/Compare 0 */
2392 
SFR_16BIT(TA0CCR1);                           /* Timer0_A5 Capture/Compare 1 */
2393 
SFR_16BIT(TA0CCR2);                           /* Timer0_A5 Capture/Compare 2 */
2394 
SFR_16BIT(TA0CCR3);                           /* Timer0_A5 Capture/Compare 3 */
2395 
SFR_16BIT(TA0CCR4);                           /* Timer0_A5 Capture/Compare 4 */
2396 
SFR_16BIT(TA0IV);                             /* Timer0_A5 Interrupt Vector Word */
2397 
SFR_16BIT(TA0EX0);                            /* Timer0_A5 Expansion Register 0 */
2398 
 
2399 
/* TAxCTL Control Bits */
2400 
#define TASSEL1                (0x0200)       /* Timer A clock source select 0 */
2401 
#define TASSEL0                (0x0100)       /* Timer A clock source select 1 */
2402 
#define ID1                    (0x0080)       /* Timer A clock input divider 1 */
2403 
#define ID0                    (0x0040)       /* Timer A clock input divider 0 */
2404 
#define MC1                    (0x0020)       /* Timer A mode control 1 */
2405 
#define MC0                    (0x0010)       /* Timer A mode control 0 */
2406 
#define TACLR                  (0x0004)       /* Timer A counter clear */
2407 
#define TAIE                   (0x0002)       /* Timer A counter interrupt enable */
2408 
#define TAIFG                  (0x0001)       /* Timer A counter interrupt flag */
2409 
 
2410 
#define MC_0                   (0*0x10u)      /* Timer A mode control: 0 - Stop */
2411 
#define MC_1                   (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
2412 
#define MC_2                   (2*0x10u)      /* Timer A mode control: 2 - Continous up */
2413 
#define MC_3                   (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
2414 
#define ID_0                   (0*0x40u)      /* Timer A input divider: 0 - /1 */
2415 
#define ID_1                   (1*0x40u)      /* Timer A input divider: 1 - /2 */
2416 
#define ID_2                   (2*0x40u)      /* Timer A input divider: 2 - /4 */
2417 
#define ID_3                   (3*0x40u)      /* Timer A input divider: 3 - /8 */
2418 
#define TASSEL_0               (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
2419 
#define TASSEL_1               (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
2420 
#define TASSEL_2               (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
2421 
#define TASSEL_3               (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
2422 
#define MC__STOP               (0*0x10u)      /* Timer A mode control: 0 - Stop */
2423 
#define MC__UP                 (1*0x10u)      /* Timer A mode control: 1 - Up to CCR0 */
2424 
#define MC__CONTINOUS          (2*0x10u)      /* Timer A mode control: 2 - Continous up */
2425 
#define MC__UPDOWN             (3*0x10u)      /* Timer A mode control: 3 - Up/Down */
2426 
#define ID__1                  (0*0x40u)      /* Timer A input divider: 0 - /1 */
2427 
#define ID__2                  (1*0x40u)      /* Timer A input divider: 1 - /2 */
2428 
#define ID__4                  (2*0x40u)      /* Timer A input divider: 2 - /4 */
2429 
#define ID__8                  (3*0x40u)      /* Timer A input divider: 3 - /8 */
2430 
#define TASSEL__TACLK          (0*0x100u)     /* Timer A clock source select: 0 - TACLK */
2431 
#define TASSEL__ACLK           (1*0x100u)     /* Timer A clock source select: 1 - ACLK  */
2432 
#define TASSEL__SMCLK          (2*0x100u)     /* Timer A clock source select: 2 - SMCLK */
2433 
#define TASSEL__INCLK          (3*0x100u)     /* Timer A clock source select: 3 - INCLK */
2434 
 
2435 
/* TAxCCTLx Control Bits */
2436 
#define CM1                    (0x8000)       /* Capture mode 1 */
2437 
#define CM0                    (0x4000)       /* Capture mode 0 */
2438 
#define CCIS1                  (0x2000)       /* Capture input select 1 */
2439 
#define CCIS0                  (0x1000)       /* Capture input select 0 */
2440 
#define SCS                    (0x0800)       /* Capture sychronize */
2441 
#define SCCI                   (0x0400)       /* Latched capture signal (read) */
2442 
#define CAP                    (0x0100)       /* Capture mode: 1 /Compare mode : 0 */
2443 
#define OUTMOD2                (0x0080)       /* Output mode 2 */
2444 
#define OUTMOD1                (0x0040)       /* Output mode 1 */
2445 
#define OUTMOD0                (0x0020)       /* Output mode 0 */
2446 
#define CCIE                   (0x0010)       /* Capture/compare interrupt enable */
2447 
#define CCI                    (0x0008)       /* Capture input signal (read) */
2448 
#define OUT                    (0x0004)       /* PWM Output signal if output mode 0 */
2449 
#define COV                    (0x0002)       /* Capture/compare overflow flag */
2450 
#define CCIFG                  (0x0001)       /* Capture/compare interrupt flag */
2451 
 
2452 
#define OUTMOD_0               (0*0x20u)      /* PWM output mode: 0 - output only */
2453 
#define OUTMOD_1               (1*0x20u)      /* PWM output mode: 1 - set */
2454 
#define OUTMOD_2               (2*0x20u)      /* PWM output mode: 2 - PWM toggle/reset */
2455 
#define OUTMOD_3               (3*0x20u)      /* PWM output mode: 3 - PWM set/reset */
2456 
#define OUTMOD_4               (4*0x20u)      /* PWM output mode: 4 - toggle */
2457 
#define OUTMOD_5               (5*0x20u)      /* PWM output mode: 5 - Reset */
2458 
#define OUTMOD_6               (6*0x20u)      /* PWM output mode: 6 - PWM toggle/set */
2459 
#define OUTMOD_7               (7*0x20u)      /* PWM output mode: 7 - PWM reset/set */
2460 
#define CCIS_0                 (0*0x1000u)    /* Capture input select: 0 - CCIxA */
2461 
#define CCIS_1                 (1*0x1000u)    /* Capture input select: 1 - CCIxB */
2462 
#define CCIS_2                 (2*0x1000u)    /* Capture input select: 2 - GND */
2463 
#define CCIS_3                 (3*0x1000u)    /* Capture input select: 3 - Vcc */
2464 
#define CM_0                   (0*0x4000u)    /* Capture mode: 0 - disabled */
2465 
#define CM_1                   (1*0x4000u)    /* Capture mode: 1 - pos. edge */
2466 
#define CM_2                   (2*0x4000u)    /* Capture mode: 1 - neg. edge */
2467 
#define CM_3                   (3*0x4000u)    /* Capture mode: 1 - both edges */
2468 
 
2469 
/* TAxEX0 Control Bits */
2470 
#define TAIDEX0                (0x0001)       /* Timer A Input divider expansion Bit: 0 */
2471 
#define TAIDEX1                (0x0002)       /* Timer A Input divider expansion Bit: 1 */
2472 
#define TAIDEX2                (0x0004)       /* Timer A Input divider expansion Bit: 2 */
2473 
 
2474 
#define TAIDEX_0               (0*0x0001u)    /* Timer A Input divider expansion : /1 */
2475 
#define TAIDEX_1               (1*0x0001u)    /* Timer A Input divider expansion : /2 */
2476 
#define TAIDEX_2               (2*0x0001u)    /* Timer A Input divider expansion : /3 */
2477 
#define TAIDEX_3               (3*0x0001u)    /* Timer A Input divider expansion : /4 */
2478 
#define TAIDEX_4               (4*0x0001u)    /* Timer A Input divider expansion : /5 */
2479 
#define TAIDEX_5               (5*0x0001u)    /* Timer A Input divider expansion : /6 */
2480 
#define TAIDEX_6               (6*0x0001u)    /* Timer A Input divider expansion : /7 */
2481 
#define TAIDEX_7               (7*0x0001u)    /* Timer A Input divider expansion : /8 */
2482 
 
2483 
/* T0A5IV Definitions */
2484 
#define TA0IV_NONE             (0x0000)       /* No Interrupt pending */
2485 
#define TA0IV_TA0CCR1          (0x0002)       /* TA0CCR1_CCIFG */
2486 
#define TA0IV_TA0CCR2          (0x0004)       /* TA0CCR2_CCIFG */
2487 
#define TA0IV_TA0CCR3          (0x0006)       /* TA0CCR3_CCIFG */
2488 
#define TA0IV_TA0CCR4          (0x0008)       /* TA0CCR4_CCIFG */
2489 
#define TA0IV_5                (0x000A)       /* Reserved */
2490 
#define TA0IV_6                (0x000C)       /* Reserved */
2491 
#define TA0IV_TA0IFG           (0x000E)       /* TA0IFG */
2492 
 
2493 
/************************************************************
2494 
* Timer1_A3
2495 
************************************************************/
2496 
#define __MSP430_HAS_T1A3__                   /* Definition to show that Module is available */
2497 
#define __MSP430_BASEADDRESS_T1A3__ 0x0380
2498 
 
2499 
SFR_16BIT(TA1CTL);                            /* Timer1_A3 Control */
2500 
SFR_16BIT(TA1CCTL0);                          /* Timer1_A3 Capture/Compare Control 0 */
2501 
SFR_16BIT(TA1CCTL1);                          /* Timer1_A3 Capture/Compare Control 1 */
2502 
SFR_16BIT(TA1CCTL2);                          /* Timer1_A3 Capture/Compare Control 2 */
2503 
SFR_16BIT(TA1R);                              /* Timer1_A3 */
2504 
SFR_16BIT(TA1CCR0);                           /* Timer1_A3 Capture/Compare 0 */
2505 
SFR_16BIT(TA1CCR1);                           /* Timer1_A3 Capture/Compare 1 */
2506 
SFR_16BIT(TA1CCR2);                           /* Timer1_A3 Capture/Compare 2 */
2507 
SFR_16BIT(TA1IV);                             /* Timer1_A3 Interrupt Vector Word */
2508 
SFR_16BIT(TA1EX0);                            /* Timer1_A3 Expansion Register 0 */
2509 
 
2510 
/* Bits are already defined within the Timer0_Ax */
2511 
 
2512 
/* TA1IV Definitions */
2513 
#define TA1IV_NONE             (0x0000)       /* No Interrupt pending */
2514 
#define TA1IV_TA1CCR1          (0x0002)       /* TA1CCR1_CCIFG */
2515 
#define TA1IV_TA1CCR2          (0x0004)       /* TA1CCR2_CCIFG */
2516 
#define TA1IV_3                (0x0006)       /* Reserved */
2517 
#define TA1IV_4                (0x0008)       /* Reserved */
2518 
#define TA1IV_5                (0x000A)       /* Reserved */
2519 
#define TA1IV_6                (0x000C)       /* Reserved */
2520 
#define TA1IV_TA1IFG           (0x000E)       /* TA1IFG */
2521 
 
2522 
/************************************************************
2523 
* Timer0_B7
2524 
************************************************************/
2525 
#define __MSP430_HAS_T0B7__                   /* Definition to show that Module is available */
2526 
#define __MSP430_BASEADDRESS_T0B7__ 0x03C0
2527 
 
2528 
SFR_16BIT(TB0CTL);                            /* Timer0_B7 Control */
2529 
SFR_16BIT(TB0CCTL0);                          /* Timer0_B7 Capture/Compare Control 0 */
2530 
SFR_16BIT(TB0CCTL1);                          /* Timer0_B7 Capture/Compare Control 1 */
2531 
SFR_16BIT(TB0CCTL2);                          /* Timer0_B7 Capture/Compare Control 2 */
2532 
SFR_16BIT(TB0CCTL3);                          /* Timer0_B7 Capture/Compare Control 3 */
2533 
SFR_16BIT(TB0CCTL4);                          /* Timer0_B7 Capture/Compare Control 4 */
2534 
SFR_16BIT(TB0CCTL5);                          /* Timer0_B7 Capture/Compare Control 5 */
2535 
SFR_16BIT(TB0CCTL6);                          /* Timer0_B7 Capture/Compare Control 6 */
2536 
SFR_16BIT(TB0R);                              /* Timer0_B7 */
2537 
SFR_16BIT(TB0CCR0);                           /* Timer0_B7 Capture/Compare 0 */
2538 
SFR_16BIT(TB0CCR1);                           /* Timer0_B7 Capture/Compare 1 */
2539 
SFR_16BIT(TB0CCR2);                           /* Timer0_B7 Capture/Compare 2 */
2540 
SFR_16BIT(TB0CCR3);                           /* Timer0_B7 Capture/Compare 3 */
2541 
SFR_16BIT(TB0CCR4);                           /* Timer0_B7 Capture/Compare 4 */
2542 
SFR_16BIT(TB0CCR5);                           /* Timer0_B7 Capture/Compare 5 */
2543 
SFR_16BIT(TB0CCR6);                           /* Timer0_B7 Capture/Compare 6 */
2544 
SFR_16BIT(TB0EX0);                            /* Timer0_B7 Expansion Register 0 */
2545 
SFR_16BIT(TB0IV);                             /* Timer0_B7 Interrupt Vector Word */
2546 
 
2547 
/* Legacy Type Definitions for TimerB */
2548 
#define TBCTL                  TB0CTL         /* Timer0_B7 Control */
2549 
#define TBCCTL0                TB0CCTL0       /* Timer0_B7 Capture/Compare Control 0 */
2550 
#define TBCCTL1                TB0CCTL1       /* Timer0_B7 Capture/Compare Control 1 */
2551 
#define TBCCTL2                TB0CCTL2       /* Timer0_B7 Capture/Compare Control 2 */
2552 
#define TBCCTL3                TB0CCTL3       /* Timer0_B7 Capture/Compare Control 3 */
2553 
#define TBCCTL4                TB0CCTL4       /* Timer0_B7 Capture/Compare Control 4 */
2554 
#define TBCCTL5                TB0CCTL5       /* Timer0_B7 Capture/Compare Control 5 */
2555 
#define TBCCTL6                TB0CCTL6       /* Timer0_B7 Capture/Compare Control 6 */
2556 
#define TBR                    TB0R           /* Timer0_B7 */
2557 
#define TBCCR0                 TB0CCR0        /* Timer0_B7 Capture/Compare 0 */
2558 
#define TBCCR1                 TB0CCR1        /* Timer0_B7 Capture/Compare 1 */
2559 
#define TBCCR2                 TB0CCR2        /* Timer0_B7 Capture/Compare 2 */
2560 
#define TBCCR3                 TB0CCR3        /* Timer0_B7 Capture/Compare 3 */
2561 
#define TBCCR4                 TB0CCR4        /* Timer0_B7 Capture/Compare 4 */
2562 
#define TBCCR5                 TB0CCR5        /* Timer0_B7 Capture/Compare 5 */
2563 
#define TBCCR6                 TB0CCR6        /* Timer0_B7 Capture/Compare 6 */
2564 
#define TBEX0                  TB0EX0         /* Timer0_B7 Expansion Register 0 */
2565 
#define TBIV                   TB0IV          /* Timer0_B7 Interrupt Vector Word */
2566 
#define TIMERB1_VECTOR       TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
2567 
#define TIMERB0_VECTOR       TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
2568 
 
2569 
/* TBxCTL Control Bits */
2570 
#define TBCLGRP1               (0x4000)       /* Timer0_B7 Compare latch load group 1 */
2571 
#define TBCLGRP0               (0x2000)       /* Timer0_B7 Compare latch load group 0 */
2572 
#define CNTL1                  (0x1000)       /* Counter lenght 1 */
2573 
#define CNTL0                  (0x0800)       /* Counter lenght 0 */
2574 
#define TBSSEL1                (0x0200)       /* Clock source 1 */
2575 
#define TBSSEL0                (0x0100)       /* Clock source 0 */
2576 
#define TBCLR                  (0x0004)       /* Timer0_B7 counter clear */
2577 
#define TBIE                   (0x0002)       /* Timer0_B7 interrupt enable */
2578 
#define TBIFG                  (0x0001)       /* Timer0_B7 interrupt flag */
2579 
 
2580 
#define SHR1                   (0x4000)       /* Timer0_B7 Compare latch load group 1 */
2581 
#define SHR0                   (0x2000)       /* Timer0_B7 Compare latch load group 0 */
2582 
 
2583 
#define TBSSEL_0               (0*0x0100u)    /* Clock Source: TBCLK */
2584 
#define TBSSEL_1               (1*0x0100u)    /* Clock Source: ACLK  */
2585 
#define TBSSEL_2               (2*0x0100u)    /* Clock Source: SMCLK */
2586 
#define TBSSEL_3               (3*0x0100u)    /* Clock Source: INCLK */
2587 
#define CNTL_0                 (0*0x0800u)    /* Counter lenght: 16 bit */
2588 
#define CNTL_1                 (1*0x0800u)    /* Counter lenght: 12 bit */
2589 
#define CNTL_2                 (2*0x0800u)    /* Counter lenght: 10 bit */
2590 
#define CNTL_3                 (3*0x0800u)    /* Counter lenght:  8 bit */
2591 
#define SHR_0                  (0*0x2000u)    /* Timer0_B7 Group: 0 - individually */
2592 
#define SHR_1                  (1*0x2000u)    /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
2593 
#define SHR_2                  (2*0x2000u)    /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
2594 
#define SHR_3                  (3*0x2000u)    /* Timer0_B7 Group: 3 - 1 group (all) */
2595 
#define TBCLGRP_0              (0*0x2000u)    /* Timer0_B7 Group: 0 - individually */
2596 
#define TBCLGRP_1              (1*0x2000u)    /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
2597 
#define TBCLGRP_2              (2*0x2000u)    /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
2598 
#define TBCLGRP_3              (3*0x2000u)    /* Timer0_B7 Group: 3 - 1 group (all) */
2599 
#define TBSSEL__TACLK          (0*0x100u)     /* Timer0_B7 clock source select: 0 - TACLK */
2600 
#define TBSSEL__ACLK           (1*0x100u)     /* Timer0_B7 clock source select: 1 - ACLK  */
2601 
#define TBSSEL__SMCLK          (2*0x100u)     /* Timer0_B7 clock source select: 2 - SMCLK */
2602 
#define TBSSEL__INCLK          (3*0x100u)     /* Timer0_B7 clock source select: 3 - INCLK */
2603 
#define CNTL__16               (0*0x0800u)    /* Counter lenght: 16 bit */
2604 
#define CNTL__12               (1*0x0800u)    /* Counter lenght: 12 bit */
2605 
#define CNTL__10               (2*0x0800u)    /* Counter lenght: 10 bit */
2606 
#define CNTL__8                (3*0x0800u)    /* Counter lenght:  8 bit */
2607 
 
2608 
/* Additional Timer B Control Register bits are defined in Timer A */
2609 
/* TBxCCTLx Control Bits */
2610 
#define CLLD1                  (0x0400)       /* Compare latch load source 1 */
2611 
#define CLLD0                  (0x0200)       /* Compare latch load source 0 */
2612 
 
2613 
#define SLSHR1                 (0x0400)       /* Compare latch load source 1 */
2614 
#define SLSHR0                 (0x0200)       /* Compare latch load source 0 */
2615 
 
2616 
#define SLSHR_0                (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
2617 
#define SLSHR_1                (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
2618 
#define SLSHR_2                (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
2619 
#define SLSHR_3                (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
2620 
 
2621 
#define CLLD_0                 (0*0x0200u)    /* Compare latch load sourec : 0 - immediate */
2622 
#define CLLD_1                 (1*0x0200u)    /* Compare latch load sourec : 1 - TBR counts to 0 */
2623 
#define CLLD_2                 (2*0x0200u)    /* Compare latch load sourec : 2 - up/down */
2624 
#define CLLD_3                 (3*0x0200u)    /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
2625 
 
2626 
/* TBxEX0 Control Bits */
2627 
#define TBIDEX0                (0x0001)       /* Timer0_B7 Input divider expansion Bit: 0 */
2628 
#define TBIDEX1                (0x0002)       /* Timer0_B7 Input divider expansion Bit: 1 */
2629 
#define TBIDEX2                (0x0004)       /* Timer0_B7 Input divider expansion Bit: 2 */
2630 
 
2631 
#define TBIDEX_0               (0*0x0001u)    /* Timer0_B7 Input divider expansion : /1 */
2632 
#define TBIDEX_1               (1*0x0001u)    /* Timer0_B7 Input divider expansion : /2 */
2633 
#define TBIDEX_2               (2*0x0001u)    /* Timer0_B7 Input divider expansion : /3 */
2634 
#define TBIDEX_3               (3*0x0001u)    /* Timer0_B7 Input divider expansion : /4 */
2635 
#define TBIDEX_4               (4*0x0001u)    /* Timer0_B7 Input divider expansion : /5 */
2636 
#define TBIDEX_5               (5*0x0001u)    /* Timer0_B7 Input divider expansion : /6 */
2637 
#define TBIDEX_6               (6*0x0001u)    /* Timer0_B7 Input divider expansion : /7 */
2638 
#define TBIDEX_7               (7*0x0001u)    /* Timer0_B7 Input divider expansion : /8 */
2639 
#define TBIDEX__1              (0*0x0001u)    /* Timer0_B7 Input divider expansion : /1 */
2640 
#define TBIDEX__2              (1*0x0001u)    /* Timer0_B7 Input divider expansion : /2 */
2641 
#define TBIDEX__3              (2*0x0001u)    /* Timer0_B7 Input divider expansion : /3 */
2642 
#define TBIDEX__4              (3*0x0001u)    /* Timer0_B7 Input divider expansion : /4 */
2643 
#define TBIDEX__5              (4*0x0001u)    /* Timer0_B7 Input divider expansion : /5 */
2644 
#define TBIDEX__6              (5*0x0001u)    /* Timer0_B7 Input divider expansion : /6 */
2645 
#define TBIDEX__7              (6*0x0001u)    /* Timer0_B7 Input divider expansion : /7 */
2646 
#define TBIDEX__8              (7*0x0001u)    /* Timer0_B7 Input divider expansion : /8 */
2647 
 
2648 
/* TB0IV Definitions */
2649 
#define TB0IV_NONE             (0x0000)       /* No Interrupt pending */
2650 
#define TB0IV_TB1CCR1          (0x0002)       /* TBCCR1_CCIFG */
2651 
#define TB0IV_TB1CCR2          (0x0004)       /* TBCCR2_CCIFG */
2652 
#define TB0IV_3                (0x0006)       /* Reserved */
2653 
#define TB0IV_4                (0x0008)       /* Reserved */
2654 
#define TB0IV_5                (0x000A)       /* Reserved */
2655 
#define TB0IV_6                (0x000C)       /* Reserved */
2656 
#define TB0IV_TB0IFG           (0x000E)       /* TBIFG */
2657 
 
2658 
 
2659 
/************************************************************
2660 
* UNIFIED CLOCK SYSTEM
2661 
************************************************************/
2662 
#define __MSP430_HAS_UCS__                    /* Definition to show that Module is available */
2663 
#define __MSP430_BASEADDRESS_UCS__ 0x0160
2664 
 
2665 
SFR_16BIT(UCSCTL0);                           /* UCS Control Register 0 */
2666 
SFR_8BIT(UCSCTL0_L);                          /* UCS Control Register 0 */
2667 
SFR_8BIT(UCSCTL0_H);                          /* UCS Control Register 0 */
2668 
SFR_16BIT(UCSCTL1);                           /* UCS Control Register 1 */
2669 
SFR_8BIT(UCSCTL1_L);                          /* UCS Control Register 1 */
2670 
SFR_8BIT(UCSCTL1_H);                          /* UCS Control Register 1 */
2671 
SFR_16BIT(UCSCTL2);                           /* UCS Control Register 2 */
2672 
SFR_8BIT(UCSCTL2_L);                          /* UCS Control Register 2 */
2673 
SFR_8BIT(UCSCTL2_H);                          /* UCS Control Register 2 */
2674 
SFR_16BIT(UCSCTL3);                           /* UCS Control Register 3 */
2675 
SFR_8BIT(UCSCTL3_L);                          /* UCS Control Register 3 */
2676 
SFR_8BIT(UCSCTL3_H);                          /* UCS Control Register 3 */
2677 
SFR_16BIT(UCSCTL4);                           /* UCS Control Register 4 */
2678 
SFR_8BIT(UCSCTL4_L);                          /* UCS Control Register 4 */
2679 
SFR_8BIT(UCSCTL4_H);                          /* UCS Control Register 4 */
2680 
SFR_16BIT(UCSCTL5);                           /* UCS Control Register 5 */
2681 
SFR_8BIT(UCSCTL5_L);                          /* UCS Control Register 5 */
2682 
SFR_8BIT(UCSCTL5_H);                          /* UCS Control Register 5 */
2683 
SFR_16BIT(UCSCTL6);                           /* UCS Control Register 6 */
2684 
SFR_8BIT(UCSCTL6_L);                          /* UCS Control Register 6 */
2685 
SFR_8BIT(UCSCTL6_H);                          /* UCS Control Register 6 */
2686 
SFR_16BIT(UCSCTL7);                           /* UCS Control Register 7 */
2687 
SFR_8BIT(UCSCTL7_L);                          /* UCS Control Register 7 */
2688 
SFR_8BIT(UCSCTL7_H);                          /* UCS Control Register 7 */
2689 
SFR_16BIT(UCSCTL8);                           /* UCS Control Register 8 */
2690 
SFR_8BIT(UCSCTL8_L);                          /* UCS Control Register 8 */
2691 
SFR_8BIT(UCSCTL8_H);                          /* UCS Control Register 8 */
2692 
 
2693 
/* UCSCTL0 Control Bits */
2694 
//#define RESERVED            (0x0001)    /* RESERVED */
2695 
//#define RESERVED            (0x0002)    /* RESERVED */
2696 
//#define RESERVED            (0x0004)    /* RESERVED */
2697 
#define MOD0                   (0x0008)       /* Modulation Bit Counter Bit : 0 */
2698 
#define MOD1                   (0x0010)       /* Modulation Bit Counter Bit : 1 */
2699 
#define MOD2                   (0x0020)       /* Modulation Bit Counter Bit : 2 */
2700 
#define MOD3                   (0x0040)       /* Modulation Bit Counter Bit : 3 */
2701 
#define MOD4                   (0x0080)       /* Modulation Bit Counter Bit : 4 */
2702 
#define DCO0                   (0x0100)       /* DCO TAP Bit : 0 */
2703 
#define DCO1                   (0x0200)       /* DCO TAP Bit : 1 */
2704 
#define DCO2                   (0x0400)       /* DCO TAP Bit : 2 */
2705 
#define DCO3                   (0x0800)       /* DCO TAP Bit : 3 */
2706 
#define DCO4                   (0x1000)       /* DCO TAP Bit : 4 */
2707 
//#define RESERVED            (0x2000)    /* RESERVED */
2708 
//#define RESERVED            (0x4000)    /* RESERVED */
2709 
//#define RESERVED            (0x8000)    /* RESERVED */
2710 
 
2711 
/* UCSCTL0 Control Bits */
2712 
//#define RESERVED            (0x0001)    /* RESERVED */
2713 
//#define RESERVED            (0x0002)    /* RESERVED */
2714 
//#define RESERVED            (0x0004)    /* RESERVED */
2715 
#define MOD0_L                 (0x0008)       /* Modulation Bit Counter Bit : 0 */
2716 
#define MOD1_L                 (0x0010)       /* Modulation Bit Counter Bit : 1 */
2717 
#define MOD2_L                 (0x0020)       /* Modulation Bit Counter Bit : 2 */
2718 
#define MOD3_L                 (0x0040)       /* Modulation Bit Counter Bit : 3 */
2719 
#define MOD4_L                 (0x0080)       /* Modulation Bit Counter Bit : 4 */
2720 
//#define RESERVED            (0x2000)    /* RESERVED */
2721 
//#define RESERVED            (0x4000)    /* RESERVED */
2722 
//#define RESERVED            (0x8000)    /* RESERVED */
2723 
 
2724 
/* UCSCTL0 Control Bits */
2725 
//#define RESERVED            (0x0001)    /* RESERVED */
2726 
//#define RESERVED            (0x0002)    /* RESERVED */
2727 
//#define RESERVED            (0x0004)    /* RESERVED */
2728 
#define DCO0_H                 (0x0001)       /* DCO TAP Bit : 0 */
2729 
#define DCO1_H                 (0x0002)       /* DCO TAP Bit : 1 */
2730 
#define DCO2_H                 (0x0004)       /* DCO TAP Bit : 2 */
2731 
#define DCO3_H                 (0x0008)       /* DCO TAP Bit : 3 */
2732 
#define DCO4_H                 (0x0010)       /* DCO TAP Bit : 4 */
2733 
//#define RESERVED            (0x2000)    /* RESERVED */
2734 
//#define RESERVED            (0x4000)    /* RESERVED */
2735 
//#define RESERVED            (0x8000)    /* RESERVED */
2736 
 
2737 
/* UCSCTL1 Control Bits */
2738 
#define DISMOD                 (0x0001)       /* Disable Modulation */
2739 
//#define RESERVED            (0x0002)    /* RESERVED */
2740 
//#define RESERVED            (0x0004)    /* RESERVED */
2741 
//#define RESERVED            (0x0008)    /* RESERVED */
2742 
#define DCORSEL0               (0x0010)       /* DCO Freq. Range Select Bit : 0 */
2743 
#define DCORSEL1               (0x0020)       /* DCO Freq. Range Select Bit : 1 */
2744 
#define DCORSEL2               (0x0040)       /* DCO Freq. Range Select Bit : 2 */
2745 
//#define RESERVED            (0x0080)    /* RESERVED */
2746 
//#define RESERVED            (0x0100)    /* RESERVED */
2747 
//#define RESERVED            (0x0200)    /* RESERVED */
2748 
//#define RESERVED            (0x0400)    /* RESERVED */
2749 
//#define RESERVED            (0x0800)    /* RESERVED */
2750 
//#define RESERVED            (0x1000)    /* RESERVED */
2751 
//#define RESERVED            (0x2000)    /* RESERVED */
2752 
//#define RESERVED            (0x4000)    /* RESERVED */
2753 
//#define RESERVED            (0x8000)    /* RESERVED */
2754 
 
2755 
/* UCSCTL1 Control Bits */
2756 
#define DISMOD_L               (0x0001)       /* Disable Modulation */
2757 
//#define RESERVED            (0x0002)    /* RESERVED */
2758 
//#define RESERVED            (0x0004)    /* RESERVED */
2759 
//#define RESERVED            (0x0008)    /* RESERVED */
2760 
#define DCORSEL0_L             (0x0010)       /* DCO Freq. Range Select Bit : 0 */
2761 
#define DCORSEL1_L             (0x0020)       /* DCO Freq. Range Select Bit : 1 */
2762 
#define DCORSEL2_L             (0x0040)       /* DCO Freq. Range Select Bit : 2 */
2763 
//#define RESERVED            (0x0080)    /* RESERVED */
2764 
//#define RESERVED            (0x0100)    /* RESERVED */
2765 
//#define RESERVED            (0x0200)    /* RESERVED */
2766 
//#define RESERVED            (0x0400)    /* RESERVED */
2767 
//#define RESERVED            (0x0800)    /* RESERVED */
2768 
//#define RESERVED            (0x1000)    /* RESERVED */
2769 
//#define RESERVED            (0x2000)    /* RESERVED */
2770 
//#define RESERVED            (0x4000)    /* RESERVED */
2771 
//#define RESERVED            (0x8000)    /* RESERVED */
2772 
 
2773 
/* UCSCTL1 Control Bits */
2774 
//#define RESERVED            (0x0002)    /* RESERVED */
2775 
//#define RESERVED            (0x0004)    /* RESERVED */
2776 
//#define RESERVED            (0x0008)    /* RESERVED */
2777 
//#define RESERVED            (0x0080)    /* RESERVED */
2778 
//#define RESERVED            (0x0100)    /* RESERVED */
2779 
//#define RESERVED            (0x0200)    /* RESERVED */
2780 
//#define RESERVED            (0x0400)    /* RESERVED */
2781 
//#define RESERVED            (0x0800)    /* RESERVED */
2782 
//#define RESERVED            (0x1000)    /* RESERVED */
2783 
//#define RESERVED            (0x2000)    /* RESERVED */
2784 
//#define RESERVED            (0x4000)    /* RESERVED */
2785 
//#define RESERVED            (0x8000)    /* RESERVED */
2786 
 
2787 
#define DCORSEL_0              (0x0000)       /* DCO RSEL 0 */
2788 
#define DCORSEL_1              (0x0010)       /* DCO RSEL 1 */
2789 
#define DCORSEL_2              (0x0020)       /* DCO RSEL 2 */
2790 
#define DCORSEL_3              (0x0030)       /* DCO RSEL 3 */
2791 
#define DCORSEL_4              (0x0040)       /* DCO RSEL 4 */
2792 
#define DCORSEL_5              (0x0050)       /* DCO RSEL 5 */
2793 
#define DCORSEL_6              (0x0060)       /* DCO RSEL 6 */
2794 
#define DCORSEL_7              (0x0070)       /* DCO RSEL 7 */
2795 
 
2796 
/* UCSCTL2 Control Bits */
2797 
#define FLLN0                  (0x0001)       /* FLL Multipier Bit : 0 */
2798 
#define FLLN1                  (0x0002)       /* FLL Multipier Bit : 1 */
2799 
#define FLLN2                  (0x0004)       /* FLL Multipier Bit : 2 */
2800 
#define FLLN3                  (0x0008)       /* FLL Multipier Bit : 3 */
2801 
#define FLLN4                  (0x0010)       /* FLL Multipier Bit : 4 */
2802 
#define FLLN5                  (0x0020)       /* FLL Multipier Bit : 5 */
2803 
#define FLLN6                  (0x0040)       /* FLL Multipier Bit : 6 */
2804 
#define FLLN7                  (0x0080)       /* FLL Multipier Bit : 7 */
2805 
#define FLLN8                  (0x0100)       /* FLL Multipier Bit : 8 */
2806 
#define FLLN9                  (0x0200)       /* FLL Multipier Bit : 9 */
2807 
//#define RESERVED            (0x0400)    /* RESERVED */
2808 
//#define RESERVED            (0x0800)    /* RESERVED */
2809 
#define FLLD0                  (0x1000)       /* Loop Divider Bit : 0 */
2810 
#define FLLD1                  (0x2000)       /* Loop Divider Bit : 1 */
2811 
#define FLLD2                  (0x4000)       /* Loop Divider Bit : 1 */
2812 
//#define RESERVED            (0x8000)    /* RESERVED */
2813 
 
2814 
/* UCSCTL2 Control Bits */
2815 
#define FLLN0_L                (0x0001)       /* FLL Multipier Bit : 0 */
2816 
#define FLLN1_L                (0x0002)       /* FLL Multipier Bit : 1 */
2817 
#define FLLN2_L                (0x0004)       /* FLL Multipier Bit : 2 */
2818 
#define FLLN3_L                (0x0008)       /* FLL Multipier Bit : 3 */
2819 
#define FLLN4_L                (0x0010)       /* FLL Multipier Bit : 4 */
2820 
#define FLLN5_L                (0x0020)       /* FLL Multipier Bit : 5 */
2821 
#define FLLN6_L                (0x0040)       /* FLL Multipier Bit : 6 */
2822 
#define FLLN7_L                (0x0080)       /* FLL Multipier Bit : 7 */
2823 
//#define RESERVED            (0x0400)    /* RESERVED */
2824 
//#define RESERVED            (0x0800)    /* RESERVED */
2825 
//#define RESERVED            (0x8000)    /* RESERVED */
2826 
 
2827 
/* UCSCTL2 Control Bits */
2828 
#define FLLN8_H                (0x0001)       /* FLL Multipier Bit : 8 */
2829 
#define FLLN9_H                (0x0002)       /* FLL Multipier Bit : 9 */
2830 
//#define RESERVED            (0x0400)    /* RESERVED */
2831 
//#define RESERVED            (0x0800)    /* RESERVED */
2832 
#define FLLD0_H                (0x0010)       /* Loop Divider Bit : 0 */
2833 
#define FLLD1_H                (0x0020)       /* Loop Divider Bit : 1 */
2834 
#define FLLD2_H                (0x0040)       /* Loop Divider Bit : 1 */
2835 
//#define RESERVED            (0x8000)    /* RESERVED */
2836 
 
2837 
#define FLLD_0                 (0x0000)       /* Multiply Selected Loop Freq. 1 */
2838 
#define FLLD_1                 (0x1000)       /* Multiply Selected Loop Freq. 2 */
2839 
#define FLLD_2                 (0x2000)       /* Multiply Selected Loop Freq. 4 */
2840 
#define FLLD_3                 (0x3000)       /* Multiply Selected Loop Freq. 8 */
2841 
#define FLLD_4                 (0x4000)       /* Multiply Selected Loop Freq. 16 */
2842 
#define FLLD_5                 (0x5000)       /* Multiply Selected Loop Freq. 32 */
2843 
#define FLLD_6                 (0x6000)       /* Multiply Selected Loop Freq. 32 */
2844 
#define FLLD_7                 (0x7000)       /* Multiply Selected Loop Freq. 32 */
2845 
#define FLLD__1                (0x0000)       /* Multiply Selected Loop Freq. By 1 */
2846 
#define FLLD__2                (0x1000)       /* Multiply Selected Loop Freq. By 2 */
2847 
#define FLLD__4                (0x2000)       /* Multiply Selected Loop Freq. By 4 */
2848 
#define FLLD__8                (0x3000)       /* Multiply Selected Loop Freq. By 8 */
2849 
#define FLLD__16               (0x4000)       /* Multiply Selected Loop Freq. By 16 */
2850 
#define FLLD__32               (0x5000)       /* Multiply Selected Loop Freq. By 32 */
2851 
 
2852 
/* UCSCTL3 Control Bits */
2853 
#define FLLREFDIV0             (0x0001)       /* Reference Divider Bit : 0 */
2854 
#define FLLREFDIV1             (0x0002)       /* Reference Divider Bit : 1 */
2855 
#define FLLREFDIV2             (0x0004)       /* Reference Divider Bit : 2 */
2856 
//#define RESERVED            (0x0008)    /* RESERVED */
2857 
#define SELREF0                (0x0010)       /* FLL Reference Clock Select Bit : 0 */
2858 
#define SELREF1                (0x0020)       /* FLL Reference Clock Select Bit : 1 */
2859 
#define SELREF2                (0x0040)       /* FLL Reference Clock Select Bit : 2 */
2860 
//#define RESERVED            (0x0080)    /* RESERVED */
2861 
//#define RESERVED            (0x0100)    /* RESERVED */
2862 
//#define RESERVED            (0x0200)    /* RESERVED */
2863 
//#define RESERVED            (0x0400)    /* RESERVED */
2864 
//#define RESERVED            (0x0800)    /* RESERVED */
2865 
//#define RESERVED            (0x1000)    /* RESERVED */
2866 
//#define RESERVED            (0x2000)    /* RESERVED */
2867 
//#define RESERVED            (0x4000)    /* RESERVED */
2868 
//#define RESERVED            (0x8000)    /* RESERVED */
2869 
 
2870 
/* UCSCTL3 Control Bits */
2871 
#define FLLREFDIV0_L           (0x0001)       /* Reference Divider Bit : 0 */
2872 
#define FLLREFDIV1_L           (0x0002)       /* Reference Divider Bit : 1 */
2873 
#define FLLREFDIV2_L           (0x0004)       /* Reference Divider Bit : 2 */
2874 
//#define RESERVED            (0x0008)    /* RESERVED */
2875 
#define SELREF0_L              (0x0010)       /* FLL Reference Clock Select Bit : 0 */
2876 
#define SELREF1_L              (0x0020)       /* FLL Reference Clock Select Bit : 1 */
2877 
#define SELREF2_L              (0x0040)       /* FLL Reference Clock Select Bit : 2 */
2878 
//#define RESERVED            (0x0080)    /* RESERVED */
2879 
//#define RESERVED            (0x0100)    /* RESERVED */
2880 
//#define RESERVED            (0x0200)    /* RESERVED */
2881 
//#define RESERVED            (0x0400)    /* RESERVED */
2882 
//#define RESERVED            (0x0800)    /* RESERVED */
2883 
//#define RESERVED            (0x1000)    /* RESERVED */
2884 
//#define RESERVED            (0x2000)    /* RESERVED */
2885 
//#define RESERVED            (0x4000)    /* RESERVED */
2886 
//#define RESERVED            (0x8000)    /* RESERVED */
2887 
 
2888 
/* UCSCTL3 Control Bits */
2889 
//#define RESERVED            (0x0008)    /* RESERVED */
2890 
//#define RESERVED            (0x0080)    /* RESERVED */
2891 
//#define RESERVED            (0x0100)    /* RESERVED */
2892 
//#define RESERVED            (0x0200)    /* RESERVED */
2893 
//#define RESERVED            (0x0400)    /* RESERVED */
2894 
//#define RESERVED            (0x0800)    /* RESERVED */
2895 
//#define RESERVED            (0x1000)    /* RESERVED */
2896 
//#define RESERVED            (0x2000)    /* RESERVED */
2897 
//#define RESERVED            (0x4000)    /* RESERVED */
2898 
//#define RESERVED            (0x8000)    /* RESERVED */
2899 
 
2900 
#define FLLREFDIV_0            (0x0000)       /* Reference Divider: f(LFCLK)/1 */
2901 
#define FLLREFDIV_1            (0x0001)       /* Reference Divider: f(LFCLK)/2 */
2902 
#define FLLREFDIV_2            (0x0002)       /* Reference Divider: f(LFCLK)/4 */
2903 
#define FLLREFDIV_3            (0x0003)       /* Reference Divider: f(LFCLK)/8 */
2904 
#define FLLREFDIV_4            (0x0004)       /* Reference Divider: f(LFCLK)/12 */
2905 
#define FLLREFDIV_5            (0x0005)       /* Reference Divider: f(LFCLK)/16 */
2906 
#define FLLREFDIV_6            (0x0006)       /* Reference Divider: f(LFCLK)/16 */
2907 
#define FLLREFDIV_7            (0x0007)       /* Reference Divider: f(LFCLK)/16 */
2908 
#define FLLREFDIV__1           (0x0000)       /* Reference Divider: f(LFCLK)/1 */
2909 
#define FLLREFDIV__2           (0x0001)       /* Reference Divider: f(LFCLK)/2 */
2910 
#define FLLREFDIV__4           (0x0002)       /* Reference Divider: f(LFCLK)/4 */
2911 
#define FLLREFDIV__8           (0x0003)       /* Reference Divider: f(LFCLK)/8 */
2912 
#define FLLREFDIV__12          (0x0004)       /* Reference Divider: f(LFCLK)/12 */
2913 
#define FLLREFDIV__16          (0x0005)       /* Reference Divider: f(LFCLK)/16 */
2914 
#define SELREF_0               (0x0000)       /* FLL Reference Clock Select 0 */
2915 
#define SELREF_1               (0x0010)       /* FLL Reference Clock Select 1 */
2916 
#define SELREF_2               (0x0020)       /* FLL Reference Clock Select 2 */
2917 
#define SELREF_3               (0x0030)       /* FLL Reference Clock Select 3 */
2918 
#define SELREF_4               (0x0040)       /* FLL Reference Clock Select 4 */
2919 
#define SELREF_5               (0x0050)       /* FLL Reference Clock Select 5 */
2920 
#define SELREF_6               (0x0060)       /* FLL Reference Clock Select 6 */
2921 
#define SELREF_7               (0x0070)       /* FLL Reference Clock Select 7 */
2922 
#define SELREF__XT1CLK         (0x0000)       /* Multiply Selected Loop Freq. By XT1CLK */
2923 
#define SELREF__REFOCLK        (0x0020)       /* Multiply Selected Loop Freq. By REFOCLK */
2924 
#define SELREF__XT2CLK         (0x0050)       /* Multiply Selected Loop Freq. By XT2CLK */
2925 
 
2926 
/* UCSCTL4 Control Bits */
2927 
#define SELM0                  (0x0001)       /* MCLK Source Select Bit: 0 */
2928 
#define SELM1                  (0x0002)       /* MCLK Source Select Bit: 1 */
2929 
#define SELM2                  (0x0004)       /* MCLK Source Select Bit: 2 */
2930 
//#define RESERVED            (0x0008)    /* RESERVED */
2931 
#define SELS0                  (0x0010)       /* SMCLK Source Select Bit: 0 */
2932 
#define SELS1                  (0x0020)       /* SMCLK Source Select Bit: 1 */
2933 
#define SELS2                  (0x0040)       /* SMCLK Source Select Bit: 2 */
2934 
//#define RESERVED            (0x0080)    /* RESERVED */
2935 
#define SELA0                  (0x0100)       /* ACLK Source Select Bit: 0 */
2936 
#define SELA1                  (0x0200)       /* ACLK Source Select Bit: 1 */
2937 
#define SELA2                  (0x0400)       /* ACLK Source Select Bit: 2 */
2938 
//#define RESERVED            (0x0800)    /* RESERVED */
2939 
//#define RESERVED            (0x1000)    /* RESERVED */
2940 
//#define RESERVED            (0x2000)    /* RESERVED */
2941 
//#define RESERVED            (0x4000)    /* RESERVED */
2942 
//#define RESERVED            (0x8000)    /* RESERVED */
2943 
 
2944 
/* UCSCTL4 Control Bits */
2945 
#define SELM0_L                (0x0001)       /* MCLK Source Select Bit: 0 */
2946 
#define SELM1_L                (0x0002)       /* MCLK Source Select Bit: 1 */
2947 
#define SELM2_L                (0x0004)       /* MCLK Source Select Bit: 2 */
2948 
//#define RESERVED            (0x0008)    /* RESERVED */
2949 
#define SELS0_L                (0x0010)       /* SMCLK Source Select Bit: 0 */
2950 
#define SELS1_L                (0x0020)       /* SMCLK Source Select Bit: 1 */
2951 
#define SELS2_L                (0x0040)       /* SMCLK Source Select Bit: 2 */
2952 
//#define RESERVED            (0x0080)    /* RESERVED */
2953 
//#define RESERVED            (0x0800)    /* RESERVED */
2954 
//#define RESERVED            (0x1000)    /* RESERVED */
2955 
//#define RESERVED            (0x2000)    /* RESERVED */
2956 
//#define RESERVED            (0x4000)    /* RESERVED */
2957 
//#define RESERVED            (0x8000)    /* RESERVED */
2958 
 
2959 
/* UCSCTL4 Control Bits */
2960 
//#define RESERVED            (0x0008)    /* RESERVED */
2961 
//#define RESERVED            (0x0080)    /* RESERVED */
2962 
#define SELA0_H                (0x0001)       /* ACLK Source Select Bit: 0 */
2963 
#define SELA1_H                (0x0002)       /* ACLK Source Select Bit: 1 */
2964 
#define SELA2_H                (0x0004)       /* ACLK Source Select Bit: 2 */
2965 
//#define RESERVED            (0x0800)    /* RESERVED */
2966 
//#define RESERVED            (0x1000)    /* RESERVED */
2967 
//#define RESERVED            (0x2000)    /* RESERVED */
2968 
//#define RESERVED            (0x4000)    /* RESERVED */
2969 
//#define RESERVED            (0x8000)    /* RESERVED */
2970 
 
2971 
#define SELM_0                 (0x0000)       /* MCLK Source Select 0 */
2972 
#define SELM_1                 (0x0001)       /* MCLK Source Select 1 */
2973 
#define SELM_2                 (0x0002)       /* MCLK Source Select 2 */
2974 
#define SELM_3                 (0x0003)       /* MCLK Source Select 3 */
2975 
#define SELM_4                 (0x0004)       /* MCLK Source Select 4 */
2976 
#define SELM_5                 (0x0005)       /* MCLK Source Select 5 */
2977 
#define SELM_6                 (0x0006)       /* MCLK Source Select 6 */
2978 
#define SELM_7                 (0x0007)       /* MCLK Source Select 7 */
2979 
#define SELM__XT1CLK           (0x0000)       /* MCLK Source Select XT1CLK */
2980 
#define SELM__VLOCLK           (0x0001)       /* MCLK Source Select VLOCLK */
2981 
#define SELM__REFOCLK          (0x0002)       /* MCLK Source Select REFOCLK */
2982 
#define SELM__DCOCLK           (0x0003)       /* MCLK Source Select DCOCLK */
2983 
#define SELM__DCOCLKDIV        (0x0004)       /* MCLK Source Select DCOCLKDIV */
2984 
#define SELM__XT2CLK           (0x0005)       /* MCLK Source Select XT2CLK */
2985 
 
2986 
#define SELS_0                 (0x0000)       /* SMCLK Source Select 0 */
2987 
#define SELS_1                 (0x0010)       /* SMCLK Source Select 1 */
2988 
#define SELS_2                 (0x0020)       /* SMCLK Source Select 2 */
2989 
#define SELS_3                 (0x0030)       /* SMCLK Source Select 3 */
2990 
#define SELS_4                 (0x0040)       /* SMCLK Source Select 4 */
2991 
#define SELS_5                 (0x0050)       /* SMCLK Source Select 5 */
2992 
#define SELS_6                 (0x0060)       /* SMCLK Source Select 6 */
2993 
#define SELS_7                 (0x0070)       /* SMCLK Source Select 7 */
2994 
#define SELS__XT1CLK           (0x0000)       /* SMCLK Source Select XT1CLK */
2995 
#define SELS__VLOCLK           (0x0010)       /* SMCLK Source Select VLOCLK */
2996 
#define SELS__REFOCLK          (0x0020)       /* SMCLK Source Select REFOCLK */
2997 
#define SELS__DCOCLK           (0x0030)       /* SMCLK Source Select DCOCLK */
2998 
#define SELS__DCOCLKDIV        (0x0040)       /* SMCLK Source Select DCOCLKDIV */
2999 
#define SELS__XT2CLK           (0x0050)       /* SMCLK Source Select XT2CLK */
3000 
 
3001 
#define SELA_0                 (0x0000)       /* ACLK Source Select 0 */
3002 
#define SELA_1                 (0x0100)       /* ACLK Source Select 1 */
3003 
#define SELA_2                 (0x0200)       /* ACLK Source Select 2 */
3004 
#define SELA_3                 (0x0300)       /* ACLK Source Select 3 */
3005 
#define SELA_4                 (0x0400)       /* ACLK Source Select 4 */
3006 
#define SELA_5                 (0x0500)       /* ACLK Source Select 5 */
3007 
#define SELA_6                 (0x0600)       /* ACLK Source Select 6 */
3008 
#define SELA_7                 (0x0700)       /* ACLK Source Select 7 */
3009 
#define SELA__XT1CLK           (0x0000)       /* ACLK Source Select XT1CLK */
3010 
#define SELA__VLOCLK           (0x0100)       /* ACLK Source Select VLOCLK */
3011 
#define SELA__REFOCLK          (0x0200)       /* ACLK Source Select REFOCLK */
3012 
#define SELA__DCOCLK           (0x0300)       /* ACLK Source Select DCOCLK */
3013 
#define SELA__DCOCLKDIV        (0x0400)       /* ACLK Source Select DCOCLKDIV */
3014 
#define SELA__XT2CLK           (0x0500)       /* ACLK Source Select XT2CLK */
3015 
 
3016 
/* UCSCTL5 Control Bits */
3017 
#define DIVM0                  (0x0001)       /* MCLK Divider Bit: 0 */
3018 
#define DIVM1                  (0x0002)       /* MCLK Divider Bit: 1 */
3019 
#define DIVM2                  (0x0004)       /* MCLK Divider Bit: 2 */
3020 
//#define RESERVED            (0x0008)    /* RESERVED */
3021 
#define DIVS0                  (0x0010)       /* SMCLK Divider Bit: 0 */
3022 
#define DIVS1                  (0x0020)       /* SMCLK Divider Bit: 1 */
3023 
#define DIVS2                  (0x0040)       /* SMCLK Divider Bit: 2 */
3024 
//#define RESERVED            (0x0080)    /* RESERVED */
3025 
#define DIVA0                  (0x0100)       /* ACLK Divider Bit: 0 */
3026 
#define DIVA1                  (0x0200)       /* ACLK Divider Bit: 1 */
3027 
#define DIVA2                  (0x0400)       /* ACLK Divider Bit: 2 */
3028 
//#define RESERVED            (0x0800)    /* RESERVED */
3029 
#define DIVPA0                 (0x1000)       /* ACLK from Pin Divider Bit: 0 */
3030 
#define DIVPA1                 (0x2000)       /* ACLK from Pin Divider Bit: 1 */
3031 
#define DIVPA2                 (0x4000)       /* ACLK from Pin Divider Bit: 2 */
3032 
//#define RESERVED            (0x8000)    /* RESERVED */
3033 
 
3034 
/* UCSCTL5 Control Bits */
3035 
#define DIVM0_L                (0x0001)       /* MCLK Divider Bit: 0 */
3036 
#define DIVM1_L                (0x0002)       /* MCLK Divider Bit: 1 */
3037 
#define DIVM2_L                (0x0004)       /* MCLK Divider Bit: 2 */
3038 
//#define RESERVED            (0x0008)    /* RESERVED */
3039 
#define DIVS0_L                (0x0010)       /* SMCLK Divider Bit: 0 */
3040 
#define DIVS1_L                (0x0020)       /* SMCLK Divider Bit: 1 */
3041 
#define DIVS2_L                (0x0040)       /* SMCLK Divider Bit: 2 */
3042 
//#define RESERVED            (0x0080)    /* RESERVED */
3043 
//#define RESERVED            (0x0800)    /* RESERVED */
3044 
//#define RESERVED            (0x8000)    /* RESERVED */
3045 
 
3046 
/* UCSCTL5 Control Bits */
3047 
//#define RESERVED            (0x0008)    /* RESERVED */
3048 
//#define RESERVED            (0x0080)    /* RESERVED */
3049 
#define DIVA0_H                (0x0001)       /* ACLK Divider Bit: 0 */
3050 
#define DIVA1_H                (0x0002)       /* ACLK Divider Bit: 1 */
3051 
#define DIVA2_H                (0x0004)       /* ACLK Divider Bit: 2 */
3052 
//#define RESERVED            (0x0800)    /* RESERVED */
3053 
#define DIVPA0_H               (0x0010)       /* ACLK from Pin Divider Bit: 0 */
3054 
#define DIVPA1_H               (0x0020)       /* ACLK from Pin Divider Bit: 1 */
3055 
#define DIVPA2_H               (0x0040)       /* ACLK from Pin Divider Bit: 2 */
3056 
//#define RESERVED            (0x8000)    /* RESERVED */
3057 
 
3058 
#define DIVM_0                 (0x0000)       /* MCLK Source Divider 0 */
3059 
#define DIVM_1                 (0x0001)       /* MCLK Source Divider 1 */
3060 
#define DIVM_2                 (0x0002)       /* MCLK Source Divider 2 */
3061 
#define DIVM_3                 (0x0003)       /* MCLK Source Divider 3 */
3062 
#define DIVM_4                 (0x0004)       /* MCLK Source Divider 4 */
3063 
#define DIVM_5                 (0x0005)       /* MCLK Source Divider 5 */
3064 
#define DIVM_6                 (0x0006)       /* MCLK Source Divider 6 */
3065 
#define DIVM_7                 (0x0007)       /* MCLK Source Divider 7 */
3066 
#define DIVM__1                (0x0000)       /* MCLK Source Divider f(MCLK)/1 */
3067 
#define DIVM__2                (0x0001)       /* MCLK Source Divider f(MCLK)/2 */
3068 
#define DIVM__4                (0x0002)       /* MCLK Source Divider f(MCLK)/4 */
3069 
#define DIVM__8                (0x0003)       /* MCLK Source Divider f(MCLK)/8 */
3070 
#define DIVM__16               (0x0004)       /* MCLK Source Divider f(MCLK)/16 */
3071 
#define DIVM__32               (0x0005)       /* MCLK Source Divider f(MCLK)/32 */
3072 
 
3073 
#define DIVS_0                 (0x0000)       /* SMCLK Source Divider 0 */
3074 
#define DIVS_1                 (0x0010)       /* SMCLK Source Divider 1 */
3075 
#define DIVS_2                 (0x0020)       /* SMCLK Source Divider 2 */
3076 
#define DIVS_3                 (0x0030)       /* SMCLK Source Divider 3 */
3077 
#define DIVS_4                 (0x0040)       /* SMCLK Source Divider 4 */
3078 
#define DIVS_5                 (0x0050)       /* SMCLK Source Divider 5 */
3079 
#define DIVS_6                 (0x0060)       /* SMCLK Source Divider 6 */
3080 
#define DIVS_7                 (0x0070)       /* SMCLK Source Divider 7 */
3081 
#define DIVS__1                (0x0000)       /* SMCLK Source Divider f(SMCLK)/1 */
3082 
#define DIVS__2                (0x0010)       /* SMCLK Source Divider f(SMCLK)/2 */
3083 
#define DIVS__4                (0x0020)       /* SMCLK Source Divider f(SMCLK)/4 */
3084 
#define DIVS__8                (0x0030)       /* SMCLK Source Divider f(SMCLK)/8 */
3085 
#define DIVS__16               (0x0040)       /* SMCLK Source Divider f(SMCLK)/16 */
3086 
#define DIVS__32               (0x0050)       /* SMCLK Source Divider f(SMCLK)/32 */
3087 
 
3088 
#define DIVA_0                 (0x0000)       /* ACLK Source Divider 0 */
3089 
#define DIVA_1                 (0x0100)       /* ACLK Source Divider 1 */
3090 
#define DIVA_2                 (0x0200)       /* ACLK Source Divider 2 */
3091 
#define DIVA_3                 (0x0300)       /* ACLK Source Divider 3 */
3092 
#define DIVA_4                 (0x0400)       /* ACLK Source Divider 4 */
3093 
#define DIVA_5                 (0x0500)       /* ACLK Source Divider 5 */
3094 
#define DIVA_6                 (0x0600)       /* ACLK Source Divider 6 */
3095 
#define DIVA_7                 (0x0700)       /* ACLK Source Divider 7 */
3096 
#define DIVA__1                (0x0000)       /* ACLK Source Divider f(ACLK)/1 */
3097 
#define DIVA__2                (0x0100)       /* ACLK Source Divider f(ACLK)/2 */
3098 
#define DIVA__4                (0x0200)       /* ACLK Source Divider f(ACLK)/4 */
3099 
#define DIVA__8                (0x0300)       /* ACLK Source Divider f(ACLK)/8 */
3100 
#define DIVA__16               (0x0400)       /* ACLK Source Divider f(ACLK)/16 */
3101 
#define DIVA__32               (0x0500)       /* ACLK Source Divider f(ACLK)/32 */
3102 
 
3103 
#define DIVPA_0                (0x0000)       /* ACLK from Pin Source Divider 0 */
3104 
#define DIVPA_1                (0x1000)       /* ACLK from Pin Source Divider 1 */
3105 
#define DIVPA_2                (0x2000)       /* ACLK from Pin Source Divider 2 */
3106 
#define DIVPA_3                (0x3000)       /* ACLK from Pin Source Divider 3 */
3107 
#define DIVPA_4                (0x4000)       /* ACLK from Pin Source Divider 4 */
3108 
#define DIVPA_5                (0x5000)       /* ACLK from Pin Source Divider 5 */
3109 
#define DIVPA_6                (0x6000)       /* ACLK from Pin Source Divider 6 */
3110 
#define DIVPA_7                (0x7000)       /* ACLK from Pin Source Divider 7 */
3111 
#define DIVPA__1               (0x0000)       /* ACLK from Pin Source Divider f(ACLK)/1 */
3112 
#define DIVPA__2               (0x1000)       /* ACLK from Pin Source Divider f(ACLK)/2 */
3113 
#define DIVPA__4               (0x2000)       /* ACLK from Pin Source Divider f(ACLK)/4 */
3114 
#define DIVPA__8               (0x3000)       /* ACLK from Pin Source Divider f(ACLK)/8 */
3115 
#define DIVPA__16              (0x4000)       /* ACLK from Pin Source Divider f(ACLK)/16 */
3116 
#define DIVPA__32              (0x5000)       /* ACLK from Pin Source Divider f(ACLK)/32 */
3117 
 
3118 
/* UCSCTL6 Control Bits */
3119 
#define XT1OFF                 (0x0001)       /* High Frequency Oscillator 1 (XT1) disable */
3120 
#define SMCLKOFF               (0x0002)       /* SMCLK Off */
3121 
#define XCAP0                  (0x0004)       /* XIN/XOUT Cap Bit: 0 */
3122 
#define XCAP1                  (0x0008)       /* XIN/XOUT Cap Bit: 1 */
3123 
#define XT1BYPASS              (0x0010)       /* XT1 bypass mode : 0: internal 1:sourced from external pin */
3124 
#define XTS                    (0x0020)       /* 1: Selects high-freq. oscillator */
3125 
#define XT1DRIVE0              (0x0040)       /* XT1 Drive Level mode Bit 0 */
3126 
#define XT1DRIVE1              (0x0080)       /* XT1 Drive Level mode Bit 1 */
3127 
#define XT2OFF                 (0x0100)       /* High Frequency Oscillator 2 (XT2) disable */
3128 
//#define RESERVED            (0x0200)    /* RESERVED */
3129 
//#define RESERVED            (0x0400)    /* RESERVED */
3130 
//#define RESERVED            (0x0800)    /* RESERVED */
3131 
#define XT2BYPASS              (0x1000)       /* XT2 bypass mode : 0: internal 1:sourced from external pin */
3132 
//#define RESERVED            (0x2000)    /* RESERVED */
3133 
#define XT2DRIVE0              (0x4000)       /* XT2 Drive Level mode Bit 0 */
3134 
#define XT2DRIVE1              (0x8000)       /* XT2 Drive Level mode Bit 1 */
3135 
 
3136 
/* UCSCTL6 Control Bits */
3137 
#define XT1OFF_L               (0x0001)       /* High Frequency Oscillator 1 (XT1) disable */
3138 
#define SMCLKOFF_L             (0x0002)       /* SMCLK Off */
3139 
#define XCAP0_L                (0x0004)       /* XIN/XOUT Cap Bit: 0 */
3140 
#define XCAP1_L                (0x0008)       /* XIN/XOUT Cap Bit: 1 */
3141 
#define XT1BYPASS_L            (0x0010)       /* XT1 bypass mode : 0: internal 1:sourced from external pin */
3142 
#define XTS_L                  (0x0020)       /* 1: Selects high-freq. oscillator */
3143 
#define XT1DRIVE0_L            (0x0040)       /* XT1 Drive Level mode Bit 0 */
3144 
#define XT1DRIVE1_L            (0x0080)       /* XT1 Drive Level mode Bit 1 */
3145 
//#define RESERVED            (0x0200)    /* RESERVED */
3146 
//#define RESERVED            (0x0400)    /* RESERVED */
3147 
//#define RESERVED            (0x0800)    /* RESERVED */
3148 
//#define RESERVED            (0x2000)    /* RESERVED */
3149 
 
3150 
/* UCSCTL6 Control Bits */
3151 
#define XT2OFF_H               (0x0001)       /* High Frequency Oscillator 2 (XT2) disable */
3152 
//#define RESERVED            (0x0200)    /* RESERVED */
3153 
//#define RESERVED            (0x0400)    /* RESERVED */
3154 
//#define RESERVED            (0x0800)    /* RESERVED */
3155 
#define XT2BYPASS_H            (0x0010)       /* XT2 bypass mode : 0: internal 1:sourced from external pin */
3156 
//#define RESERVED            (0x2000)    /* RESERVED */
3157 
#define XT2DRIVE0_H            (0x0040)       /* XT2 Drive Level mode Bit 0 */
3158 
#define XT2DRIVE1_H            (0x0080)       /* XT2 Drive Level mode Bit 1 */
3159 
 
3160 
#define XCAP_0                 (0x0000)       /* XIN/XOUT Cap 0 */
3161 
#define XCAP_1                 (0x0004)       /* XIN/XOUT Cap 1 */
3162 
#define XCAP_2                 (0x0008)       /* XIN/XOUT Cap 2 */
3163 
#define XCAP_3                 (0x000C)       /* XIN/XOUT Cap 3 */
3164 
#define XT1DRIVE_0             (0x0000)       /* XT1 Drive Level mode: 0 */
3165 
#define XT1DRIVE_1             (0x0040)       /* XT1 Drive Level mode: 1 */
3166 
#define XT1DRIVE_2             (0x0080)       /* XT1 Drive Level mode: 2 */
3167 
#define XT1DRIVE_3             (0x00C0)       /* XT1 Drive Level mode: 3 */
3168 
#define XT2DRIVE_0             (0x0000)       /* XT2 Drive Level mode: 0 */
3169 
#define XT2DRIVE_1             (0x4000)       /* XT2 Drive Level mode: 1 */
3170 
#define XT2DRIVE_2             (0x8000)       /* XT2 Drive Level mode: 2 */
3171 
#define XT2DRIVE_3             (0xC000)       /* XT2 Drive Level mode: 3 */
3172 
 
3173 
/* UCSCTL7 Control Bits */
3174 
#define DCOFFG                 (0x0001)       /* DCO Fault Flag */
3175 
#define XT1LFOFFG              (0x0002)       /* XT1 Low Frequency Oscillator Fault Flag */
3176 
#define XT1HFOFFG              (0x0004)       /* XT1 High Frequency Oscillator 1 Fault Flag */
3177 
#define XT2OFFG                (0x0008)       /* High Frequency Oscillator 2 Fault Flag */
3178 
//#define RESERVED            (0x0010)    /* RESERVED */
3179 
//#define RESERVED            (0x0020)    /* RESERVED */
3180 
//#define RESERVED            (0x0040)    /* RESERVED */
3181 
//#define RESERVED            (0x0080)    /* RESERVED */
3182 
//#define RESERVED            (0x0100)    /* RESERVED */
3183 
//#define RESERVED            (0x0200)    /* RESERVED */
3184 
//#define RESERVED            (0x0400)    /* RESERVED */
3185 
//#define RESERVED            (0x0800)    /* RESERVED */
3186 
//#define RESERVED            (0x1000)    /* RESERVED */
3187 
//#define RESERVED            (0x2000)    /* RESERVED */
3188 
//#define RESERVED            (0x4000)    /* RESERVED */
3189 
//#define RESERVED            (0x8000)    /* RESERVED */
3190 
 
3191 
/* UCSCTL7 Control Bits */
3192 
#define DCOFFG_L               (0x0001)       /* DCO Fault Flag */
3193 
#define XT1LFOFFG_L            (0x0002)       /* XT1 Low Frequency Oscillator Fault Flag */
3194 
#define XT1HFOFFG_L            (0x0004)       /* XT1 High Frequency Oscillator 1 Fault Flag */
3195 
#define XT2OFFG_L              (0x0008)       /* High Frequency Oscillator 2 Fault Flag */
3196 
//#define RESERVED            (0x0010)    /* RESERVED */
3197 
//#define RESERVED            (0x0020)    /* RESERVED */
3198 
//#define RESERVED            (0x0040)    /* RESERVED */
3199 
//#define RESERVED            (0x0080)    /* RESERVED */
3200 
//#define RESERVED            (0x0100)    /* RESERVED */
3201 
//#define RESERVED            (0x0200)    /* RESERVED */
3202 
//#define RESERVED            (0x0400)    /* RESERVED */
3203 
//#define RESERVED            (0x0800)    /* RESERVED */
3204 
//#define RESERVED            (0x1000)    /* RESERVED */
3205 
//#define RESERVED            (0x2000)    /* RESERVED */
3206 
//#define RESERVED            (0x4000)    /* RESERVED */
3207 
//#define RESERVED            (0x8000)    /* RESERVED */
3208 
 
3209 
/* UCSCTL7 Control Bits */
3210 
//#define RESERVED            (0x0010)    /* RESERVED */
3211 
//#define RESERVED            (0x0020)    /* RESERVED */
3212 
//#define RESERVED            (0x0040)    /* RESERVED */
3213 
//#define RESERVED            (0x0080)    /* RESERVED */
3214 
//#define RESERVED            (0x0100)    /* RESERVED */
3215 
//#define RESERVED            (0x0200)    /* RESERVED */
3216 
//#define RESERVED            (0x0400)    /* RESERVED */
3217 
//#define RESERVED            (0x0800)    /* RESERVED */
3218 
//#define RESERVED            (0x1000)    /* RESERVED */
3219 
//#define RESERVED            (0x2000)    /* RESERVED */
3220 
//#define RESERVED            (0x4000)    /* RESERVED */
3221 
//#define RESERVED            (0x8000)    /* RESERVED */
3222 
 
3223 
/* UCSCTL8 Control Bits */
3224 
#define ACLKREQEN              (0x0001)       /* ACLK Clock Request Enable */
3225 
#define MCLKREQEN              (0x0002)       /* MCLK Clock Request Enable */
3226 
#define SMCLKREQEN             (0x0004)       /* SMCLK Clock Request Enable */
3227 
#define MODOSCREQEN            (0x0008)       /* MODOSC Clock Request Enable */
3228 
//#define RESERVED            (0x0010)    /* RESERVED */
3229 
//#define RESERVED            (0x0020)    /* RESERVED */
3230 
//#define RESERVED            (0x0040)    /* RESERVED */
3231 
//#define RESERVED            (0x0080)    /* RESERVED */
3232 
//#define RESERVED            (0x0100)    /* RESERVED */
3233 
//#define RESERVED            (0x0200)    /* RESERVED */
3234 
//#define RESERVED            (0x0400)    /* RESERVED */
3235 
//#define RESERVED            (0x0800)    /* RESERVED */
3236 
//#define RESERVED            (0x1000)    /* RESERVED */
3237 
//#define RESERVED            (0x2000)    /* RESERVED */
3238 
//#define RESERVED            (0x4000)    /* RESERVED */
3239 
//#define RESERVED            (0x8000)    /* RESERVED */
3240 
 
3241 
/* UCSCTL8 Control Bits */
3242 
#define ACLKREQEN_L            (0x0001)       /* ACLK Clock Request Enable */
3243 
#define MCLKREQEN_L            (0x0002)       /* MCLK Clock Request Enable */
3244 
#define SMCLKREQEN_L           (0x0004)       /* SMCLK Clock Request Enable */
3245 
#define MODOSCREQEN_L          (0x0008)       /* MODOSC Clock Request Enable */
3246 
//#define RESERVED            (0x0010)    /* RESERVED */
3247 
//#define RESERVED            (0x0020)    /* RESERVED */
3248 
//#define RESERVED            (0x0040)    /* RESERVED */
3249 
//#define RESERVED            (0x0080)    /* RESERVED */
3250 
//#define RESERVED            (0x0100)    /* RESERVED */
3251 
//#define RESERVED            (0x0200)    /* RESERVED */
3252 
//#define RESERVED            (0x0400)    /* RESERVED */
3253 
//#define RESERVED            (0x0800)    /* RESERVED */
3254 
//#define RESERVED            (0x1000)    /* RESERVED */
3255 
//#define RESERVED            (0x2000)    /* RESERVED */
3256 
//#define RESERVED            (0x4000)    /* RESERVED */
3257 
//#define RESERVED            (0x8000)    /* RESERVED */
3258 
 
3259 
/* UCSCTL8 Control Bits */
3260 
//#define RESERVED            (0x0010)    /* RESERVED */
3261 
//#define RESERVED            (0x0020)    /* RESERVED */
3262 
//#define RESERVED            (0x0040)    /* RESERVED */
3263 
//#define RESERVED            (0x0080)    /* RESERVED */
3264 
//#define RESERVED            (0x0100)    /* RESERVED */
3265 
//#define RESERVED            (0x0200)    /* RESERVED */
3266 
//#define RESERVED            (0x0400)    /* RESERVED */
3267 
//#define RESERVED            (0x0800)    /* RESERVED */
3268 
//#define RESERVED            (0x1000)    /* RESERVED */
3269 
//#define RESERVED            (0x2000)    /* RESERVED */
3270 
//#define RESERVED            (0x4000)    /* RESERVED */
3271 
//#define RESERVED            (0x8000)    /* RESERVED */
3272 
 
3273 
/************************************************************
3274 
* USCI A0
3275 
************************************************************/
3276 
#define __MSP430_HAS_USCI_A0__                /* Definition to show that Module is available */
3277 
#define __MSP430_BASEADDRESS_USCI_A0__ 0x05C0
3278 
 
3279 
SFR_16BIT(UCA0CTLW0);                         /* USCI A0 Control Word Register 0 */
3280 
SFR_8BIT(UCA0CTLW0_L);                        /* USCI A0 Control Word Register 0 */
3281 
SFR_8BIT(UCA0CTLW0_H);                        /* USCI A0 Control Word Register 0 */
3282 
#define UCA0CTL1               UCA0CTLW0_L    /* USCI A0 Control Register 1 */
3283 
#define UCA0CTL0               UCA0CTLW0_H    /* USCI A0 Control Register 0 */
3284 
SFR_16BIT(UCA0BRW);                           /* USCI A0 Baud Word Rate 0 */
3285 
SFR_8BIT(UCA0BRW_L);                          /* USCI A0 Baud Word Rate 0 */
3286 
SFR_8BIT(UCA0BRW_H);                          /* USCI A0 Baud Word Rate 0 */
3287 
#define UCA0BR0                UCA0BRW_L      /* USCI A0 Baud Rate 0 */
3288 
#define UCA0BR1                UCA0BRW_H      /* USCI A0 Baud Rate 1 */
3289 
SFR_8BIT(UCA0MCTL);                           /* USCI A0 Modulation Control */
3290 
SFR_8BIT(UCA0STAT);                           /* USCI A0 Status Register */
3291 
SFR_8BIT(UCA0RXBUF);                          /* USCI A0 Receive Buffer */
3292 
SFR_8BIT(UCA0TXBUF);                          /* USCI A0 Transmit Buffer */
3293 
SFR_8BIT(UCA0ABCTL);                          /* USCI A0 LIN Control */
3294 
SFR_16BIT(UCA0IRCTL);                         /* USCI A0 IrDA Transmit Control */
3295 
SFR_8BIT(UCA0IRCTL_L);                        /* USCI A0 IrDA Transmit Control */
3296 
SFR_8BIT(UCA0IRCTL_H);                        /* USCI A0 IrDA Transmit Control */
3297 
#define UCA0IRTCTL             UCA0IRCTL_L    /* USCI A0 IrDA Transmit Control */
3298 
#define UCA0IRRCTL             UCA0IRCTL_H    /* USCI A0 IrDA Receive Control */
3299 
SFR_16BIT(UCA0ICTL);                          /* USCI A0 Interrupt Enable Register */
3300 
SFR_8BIT(UCA0ICTL_L);                         /* USCI A0 Interrupt Enable Register */
3301 
SFR_8BIT(UCA0ICTL_H);                         /* USCI A0 Interrupt Enable Register */
3302 
#define UCA0IE                 UCA0ICTL_L     /* USCI A0 Interrupt Enable Register */
3303 
#define UCA0IFG                UCA0ICTL_H     /* USCI A0 Interrupt Flags Register */
3304 
SFR_16BIT(UCA0IV);                            /* USCI A0 Interrupt Vector Register */
3305 
 
3306 
 
3307 
/************************************************************
3308 
* USCI B0
3309 
************************************************************/
3310 
#define __MSP430_HAS_USCI_B0__                /* Definition to show that Module is available */
3311 
#define __MSP430_BASEADDRESS_USCI_B0__ 0x05E0
3312 
 
3313 
 
3314 
SFR_16BIT(UCB0CTLW0);                         /* USCI B0 Control Word Register 0 */
3315 
SFR_8BIT(UCB0CTLW0_L);                        /* USCI B0 Control Word Register 0 */
3316 
SFR_8BIT(UCB0CTLW0_H);                        /* USCI B0 Control Word Register 0 */
3317 
#define UCB0CTL1               UCB0CTLW0_L    /* USCI B0 Control Register 1 */
3318 
#define UCB0CTL0               UCB0CTLW0_H    /* USCI B0 Control Register 0 */
3319 
SFR_16BIT(UCB0BRW);                           /* USCI B0 Baud Word Rate 0 */
3320 
SFR_8BIT(UCB0BRW_L);                          /* USCI B0 Baud Word Rate 0 */
3321 
SFR_8BIT(UCB0BRW_H);                          /* USCI B0 Baud Word Rate 0 */
3322 
#define UCB0BR0                UCB0BRW_L      /* USCI B0 Baud Rate 0 */
3323 
#define UCB0BR1                UCB0BRW_H      /* USCI B0 Baud Rate 1 */
3324 
SFR_8BIT(UCB0STAT);                           /* USCI B0 Status Register */
3325 
SFR_8BIT(UCB0RXBUF);                          /* USCI B0 Receive Buffer */
3326 
SFR_8BIT(UCB0TXBUF);                          /* USCI B0 Transmit Buffer */
3327 
SFR_16BIT(UCB0I2COA);                         /* USCI B0 I2C Own Address */
3328 
SFR_8BIT(UCB0I2COA_L);                        /* USCI B0 I2C Own Address */
3329 
SFR_8BIT(UCB0I2COA_H);                        /* USCI B0 I2C Own Address */
3330 
SFR_16BIT(UCB0I2CSA);                         /* USCI B0 I2C Slave Address */
3331 
SFR_8BIT(UCB0I2CSA_L);                        /* USCI B0 I2C Slave Address */
3332 
SFR_8BIT(UCB0I2CSA_H);                        /* USCI B0 I2C Slave Address */
3333 
SFR_16BIT(UCB0ICTL);                          /* USCI B0 Interrupt Enable Register */
3334 
SFR_8BIT(UCB0ICTL_L);                         /* USCI B0 Interrupt Enable Register */
3335 
SFR_8BIT(UCB0ICTL_H);                         /* USCI B0 Interrupt Enable Register */
3336 
#define UCB0IE                 UCB0ICTL_L     /* USCI B0 Interrupt Enable Register */
3337 
#define UCB0IFG                UCB0ICTL_H     /* USCI B0 Interrupt Flags Register */
3338 
SFR_16BIT(UCB0IV);                            /* USCI B0 Interrupt Vector Register */
3339 
 
3340 
// UCAxCTL0 UART-Mode Control Bits
3341 
#define UCPEN                  (0x80)         /* Async. Mode: Parity enable */
3342 
#define UCPAR                  (0x40)         /* Async. Mode: Parity     0:odd / 1:even */
3343 
#define UCMSB                  (0x20)         /* Async. Mode: MSB first  0:LSB / 1:MSB */
3344 
#define UC7BIT                 (0x10)         /* Async. Mode: Data Bits  0:8-bits / 1:7-bits */
3345 
#define UCSPB                  (0x08)         /* Async. Mode: Stop Bits  0:one / 1: two */
3346 
#define UCMODE1                (0x04)         /* Async. Mode: USCI Mode 1 */
3347 
#define UCMODE0                (0x02)         /* Async. Mode: USCI Mode 0 */
3348 
#define UCSYNC                 (0x01)         /* Sync-Mode  0:UART-Mode / 1:SPI-Mode */
3349 
 
3350 
// UCxxCTL0 SPI-Mode Control Bits
3351 
#define UCCKPH                 (0x80)         /* Sync. Mode: Clock Phase */
3352 
#define UCCKPL                 (0x40)         /* Sync. Mode: Clock Polarity */
3353 
#define UCMST                  (0x08)         /* Sync. Mode: Master Select */
3354 
 
3355 
// UCBxCTL0 I2C-Mode Control Bits
3356 
#define UCA10                  (0x80)         /* 10-bit Address Mode */
3357 
#define UCSLA10                (0x40)         /* 10-bit Slave Address Mode */
3358 
#define UCMM                   (0x20)         /* Multi-Master Environment */
3359 
//#define res               (0x10)    /* reserved */
3360 
#define UCMODE_0               (0x00)         /* Sync. Mode: USCI Mode: 0 */
3361 
#define UCMODE_1               (0x02)         /* Sync. Mode: USCI Mode: 1 */
3362 
#define UCMODE_2               (0x04)         /* Sync. Mode: USCI Mode: 2 */
3363 
#define UCMODE_3               (0x06)         /* Sync. Mode: USCI Mode: 3 */
3364 
 
3365 
// UCAxCTL1 UART-Mode Control Bits
3366 
#define UCSSEL1                (0x80)         /* USCI 0 Clock Source Select 1 */
3367 
#define UCSSEL0                (0x40)         /* USCI 0 Clock Source Select 0 */
3368 
#define UCRXEIE                (0x20)         /* RX Error interrupt enable */
3369 
#define UCBRKIE                (0x10)         /* Break interrupt enable */
3370 
#define UCDORM                 (0x08)         /* Dormant (Sleep) Mode */
3371 
#define UCTXADDR               (0x04)         /* Send next Data as Address */
3372 
#define UCTXBRK                (0x02)         /* Send next Data as Break */
3373 
#define UCSWRST                (0x01)         /* USCI Software Reset */
3374 
 
3375 
// UCxxCTL1 SPI-Mode Control Bits
3376 
//#define res               (0x20)    /* reserved */
3377 
//#define res               (0x10)    /* reserved */
3378 
//#define res               (0x08)    /* reserved */
3379 
//#define res               (0x04)    /* reserved */
3380 
//#define res               (0x02)    /* reserved */
3381 
 
3382 
// UCBxCTL1 I2C-Mode Control Bits
3383 
//#define res               (0x20)    /* reserved */
3384 
#define UCTR                   (0x10)         /* Transmit/Receive Select/Flag */
3385 
#define UCTXNACK               (0x08)         /* Transmit NACK */
3386 
#define UCTXSTP                (0x04)         /* Transmit STOP */
3387 
#define UCTXSTT                (0x02)         /* Transmit START */
3388 
#define UCSSEL_0               (0x00)         /* USCI 0 Clock Source: 0 */
3389 
#define UCSSEL_1               (0x40)         /* USCI 0 Clock Source: 1 */
3390 
#define UCSSEL_2               (0x80)         /* USCI 0 Clock Source: 2 */
3391 
#define UCSSEL_3               (0xC0)         /* USCI 0 Clock Source: 3 */
3392 
#define UCSSEL__UCLK           (0x00)         /* USCI 0 Clock Source: UCLK */
3393 
#define UCSSEL__ACLK           (0x40)         /* USCI 0 Clock Source: ACLK */
3394 
#define UCSSEL__SMCLK          (0x80)         /* USCI 0 Clock Source: SMCLK */
3395 
 
3396 
/* UCAxMCTL Control Bits */
3397 
#define UCBRF3                 (0x80)         /* USCI First Stage Modulation Select 3 */
3398 
#define UCBRF2                 (0x40)         /* USCI First Stage Modulation Select 2 */
3399 
#define UCBRF1                 (0x20)         /* USCI First Stage Modulation Select 1 */
3400 
#define UCBRF0                 (0x10)         /* USCI First Stage Modulation Select 0 */
3401 
#define UCBRS2                 (0x08)         /* USCI Second Stage Modulation Select 2 */
3402 
#define UCBRS1                 (0x04)         /* USCI Second Stage Modulation Select 1 */
3403 
#define UCBRS0                 (0x02)         /* USCI Second Stage Modulation Select 0 */
3404 
#define UCOS16                 (0x01)         /* USCI 16-times Oversampling enable */
3405 
 
3406 
#define UCBRF_0                (0x00)         /* USCI First Stage Modulation: 0 */
3407 
#define UCBRF_1                (0x10)         /* USCI First Stage Modulation: 1 */
3408 
#define UCBRF_2                (0x20)         /* USCI First Stage Modulation: 2 */
3409 
#define UCBRF_3                (0x30)         /* USCI First Stage Modulation: 3 */
3410 
#define UCBRF_4                (0x40)         /* USCI First Stage Modulation: 4 */
3411 
#define UCBRF_5                (0x50)         /* USCI First Stage Modulation: 5 */
3412 
#define UCBRF_6                (0x60)         /* USCI First Stage Modulation: 6 */
3413 
#define UCBRF_7                (0x70)         /* USCI First Stage Modulation: 7 */
3414 
#define UCBRF_8                (0x80)         /* USCI First Stage Modulation: 8 */
3415 
#define UCBRF_9                (0x90)         /* USCI First Stage Modulation: 9 */
3416 
#define UCBRF_10               (0xA0)         /* USCI First Stage Modulation: A */
3417 
#define UCBRF_11               (0xB0)         /* USCI First Stage Modulation: B */
3418 
#define UCBRF_12               (0xC0)         /* USCI First Stage Modulation: C */
3419 
#define UCBRF_13               (0xD0)         /* USCI First Stage Modulation: D */
3420 
#define UCBRF_14               (0xE0)         /* USCI First Stage Modulation: E */
3421 
#define UCBRF_15               (0xF0)         /* USCI First Stage Modulation: F */
3422 
 
3423 
#define UCBRS_0                (0x00)         /* USCI Second Stage Modulation: 0 */
3424 
#define UCBRS_1                (0x02)         /* USCI Second Stage Modulation: 1 */
3425 
#define UCBRS_2                (0x04)         /* USCI Second Stage Modulation: 2 */
3426 
#define UCBRS_3                (0x06)         /* USCI Second Stage Modulation: 3 */
3427 
#define UCBRS_4                (0x08)         /* USCI Second Stage Modulation: 4 */
3428 
#define UCBRS_5                (0x0A)         /* USCI Second Stage Modulation: 5 */
3429 
#define UCBRS_6                (0x0C)         /* USCI Second Stage Modulation: 6 */
3430 
#define UCBRS_7                (0x0E)         /* USCI Second Stage Modulation: 7 */
3431 
 
3432 
/* UCAxSTAT Control Bits */
3433 
#define UCLISTEN               (0x80)         /* USCI Listen mode */
3434 
#define UCFE                   (0x40)         /* USCI Frame Error Flag */
3435 
#define UCOE                   (0x20)         /* USCI Overrun Error Flag */
3436 
#define UCPE                   (0x10)         /* USCI Parity Error Flag */
3437 
#define UCBRK                  (0x08)         /* USCI Break received */
3438 
#define UCRXERR                (0x04)         /* USCI RX Error Flag */
3439 
#define UCADDR                 (0x02)         /* USCI Address received Flag */
3440 
#define UCBUSY                 (0x01)         /* USCI Busy Flag */
3441 
#define UCIDLE                 (0x02)         /* USCI Idle line detected Flag */
3442 
 
3443 
/* UCBxSTAT Control Bits */
3444 
#define UCSCLLOW               (0x40)         /* SCL low */
3445 
#define UCGC                   (0x20)         /* General Call address received Flag */
3446 
#define UCBBUSY                (0x10)         /* Bus Busy Flag */
3447 
 
3448 
/* UCAxIRTCTL Control Bits */
3449 
#define UCIRTXPL5              (0x80)         /* IRDA Transmit Pulse Length 5 */
3450 
#define UCIRTXPL4              (0x40)         /* IRDA Transmit Pulse Length 4 */
3451 
#define UCIRTXPL3              (0x20)         /* IRDA Transmit Pulse Length 3 */
3452 
#define UCIRTXPL2              (0x10)         /* IRDA Transmit Pulse Length 2 */
3453 
#define UCIRTXPL1              (0x08)         /* IRDA Transmit Pulse Length 1 */
3454 
#define UCIRTXPL0              (0x04)         /* IRDA Transmit Pulse Length 0 */
3455 
#define UCIRTXCLK              (0x02)         /* IRDA Transmit Pulse Clock Select */
3456 
#define UCIREN                 (0x01)         /* IRDA Encoder/Decoder enable */
3457 
 
3458 
/* UCAxIRRCTL Control Bits */
3459 
#define UCIRRXFL5              (0x80)         /* IRDA Receive Filter Length 5 */
3460 
#define UCIRRXFL4              (0x40)         /* IRDA Receive Filter Length 4 */
3461 
#define UCIRRXFL3              (0x20)         /* IRDA Receive Filter Length 3 */
3462 
#define UCIRRXFL2              (0x10)         /* IRDA Receive Filter Length 2 */
3463 
#define UCIRRXFL1              (0x08)         /* IRDA Receive Filter Length 1 */
3464 
#define UCIRRXFL0              (0x04)         /* IRDA Receive Filter Length 0 */
3465 
#define UCIRRXPL               (0x02)         /* IRDA Receive Input Polarity */
3466 
#define UCIRRXFE               (0x01)         /* IRDA Receive Filter enable */
3467 
 
3468 
/* UCAxABCTL Control Bits */
3469 
//#define res               (0x80)    /* reserved */
3470 
//#define res               (0x40)    /* reserved */
3471 
#define UCDELIM1               (0x20)         /* Break Sync Delimiter 1 */
3472 
#define UCDELIM0               (0x10)         /* Break Sync Delimiter 0 */
3473 
#define UCSTOE                 (0x08)         /* Sync-Field Timeout error */
3474 
#define UCBTOE                 (0x04)         /* Break Timeout error */
3475 
//#define res               (0x02)    /* reserved */
3476 
#define UCABDEN                (0x01)         /* Auto Baud Rate detect enable */
3477 
 
3478 
/* UCBxI2COA Control Bits */
3479 
#define UCGCEN                 (0x8000)       /* I2C General Call enable */
3480 
#define UCOA9                  (0x0200)       /* I2C Own Address 9 */
3481 
#define UCOA8                  (0x0100)       /* I2C Own Address 8 */
3482 
#define UCOA7                  (0x0080)       /* I2C Own Address 7 */
3483 
#define UCOA6                  (0x0040)       /* I2C Own Address 6 */
3484 
#define UCOA5                  (0x0020)       /* I2C Own Address 5 */
3485 
#define UCOA4                  (0x0010)       /* I2C Own Address 4 */
3486 
#define UCOA3                  (0x0008)       /* I2C Own Address 3 */
3487 
#define UCOA2                  (0x0004)       /* I2C Own Address 2 */
3488 
#define UCOA1                  (0x0002)       /* I2C Own Address 1 */
3489 
#define UCOA0                  (0x0001)       /* I2C Own Address 0 */
3490 
 
3491 
/* UCBxI2COA Control Bits */
3492 
#define UCOA7_L                (0x0080)       /* I2C Own Address 7 */
3493 
#define UCOA6_L                (0x0040)       /* I2C Own Address 6 */
3494 
#define UCOA5_L                (0x0020)       /* I2C Own Address 5 */
3495 
#define UCOA4_L                (0x0010)       /* I2C Own Address 4 */
3496 
#define UCOA3_L                (0x0008)       /* I2C Own Address 3 */
3497 
#define UCOA2_L                (0x0004)       /* I2C Own Address 2 */
3498 
#define UCOA1_L                (0x0002)       /* I2C Own Address 1 */
3499 
#define UCOA0_L                (0x0001)       /* I2C Own Address 0 */
3500 
 
3501 
/* UCBxI2COA Control Bits */
3502 
#define UCGCEN_H               (0x0080)       /* I2C General Call enable */
3503 
#define UCOA9_H                (0x0002)       /* I2C Own Address 9 */
3504 
#define UCOA8_H                (0x0001)       /* I2C Own Address 8 */
3505 
 
3506 
/* UCBxI2CSA Control Bits */
3507 
#define UCSA9                  (0x0200)       /* I2C Slave Address 9 */
3508 
#define UCSA8                  (0x0100)       /* I2C Slave Address 8 */
3509 
#define UCSA7                  (0x0080)       /* I2C Slave Address 7 */
3510 
#define UCSA6                  (0x0040)       /* I2C Slave Address 6 */
3511 
#define UCSA5                  (0x0020)       /* I2C Slave Address 5 */
3512 
#define UCSA4                  (0x0010)       /* I2C Slave Address 4 */
3513 
#define UCSA3                  (0x0008)       /* I2C Slave Address 3 */
3514 
#define UCSA2                  (0x0004)       /* I2C Slave Address 2 */
3515 
#define UCSA1                  (0x0002)       /* I2C Slave Address 1 */
3516 
#define UCSA0                  (0x0001)       /* I2C Slave Address 0 */
3517 
 
3518 
/* UCBxI2CSA Control Bits */
3519 
#define UCSA7_L                (0x0080)       /* I2C Slave Address 7 */
3520 
#define UCSA6_L                (0x0040)       /* I2C Slave Address 6 */
3521 
#define UCSA5_L                (0x0020)       /* I2C Slave Address 5 */
3522 
#define UCSA4_L                (0x0010)       /* I2C Slave Address 4 */
3523 
#define UCSA3_L                (0x0008)       /* I2C Slave Address 3 */
3524 
#define UCSA2_L                (0x0004)       /* I2C Slave Address 2 */
3525 
#define UCSA1_L                (0x0002)       /* I2C Slave Address 1 */
3526 
#define UCSA0_L                (0x0001)       /* I2C Slave Address 0 */
3527 
 
3528 
/* UCBxI2CSA Control Bits */
3529 
#define UCSA9_H                (0x0002)       /* I2C Slave Address 9 */
3530 
#define UCSA8_H                (0x0001)       /* I2C Slave Address 8 */
3531 
 
3532 
/* UCAxIE Control Bits */
3533 
#define UCTXIE                 (0x0002)       /* USCI Transmit Interrupt Enable */
3534 
#define UCRXIE                 (0x0001)       /* USCI Receive Interrupt Enable */
3535 
 
3536 
/* UCBxIE Control Bits */
3537 
#define UCNACKIE               (0x0020)       /* NACK Condition interrupt enable */
3538 
#define UCALIE                 (0x0010)       /* Arbitration Lost interrupt enable */
3539 
#define UCSTPIE                (0x0008)       /* STOP Condition interrupt enable */
3540 
#define UCSTTIE                (0x0004)       /* START Condition interrupt enable */
3541 
#define UCTXIE                 (0x0002)       /* USCI Transmit Interrupt Enable */
3542 
#define UCRXIE                 (0x0001)       /* USCI Receive Interrupt Enable */
3543 
 
3544 
/* UCAxIFG Control Bits */
3545 
#define UCTXIFG                (0x0002)       /* USCI Transmit Interrupt Flag */
3546 
#define UCRXIFG                (0x0001)       /* USCI Receive Interrupt Flag */
3547 
 
3548 
/* UCBxIFG Control Bits */
3549 
#define UCNACKIFG              (0x0020)       /* NAK Condition interrupt Flag */
3550 
#define UCALIFG                (0x0010)       /* Arbitration Lost interrupt Flag */
3551 
#define UCSTPIFG               (0x0008)       /* STOP Condition interrupt Flag */
3552 
#define UCSTTIFG               (0x0004)       /* START Condition interrupt Flag */
3553 
#define UCTXIFG                (0x0002)       /* USCI Transmit Interrupt Flag */
3554 
#define UCRXIFG                (0x0001)       /* USCI Receive Interrupt Flag */
3555 
 
3556 
/* USCI Definitions */
3557 
#define USCI_NONE              (0x0000)       /* No Interrupt pending */
3558 
#define USCI_UCRXIFG           (0x0002)       /* USCI UCRXIFG */
3559 
#define USCI_UCTXIFG           (0x0004)       /* USCI UCTXIFG */
3560 
#define USCI_I2C_UCALIFG       (0x0002)       /* USCI I2C Mode: UCALIFG */
3561 
#define USCI_I2C_UCNACKIFG     (0x0004)       /* USCI I2C Mode: UCNACKIFG */
3562 
#define USCI_I2C_UCSTTIFG      (0x0006)       /* USCI I2C Mode: UCSTTIFG*/
3563 
#define USCI_I2C_UCSTPIFG      (0x0008)       /* USCI I2C Mode: UCSTPIFG*/
3564 
#define USCI_I2C_UCRXIFG       (0x000A)       /* USCI I2C Mode: UCRXIFG */
3565 
#define USCI_I2C_UCTXIFG       (0x000C)       /* USCI I2C Mode: UCTXIFG */
3566 
 
3567 
/************************************************************
3568 
* USCI A1
3569 
************************************************************/
3570 
#define __MSP430_HAS_USCI_A1__                /* Definition to show that Module is available */
3571 
#define __MSP430_BASEADDRESS_USCI_A1__ 0x0600
3572 
 
3573 
SFR_16BIT(UCA1CTLW0);                         /* USCI A1 Control Word Register 0 */
3574 
SFR_8BIT(UCA1CTLW0_L);                        /* USCI A1 Control Word Register 0 */
3575 
SFR_8BIT(UCA1CTLW0_H);                        /* USCI A1 Control Word Register 0 */
3576 
#define UCA1CTL1               UCA1CTLW0_L    /* USCI A1 Control Register 1 */
3577 
#define UCA1CTL0               UCA1CTLW0_H    /* USCI A1 Control Register 0 */
3578 
SFR_16BIT(UCA1BRW);                           /* USCI A1 Baud Word Rate 0 */
3579 
SFR_8BIT(UCA1BRW_L);                          /* USCI A1 Baud Word Rate 0 */
3580 
SFR_8BIT(UCA1BRW_H);                          /* USCI A1 Baud Word Rate 0 */
3581 
#define UCA1BR0                UCA1BRW_L      /* USCI A1 Baud Rate 0 */
3582 
#define UCA1BR1                UCA1BRW_H      /* USCI A1 Baud Rate 1 */
3583 
SFR_8BIT(UCA1MCTL);                           /* USCI A1 Modulation Control */
3584 
SFR_8BIT(UCA1STAT);                           /* USCI A1 Status Register */
3585 
SFR_8BIT(UCA1RXBUF);                          /* USCI A1 Receive Buffer */
3586 
SFR_8BIT(UCA1TXBUF);                          /* USCI A1 Transmit Buffer */
3587 
SFR_8BIT(UCA1ABCTL);                          /* USCI A1 LIN Control */
3588 
SFR_16BIT(UCA1IRCTL);                         /* USCI A1 IrDA Transmit Control */
3589 
SFR_8BIT(UCA1IRCTL_L);                        /* USCI A1 IrDA Transmit Control */
3590 
SFR_8BIT(UCA1IRCTL_H);                        /* USCI A1 IrDA Transmit Control */
3591 
#define UCA1IRTCTL             UCA1IRCTL_L    /* USCI A1 IrDA Transmit Control */
3592 
#define UCA1IRRCTL             UCA1IRCTL_H    /* USCI A1 IrDA Receive Control */
3593 
SFR_16BIT(UCA1ICTL);                          /* USCI A1 Interrupt Enable Register */
3594 
SFR_8BIT(UCA1ICTL_L);                         /* USCI A1 Interrupt Enable Register */
3595 
SFR_8BIT(UCA1ICTL_H);                         /* USCI A1 Interrupt Enable Register */
3596 
#define UCA1IE                 UCA1ICTL_L     /* USCI A1 Interrupt Enable Register */
3597 
#define UCA1IFG                UCA1ICTL_H     /* USCI A1 Interrupt Flags Register */
3598 
SFR_16BIT(UCA1IV);                            /* USCI A1 Interrupt Vector Register */
3599 
 
3600 
 
3601 
/************************************************************
3602 
* USCI B1
3603 
************************************************************/
3604 
#define __MSP430_HAS_USCI_B1__                /* Definition to show that Module is available */
3605 
#define __MSP430_BASEADDRESS_USCI_B1__ 0x0620
3606 
 
3607 
 
3608 
SFR_16BIT(UCB1CTLW0);                         /* USCI B1 Control Word Register 0 */
3609 
SFR_8BIT(UCB1CTLW0_L);                        /* USCI B1 Control Word Register 0 */
3610 
SFR_8BIT(UCB1CTLW0_H);                        /* USCI B1 Control Word Register 0 */
3611 
#define UCB1CTL1               UCB1CTLW0_L    /* USCI B1 Control Register 1 */
3612 
#define UCB1CTL0               UCB1CTLW0_H    /* USCI B1 Control Register 0 */
3613 
SFR_16BIT(UCB1BRW);                           /* USCI B1 Baud Word Rate 0 */
3614 
SFR_8BIT(UCB1BRW_L);                          /* USCI B1 Baud Word Rate 0 */
3615 
SFR_8BIT(UCB1BRW_H);                          /* USCI B1 Baud Word Rate 0 */
3616 
#define UCB1BR0                UCB1BRW_L      /* USCI B1 Baud Rate 0 */
3617 
#define UCB1BR1                UCB1BRW_H      /* USCI B1 Baud Rate 1 */
3618 
SFR_8BIT(UCB1STAT);                           /* USCI B1 Status Register */
3619 
SFR_8BIT(UCB1RXBUF);                          /* USCI B1 Receive Buffer */
3620 
SFR_8BIT(UCB1TXBUF);                          /* USCI B1 Transmit Buffer */
3621 
SFR_16BIT(UCB1I2COA);                         /* USCI B1 I2C Own Address */
3622 
SFR_8BIT(UCB1I2COA_L);                        /* USCI B1 I2C Own Address */
3623 
SFR_8BIT(UCB1I2COA_H);                        /* USCI B1 I2C Own Address */
3624 
SFR_16BIT(UCB1I2CSA);                         /* USCI B1 I2C Slave Address */
3625 
SFR_8BIT(UCB1I2CSA_L);                        /* USCI B1 I2C Slave Address */
3626 
SFR_8BIT(UCB1I2CSA_H);                        /* USCI B1 I2C Slave Address */
3627 
SFR_16BIT(UCB1ICTL);                          /* USCI B1 Interrupt Enable Register */
3628 
SFR_8BIT(UCB1ICTL_L);                         /* USCI B1 Interrupt Enable Register */
3629 
SFR_8BIT(UCB1ICTL_H);                         /* USCI B1 Interrupt Enable Register */
3630 
#define UCB1IE                 UCB1ICTL_L     /* USCI B1 Interrupt Enable Register */
3631 
#define UCB1IFG                UCB1ICTL_H     /* USCI B1 Interrupt Flags Register */
3632 
SFR_16BIT(UCB1IV);                            /* USCI B1 Interrupt Vector Register */
3633 
 
3634 
/************************************************************
3635 
* USCI A2
3636 
************************************************************/
3637 
#define __MSP430_HAS_USCI_A2__                /* Definition to show that Module is available */
3638 
#define __MSP430_BASEADDRESS_USCI_A2__ 0x0640
3639 
 
3640 
SFR_16BIT(UCA2CTLW0);                         /* USCI A2 Control Word Register 0 */
3641 
SFR_8BIT(UCA2CTLW0_L);                        /* USCI A2 Control Word Register 0 */
3642 
SFR_8BIT(UCA2CTLW0_H);                        /* USCI A2 Control Word Register 0 */
3643 
#define UCA2CTL1               UCA2CTLW0_L    /* USCI A2 Control Register 1 */
3644 
#define UCA2CTL0               UCA2CTLW0_H    /* USCI A2 Control Register 0 */
3645 
SFR_16BIT(UCA2BRW);                           /* USCI A2 Baud Word Rate 0 */
3646 
SFR_8BIT(UCA2BRW_L);                          /* USCI A2 Baud Word Rate 0 */
3647 
SFR_8BIT(UCA2BRW_H);                          /* USCI A2 Baud Word Rate 0 */
3648 
#define UCA2BR0                UCA2BRW_L      /* USCI A2 Baud Rate 0 */
3649 
#define UCA2BR1                UCA2BRW_H      /* USCI A2 Baud Rate 1 */
3650 
SFR_8BIT(UCA2MCTL);                           /* USCI A2 Modulation Control */
3651 
SFR_8BIT(UCA2STAT);                           /* USCI A2 Status Register */
3652 
SFR_8BIT(UCA2RXBUF);                          /* USCI A2 Receive Buffer */
3653 
SFR_8BIT(UCA2TXBUF);                          /* USCI A2 Transmit Buffer */
3654 
SFR_8BIT(UCA2ABCTL);                          /* USCI A2 LIN Control */
3655 
SFR_16BIT(UCA2IRCTL);                         /* USCI A2 IrDA Transmit Control */
3656 
SFR_8BIT(UCA2IRCTL_L);                        /* USCI A2 IrDA Transmit Control */
3657 
SFR_8BIT(UCA2IRCTL_H);                        /* USCI A2 IrDA Transmit Control */
3658 
#define UCA2IRTCTL             UCA2IRCTL_L    /* USCI A2 IrDA Transmit Control */
3659 
#define UCA2IRRCTL             UCA2IRCTL_H    /* USCI A2 IrDA Receive Control */
3660 
SFR_16BIT(UCA2ICTL);                          /* USCI A2 Interrupt Enable Register */
3661 
SFR_8BIT(UCA2ICTL_L);                         /* USCI A2 Interrupt Enable Register */
3662 
SFR_8BIT(UCA2ICTL_H);                         /* USCI A2 Interrupt Enable Register */
3663 
#define UCA2IE                 UCA2ICTL_L     /* USCI A2 Interrupt Enable Register */
3664 
#define UCA2IFG                UCA2ICTL_H     /* USCI A2 Interrupt Flags Register */
3665 
SFR_16BIT(UCA2IV);                            /* USCI A2 Interrupt Vector Register */
3666 
 
3667 
 
3668 
/************************************************************
3669 
* USCI B2
3670 
************************************************************/
3671 
#define __MSP430_HAS_USCI_B2__                /* Definition to show that Module is available */
3672 
#define __MSP430_BASEADDRESS_USCI_B2__ 0x0660
3673 
 
3674 
 
3675 
SFR_16BIT(UCB2CTLW0);                         /* USCI B2 Control Word Register 0 */
3676 
SFR_8BIT(UCB2CTLW0_L);                        /* USCI B2 Control Word Register 0 */
3677 
SFR_8BIT(UCB2CTLW0_H);                        /* USCI B2 Control Word Register 0 */
3678 
#define UCB2CTL1               UCB2CTLW0_L    /* USCI B2 Control Register 1 */
3679 
#define UCB2CTL0               UCB2CTLW0_H    /* USCI B2 Control Register 0 */
3680 
SFR_16BIT(UCB2BRW);                           /* USCI B2 Baud Word Rate 0 */
3681 
SFR_8BIT(UCB2BRW_L);                          /* USCI B2 Baud Word Rate 0 */
3682 
SFR_8BIT(UCB2BRW_H);                          /* USCI B2 Baud Word Rate 0 */
3683 
#define UCB2BR0                UCB2BRW_L      /* USCI B2 Baud Rate 0 */
3684 
#define UCB2BR1                UCB2BRW_H      /* USCI B2 Baud Rate 1 */
3685 
SFR_8BIT(UCB2STAT);                           /* USCI B2 Status Register */
3686 
SFR_8BIT(UCB2RXBUF);                          /* USCI B2 Receive Buffer */
3687 
SFR_8BIT(UCB2TXBUF);                          /* USCI B2 Transmit Buffer */
3688 
SFR_16BIT(UCB2I2COA);                         /* USCI B2 I2C Own Address */
3689 
SFR_8BIT(UCB2I2COA_L);                        /* USCI B2 I2C Own Address */
3690 
SFR_8BIT(UCB2I2COA_H);                        /* USCI B2 I2C Own Address */
3691 
SFR_16BIT(UCB2I2CSA);                         /* USCI B2 I2C Slave Address */
3692 
SFR_8BIT(UCB2I2CSA_L);                        /* USCI B2 I2C Slave Address */
3693 
SFR_8BIT(UCB2I2CSA_H);                        /* USCI B2 I2C Slave Address */
3694 
SFR_16BIT(UCB2ICTL);                          /* USCI B2 Interrupt Enable Register */
3695 
SFR_8BIT(UCB2ICTL_L);                         /* USCI B2 Interrupt Enable Register */
3696 
SFR_8BIT(UCB2ICTL_H);                         /* USCI B2 Interrupt Enable Register */
3697 
#define UCB2IE                 UCB2ICTL_L     /* USCI B2 Interrupt Enable Register */
3698 
#define UCB2IFG                UCB2ICTL_H     /* USCI B2 Interrupt Flags Register */
3699 
SFR_16BIT(UCB2IV);                            /* USCI B2 Interrupt Vector Register */
3700 
 
3701 
/************************************************************
3702 
* USCI A3
3703 
************************************************************/
3704 
#define __MSP430_HAS_USCI_A3__                /* Definition to show that Module is available */
3705 
#define __MSP430_BASEADDRESS_USCI_A3__ 0x0680
3706 
 
3707 
SFR_16BIT(UCA3CTLW0);                         /* USCI A3 Control Word Register 0 */
3708 
SFR_8BIT(UCA3CTLW0_L);                        /* USCI A3 Control Word Register 0 */
3709 
SFR_8BIT(UCA3CTLW0_H);                        /* USCI A3 Control Word Register 0 */
3710 
#define UCA3CTL1               UCA3CTLW0_L    /* USCI A3 Control Register 1 */
3711 
#define UCA3CTL0               UCA3CTLW0_H    /* USCI A3 Control Register 0 */
3712 
SFR_16BIT(UCA3BRW);                           /* USCI A3 Baud Word Rate 0 */
3713 
SFR_8BIT(UCA3BRW_L);                          /* USCI A3 Baud Word Rate 0 */
3714 
SFR_8BIT(UCA3BRW_H);                          /* USCI A3 Baud Word Rate 0 */
3715 
#define UCA3BR0                UCA3BRW_L      /* USCI A3 Baud Rate 0 */
3716 
#define UCA3BR1                UCA3BRW_H      /* USCI A3 Baud Rate 1 */
3717 
SFR_8BIT(UCA3MCTL);                           /* USCI A3 Modulation Control */
3718 
SFR_8BIT(UCA3STAT);                           /* USCI A3 Status Register */
3719 
SFR_8BIT(UCA3RXBUF);                          /* USCI A3 Receive Buffer */
3720 
SFR_8BIT(UCA3TXBUF);                          /* USCI A3 Transmit Buffer */
3721 
SFR_8BIT(UCA3ABCTL);                          /* USCI A3 LIN Control */
3722 
SFR_16BIT(UCA3IRCTL);                         /* USCI A3 IrDA Transmit Control */
3723 
SFR_8BIT(UCA3IRCTL_L);                        /* USCI A3 IrDA Transmit Control */
3724 
SFR_8BIT(UCA3IRCTL_H);                        /* USCI A3 IrDA Transmit Control */
3725 
#define UCA3IRTCTL             UCA3IRCTL_L    /* USCI A3 IrDA Transmit Control */
3726 
#define UCA3IRRCTL             UCA3IRCTL_H    /* USCI A3 IrDA Receive Control */
3727 
SFR_16BIT(UCA3ICTL);                          /* USCI A3 Interrupt Enable Register */
3728 
SFR_8BIT(UCA3ICTL_L);                         /* USCI A3 Interrupt Enable Register */
3729 
SFR_8BIT(UCA3ICTL_H);                         /* USCI A3 Interrupt Enable Register */
3730 
#define UCA3IE                 UCA3ICTL_L     /* USCI A3 Interrupt Enable Register */
3731 
#define UCA3IFG                UCA3ICTL_H     /* USCI A3 Interrupt Flags Register */
3732 
SFR_16BIT(UCA3IV);                            /* USCI A3 Interrupt Vector Register */
3733 
 
3734 
 
3735 
/************************************************************
3736 
* USCI B3
3737 
************************************************************/
3738 
#define __MSP430_HAS_USCI_B3__                /* Definition to show that Module is available */
3739 
#define __MSP430_BASEADDRESS_USCI_B3__ 0x06A0
3740 
 
3741 
 
3742 
SFR_16BIT(UCB3CTLW0);                         /* USCI B3 Control Word Register 0 */
3743 
SFR_8BIT(UCB3CTLW0_L);                        /* USCI B3 Control Word Register 0 */
3744 
SFR_8BIT(UCB3CTLW0_H);                        /* USCI B3 Control Word Register 0 */
3745 
#define UCB3CTL1               UCB3CTLW0_L    /* USCI B3 Control Register 1 */
3746 
#define UCB3CTL0               UCB3CTLW0_H    /* USCI B3 Control Register 0 */
3747 
SFR_16BIT(UCB3BRW);                           /* USCI B3 Baud Word Rate 0 */
3748 
SFR_8BIT(UCB3BRW_L);                          /* USCI B3 Baud Word Rate 0 */
3749 
SFR_8BIT(UCB3BRW_H);                          /* USCI B3 Baud Word Rate 0 */
3750 
#define UCB3BR0                UCB3BRW_L      /* USCI B3 Baud Rate 0 */
3751 
#define UCB3BR1                UCB3BRW_H      /* USCI B3 Baud Rate 1 */
3752 
SFR_8BIT(UCB3STAT);                           /* USCI B3 Status Register */
3753 
SFR_8BIT(UCB3RXBUF);                          /* USCI B3 Receive Buffer */
3754 
SFR_8BIT(UCB3TXBUF);                          /* USCI B3 Transmit Buffer */
3755 
SFR_16BIT(UCB3I2COA);                         /* USCI B3 I2C Own Address */
3756 
SFR_8BIT(UCB3I2COA_L);                        /* USCI B3 I2C Own Address */
3757 
SFR_8BIT(UCB3I2COA_H);                        /* USCI B3 I2C Own Address */
3758 
SFR_16BIT(UCB3I2CSA);                         /* USCI B3 I2C Slave Address */
3759 
SFR_8BIT(UCB3I2CSA_L);                        /* USCI B3 I2C Slave Address */
3760 
SFR_8BIT(UCB3I2CSA_H);                        /* USCI B3 I2C Slave Address */
3761 
SFR_16BIT(UCB3ICTL);                          /* USCI B3 Interrupt Enable Register */
3762 
SFR_8BIT(UCB3ICTL_L);                         /* USCI B3 Interrupt Enable Register */
3763 
SFR_8BIT(UCB3ICTL_H);                         /* USCI B3 Interrupt Enable Register */
3764 
#define UCB3IE                 UCB3ICTL_L     /* USCI B3 Interrupt Enable Register */
3765 
#define UCB3IFG                UCB3ICTL_H     /* USCI B3 Interrupt Flags Register */
3766 
SFR_16BIT(UCB3IV);                            /* USCI B3 Interrupt Vector Register */
3767 
 
3768 
/************************************************************
3769 
* WATCHDOG TIMER A
3770 
************************************************************/
3771 
#define __MSP430_HAS_WDT_A__                  /* Definition to show that Module is available */
3772 
#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
3773 
 
3774 
SFR_16BIT(WDTCTL);                            /* Watchdog Timer Control */
3775 
SFR_8BIT(WDTCTL_L);                           /* Watchdog Timer Control */
3776 
SFR_8BIT(WDTCTL_H);                           /* Watchdog Timer Control */
3777 
/* The bit names have been prefixed with "WDT" */
3778 
/* WDTCTL Control Bits */
3779 
#define WDTIS0                 (0x0001)       /* WDT - Timer Interval Select 0 */
3780 
#define WDTIS1                 (0x0002)       /* WDT - Timer Interval Select 1 */
3781 
#define WDTIS2                 (0x0004)       /* WDT - Timer Interval Select 2 */
3782 
#define WDTCNTCL               (0x0008)       /* WDT - Timer Clear */
3783 
#define WDTTMSEL               (0x0010)       /* WDT - Timer Mode Select */
3784 
#define WDTSSEL0               (0x0020)       /* WDT - Timer Clock Source Select 0 */
3785 
#define WDTSSEL1               (0x0040)       /* WDT - Timer Clock Source Select 1 */
3786 
#define WDTHOLD                (0x0080)       /* WDT - Timer hold */
3787 
 
3788 
/* WDTCTL Control Bits */
3789 
#define WDTIS0_L               (0x0001)       /* WDT - Timer Interval Select 0 */
3790 
#define WDTIS1_L               (0x0002)       /* WDT - Timer Interval Select 1 */
3791 
#define WDTIS2_L               (0x0004)       /* WDT - Timer Interval Select 2 */
3792 
#define WDTCNTCL_L             (0x0008)       /* WDT - Timer Clear */
3793 
#define WDTTMSEL_L             (0x0010)       /* WDT - Timer Mode Select */
3794 
#define WDTSSEL0_L             (0x0020)       /* WDT - Timer Clock Source Select 0 */
3795 
#define WDTSSEL1_L             (0x0040)       /* WDT - Timer Clock Source Select 1 */
3796 
#define WDTHOLD_L              (0x0080)       /* WDT - Timer hold */
3797 
 
3798 
/* WDTCTL Control Bits */
3799 
 
3800 
#define WDTPW                  (0x5A00)
3801 
 
3802 
#define WDTIS_0                (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
3803 
#define WDTIS_1                (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
3804 
#define WDTIS_2                (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
3805 
#define WDTIS_3                (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
3806 
#define WDTIS_4                (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
3807 
#define WDTIS_5                (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
3808 
#define WDTIS_6                (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
3809 
#define WDTIS_7                (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
3810 
#define WDTIS__2G              (0*0x0001u)    /* WDT - Timer Interval Select: /2G */
3811 
#define WDTIS__128M            (1*0x0001u)    /* WDT - Timer Interval Select: /128M */
3812 
#define WDTIS__8192K           (2*0x0001u)    /* WDT - Timer Interval Select: /8192k */
3813 
#define WDTIS__512K            (3*0x0001u)    /* WDT - Timer Interval Select: /512k */
3814 
#define WDTIS__32K             (4*0x0001u)    /* WDT - Timer Interval Select: /32k */
3815 
#define WDTIS__8192            (5*0x0001u)    /* WDT - Timer Interval Select: /8192 */
3816 
#define WDTIS__512             (6*0x0001u)    /* WDT - Timer Interval Select: /512 */
3817 
#define WDTIS__64              (7*0x0001u)    /* WDT - Timer Interval Select: /64 */
3818 
 
3819 
#define WDTSSEL_0              (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
3820 
#define WDTSSEL_1              (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
3821 
#define WDTSSEL_2              (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
3822 
#define WDTSSEL_3              (3*0x0020u)    /* WDT - Timer Clock Source Select: reserved */
3823 
#define WDTSSEL__SMCLK         (0*0x0020u)    /* WDT - Timer Clock Source Select: SMCLK */
3824 
#define WDTSSEL__ACLK          (1*0x0020u)    /* WDT - Timer Clock Source Select: ACLK */
3825 
#define WDTSSEL__VLO           (2*0x0020u)    /* WDT - Timer Clock Source Select: VLO_CLK */
3826 
 
3827 
/* WDT-interval times [1ms] coded with Bits 0-2 */
3828 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
3829 
#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2)                         /* 32ms interval (default) */
3830 
#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0)                  /* 8ms     " */
3831 
#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1)                  /* 0.5ms   " */
3832 
#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)           /* 0.064ms " */
3833 
/* WDT is clocked by fACLK (assumed 32KHz) */
3834 
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)                /* 1000ms  " */
3835 
#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0)         /* 250ms   " */
3836 
#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1)         /* 16ms    " */
3837 
#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0)  /* 1.9ms   " */
3838 
/* Watchdog mode -> reset after expired time */
3839 
/* WDT is clocked by fSMCLK (assumed 1MHz) */
3840 
#define WDT_MRST_32         (WDTPW+WDTCNTCL+WDTIS2)                                  /* 32ms interval (default) */
3841 
#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS2+WDTIS0)                           /* 8ms     " */
3842 
#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS2+WDTIS1)                           /* 0.5ms   " */
3843 
#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0)                    /* 0.064ms " */
3844 
/* WDT is clocked by fACLK (assumed 32KHz) */
3845 
#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2)                         /* 1000ms  " */
3846 
#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0)                  /* 250ms   " */
3847 
#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1)                  /* 16ms    " */
3848 
#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0)           /* 1.9ms   " */
3849 
 
3850 
 
3851 
/************************************************************
3852 
* TLV Descriptors
3853 
************************************************************/
3854 
#define __MSP430_HAS_TLV__                    /* Definition to show that Module is available */
3855 
 
3856 
#define TLV_START              (0x1A08)       /* Start Address of the TLV structure */
3857 
#define TLV_END                (0x1AFF)       /* End Address of the TLV structure */
3858 
 
3859 
#define TLV_LDTAG              (0x01)         /*  Legacy descriptor (1xx, 2xx, 4xx families) */
3860 
#define TLV_PDTAG              (0x02)         /*  Peripheral discovery descriptor */
3861 
#define TLV_Reserved3          (0x03)         /*  Future usage */
3862 
#define TLV_Reserved4          (0x04)         /*  Future usage */
3863 
#define TLV_BLANK              (0x05)         /*  Blank descriptor */
3864 
#define TLV_Reserved6          (0x06)         /*  Future usage */
3865 
#define TLV_Reserved7          (0x07)         /*  Serial Number */
3866 
#define TLV_DIERECORD          (0x08)         /*  Die Record  */
3867 
#define TLV_ADCCAL             (0x11)         /*  ADC12 calibration */
3868 
#define TLV_ADC12CAL           (0x11)         /*  ADC12 calibration */
3869 
#define TLV_ADC10CAL           (0x13)         /*  ADC10 calibration */
3870 
#define TLV_REFCAL             (0x12)         /*  REF calibration */
3871 
#define TLV_TAGEXT             (0xFE)         /*  Tag extender */
3872 
#define TLV_TAGEND             (0xFF)         //  Tag End of Table
3873 
 
3874 
/************************************************************
3875 
* Interrupt Vectors (offset from 0xFF80)
3876 
************************************************************/
3877 
 
3878 
#pragma diag_suppress 1107
3879 
#define VECTOR_NAME(name)             name##_ptr
3880 
#define EMIT_PRAGMA(x)                _Pragma(#x)
3881 
#define CREATE_VECTOR(name)           void * const VECTOR_NAME(name) = (void *)(long)&name
3882 
#define PLACE_VECTOR(vector,section)  EMIT_PRAGMA(DATA_SECTION(vector,section))
3883 
#define PLACE_INTERRUPT(func)         EMIT_PRAGMA(CODE_SECTION(func,".text:_isr"))
3884 
#define ISR_VECTOR(func,offset)       CREATE_VECTOR(func); \
3885 
                                      PLACE_VECTOR(VECTOR_NAME(func), offset) \
3886 
                                      PLACE_INTERRUPT(func)
3887 
 
3888 
 
3889 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3890 
#define RTC_VECTOR              ".int41"                    /* 0xFFD2 RTC */
3891 
#else
3892 
#define RTC_VECTOR              (41 * 1u)                    /* 0xFFD2 RTC */
3893 
/*#define RTC_ISR(func)           ISR_VECTOR(func, ".int41")  */ /* 0xFFD2 RTC */ /* CCE V2 Style */
3894 
#endif
3895 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3896 
#define PORT2_VECTOR            ".int42"                    /* 0xFFD4 Port 2 */
3897 
#else
3898 
#define PORT2_VECTOR            (42 * 1u)                    /* 0xFFD4 Port 2 */
3899 
/*#define PORT2_ISR(func)         ISR_VECTOR(func, ".int42")  */ /* 0xFFD4 Port 2 */ /* CCE V2 Style */
3900 
#endif
3901 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3902 
#define USCI_B3_VECTOR          ".int43"                    /* 0xFFD6 USCI B3 Receive/Transmit */
3903 
#else
3904 
#define USCI_B3_VECTOR          (43 * 1u)                    /* 0xFFD6 USCI B3 Receive/Transmit */
3905 
/*#define USCI_B3_ISR(func)       ISR_VECTOR(func, ".int43")  */ /* 0xFFD6 USCI B3 Receive/Transmit */ /* CCE V2 Style */
3906 
#endif
3907 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3908 
#define USCI_A3_VECTOR          ".int44"                    /* 0xFFD8 USCI A3 Receive/Transmit */
3909 
#else
3910 
#define USCI_A3_VECTOR          (44 * 1u)                    /* 0xFFD8 USCI A3 Receive/Transmit */
3911 
/*#define USCI_A3_ISR(func)       ISR_VECTOR(func, ".int44")  */ /* 0xFFD8 USCI A3 Receive/Transmit */ /* CCE V2 Style */
3912 
#endif
3913 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3914 
#define USCI_B1_VECTOR          ".int45"                    /* 0xFFDA USCI B1 Receive/Transmit */
3915 
#else
3916 
#define USCI_B1_VECTOR          (45 * 1u)                    /* 0xFFDA USCI B1 Receive/Transmit */
3917 
/*#define USCI_B1_ISR(func)       ISR_VECTOR(func, ".int45")  */ /* 0xFFDA USCI B1 Receive/Transmit */ /* CCE V2 Style */
3918 
#endif
3919 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3920 
#define USCI_A1_VECTOR          ".int46"                    /* 0xFFDC USCI A1 Receive/Transmit */
3921 
#else
3922 
#define USCI_A1_VECTOR          (46 * 1u)                    /* 0xFFDC USCI A1 Receive/Transmit */
3923 
/*#define USCI_A1_ISR(func)       ISR_VECTOR(func, ".int46")  */ /* 0xFFDC USCI A1 Receive/Transmit */ /* CCE V2 Style */
3924 
#endif
3925 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3926 
#define PORT1_VECTOR            ".int47"                    /* 0xFFDE Port 1 */
3927 
#else
3928 
#define PORT1_VECTOR            (47 * 1u)                    /* 0xFFDE Port 1 */
3929 
/*#define PORT1_ISR(func)         ISR_VECTOR(func, ".int47")  */ /* 0xFFDE Port 1 */ /* CCE V2 Style */
3930 
#endif
3931 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3932 
#define TIMER1_A1_VECTOR        ".int48"                    /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
3933 
#else
3934 
#define TIMER1_A1_VECTOR        (48 * 1u)                    /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
3935 
/*#define TIMER1_A1_ISR(func)     ISR_VECTOR(func, ".int48")  */ /* 0xFFE0 Timer1_A3 CC1-2, TA1 */ /* CCE V2 Style */
3936 
#endif
3937 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3938 
#define TIMER1_A0_VECTOR        ".int49"                    /* 0xFFE2 Timer1_A3 CC0 */
3939 
#else
3940 
#define TIMER1_A0_VECTOR        (49 * 1u)                    /* 0xFFE2 Timer1_A3 CC0 */
3941 
/*#define TIMER1_A0_ISR(func)     ISR_VECTOR(func, ".int49")  */ /* 0xFFE2 Timer1_A3 CC0 */ /* CCE V2 Style */
3942 
#endif
3943 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3944 
#define DMA_VECTOR              ".int50"                    /* 0xFFE4 DMA */
3945 
#else
3946 
#define DMA_VECTOR              (50 * 1u)                    /* 0xFFE4 DMA */
3947 
/*#define DMA_ISR(func)           ISR_VECTOR(func, ".int50")  */ /* 0xFFE4 DMA */ /* CCE V2 Style */
3948 
#endif
3949 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3950 
#define USCI_B2_VECTOR          ".int51"                    /* 0xFFE6 USCI B2 Receive/Transmit */
3951 
#else
3952 
#define USCI_B2_VECTOR          (51 * 1u)                    /* 0xFFE6 USCI B2 Receive/Transmit */
3953 
/*#define USCI_B2_ISR(func)       ISR_VECTOR(func, ".int51")  */ /* 0xFFE6 USCI B2 Receive/Transmit */ /* CCE V2 Style */
3954 
#endif
3955 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3956 
#define USCI_A2_VECTOR          ".int52"                    /* 0xFFE8 USCI A2 Receive/Transmit */
3957 
#else
3958 
#define USCI_A2_VECTOR          (52 * 1u)                    /* 0xFFE8 USCI A2 Receive/Transmit */
3959 
/*#define USCI_A2_ISR(func)       ISR_VECTOR(func, ".int52")  */ /* 0xFFE8 USCI A2 Receive/Transmit */ /* CCE V2 Style */
3960 
#endif
3961 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3962 
#define TIMER0_A1_VECTOR        ".int53"                    /* 0xFFEA Timer0_A5 CC1-4, TA */
3963 
#else
3964 
#define TIMER0_A1_VECTOR        (53 * 1u)                    /* 0xFFEA Timer0_A5 CC1-4, TA */
3965 
/*#define TIMER0_A1_ISR(func)     ISR_VECTOR(func, ".int53")  */ /* 0xFFEA Timer0_A5 CC1-4, TA */ /* CCE V2 Style */
3966 
#endif
3967 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3968 
#define TIMER0_A0_VECTOR        ".int54"                    /* 0xFFEC Timer0_A5 CC0 */
3969 
#else
3970 
#define TIMER0_A0_VECTOR        (54 * 1u)                    /* 0xFFEC Timer0_A5 CC0 */
3971 
/*#define TIMER0_A0_ISR(func)     ISR_VECTOR(func, ".int54")  */ /* 0xFFEC Timer0_A5 CC0 */ /* CCE V2 Style */
3972 
#endif
3973 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3974 
#define ADC12_VECTOR            ".int55"                    /* 0xFFEE ADC */
3975 
#else
3976 
#define ADC12_VECTOR            (55 * 1u)                    /* 0xFFEE ADC */
3977 
/*#define ADC12_ISR(func)         ISR_VECTOR(func, ".int55")  */ /* 0xFFEE ADC */ /* CCE V2 Style */
3978 
#endif
3979 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3980 
#define USCI_B0_VECTOR          ".int56"                    /* 0xFFF0 USCI B0 Receive/Transmit */
3981 
#else
3982 
#define USCI_B0_VECTOR          (56 * 1u)                    /* 0xFFF0 USCI B0 Receive/Transmit */
3983 
/*#define USCI_B0_ISR(func)       ISR_VECTOR(func, ".int56")  */ /* 0xFFF0 USCI B0 Receive/Transmit */ /* CCE V2 Style */
3984 
#endif
3985 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3986 
#define USCI_A0_VECTOR          ".int57"                    /* 0xFFF2 USCI A0 Receive/Transmit */
3987 
#else
3988 
#define USCI_A0_VECTOR          (57 * 1u)                    /* 0xFFF2 USCI A0 Receive/Transmit */
3989 
/*#define USCI_A0_ISR(func)       ISR_VECTOR(func, ".int57")  */ /* 0xFFF2 USCI A0 Receive/Transmit */ /* CCE V2 Style */
3990 
#endif
3991 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3992 
#define WDT_VECTOR              ".int58"                    /* 0xFFF4 Watchdog Timer */
3993 
#else
3994 
#define WDT_VECTOR              (58 * 1u)                    /* 0xFFF4 Watchdog Timer */
3995 
/*#define WDT_ISR(func)           ISR_VECTOR(func, ".int58")  */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */
3996 
#endif
3997 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
3998 
#define TIMER0_B1_VECTOR        ".int59"                    /* 0xFFF6 Timer0_B7 CC1-6, TB */
3999 
#else
4000 
#define TIMER0_B1_VECTOR        (59 * 1u)                    /* 0xFFF6 Timer0_B7 CC1-6, TB */
4001 
/*#define TIMER0_B1_ISR(func)     ISR_VECTOR(func, ".int59")  */ /* 0xFFF6 Timer0_B7 CC1-6, TB */ /* CCE V2 Style */
4002 
#endif
4003 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4004 
#define TIMER0_B0_VECTOR        ".int60"                    /* 0xFFF8 Timer0_B7 CC0 */
4005 
#else
4006 
#define TIMER0_B0_VECTOR        (60 * 1u)                    /* 0xFFF8 Timer0_B7 CC0 */
4007 
/*#define TIMER0_B0_ISR(func)     ISR_VECTOR(func, ".int60")  */ /* 0xFFF8 Timer0_B7 CC0 */ /* CCE V2 Style */
4008 
#endif
4009 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4010 
#define UNMI_VECTOR             ".int61"                    /* 0xFFFA User Non-maskable */
4011 
#else
4012 
#define UNMI_VECTOR             (61 * 1u)                    /* 0xFFFA User Non-maskable */
4013 
/*#define UNMI_ISR(func)          ISR_VECTOR(func, ".int61")  */ /* 0xFFFA User Non-maskable */ /* CCE V2 Style */
4014 
#endif
4015 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4016 
#define SYSNMI_VECTOR           ".int62"                    /* 0xFFFC System Non-maskable */
4017 
#else
4018 
#define SYSNMI_VECTOR           (62 * 1u)                    /* 0xFFFC System Non-maskable */
4019 
/*#define SYSNMI_ISR(func)        ISR_VECTOR(func, ".int62")  */ /* 0xFFFC System Non-maskable */ /* CCE V2 Style */
4020 
#endif
4021 
#ifdef __ASM_HEADER__ /* Begin #defines for assembler */
4022 
#define RESET_VECTOR            ".reset"                    /* 0xFFFE Reset [Highest Priority] */
4023 
#else
4024 
#define RESET_VECTOR            (63 * 1u)                    /* 0xFFFE Reset [Highest Priority] */
4025 
/*#define RESET_ISR(func)         ISR_VECTOR(func, ".int63")  */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */
4026 
#endif
4027 
 
4028 
/************************************************************
4029 
* End of Modules
4030 
************************************************************/
4031 
 
4032 
#ifdef __cplusplus
4033 
}
4034 
#endif /* extern "C" */
4035 
 
4036 
#endif /* #ifndef __msp430x54xA */
4037